A 4.9-dB NF 53.5-62-GHz Micro-machined CMOS Wideband LNA
- 格式：pdf
- 大小：802.62 KB
- 文档页数：4
978-1-4244-7732-6/10/$26.00 ©2010
IEEE
489
Abstract- A 53.5-62-GHz wideband CMOS low-noise amplifier
(LNA) with excellent phase linearity property is reported. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (Sl 1) of -10.3- -19.5 dB, output return loss ( S22) of -13.8- -27.8 dB, forward gain ( S21) of 8.1- 11.1 dB, and reverse isolation ( S12) of -49.9- -60.2 dB over the 53.5-62-GHz-band. The minimum NF (NFmi ) is 5.4 dB at 62 GHz. To reduce the substrate
n
power dissipation [6]. To reduce the substrate loss,the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology was used to remove the silicon underneath the LNA [71-
II.
CIRCUIT DESIGN
loss, the CMOS process compatible backside inductively-coupled plasma (ICP) deep trench technology is used to remove the silicon underneath the LNA. After the ICP etching, the LNA (ICP LNA) achieved maximum S21 ( S21-max) of 13.2 dB, 2.1 dB higher than that (11.1 dB) of the STD LNA. In addition, the ICP LNA achieved NFmin of 4.9 dB, 0.5 dB lower than that (5.4 dB) of the STD LNA. These results demonstrate the proposed LNA architecture in conjunction with the backside ICP technology is very promising for 60-GHz-band RFIC applications.
Index Terms- 60-GHz, CMOS, wideband, low-noise amplifier,Biblioteka gain, linearity
I.
INTRODUCTION
In USA, Canada, and Japan, there is 7-GHz-wide unlicensed band around 60 GHz for wireless personal area network (WPAN) system applications [1]. A 60 GHz WPAN system can provide short-range «10 m) and high-speed (>2 Gb/s) multi-media data access to nearby consumer appliances and computer terminals. In the past, III-V semiconductor technologies were adopted in most of the applications for frequencies around 60 GHz and above. Recently,thanks to the rapid development of CMOS/BiCMOS processes, it has become possible to use them to implement 60 GHz WPAN system and even 77 GHz radar system. Low-noise amplifier (LNA) is the first block in a receiver front-end. The basic requirements of an LNA include good input impedance matching, flat and low noise, and flat and high gain over the band of interest Recently,several excellent 60 GHz CMOS LNAs have been reported [2]-[5]. However, their NF and power consumption were not satisfactory_ In this work, a 53.5-62-GHz wideband LNA with excellent phase linearity property using standard 0.13 m CMOS technology is reported. Current-sharing technique was adopted to reduce
Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, ROC Tel: 886-492912198; Fax: 886-492917810; Email: stephenlin@.tw *Graduate Institute of Electronics Engineering and Department of Electrical Engineering, Na ti onal Taiwan Uni versi ty, 1 06 Tai pei, Taiwan, R.O.C.; E-mail: s sl u@n tu . edu.tw
A 4.9-dB NF 53.5-62-GHz Micro-machined CMOS Wideband LNA
with Small Group-Delay-Variation
Chi-Chen Chen, Yo-Sheng Lin, Pen-Li Huang*, Jin-Fa Chang, and Shey-Shi Lu*
The 60-GHz CMOS LNA was designed and implemented by a standard 0_13 11m CMOS process (on a p-type silicon substrate with thickness of 300 m and resistivity of 8-12 Q·cm) provided by a commercial foundry. This technology offered 8 metal layers, named M] to Ms from bottom to top. The thickness of Ms was 335 m,and that of M7,M6-M2' and M] was 0.83 m,0.37 m, and 0.26 m, respectively. The IMD (inter-metal dielectric) thickness was 0_695 m between Ms and M7, 0.67 m between M7 and M6, 0-45 m between other adjacent metal layers,and 0-49 m between M] and the silicon substrate. The interconnection lines as well as the microstrip-line (MSL) inductors were placed on the 3.35- m thick topmost metal to minimize the resistive loss. Fig_ l(a) shows the complete schematic of the 60-GHz CMOS LNA. To achieve sufficient gain, this LNA was composed of six cascade common-source stages. The output of each stage was loaded with a bandpass combination of L and C to provide parallel resonance, i.e. to maximize the gain, over the 60-GHz-band of interest Since the DC current of the third and the fifth stage of the LNA was reused in the second and the fourth stage, respectively, no additional driving current was needed for the second and the fourth stage. In this way, low power consumption could be achieved. Based on the method in [8], simultaneous input impedance and noise matching over the 60-GHz-band of interest was achieved by appropriately selecting the values of the T-type input network, the source-degenerative inductor, and the size and bias of transistor M], i.e. Cgs] and gm], of the input stage. Besides, a source degenerative inductor was used in the output stage to achieve output impedance matching and improve stability. The corresponding inductance of all the interconnection lines as well as the MSL inductors is listed in Fig_ l(a). The other component parameters adopted are as follows: R] :=R2= R3= �= Rs= 3.3 k ,�= 5 k ,C]= 1.07 pF,C2= 125.7 iF, C3= 512_2 iF, C4 = 240_6 iF, Cs= 131.9 iF,
