ATmega16中文手册

ATmega16 包含512 字节的EEPROM 数据存储器。

它是作为一个独立的数据空间而存在的，可以按字节读写。

EEPROM 的寿命至少为100,000 次擦除周期。

EEPROM 的访问由地址寄存器、数据寄存器和控制寄存器决定。

通过SPI和JTAG及并行电缆下载EEPROM数据的操作请分别参见P260、P265及P250。

EEPROM 读/ 写访问EEPROM 读/ 写访问EEPROM 的访问寄存器位于I/O 空间。

EEPROM的写访问时间由Table 1给出。

自定时功能可以让用户软件监测何时可以开始写下一字节。

用户操作EEPROM 需要注意如下问题：在电源滤波时间常数比较大的电路中，上电/ 下电时VCC 上升/ 下降速度会比较慢。

此时CPU 可能工作于低于晶振所要求的电源电压。

请参见P20“ 防止EEPROM 数据丢失” 以避免出现EEPROM 数据丢失的问题。

为了防止无意识的EEPROM 写操作，需要执行一个特定的写时序。

具体参看EEPROM控制寄存器的内容。

执行EEPROM 读操作时，CPU 会停止工作4 个周期，然后再执行后续指令；执行EEPROM 写操作时，CPU 会停止工作2 个周期，然后再执行后续指令。

EEPROM 地址寄存器－EEARH和EEARL· Bits 15..9 – Res: 保留保留位，读操作返回值为零。

· Bits 8..0 – EEAR8..0: EEPROM 地址EEPROM地址寄存器– EEARH和EEARL指定了512字节的EEPROM空间。

EEPROM地址是线性的，从0 到511。

EEAR 的初始值没有定义。

在访问EEPROM 之前必须为其赋予正确的数据。

EEPROM 数据寄存器－EEDR· Bits 7..0 – EEDR7.0: EEPROM 数据对于EEPROM 写操作，EEDR 是需要写到EEAR 单元的数据；对于读操作，EEDR 是从地址EEAR 读取的数据。

Features•High-performance, low-power 8-bit Atmel ® AVR ® Microcontroller •Advanced RISC architecture–131 powerful Instructions – most single-clock cycle execution –32 × 8 general purpose working registers –Fully static operation–Up to 20MIPS throughput at 20MHz –On-chip 2-cycle multiplier•High endurance non-volatile memory segments–16/32/64/128KBytes of In-System Self-programmable Flash program memory –512/1K/2K/4KBytes EEPROM –1/2/4/16KBytes Internal SRAM–Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM –Data retention: 20 years at 85°C/ 100 years at 25°C (1)–Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot Program True Read-While-Write Operation–Programming Lock for Software Security •Atmel QTouch ® library support–Capacitive touch buttons, sliders and wheels –QTouch and QMatrix acquisition –Up to 64 sense channels•JTAG (IEEE std. 1149.1 Compliant) Interface–Boundary-scan Capabilities According to the JTAG Standard –Extensive On-chip Debug Support–Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface •Peripheral Features–Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes–One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode –Real Time Counter with Separate Oscillator –Six PWM Channels –8-channel, 10-bit ADCDifferential mode with selectable gain at 1×, 10× or 200×–Byte-oriented Two-wire Serial Interface –Two Programmable Serial USART –Master/Slave SPI Serial Interface–Programmable Watchdog Timer with Separate On-chip Oscillator –On-chip Analog Comparator–Interrupt and Wake-up on Pin Change •Special Microcontroller Features–Power-on Reset and Programmable Brown-out Detection –Internal Calibrated RC Oscillator–External and Internal Interrupt Sources–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby •I/O and Packages–32 Programmable I/O Lines–40-pin PDIP , 44-lead TQFP, 44-pad VQFN/QFN/MLF –44-pad DRQFN –49-ball VFBGA •Operating Voltages – 1.8 - 5.5V •Speed Grades–0 - 4MHz @ 1.8 - 5.5V –0 - 10MHz @ 2.7 - 5.5V –0 - 20MHz @ 4.5 - 5.5V•Power Consumption at 1MHz, 1.8V, 25°C –Active: 0.4mA–Power-down Mode: 0.1µA–Power-save Mode: 0.6µA (Including 32kHz RTC)Note:1.See ”Data retention” on page 9 for details.8-bit AtmelMicrocontroller with16/32/64/128K Bytes In-System Programmable FlashATmega164A ATmega164PA ATmega324A ATmega324PA ATmega644A ATmega644PA ATmega1284ATmega1284PSummary8272DS–AVR–05/121.Pin configurations1.1Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284PFigure 1-1.Pinout.Note:The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground onthe board to ensure good mechanical stability.Figure 1-2.DRQFN - pinout.Table 1-1.DRQFN - pinout.A1PB5A7PD3A13PC4A19P A3 B1PB6B6PD4B11PC5B16P A2 A2PB7A8PD5A14PC6A20P A1 B2RESET B7PD6B12PC7B17P A0 A3VCC A9PD7A15AVCC A21VCC B3GND B8VCC B13GND B18GND A4XT AL2A10GND A16AREF A22PB0 B4XT AL1B9PC0B14P A7B19PB1 A5PD0A11PC1A17P A6A23PB2 B5PD1B10PC2B15P A5B20PB3 A6PD2A12PC3A18P A4A24PB4Figure 1-3.VFBGA - pinout.Table 1-2.BGA - pinout.1234567A GND PB4PB2GND VCC P A2GND B PB6PB5PB3PB0P A0P A3P A5C VCC RESET PB7PB1P A1P A6AREF D GND XT AL2PD0GND P A4P A7GND E XTAL1PD1PD5PD7PC5PC7AVCC F PD2PD3PD6PC0PC2PC4PC6GGNDPD4VCCGNDPC1PC3GND2.OverviewThe Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerfuli n s t r u c t i o n s i n a s i n g l e c l o c k c y c l e,t h eATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs approach-ing 1 MIPS per MHz allowing the system designer to optimize power consumption versusprocessing speed.2.1Block diagramFigure 2-1.Block diagram.The AVR core combines a rich instruction set with 32 general purpose working registers. All the32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independentregisters to be accessed in one single instruction executed in one clock cycle. The resultingarchitecture is more code efficient while achieving throughputs up to ten times faster thanconventional CISC microcontrollers.The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provide the following features:16/32/64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K/4Kbytes EEPROM, 1/2/4/16Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with com-pare modes and PWM, 2 USARTs, a byte oriented two-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std.1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software select-able power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Reso-nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a powerful microcon-troller that provides a highly flexible and cost effective solution to many embedded control applications.The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.2.2Comparison between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P2.3Pin Descriptions2.3.1VCCDigital supply voltage.2.3.2GNDGround.2.3.3Port A (PA7:PA0)Port A serves as analog inputs to the Analog-to-digital Converter.Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t A a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e A t m e l ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 80.2.3.4Port B (PB7:PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,even if the clock is not running.P o r t B a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 82.2.3.5Port C (PC7:PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and sourceTable 2-1.Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P.Device Flash EEPROM RAM UnitsA Tmega164A 16K 5121K bytes A Tmega164P A 16K 5121K A Tmega324A 32K 1K 2K A Tmega324P A 32K 1K 2K A Tmega644A 64K 2K 4K A Tmega644P A 64K 2K 4K A Tmega1284128K 4K 16K A Tmega1284P128K4K16Kcapability. As inputs, Port C pins that are externally pulled low will source current if the pull-upresistors are activated. The Port C pins are tri-stated when a reset condition becomes active,even if the clock is not running.Port C also serves the functions of the JTAG interface, along with special features of the AtmelATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 85.2.3.6Port D (PD7:PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort D output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port D pins that are externally pulled low will source current if the pull-upresistors are activated. The Port D pins are tri-stated when a reset condition becomes active,even if the clock is not running.P o r t D a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h eATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 88.2.3.7RESETReset input. A low level on this pin for longer than the minimum pulse length will generate areset, even if the clock is not running. The minimum pulse length is given in ”” on page 336.Shorter pulses are not guaranteed to generate a reset.2.3.8XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.2.3.9XTAL2Output from the inverting Oscillator amplifier.2.3.10AVCCAVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be exter-nally connected to V CC, even if the ADC is not used. If the ADC is used, it should be connectedto V CC through a low-pass filter.2.3.11AREFThis is the analog reference pin for the Analog-to-digital Converter.3.ResourcesA comprehensive set of development tools, application notes and datasheetsare available fordownload on /avr.4.About code examplesThis documentation contains simple code examples that briefly show how to use various parts ofthe device. Be aware that not all C compiler vendors include bit definitions in the header filesand interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.The code examples assume that the part specific header file is included before compilation. ForI/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instruc-tions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and"STS" combined with "SBRS", "SBRC", "SBR", and "CBR".5.Data retentionReliability Qualification results show that the projected data retention failure rate is much lessthan 1 PPM over 20 years at 85°C or 100 years at 25°C.6.Capacitive touch sensingThe Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaceson most Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch andQMatrix acquisition methods.Touch sensing can be added to any application by linking the appropriate Atmel QTouch Libraryfor the AVR Microcontroller. This is done by using a simple set of APIs to define the touch chan-nels and sensors, and then calling the touch sensing API’s to retrieve the channel informationand determine the touch sensor states.The QTouch Library is FREE and downloadable from the Atmel website at the following location:/qtouchlibrary. For implementation details and other information, refer to theAtmel QTouch Library User Guide - also available for download from the Atmel website.7.Register summaryAddress Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page (0xFF)Reserved-------(0xFE)Reserved--------(0xFD)Reserved--------(0xFC)Reserved--------(0xFB)Reserved-------(0xFA)Reserved--------(0xF9)Reserved-------(0xF8)Reserved--------(0xF7)Reserved--------(0xF6)Reserved--------(0xF5)Reserved-------(0xF4)Reserved--------(0xF3)Reserved--------(0xF2)Reserved--------(0xF1)Reserved-------(0xF0)Reserved--------(0xEF)Reserved-------(0xEE)Reserved--------(0xED)Reserved--------(0xEC)Reserved--------(0xEB)Reserved-------(0xEA)Reserved--------(0xE9)Reserved--------(0xE8)Reserved--------(0xE7)Reserved-------(0xE6)Reserved--------(0xE5)Reserved--------(0xE4)Reserved--------(0xE3)Reserved-------(0xE2)Reserved--------(0xE1)Reserved-------(0xE0)Reserved-------(0xDF)Reserved--------(0xDE)Reserved--------(0xDD)Reserved--------(0xDC)Reserved-------(0xDB)Reserved--------(0xDA)Reserved--------(0xD9)Reserved--------(0xD8)Reserved--------(0xD7)Reserved--------(0xD6)Reserved--------(0xD5)Reserved--------(0xD4)Reserved--------(0xD3)Reserved--------(0xD2)Reserved--------(0xD1)Reserved--------(0xD0)Reserved--------(0xCF)Reserved--------(0xCE)UDR1 USART1 I/O Data Register192 (0xCD)UBRR1H----USART1 Baud Rate Register High Byte196/209 (0xCC)UBRR1L USART1 Baud Rate Register Low Byte196/209 (0xCB)Reserved--------(0xCA)UCSR1C UMSEL11UMSEL10UPM11UPM10USBS1UCSZ11/UDORD0(5)UCSZ10/UCPHA0(5)UCPOL1194/208 (0xC9)UCSR1B RXCIE1TXCIE1UDRIE1RXEN1TXEN1UCSZ12RXB81TXB81193/207 (0xC8)UCSR1A RXC1TXC1UDRE1FE1DOR1UPE1U2X1MPCM1192/207 (0xC7)Reserved--------(0xC6)UDR0 USART0 I/O Data Register192 (0xC5)UBRR0H----USART0 Baud Rate Register High Byte196/209 (0xC4)UBRR0L USART0 Baud Rate Register Low Byte196/209 (0xC3)Reserved--------(0xC2)UCSR0C UMSEL01UMSEL00UPM01UPM00USBS0UCSZ01/UDORD0(5)UCSZ00/UCPHA0(5)UCPOL0194/208 (0xC1)UCSR0B RXCIE0TXCIE0UDRIE0RXEN0TXEN0UCSZ02RXB80TXB80193/207分销商库存信息:ATMELATMEGA164PA-ANR ATMEGA164PA-MNR。

ATmega16A引脚功能说明
引脚功能说明：
VCC 数字电路的电源
GND地
端口A(PA7..PA0) 端口A 做为A/D 转换器的模拟输入端
端口B(PB7..PB0) 端口B 为8 位双向I/O 口，具有可编程的内部上拉电阻
端口C(PC7..PC0)端口C 为8 位双向I/O 口，具有可编程的内部上拉电阻。

端口D(PD7..PD0)端口D 为8 位双向I/O 口，具有可编程的内部上拉电阻RESET复位输入引脚。

持续时间超过最小门限时间的低电平将引起系统复位
XTAL1反向振荡放大器与片内时钟操作电路的输入端。

XTAL2反向振荡放大器的输出端。

AVCC AVCC是端口A与A/D转换器的电源。

不使用ADC时，该引脚应直接与VCC连接。

使用ADC
时应通过一个低通滤波器与VCC 连接。

AREF A/D 的模拟基准输入引脚。

Features•High-performance, Low-power AVR® 8-bit Microcontroller •Advanced RISC Architecture–131 Powerful Instructions – Most Single-clock Cycle Execution –32 x 8 General Purpose Working Registers–Fully Static Operation–Up to 16 MIPS Throughput at 16 MHz–On-chip 2-cycle Multiplier•Nonvolatile Program and Data Memories–16K Bytes of In-System Self-Programmable FlashEndurance: 10,000 Write/Erase Cycles–Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation–512 Bytes EEPROMEndurance: 100,000 Write/Erase Cycles–1K Byte Internal SRAM–Programming Lock for Software Security•JTAG (IEEE std. 1149.1 Compliant) Interface–Boundary-scan Capabilities According to the JTAG Standard–Extensive On-chip Debug Support–Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface •Peripheral Features–Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode–Real Time Counter with Separate Oscillator–Four PWM Channels–8-channel, 10-bit ADC8 Single-ended Channels7 Differential Channels in TQFP Package Only2 Differential Channels with Programmable Gain at 1x, 10x, or 200x–Byte-oriented Two-wire Serial Interface–Programmable Serial USART–Master/Slave SPI Serial Interface–Programmable Watchdog Timer with Separate On-chip Oscillator–On-chip Analog Comparator•Special Microcontroller Features–Power-on Reset and Programmable Brown-out Detection–Internal Calibrated RC Oscillator–External and Internal Interrupt Sources–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby•I/O and Packages–32 Programmable I/O Lines–40-pin PDIP, 44-lead TQFP, and 44-pad MLF•Operating Voltages–2.7 - 5.5V for ATmega16L–4.5 - 5.5V for ATmega16•Speed Grades–0 - 8 MHz for ATmega16L–0 - 16 MHz for ATmega16•Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L–Active: 1.1 mA–Idle Mode: 0.35 mA–Power-down Mode: < 1 µA 8-bit Microcontrollerwith 16K BytesNote: This is a summary document. A complete document is available on our Web site at .2ATmega16(L)2466HS–AVR–12/03Pin ConfigurationsFigure 1. Pinouts ATmega16DisclaimerTypical values contained in this datasheet are based on simulations and characteriza-tion of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.3ATmega16(L)2466HS–AVR–12/03OverviewThe ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.Block DiagramFigure 2. Block Diagram4ATmega16(L)2466HS–AVR–12/03The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.The ATmega16 provides the following features: 16K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only),a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register con-tents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchro-nous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping.This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel’s high density nonvolatile memory technology.The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Soft-ware in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.Pin DescriptionsVCC Digital supply voltage.GNDGround.Port A (PA7..PA0)Port A serves as the analog inputs to the A/D Converter.Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability.When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.5ATmega16(L)2466HS–AVR–12/03Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port B also serves the functions of various special features of the ATmega16 as listed on page 56.Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be acti-vated even if a reset occurs.Port C also serves the functions of the JTAG interface and other special features of the ATmega16 as listed on page 59.Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port D also serves the functions of various special features of the ATmega16 as listed on page 61.RESETReset Input. A low level on this pin for longer than the minimum pulse length will gener-ate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 36. Shorter pulses are not guaranteed to generate a reset.XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting Oscillator amplifier.AVCCAVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to V CC , even if the ADC is not used. If the ADC is used, it should be con-nected to V CC through a low-pass filter.AREFAREF is the analog reference pin for the A/D Converter.6ATmega16(L)2466HS–AVR–12/03Register Summary7ATmega16(L)2466HS–AVR–12/03Notes:1.When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debug-ger specific documentation for details on how to use the OCDR Register.2.Refer to the USART description for details on how to access UBRRH and UCSRC.3.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addressesshould never be written.4.Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate onall bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.$01 ($21)TWSR TWS7TWS6TWS5TWS4TWS3–TWPS1TWPS0179$00 ($20)TWBRTwo-wire Serial Interface Bit Rate Register178AddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page8ATmega16(L)2466HS–AVR–12/03Instruction Set SummaryMnemonicsOperandsDescriptionOperationFlags#ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add two RegistersRd ← Rd + Rr Z,C,N,V,H 1ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2SUB Rd, Rr Subtract two RegistersRd ← Rd - Rr Z,C,N,V,H 1SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1SBCI Rd, K Subtract with Carry Constant from Reg.Rd ← Rd - K - C Z,C,N,V,H 1SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2AND Rd, Rr Logical AND RegistersRd ← Rd • Rr Z,N,V 1ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1OR Rd, Rr Logical OR RegistersRd ← Rd v Rr Z,N,V 1ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V 1NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H 1SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FF - K)Z,N,V 1INC Rd Increment Rd ← Rd + 1Z,N,V 1DEC Rd DecrementRd ← Rd − 1 Z,N,V 1TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1SER Rd Set Register Rd ← $FF None 1MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2MULS Rd, Rr Multiply SignedR1:R0 ← Rd x Rr Z,C 2MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1Z,C 2FMULS Rd, Rr Fractional Multiply SignedR1:R0 ← (Rd x Rr) << 1Z,C 2FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1Z,C 2BRANCH INSTRUCTIONSRJMP kRelative Jump PC ← PC + k + 1None 2IJMP Indirect Jump to (Z)PC ← ZNone 2JMP k Direct JumpPC ← kNone 3RCALL kRelative Subroutine Call PC ← PC + k + 1None 3ICALL Indirect Call to (Z)PC ← Z None 3CALL k Direct Subroutine Call PC ← kNone 4RET Subroutine Return PC ← STACK None 4RETI Interrupt Return PC ← STACKI 4CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3None 1 / 2 / 3CP Rd,Rr CompareRd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with CarryRd − Rr − C Z, N,V,C,H 1CPI Rd,K Compare Register with Immediate Rd − KZ, N,V,C,H 1SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3None 1 / 2 / 3SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3None 1 / 2 / 3BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC+k + 1None 1 / 2BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC+k + 1None 1 / 2BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1None 1 / 2BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1None 1 / 2BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1None 1 / 2BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1None 1 / 2BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1None 1 / 2BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1None 1 / 2BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1None 1 / 2BRPL k Branch if Plusif (N = 0) then PC ← PC + k + 1None 1 / 2BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1None 1 / 2BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1None 1 / 2BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1None 1 / 2BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1None 1 / 2BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1None 1 / 2BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1None 1 / 2BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1None 1 / 2BRVCk Branch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1 / 29ATmega16(L)2466HS–AVR–12/03BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1None 1 / 2BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1None 1 / 2DATA TRANSFER INSTRUCTIONSMOV Rd, Rr Move Between Registers Rd ← RrNone 1MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:RrNone 1LDI Rd, K Load Immediate Rd ← KNone 1LD Rd, X Load IndirectRd ← (X)None 2LD Rd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None 2LD Rd, - X Load Indirect and Pre-Dec.X ← X - 1, Rd ← (X)None 2LD Rd, Y Load IndirectRd ← (Y)None 2LD Rd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1None 2LD Rd, - Y Load Indirect and Pre-Dec.Y ← Y - 1, Rd ← (Y)None 2LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q)None 2LD Rd, Z Load IndirectRd ← (Z)None 2LD Rd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None 2LD Rd, -Z Load Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)None 2LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q)None 2LDS Rd, k Load Direct from SRAM Rd ← (k)None 2ST X, Rr Store Indirect(X) ← RrNone 2ST X+, Rr Store Indirect and Post-Inc.(X) ← Rr, X ← X + 1None 2ST - X, Rr Store Indirect and Pre-Dec.X ← X - 1, (X) ← Rr None 2ST Y, Rr Store Indirect(Y) ← RrNone 2ST Y+, Rr Store Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None 2ST - Y, Rr Store Indirect and Pre-Dec.Y ← Y - 1, (Y) ← Rr None 2STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2ST Z, Rr Store Indirect(Z) ← RrNone 2ST Z+, Rr Store Indirect and Post-Inc.(Z) ← Rr, Z ← Z + 1None 2ST -Z, Rr Store Indirect and Pre-Dec.Z ← Z - 1, (Z) ← Rr None 2STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2STS k, RrStore Direct to SRAM (k) ← Rr None 2LPM Load Program Memory R0 ← (Z)None 3LPM Rd, Z Load Program MemoryRd ← (Z)None 3LPM Rd, Z+Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1None 3SPM Store Program Memory (Z) ← R1:R0None -IN Rd, P In Port Rd ← PNone 1OUT P, Rr Out PortP ← Rr None 1PUSH Rr Push Register on Stack STACK ← Rr None 2POP Rd Pop Register from Stack Rd ← STACKNone 2BIT AND BIT-TEST INSTRUCTIONSSBI P,b Set Bit in I/O Register I/O(P,b) ← 1None 2CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None 2LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V 1LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V 1ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C ←Rd(7)Z,C,N,V 1ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C ←Rd(0)Z,C,N,V 1ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6Z,C,N,V 1SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)None 1BSET s Flag Set SREG(s) ← 1SREG(s)1BCLR s Flag ClearSREG(s) ← 0 SREG(s)1BST Rr, b Bit Store from Register to T T ← Rr(b)T 1BLD Rd, b Bit load from T to Register Rd(b) ← TNone 1SEC Set Carry C ← 1C 1CLC Clear Carry C ← 0C 1SEN Set Negative Flag N ← 1N 1CLN Clear Negative Flag N ← 0N 1SEZ Set Zero Flag Z ← 1Z 1CLZ Clear Zero Flag Z ← 0Z 1SEI Global Interrupt Enable I ← 1I 1CLI Global Interrupt Disable I ← 0I 1SES Set Signed Test Flag S ← 1S 1CLS Clear Signed Test FlagS ← 0S 1SEVSet Twos Complement Overflow.V ← 1V1CLVClear Twos Complement Overflow V ← 0 V1SET Set T in SREG T ← 1T 1CLT Clear T in SREG T ← 0 T 1SEH Set Half Carry Flag in SREG H ← 1H 1MnemonicsOperandsDescriptionOperationFlags#Clocks10ATmega16(L)2466HS–AVR–12/03CLHClear Half Carry Flag in SREG H ← 0H1MCU CONTROL INSTRUCTIONS NOP No Operation None 1SLEEP Sleep(see specific descr. for Sleep function)None 1WDR Watchdog Reset (see specific descr. for WDR/timer)None 1BREAKBreakFor On-Chip Debug OnlyNoneN/AMnemonics Operands DescriptionOperationFlags#Clocks11ATmega16(L)2466HS–AVR–12/0312ATmega16(L)2466HS–AVR–12/03Packaging Information44A13ATmega16(L)2466HS–AVR–12/0340P614ATmega16(L)2466HS–AVR–12/0344M115ATmega16(L)2466HS–AVR–12/03ErrataThe revision letter in this section refers to the revision of the ATmega16 device.ATmega16(L) Rev. I•IDCODE masks data from TDI input 1.IDCODE masks data from TDI inputThe JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR.Problem Fix / Workaround –If A Tmega16 is the only device in the scan chain, the problem is not visible.–Select the Device ID Register of the A Tmega16 by issuing the IDCODE instruction or by entering the T est-Logic-Reset state of the T AP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYP ASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain.–If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the A Tmega16 must be the fist device in the chain.ATmega16(L) Rev. H•IDCODE masks data from TDI input 1.IDCODE masks data from TDI inputThe JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR.Problem Fix / Workaround –If A Tmega16 is the only device in the scan chain, the problem is not visible.–Select the Device ID Register of the A Tmega16 by issuing the IDCODE instruction or by entering the T est-Logic-Reset state of the T AP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYP ASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain.–If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the A Tmega16 must be the fist device in the chain.ATmega16(L) Rev. G•IDCODE masks data from TDI input 1.IDCODE masks data from TDI inputThe JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR.Problem Fix / Workaround –If A Tmega16 is the only device in the scan chain, the problem is not visible.–Select the Device ID Register of the A Tmega16 by issuing the IDCODE instruction or by entering the T est-Logic-Reset state of the T AP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYP ASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain.16ATmega16(L)2466HS–AVR–12/03–If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the A Tmega16 must be the fist device in the chain.17ATmega16(L)2466HS–AVR–12/03Datasheet Change Log for ATmega16This section contains a log on the changes made to the datasheet for ATmega16.Changes from Rev. 2466G-10/03 to Rev. 2466H-12/03All page numbers refer to this document.1.Updated “Calibrated Internal RC Oscillator” on page 27.Changes from Rev. 2466F-02/03 to Rev. 2466G-10/03All page numbers refer to this document.1.Removed “Preliminary” from the datasheet.2.Changed ICP to ICP1 in the datasheet.3.Updated “JTAG Interface and On-chip Debug System” on page 34.4.Updated assembly and C code examples in “Watchdog Timer Control Regis-ter – WDTCR” on page 41.5.Updated Figure 46 on page 101.6.Updated Table 15 on page 36, Table 82 on page 215 and Table 115 on page274.7.Updated “Test Access Port – TAP” on page 220 regarding JTAGEN.8.Updated description for the JTD bit on page 229.9.Added note 2 to Figure 126 on page 251.10.Added a note regarding JTAGEN fuse to Table 105 on page 259.11.Updated Absolute Maximum Ratings* and DC Characteristics in “ElectricalCharacteristics” on page 289.12.Updated “ATmega16 Typical Characteristics” on page 297.13.Fixed typo for 16 MHz MLF package in “Ordering Information” on page 11.14.Added a proposal for solving problems regarding the JTAG instructionIDCODE in “Errata” on page 15.Changes from Rev. 2466E-10/02 to Rev. 2466F-02/03All page numbers refer to this document.1.Added note about masking out unused bits when reading the ProgramCounter in “Stack Pointer” on page 10.2.Added Chip Erase as a first step in “Programming the Flash” on page 286 and“Programming the EEPROM” on page 287.3.Added the section “Unconnected pins” on page 53.18ATmega16(L)2466HS–AVR–12/034.Added tips on how to disable the OCD system in “On-chip Debug System” onpage 34.5.Removed reference to the “Multi-purpose Oscillator” application note and“32kHz Crystal Oscillator” application note, which do not exist.6.Added information about PWM symmetry for Timer0 and Timer2.7.Added note in “Filling the Temporary Buffer (Page Loading)” on page 252about writing to the EEPROM during an SPM Page Load.8.Removed ADHSM completely.9.Added Table 73, “TWI Bit Rate Prescaler,” on page 180 to describe the TWPSbits in the “TWI Status Register – TWSR” on page 179.10.Added section “Default Clock Source” on page 23.11.Added note about frequency variation when using an external clock. Noteadded in “External Clock” on page 29. An extra row and a note added in Table 118 on page 291. 12.Various minor TWI corrections.13.Added “Power Consumption” data in “Features” on page 1.14.Added section “EEPROM Write During Power-down Sleep Mode” on page 20.15.Added note about Differential Mode with Auto Triggering in “Prescaling andConversion Timing” on page 205.16.Added updated “Packaging Information” on page 12.Changes from Rev. 2466D-09/02 to Rev. 2466E-10/02All page numbers refer to this document.1.Updated “DC Characteristics” on page 289.Changes from Rev. 2466C-03/02 to Rev. 2466D-09/02All page numbers refer to this document.1.Changed all Flash write/erase cycles from 1,000 to 10,000.2.Updated the following tables: Table 4 on page 24, Table 15 on page 36, Table42 on page 83, Table 45 on page 110, Table 46 on page 110, Table 59 on page 141, Table 67 on page 165, Table 90 on page 233, Table 102 on page 257, “DC Characteristics” on page 289, Table 119 on page 291, Table 121 on page 293,and Table 122 on page 295.3.Updated “Errata” on page 15.Changes from Rev. 2466B-09/01 to Rev. 2466C-03/02All page numbers refer to this document.1.Updated typical EEPROM programming time, Table 1 on page 18.19ATmega16(L)2466HS–AVR–12/032.Updated typical start-up time in the following tables:Table 3 on page 23, Table 5 on page 25, Table 6 on page 26, Table 8 on page 27,Table 9 on page 27, and Table 10 on page 28.3.Updated Table 17 on page 41 with typical WDT Time-out.4.Added Some Preliminary Test Limits and Characterization Data.Removed some of the TBD's in the following tables and pages:Table 15 on page 36, Table 16 on page 40, Table 116 on page 272 (table removed in document review #D), “Electrical Characteristics” on page 289, Table 119 on page 291, Table 121 on page 293, and Table 122 on page 295.5.Updated TWI Chapter.Added the note at the end of the “Bit Rate Generator Unit” on page 176.6.Corrected description of ADSC bit in “ADC Control and Status Register A –ADCSRA” on page 217.7.Improved description on how to do a polarity check of the ADC doff results in“ADC Conversion Result” on page 214.8.Added JTAG version number for rev. H in Table 87 on page 227.9.Added not regarding OCDEN Fuse below Table 105 on page 259.10.Updated Programming Figures:Figure 127 on page 261 and Figure 136 on page 272 are updated to also reflect that AVCC must be connected during Programming mode. Figure 131 on page 268added to illustrate how to program the fuses.11.Added a note regarding usage of the “PROG_PAGELOAD ($6)” on page 278and “PROG_PAGEREAD ($7)” on page 278.12.Removed alternative algortihm for leaving JTAG Programming mode.See “Leaving Programming Mode” on page 286.13.Added Calibrated RC Oscillator characterization curves in section “ATmega16Typical Characteristics” on page 297.14.Corrected ordering code for MLF package (16MHz) in “Ordering Information”on page 11.15.Corrected Table 90, “Scan Signals for the Oscillators (1)(2)(3),” on page 233.Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80Literature Requests/literature2466HS–AVR–12/03© Atmel Corporation 2003. All rights reserved. Atmel ® and combinations thereof, AVR ®, and AVR Studio ® are the registered trademarks of Atmel Corporation or its subsidiaries. Microsoft ®, Windows ®, Windows NT ®, and Windows XP ® are the registered trademarks of Microsoft Corpo-ration. Other terms and product names may be the trademarks of others。