LPX471M160A3P3中文资料

DDR2 SDRAMMT47H512M4 – 64 Meg x 4 x 8 banks MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banksFeatures•V DD = 1.8V ±0.1V, V DDQ = 1.8V ±0.1V•JEDEC-standard 1.8V I/O (SSTL_18-compatible)•Differential data strobe (DQS, DQS#) option•4n-bit prefetch architecture•Duplicate output strobe (RDQS) option for x8•DLL to align DQ and DQS transitions with CK •8 internal banks for concurrent operation •Programmable CAS latency (CL)•Posted CAS additive latency (AL)•WRITE latency = READ latency - 1 t CK •Programmable burst lengths: 4 or 8•Adjustable data-output drive strength•64ms, 8192-cycle refresh•On-die termination (ODT)•Industrial temperature (IT) option•RoHS-compliant•Supports JEDEC clock jitter specification Options1Marking •Configuration–512 Meg x 4 (64 Meg x 4 x 8 banks)512M4–256 Meg x 8 (32 Meg x 8 x 8 banks)256M8–128 Meg x 16 (16 Meg x 16 x 8 banks)128M16•FBGA package (Pb-free) – x16–84-ball FBGA (11.5mm x 14mm) Rev. A HG •FBGA package (Pb-free) – x4, x8–60-ball FBGA (11.5mm x 14mm) Rev. A HG •FBGA package (Pb-free) – x16–84-ball FBGA (9mm x 12.5mm) Rev. C RT •FBGA package (Pb-free) – x4, x8–60-ball FBGA (9mm x 11.5mm) Rev. C EB •FBGA package (Lead solder) – x16–84-ball FBGA (9mm x 12.5mm) Rev. C PK •Timing – cycle time– 1.875ns @ CL = 7 (DDR2-1066)-187E– 2.5ns @ CL = 5 (DDR2-800)-25E– 2.5ns @ CL = 6 (DDR2-800)-25– 3.0ns @ CL = 5 (DDR2-667)-3•Self refresh–Standard None •Operating temperature–Commercial (0°C ื T C ื +85°C)None–Industrial (–40°C ื T C ื +95°C;–40°C ื T A ื +85°C)IT •Revision:A/:CNote: 1.Not all options listed can be combined todefine an offered product. Use the PartCatalog Search on forproduct offerings and availability.2Gb: x4, x8, x16 DDR2 SDRAMFeaturesFunctional DescriptionThe DDR2 SDRAM uses a double data rate architecture to achieve high-speed opera-tion. The double data rate architecture is essentially a 4n -prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single READ or WRITE operation for the DDR2 SDRAM effectively consists of a single 4n -bit-wide, two-clock-cycle data transfer at the internal DRAM core and four corresponding n -bit-wide, one-half-clock-cycle data transfers at the I/O balls.A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,UDQS#).The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-mands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK.Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a se-lected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The ad-dress bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be en-abled to provide a self-timed row precharge that is initiated at the end of the burst ac-cess.As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time.A self refresh mode is provided, along with a power-saving, power-down mode.All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible.Industrial TemperatureThe industrial temperature (IT) option, if offered, has two simultaneous requirements:ambient temperature surrounding the device cannot be less than –40°C or greater than 85°C, and the case temperature cannot be less than –40°C or greater than 95°C. JEDEC specifications require the refresh rate to double when T C exceeds 85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance, input/output impedance and I DD values must be derated when T C is < 0°C or > 85°C.2Gb: x4, x8, x16 DDR2 SDRAM Functional Description。

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Table 50: DDR3L Differential Output Driver Characteristics V OX(AC)Notes:1.RZQ of 240˖ ±1% with RZQ/7 enabled (default 34˖ driver) and is applicable after prop-er ZQ calibration has been performed at a stable temperature and voltage (V DDQ = V DD ;V SSQ = V SS ).2.See Figure 31 (page 75) for the test load configuration.3.See Figure 30 (page 74) for an example of a differential output signal.4.For a differential slew rate between the list values, the V OX(AC) value may be obtainedby linear interpolation.Figure 30: Differential Output SignalV OHMIN outputMAX outputV OLV OX(AC)maxV OX(AC)minReference Output LoadFigure 31 (page 75) represents the effective reference load of 25ȍ used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the out-put slew rate measurements. It is not intended to be a precise representation of a partic-ular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the tim-ing reference load to a system environment.Figure 31: Reference Output Load for AC Timing and Output Slew RateV TT = V DDQ /2V SSSlew Rate Definitions for Single-Ended Output SignalsThe single-ended output driver is summarized in Table 48 (page 72). With the reference load for timing measurements, the output slew rate for falling and rising edges is de-fined and measured between V OL(AC) and V OH(AC) for single-ended signals.Table 51: Single-Ended Output Slew Rate Definition4Gb: x4, x8, x16 DDR3L SDRAMOutput Characteristics and Operating Conditionsleast once every 70.3μs. When T C is greater than 85°C, but less the 95°C, the refresh peri-od is 32ms. When T C is greater than 95°C, but less the 105°C, the refresh period is 16ms.37.Although CKE is allowed to be registered LOW after a REFRESH command whent REFPDEN (MIN) is satisfied, there are cases where additional time such as t XPDLL (MIN) is required.38.ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins toturn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 24 (page 63). This output load is used for ODT timings (see Figure 31 (page 75)).Designs that were created prior to JEDEC tightening the maxi-mum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum.39.Half-clock output parameters must be derated by the actual t ERR10per and t JITdty wheninput clock jitter is present. This results in each parameter becoming larger. The parame-ters t ADC (MIN) and t AOF (MIN) are each required to be derated by subtracting both t ERR10per (MAX) and t JITdty (MAX). The parameters t ADC (MAX) and t AOF (MAX) are required to be derated by subtracting both t ERR10per (MAX) and t JITdty (MAX).4Gb: x4, x8, x16 DDR3L SDRAMElectrical Characteristics and AC Operating Conditions。

Bus Operations CE# LOW and RST# HIGH enable READ operations. The device internally decodes up-per address inputs to determine the accessed block. ADV# LOW opens the internal ad-dress latches. OE# LOW activates the outputs and gates selected data onto the I/O bus.Bus cycles to/from the device conform to standard microprocessor bus operations. Busoperations and the logic levels that must be applied to the device control signal inputsare shown here.Table 9: Bus OperationsNotes: 1.Refer to the Device Command Bus Cycles for valid DQ[15:0] during a WRITE operation.2.X = "Don’t Care" (H or L).3.RST# must be at V SS ± 0.2V to meet the maximum specified power-down current. ReadTo perform a READ operation, RST# and WE# must be de-asserted while CE# and OE#are asserted. CE# is the device-select control. When asserted, it enables the device. OE#is the data-output control. When asserted, the addressed flash memory data is drivenonto the I/O bus.WriteTo perform a WRITE operation, both CE# and WE# are asserted while RST# and OE# arede-asserted. During a WRITE operation, address and data are latched on the rising edgeof WE# or CE#, whichever occurs first. The Command Bus Cycles table shows the buscycle sequence for each of the supported device commands, while the Command Codesand Definitions table describes each command.Note: WRITE operations with invalid V CC and/or V PP voltages can produce spurious re-sults and should not be attempted.Output DisableWhen OE# is de-asserted, device outputs DQ[15:0] are disabled and placed in High-Zstate, WAIT is also placed in High-Z.StandbyWhen CE# is de-asserted the device is deselected and placed in standby, substantiallyreducing power consumption. In standby, the data outputs are placed in High-Z, inde-pendent of the level placed on OE#. Standby current (I CCS) is the average current meas-Status RegisterRead Status RegisterTo read the status register, issue the READ STATUS REGISTER command at any address.Status register information is available at the address that the READ STATUS REGISTER,WORD PROGRAM, or BLOCK ERASE command is issued to. Status register data is auto-matically made available following a word program, block erase, or block lock com-mand sequence. Reads from the device after any of these command sequences will out-put the devices status until another valid command is written (e.g. READ ARRAY com-mand).The status register is read using single asynchronous mode or synchronous burst modereads. Status register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. Inasynchronous mode, the falling edge of OE# or CE# (whichever occurs first) updatesand latches the status register contents. However, when reading the status register insynchronous burst mode, CE# or ADV# must be toggled to update status data.The device write status bit (SR7) provides the overall status of the device. SR[6:1]present status and error information about the PROGRAM, ERASE, SUSPEND, V PP, andBLOCK LOCK operations.Note: Reading the status register is a nonarray READ operation. When the operation oc-curs in asynchronous page mode, only the first data is valid and all subsequent data areundefined. When the operation occurs in synchronous burst mode, the same data wordrequested will be output on successive clock edges until the burst length requirementsare satisfied.Table 16: Status Register DescriptionNotes: 1.Default value = 0x80.2.Always clear the status register prior to resuming ERASE operations. This eliminates sta-tus register ambiguity when issuing commands during ERASE SUSPEND. If a commandLatency CountThe latency count (LC) bits tell the device how many clock cycles must elapse from therising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until thefirst valid data word is driven to DQ[15:0]. The input clock frequency is used to deter-mine this value. The First Access Latency Count figure shows the data output latency fordifferent LC settings.Figure 13: First Access Latency CountCLK [C]Address [A]ADV# [V]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]Note: 1.First Access Latency Count Calculation:•1 / CLK frequency = CLK period (ns)•n x (CLK period) ≥t AVQV (ns) – t CHQV (ns)•Latency Count = nFigure 14: Example Latency Count Setting Using Code 3CLKCE#ADV#A[MAX:1]D[15:0]End of Wordline ConsiderationsEnd of wordline (EOWL) wait states can result when the starting address of the burst op-eration is not aligned to a 16-word boundary; that is, A[4:1] of the start address does not equal 0x0. The figure below illustrates the end of wordline wait state(s) that occur after the first 16-word boundary is reached. The number of data words and wait states is summarized in the table below.Figure 15: End of Wordline Timing DiagramCLK ADV#OE#WAIT#A[MAX:1]DQ[15:0]Figure 18: Buffer Program ProcedureNotes: 1.Word count values on DQ0:DQ15 are loaded into the count register. Count ranges forthis device are N = 0000h to 01FFh.2.Device outputs the status register when read.3.Write buffer contents will be programmed at the device start or destination address.4.Align the start address on a write buffer boundary for maximum programming perform-ance; that is, A[9:1] of the start address = 0).5.Device aborts the BUFFERED PROGRAM command if the current address is outside theoriginal block address.6.Status register indicates an improper command sequence if the BUFFERED PROGRAMcommand is aborted. Follow this with a CLEAR STATUS REGISTER command.7.Device defaults to SR output data after BUFFERED PROGRAMMING SETUP command(E8h) is issued . CE# or OE# must be toggled to update the status register . Don’t issuethe READ SR command (70h); it is interpreted by the device as buffer word count.8.Full status check can be done after erase and write sequences complete. Write FFh afterthe last operation to reset the device to read array mode.Figure 19: Buffered Enhanced Factory Programming (BEFP) Procedure。