CD40193BDMS中文资料

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3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20V
1
+25oC
-
100 nA
2
+125oC
- 1000 nA
VDD = 18V3Fra bibliotek-55oC
-
100 nA
Output Voltage
VOL15 VDD = 15V, No Load
The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down one count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high.
1
+25oC
-
10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
-
10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20V
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
θjc 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A SUBGROUPS TEMPERATURE
LIMITS MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
元器件交易网
December 1992
CD40192BMS CD40193BMS
CMOS Presettable Up/Down Counters (Dual Clock With Reset)
Features
Description
• CD40192BMS - BCD Type • CD40193BMS - Binary Type • High Voltage Type (20V Rating) • Individual Clock Lines for Counting Up or Counting
The CARRY and BORROW signals are high when the counter is counting up or down. The CARRY signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW signal goes low one-half clock cycle after the counter reaches its minimum count in the countdown mode. Cascading of multiple packages is easily accomplished without the need for additional external circuitry by tying the BORROW and CARRY outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding counter package.
Functional Diagram
PRESET ENABLE
15 J1
1 J2
10 J3
9 J4
5 CLOCK UP
4 CLOCK DOWN
RESET
11 3 2 6 7 13 12
Q1 Q2 Q3 Q4 BORROW CARRY
14
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Pinout
CD40192BMS, CD40193BMS TOP VIEW
J2 1 Q2 2 Q1 3 CLOCK DOWN 4 CLOCK UP 5 Q3 6 Q4 7 VSS 8
16 VDD 15 J1 14 RESET 13 BORROW 12 CARRY 11 PRESET ENABLE 10 J3 9 J4
The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET ENABLE control is low.
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Down • Synchronous High-Speed Carry and Borrow Propaga-
tion Delays for Cascading • Asynchronous Reset and Preset Capability • Medium Speed Operation
- fCL = 8MHz (typ.) at 10V • 5V, 10V and 15V Parametric Ratings • Standardize Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
7-1419
File Number 3363
元器件交易网
Specifications CD40192BMS, CD40193BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals)