CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.CD4048BMSCMOS Multifunction Expandable 8 Input GatePinoutCD4048BMS TOP VIEWFunctional Diagram14151691312111012345768J (OUTPUT)Kd H G F E VSS Kb VDD A B C D Ka KcEXPAND INPUTSINPUTSBINARY CONTROL INPUTS FUNCTION CONTROL 3 STATE 14131211156543CONTROL10792Ka Kb Kc Kd A B C DEXPANDE F G HIJ OUTPUTVSS = 8VDD = 16INPUTSINPUTSFeatures•High-Voltage Type (20V Rating)•Three State Output•Many Logic Functions Available in One Package •Standardize, Symmetrical Output Characteristics •100% Tested for Quiescent Current at 20V•Maximum Input Current of 1µA at 18V Over Full Pack-age Temperature Range; 100nA at 18V and +25o C •Noise Margin (Over Full Package Temperature Range):-1V at VDD = 5V -2V at VDD = 10V - 2.5V at VDD = 15V •5V, 10V and 15V Parametric Ratings•Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”Applications•Selection of Up to 8 Logic Functions •Digital Control of Logic •General Purpose Gating Logic -Decoding -EncodingDescriptionCD4048BMS is an 8-input gate having four control inputs. Three binary control inputs - Ka, Kb, and Kc - provide the implementa-tion of eight different logic functions. These functions are OR,NOR, AND, NAND, OR/AND, OR/NAND, AND/OR and AND/NOR.A fourth control input, Kd, provides the user with a 3-state output.When control input Kd is high, the output is either a logic 1 or a logic 0 depending on the inner states. When control input Kd is low, the output is an open circuit. This feature enables the user to connect this device to a common bus line.In addition to the eight input lines, an EXPAND input is provided that permits the user to increase the number of inputs into a CD4048BMS (see Figure 2). For example, two CD4048BMS’s can be cascaded to provided a 16-input multifunction gate. When the EXPAND input is not used, it should be connected to VSS.The CD4048BMS is supplied in these 16 lead outline packages:Braze Seal DIP H4S Frit Seal DIP H1E Ceramic FlatpackH6WDecember 1992File Number3314Absolute Maximum Ratings Reliability InformationDC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . .-0.5V to +20V (Voltage Referenced to VSS Terminals)Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range. . . . . . . . . . . . . . . .-55o C to +125o C Package Types D, F, K, HStorage Temperature Range (TSTG). . . . . . . . . . .-65o C to +150o C Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . .+265o C At Distance 1/16 ± 1/32 Inch (1.59mm± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . .θjaθjc Ceramic DIP and FRIT Package. . . . .80o C/W20o C/W Flatpack Package . . . . . . . . . . . . . . . .70o C/W20o C/W Maximum Package Power Dissipation (PD) at +125o CFor TA = -55o C to +100o C (Package Type D, F, K). . . . . .500mW For TA = +100o C to +125o C (Package Type D, F, K) . . . . .DerateLinearity at 12mW/o C to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . .100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175o CTABLE1.DC ELECTRICAL PERFORMANCE CHARACTERISTICSPARAMETER SYMBOL CONDITIONS(NOTE 1)GROUP ASUBGROUPS TEMPERATURELIMITSUNITSMIN MAXSupply Current IDD VDD = 20V, VIN = VDD or GND1+25o C-0.5µA2+125o C-50µAVDD = 18V, VIN = VDD or GND3-55o C-0.5µA Input Leakage Current IIL VIN = VDD or GND VDD = 201+25o C-100-nA2+125o C-1000-nAVDD = 18V3-55o C-100-nA Input Leakage Current IIH VIN = VDD or GND VDD = 201+25o C-100nA2+125o C-1000nAVDD = 18V3-55o C-100nA Output Voltage VOL15VDD = 15V, No Load1, 2, 3+25o C, +125o C, -55o C-50mV Output Voltage VOH15VDD = 15V, No Load (Note 3)1, 2, 3+25o C, +125o C, -55o C14.95-V Output Current (Sink)IOL5VDD = 5V, VOUT = 0.4V1+25o C0.53-mA Output Current (Sink)IOL10VDD = 10V, VOUT = 0.5V1+25o C 1.4-mA Output Current (Sink)IOL15VDD = 15V, VOUT = 1.5V1+25o C 3.5-mA Output Current (Source)IOH5A VDD = 5V, VOUT = 4.6V1+25o C--0.53mA Output Current (Source)IOH5B VDD = 5V, VOUT = 2.5V1+25o C--1.8mA Output Current (Source)IOH10VDD = 10V, VOUT = 9.5V1+25o C--1.4mA Output Current (Source)IOH15VDD = 15V, VOUT = 13.5V1+25o C--3.5mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA1+25o C-2.8-0.7V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA1+25o C0.7 2.8VFunctional F VDD = 2.8V, VIN = VDD or GND7+25o C VOH >VDD/2VOL <VDD/2VVDD = 20V, VIN = VDD or GND7+25o CVDD = 18V, VIN = VDD or GND8A+125o CVDD = 3V, VIN = VDD or GND8B-55o CInput Voltage Low(Note 2)VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V1, 2, 3+25o C, +125o C, -55o C- 1.5VInput Voltage High(Note 2)VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V1, 2, 3+25o C, +125o C, -55o C 3.5-VInput Voltage Low (Note 2)VIL VDD = 15V, VOH > 13.5V,VOL < 1.5V1, 2, 3+25o C, +125o C, -55o C-4VInput Voltage High (Note 2)VIH VDD = 15V, VOH > 13.5V,VOL < 1.5V1, 2, 3+25o C, +125o C, -55o C11-VTri-State Output Leakage IOZL VIN = VDD or GNDVOUT = 0VVDD = 20V1+25o C-0.4-µA2+125o C-12-µAVDD = 18V3 -55o C-0.4-µATri-State Output Leakage IOZH VIN = VDD or GNDVOUT = VDDVDD = 20V1+25o C-0.4µA2+125o C-12µAVDD = 18V3 -55o C-0.4µANOTES: 1.All voltages referenced to device GND, 100% testing being implemented.2.Go/No Go test with limits applied to inputs.3.For accuracy, voltage is measured differentially to VDD. Limitis 0.050V max.TABLE2.AC ELECTRICAL PERFORMANCE CHARACTERISTICSPARAMETER SYMBOL CONDITIONS(NOTE 1, 2)GROUP ASUBGROUPS TEMPERATURELIMITSUNITSMIN MAXPropagation Delay Ka to Output TPHLTPLHVDD = 5V, VIN = VDD or GND9+25o C-600ns10, 11+125o C, -55o C-810nsTransition Time TTHLTTLH VDD = 5V, VIN = VDD or GND9+25o C-200ns10, 11+125o C, -55o C-270nsNOTES:1.CL = 50pF, RL = 200K, Input TR, TF < 20ns.2.-55o C and +125o C limits guaranteed, 100% testing being implemented.TABLE3.ELECTRICAL PERFORMANCE CHARACTERISTICSPARAMETER SYMBOL CONDITIONS NOTES TEMPERATURELIMITSUNITS MIN MAXSupply Current IDD VDD = 5V, VIN = VDD or GND1, 2-55o C, +25o C-0.25µA+125o C-7.5µAVDD = 10V, VIN = VDD or GND1, 2-55o C, +25o C-0.5µA+125o C-15µAVDD = 15V, VIN = VDD or GND1, 2-55o C, +25o C-0.5µA+125o C-30µA Output Voltage VOL VDD = 5V, No Load1, 2+25o C, +125o C,-55o C-50mVOutput Voltage VOL VDD = 10V, No Load1, 2+25o C, +125o C,-55o C-50mVOutput Voltage VOH VDD = 5V, No Load1, 2+25o C, +125o C,-55o C4.95-VOutput Voltage VOH VDD = 10V, No Load1, 2+25o C, +125o C,-55o C9.95-V Output Current (Sink)IOL5VDD = 5V, VOUT = 0.4V1, 2+125o C0.36-mA-55o C0.64-mA Output Current (Sink)IOL10VDD = 10V, VOUT = 0.5V1, 2+125o C0.9-mA-55o C 1.6-mA Output Current (Sink)IOL15VDD = 15V, VOUT = 1.5V1, 2+125o C 2.4-mA-55o C 4.2-mA Output Current (Source)IOH5A VDD = 5V, VOUT = 4.6V1, 2+125o C--0.36mA-55o C--0.64mA Output Current (Source)IOH5B VDD = 5V, VOUT = 2.5V1, 2+125o C--1.15mA-55o C--2.0mA Output Current (Source)IOH10VDD = 10V, VOUT = 9.5V1, 2+125o C--0.9mA-55o C--1.6mA Output Current (Source)IOH15VDD =15V, VOUT = 13.5V1, 2+125o C--2.4mA-55o C--4.2mAInput Voltage Low VIL VDD = 10V, VOH > 9V, VOL <1V 1, 2+25o C, +125o C,-55o C-3VInput Voltage High VIH VDD = 10V, VOH > 9V, VOL <1V 1, 2+25o C, +125o C,-55o C7-VPropagation Delay Ka to Output TPHL1TPLH1VDD = 10V1, 2, 3+25o C-300ns VDD = 15V1, 2, 3+25o C-240nsPropagation Delay Inputs to Output TPHL2TPLH2VDD = 5V1, 2, 3+25o C-600ns VDD = 10V1, 2, 3+25o C-300ns VDD = 15V1, 2, 3+25o C-240nsPropagation Delay Kb to Output TPHL3TPLH3VDD = 5V1, 2, 3+25o C-450ns VDD = 10V1, 2, 3+25o C-170ns VDD = 15V1, 2, 3+25o C-110nsPropagation Delay Kc to Output TPHL4TPLH4VDD = 5V1, 2, 3+25o C-280ns VDD = 10V1, 2, 3+25o C-100ns VDD = 15V1, 2, 3+25o C-80nsPropagation Delay Expand Input to Output TPHL5TPLH5VDD = 5V1, 2, 3+25o C-380ns VDD = 10V1, 2, 3+25o C-180ns VDD = 15V1, 2, 3+25o C-130nsPropagation Delay 3 StateKd to Output TPHZ, LZTPZH, ZLVDD = 5V1, 2, 4+25o C-160nsVDD = 10V1, 2, 4+25o C-70nsVDD = 15V1, 2, 4+25o C-50nsTransition Time TTLHTTHL VDD = 10V1, 2, 3+25o C-100ns VDD = 15V1, 2, 3+25o C-80nsInput Capacitance CIN Any Input1, 2+25o C-7pF3 State OutputCapacitanceCO1, 2+25o C-10pF NOTES:1.All voltages referenced to device GND.2.The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterizedon initial design release and upon design changes which would affect these characteristics.3.CL = 50pF, RL = 200K, Input TR, TF < 20ns.4.CL = 50pF, RL = 1K, Input TR, TF < 20ns.TABLE4.POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICSPARAMETER SYMBOL CONDITIONS NOTES TEMPERATURELIMITSUNITS MIN MAXSupply Current IDD VDD = 20V, VIN = VDD or GND1, 4+25o C-25µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA1, 4+25o C-2.8-0.2V N Threshold VoltageDelta∆VTN VDD = 10V, ISS = -10µA1, 4+25o C-±1V P Threshold Voltage VTP VSS = 0V, IDD = 10µA1, 4+25o C0.2 2.8V P Threshold VoltageDelta∆VTP VSS = 0V, IDD = 10µA1, 4+25o C-±1VFunctional F VDD = 18V, VIN = VDD or GND1+25o C VOH >VDD/2VOL <VDD/2VVDD = 3V, VIN = VDD or GNDPropagation Delay Time TPHLTPLH VDD = 5V1, 2, 3, 4+25o C- 1.35 x+25o CLimitnsNOTES: 1.All voltages referenced to device GND.2.CL = 50pF, RL = 200K, Input TR, TF < 20ns.3.See Table 2 for +25o C limit.4.Read and RecordTABLE3.ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURELIMITSUNITS MIN MAXTABLE5.BURN-IN AND LIFE TEST DELTA PARAMETERS +25O C PARAMETER SYMBOL DELTA LIMIT Supply Current - SSI IDD±0.1µAOutput Current (Sink)IOL5± 20% x Pre-Test Reading Output Current (Source)IOH5A± 20% x Pre-Test ReadingTABLE6.APPLICABLE SUBGROUPSCONFORMANCE GROUP MIL-STD-883METHOD GROUP A SUBGROUPS READ AND RECORDInitial Test (Pre Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A, RONDEL10 Interim Test 1 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A, RONDEL10 Interim Test 2 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A, RONDEL10 PDA (Note 1)100% 50041, 7, 9, DeltasInterim Test 3 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A, RONDEL10 PDA (Note 1)100% 50041, 7, 9, DeltasFinal Test100% 50042, 3, 8A, 8B, 10, 11Group A Sample 50051, 2, 3, 7, 8A, 8B, 9, 10, 11Group B Subgroup B-5Sample 50051, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11 Subgroup B-6Sample 50051, 7, 9Group D Sample 50051, 2, 3, 8A, 8B, 9Subgroups 1, 2 3NOTE:1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.TABLE7.TOTAL DOSE IRRADIATIONCONFORMANCE GROUPS MIL-STD-883METHODTEST READ AND RECORDPRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRADGroup E Subgroup 250051, 7, 9Table 41, 9Table 4TABLE8.BURN-IN AND IRRADIATION TEST CONNECTIONSFUNCTION OPEN GROUND VDD9V± -0.5VOSCILLATOR50kHz25kHzStatic Burn-In 1Note 11 2 - 1516Static Burn-In 2Note 118 2 - 7, 9 - 16Dynamic Burn-In Note 1-8, 152, 1619 - 14 3 - 7IrradiationNote 218 2 - 7, 9 - 16NOTE:1.Each pin except VDD and GND will have a series resistor of 10K± 5%, VDD = 18V± 0.5V2.Each pin except VDD and GND will have a series resistor of 47K±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,VDD = 10V± 0.5VLogic DiagramsFIGURE 1.BASIC LOGIC CONFIGURATIONSFIGURE 2.LOGIC DIAGRAMNORORNANDANDOR/ANDOR/NANDAND/ORAND/NORACEGB D F H ACEGB D F H ACEGB D F H ACEGB D F H A BCDEFG HA B C D E F G HA B C D E F G HA B C D E F G HEXPEXPEXPEXPEXPEXP EXP EXP 10141312111565437921KaA B C D EXP EFGH*********KbKbKcKa Kb Kc Kd ****Ka Kb Kc Kd Ka Kb KcKdKdJVDDVSSKdVDDVSS* ALL INPUTS ARE PROTECTEDBY CMOS PROTECTION NETWORKFIGURE 3.ACTUAL CIRCUIT LOGIC CONFIGURATIONSApplications of Expand InputFIGURE 4.12 INPUT OR/AND GATEFIGURE 5.16 INPUT NOR GATEIMPLEMETATION OF EXPAND INPUT FOR 9 OR MORE INPUTSOUTPUT FUNCTION FUNCTION NEEDED AT EXPAND INPUTOUTPUT BOOLEAN EXPRESSION NOR OR J=(A+B+C+D+E+F+G+H)+(EXP)OR OR J=(A+B+C+D+E+F+G+H)+(EXP)AND NAND J=(ABCDEFGH)•(EXP)NAND NAND J=(ABCDEFGH)•(EXP)OR/AND NOR J=(A+B+C+D)•(E+F+G+H)•(EXP)OR/NAND NOR J=(A+B+C+D)•(E+F+G+H)•(EXP)AND/NOR AND J=(ABCD)+(EFGH)+(EXP)AND/ORANDJ=(ABCD)+(EFGH)+(EXP)NOTES: 1.(EXP) designates the EXPAND function (i.e., X1 + X2 + . . .XN).2.Refer to FUNCTION TRUTH TABLE for connection of unused inputs.Logic Diagrams(Continued)11121314345615Ka - Kb - Kc 0 - 0 - 0NORNAND1 - 0 - 11 - 0 - 01 - 1 - 00 - 1 - 10 - 0 - 10 - 1 - 01 - 1 - 1ANDAND/NOROR/NANDORAND/OROR/AND14151691312111012345768J (OUTPUT)Kd H G F E VSSKbVDDA B C D Ka Kc VSSX1X2X3X4VDD1/2 CD4002AVDD 12 - INPUT OR/AND GATEJ = (A+B+C+D)(E+F+G+H)(X1+X2+X3+X4)..14151691312111012345768OUTPUT KdH1G1F1E1VSSKbVDDA1B1C1D1Ka KcVDDVSSVSS VDD14151691312111012345768J(OUTPUT)KdH2G2F2E2VSSKbVDD A2B2C2D2Ka KcVSSEXPVDDOR FUNCTION16 - INPUT NOR GATEJ = A1 +B1 +C1 +D1 +E1 +F1 +G1 +H1 +A2 +B2 +C2 +D2 +E2 +F2 +G2 +H2FUNCTION TRUTH TABLEOUTPUT FUNCTION BOOLEAN EXPRESSION Ka Kb Kc UNUSED INPUT*NOR J=A+B+C+D+E+F+G+H 000VSS OR J=A+B+C+D+E+F+G+H 001VSS OR/AND J=(A+B+C+D)•(E+F+G+H)010VSS OR/NAND J=(A+B+C+D)•(E+F+G+H)011VSS AND J=ABCDEFGH 100VDD NAND J=ABCDEFGH 101VDD AND/NOR J=ABCD+EFGH 110VDD AND/ORJ=ABCD+EFGH111VDDKd = 1Normal Inverter Action Kd = 0High Impedance Output EXPAND Input = 0*See Figures 1, 2, 3, 4 and 5Typical Performance CharacteristicsFIGURE 6.TYPICAL OUTPUT LOW (SINK) CURRENTCHARACTERISTICS FIGURE 7.MINIMUM OUTPUT LOW (SINK) CURRENTCHARACTERISTICS10V5VAMBIENT TEMPERATURE (T A ) = +25o CGATE-TO-SOURCE VOLTAGE (VGS) = 15V51015151********DRAIN-TO-SOURCE VOLTAGE (VDS) (V)O U T P U T L O W (S I N K ) C U R R E N T (I O L ) (m A )10V5VAMBIENT TEMPERATURE (T A ) = +25o CGATE-TO-SOURCE VOLTAGE (VGS) = 15V510157.55.02.510.012.515.0DRAIN-TO-SOURCE VOLTAGE (VDS) (V)O U T P U T L O W (S I N K ) C U R R E N T (I O L ) (m A )FIGURE 8.TYPICAL OUTPUT HIGH (SOURCE) CURRENTCHARACTERISTICSFIGURE 9.MINIMUM OUTPUT HIGH (SOURCE) CURRENTCHARACTERISTICSFIGURE 10.TYPICAL PROPAGATION DELAY TIME (LOGICINPUTS TO OUTPUT) AS A FUNCTION OF LOAD CAPACITANCEFIGURE 11.TYPICAL TRANSITION TIME vs LOADCAPACITANCEFIGURE 12.TYPICAL POWER DISSIPATION AS AFUNCTION OF INPUT FREQUENCYTypical Performance Characteristics(Continued)-10V-15VAMBIENT TEMPERATURE (T A ) = +25o CGATE-TO-SOURCE VOLTAGE (VGS) = -5V0-5-10-15DRAIN-TO-SOURCE VOLTAGE (VDS) (V)-20-25-30-5-10-15O U T P U T H I G H (S O U R C E ) C U R R E N T (I O H ) (m A )-10V-15VAMBIENT TEMPERATURE (T A ) = +25o C-5-10-15DRAIN-TO-SOURCE VOLTAGE (VDS) (V)-5-10-15O U T P U T H I G H (S O U R C E ) C U R R E N T (I O H ) (m A )GATE-TO-SOURCE VOLTAGE (VGS) = -5VLOAD CAPACITANCE (CL) (pF)0P R O P A G A T I O N D E L A Y T I M E (t P H L , t P L H ) (n s )SUPPL Y VOLTAGE (VDD) = 5V10V15V20406080100100200300AMBIENT TEMPERATURE (T A ) = +25o CAMBIENT TEMPERATURE (T A ) = +25o CLOAD CAPACITANCE (CL) (pF)40608010020050100150200SUPPL Y VOLTAGE (VDD) = 5V10V15VT R A N S I T I O N T I M E (f T H L , f T L H ) (n s )10V 15VINPUT FREQUENCY (fI) (kHz)110102103104AMBIENT TEMPERATURE (T A ) = +25o C LOAD CAPACITANCE (CL) = 50pF D Y N A M I C P O W E R D I S S I P A T I O N (P D ) (µW )103102108642864286421048642105SUPPL Y VOLTAGE (VDD) = 5V86428642864286428642105Test Circuits and Wave FormsFIGURE 13.DYNAMIC POWER DISSIPATION TEST CIRCUITFIGURE 14.TEST CIRCUIT FOR tPHL, tTHL, AND tTHL (AND)MEASUREMENTSFIGURE 15.TEST CIRCUIT FOR tPZL, tPZH, tPLZ, AND tPHZ(AND)FIGURE 16.WAVEFORMS FOR tPZL, tPZH, tPLZ AND tPHZ(AND)FIGURE 17.WAVEFORMS FOR tPHL AND tPHL (AND)FIGURE 18.WAVEFORMS FOR tTHL AND tTLH (AND)12345768141516913121110CLHPULSE GENERATORVDD500µF0.1µF12345768141516913121110CL = 15pF VDDOUTPUT OR 50pFINPUTVDD12345768141516913121110PULSE GENERATORKd(AND)50pFVDD (tPLZ)(tPZL)VSS (tPHZ)(tPZH)VDD VSStPHLOUTPUTOUTPUT50%90%10%Kd tPZLtPLZ90%tPZH10%INPUTOUTPUT50%50%tPHLOUTPUTtTHL10%90%INPUTtTLH50%All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.For information regarding Intersil Corporation and its products, see web site Sales Office HeadquartersNORTH AMERICAIntersil CorporationP. O. Box 883, Mail Stop 53-204 Melbourne, FL32902TEL:(321) 724-7000FAX: (321) 724-7240EUROPEIntersil SAMercure Center100, Rue de la Fusee1130 Brussels, BelgiumTEL: (32) 2.724.2111FAX: (32) 2.724.22.05ASIAIntersil (Taiwan) Ltd.Taiwan Limited7F-6, No. 101 Fu Hsing North RoadTaipei, TaiwanRepublic of ChinaTEL: (886) 2 2716 9310FAX: (886) 2 2715 3029CD4048BMSChip Dimensions and Pad LayoutDimensions in parentheses are in millimetersand are derived from the basic inch dimensionsas indicated. Grid graduations are in mils (10-3 inch)METALLIZATION:Thickness: 11kÅ−14kÅ, AL.PASSIVATION:10.4kÅ - 15.6kÅ, SilaneBOND PADS:0.004 inches X 0.004 inches MINDIE THICKNESS:0.0198 inches - 0.0218 inches 元器件交易网922。