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DAC101S101中文资料

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DAC101S10110-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail OutputGeneral DescriptionThe DAC101S101is a full-featured,general purpose 10-bit voltage-output digital-to-analog converter (DAC)that can operate from a single +2.7V to 5.5V supply and consumes just 175µA of current at 3.6Volts.The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 30MHz over the specified supply voltage range and is compatible with stan-dard SPI ™,QSPI,MICROWIRE and DSP -petitive devices are limited to 20MHz clock rates at supply voltages in the 2.7V to 3.6V range.The supply voltage for the DAC101S101serves as its volt-age reference,providing the widest possible output dynamic range.A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device.A power-down feature reduces power consumption to less than a microWatt.The low power consumption and small packages of the DAC101S101make it an excellent choice for use in battery operated equipment.The DAC101S101is a direct replacement for the AD5310and is one of a family of pin compatible DACs,including the 8-bit DAC081S101and the 12-bit DAC121S101.The DAC101S101operates over the extended industrial tem-perature range of −40˚C to +105˚C.Featuresn Guaranteed Monotonicity n Low Power Operationn Rail-to-Rail Voltage Outputn Power-on Reset to Zero Volts Output n SYNC Interrupt Facilityn Wide power supply range (+2.7V to +5.5V)n Small PackagesnPower Down FeatureKey Specificationsn Resolution 10bits n DNL +0.15,-0.05LSB (typ)n Output Settling Time 8µs (typ)n Zero Code Error 3.3mV (typ)n Full-Scale Error −0.06%FS (typ)nPower Consumption—Normal Mode 0.63mW (3.6V)/1.41mW (5.5V)typ —Pwr Down Mode 0.14µW (3.6V)/0.33µW (5.5V)typApplicationsn Battery-Powered Instrumentsn Digital Gain and Offset Adjustmentn Programmable Voltage &Current Sources nProgrammable AttenuatorsPin Configuration2015410120154102Ordering InformationOrder Numbers Temperature Range Package Top Mark DAC101S101CIMM −40˚C ≤T A ≤+105˚C MSOPX62C DAC101S101CIMMX −40˚C ≤T A ≤+105˚C MSOP Tape-and-ReelX62C DAC101S101CIMK −40˚C ≤T A ≤+105˚C TSOTX63C DAC101S101CIMKX −40˚C ≤T A ≤+105˚CTSOT Tape-and-Reel X63CDAC101S101EVALEvaluation BoardSPI ™is a trademark of Motorola,Inc.June 2005DAC101S10110-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output©2005National Semiconductor Corporation Block Diagram20154103Pin DescriptionsTSOT (SOT-23)Pin No.MSOP Pin No.Symbol Description14V OUT DAC Analog Output Voltage.28GND Ground reference for all on-chip circuitry.31V APower supply and Reference input.Should be decoupled to GND.47D INSerial Data Input.Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.56SCLKSerial Clock Input.Data is clocked into the input shift register on the falling edges of this pin.65SYNCFrame synchronization input for the data input.When this pin goes low,it enables the input shift register and data is transferred on the falling edges of SCLK.The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock,in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.2,3NCNo Connect.There is no internal connection to these pins.D A C 101S 101 2Absolute Maximum Ratings(Notes1,2)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage,V A 6.5V Voltage on any Input Pin−0.3V to(V A+0.3V) Input Current at Any Pin(Note3)10mA Package Input Current(Note3)20mA Power Consumption at T A=25˚C See(Note4) ESD Susceptibility(Note5)Human Body Model Machine Model 2500V 250VSoldering Temperature,Infrared,10Seconds(Note6)235˚CStorage Temperature−65˚C to+150˚COperating Ratings(Notes1,2)Operating Temperature Range−40˚C≤T A≤+105˚C Supply Voltage,V A+2.7V to5.5V Any Input Voltage(Note7)−0.1V to(V A+0.1V) Output Load0to1500pF SCLK Frequency Up to30MHzPackage Thermal ResistancesPackageθJA8-Lead MSOP240˚C/W6-Lead TSOT250˚C/WElectrical CharacteristicsValues shown in this table are design targets and are subject to change before product release.The following specifica-tions apply for V A=+2.7V to+5.5V,R L=2kΩto GND,C L=200pF to GND,f SCLK=30MHz,input code range12to1011. Boldface limits apply for T MIN≤T A≤T MAX:all other limits T A=25˚C,unless otherwise specified.Symbol Parameter Conditions Typical(Note9)Limits(Note9)Units(Limits)STATIC PERFORMANCEResolution10Bits(min)Monotonicity10Bits(min) INL Integral Non-Linearity Over Decimal codes12to1011±0.6±2.8LSB(max)DNL Differential Non-Linearity V A=2.7V to5.5V+0.15+0.35LSB(max)−0.05−0.2LSB(min)ZE Zero Code Error I OUT=0+3.3+15mV(max)FSE Full-Scale Error I OUT=0−0.06−1.0%FSR (max)GE Gain Error All ones Loaded to DAC register−0.10±1.0%FSR (max)ZCED Zero Code Error Drift−20µV/˚CTC GE Gain Error Tempco V A=3V−0.7ppm/˚C V A=5V−1.0ppm/˚COUTPUT CHARACTERISTICSOutput Voltage Range(Note10)V AV(min)V(max)ZCO Zero Code Output V A=3V,I OUT=10µA 1.8mV V A=3V,I OUT=100µA 5.0mV V A=5V,I OUT=10µA 3.7mV V A=5V,I OUT=100µA 5.4mVFSO Full Scale Output V A=3V,I OUT=10µA 2.997V V A=3V,I OUT=100µA 2.990V V A=5V,I OUT=10µA 4.995V V A=5V,I OUT=100µA 4.992VMaximum Load Capacitance R L=∞1500pF R L=2kΩ1500pFDC Output Impedance 1.3OhmDAC101S1013Electrical Characteristics(Continued)Values shown in this table are design targets and are subject to change before product release.The following specifica-tions apply for V A =+2.7V to +5.5V,R L =2k Ωto GND,C L =200pF to GND,f SCLK =30MHz,input code range 12to 1011.Boldface limits apply for T MIN ≤T A ≤T MAX :all other limits T A =25˚C,unless otherwise specified.SymbolParameterConditionsTypical (Note 9)Limits (Note 9)Units (Limits)I OSOutput Short Circuit CurrentV A =5V,V OUT =0V,Input code =3FFh −63mA V A =3V,V OUT =0V,Input code =3FFh −50mA V A =5V,V OUT =5V,Input code =000h 74mA V A =3V,V OUT =3V,Input code =000h53mALOGIC INPUTI IN Input Current (Note 10)±1µA (max)V IL Input Low Voltage (Note 10)V A =5V 0.8V (max)V A =3V 0.5V (max)V IH Input High Voltage (Note 10)V A =5V 2.4V (min)V A =3V2.1V (min)C INInput Capacitance (Note 10)3pF (max)POWER REQUIREMENTSI ASupply Current (output unloaded)Normal Mode f SCLK =30MHz V A =5.5V 256332µA (max)V A =3.6V 174226µA (max)Normal Mode f SCLK =20MHzV A =5.5V 221297µA (max)V A =3.6V 154207µA (max)Normal Mode f SCLK =0V A =5.5V 145µA (max)V A =3.6V 113µA (max)All PD Modes,f SCLK =30MHz V A =5.0V 83µA (max)V A =3.0V 42µA (max)All PD Modes,f SCLK =20MHz V A =5.0V 56µA (max)V A =3.0V 28µA (max)All PD Modes,f SCLK =0(Note 10)V A =5.5V 0.06 1.0µA (max)V A =3.6V 0.04 1.0µA (max)P CPower Consumption (output unloaded)Normal Mode f SCLK =30MHz V A =5.5V 1.41 1.83mW (max)V A =3.6V 0.630.81mW (max)Normal Mode f SCLK =20MHzV A =5.5V 1.22 1.63mW (max)V A =3.6V 0.550.74mW (max)Normal Mode f SCLK =0V A =5.5V 0.80µW (max)V A =3.6V 0.41µW (max)All PD Modes,f SCLK =30MHz V A =5.0V 0.42µW (max)V A =3.0V 0.13µW (max)All PD Modes,f SCLK =20MHz V A =5.0V 0.28µW (max)V A =3.0V 0.08µW (max)All PD Modes,f SCLK =0(Note 10)V A =5.5V 0.33 5.5µW (max)V A =3.6V 0.14 3.6µW (max)I OUT /I APower EfficiencyI LOAD =2mAV A =5V 91%V A =3V94%D A C 101S 101 4A.C.and Timing CharacteristicsValues shown in this table are design targets and are subject to change before product release.The following specifica-tions apply for V A=+2.7V to+5.5V,R L=2kΩto GND,C L=200pF to GND,f SCLK=30MHz,input code range12to1011. Boldface limits apply for T MIN≤T A≤T MAX:all other limits T A=25˚C,unless otherwise specified.Symbol Parameter Conductions Typical LimitsUnits (Limits)f SCLK SCLK Frequency30MHz(max)t s Output Voltage Settling Time(Note10)100h to300h codechange,R L=2kΩC L≤200pF57.5µs(max)SR Output Slew Rate1V/µs Glitch Impulse Code change from200h to1FFh12nV-sec Digital Feedthrough0.5nV-sect WU Wake-Up Time V A=5V 1.6µs V A=3V 1.9µs1/f SCLK SCLK Cycle Time33ns(min) t H SCLK High time513ns(min) t L SCLK Low Time513ns(min)t SUCL Set-up Time SYNC to SCLK RisingEdge−150ns(min)t SUD Data Set-Up Time 2.55ns(min) t DHD Data Hold Time 2.5 4.5ns(min)t CS SCLK fall to rise of SYNC V A=5V03ns(min) V A=3V−21ns(min)t SYNC SYNC High Time 2.7≤V A≤3.6920ns(min)3.6≤V A≤5.5510ns(min)Note1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the listed test conditions.Note2:All voltages are measured with respect to GND=0V,unless otherwise specifiedNote3:When the input voltage at any pin exceeds the power supplies(that is,less than GND,or greater than V A),the current at that pin should be limited to10mA.The20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of10mA to two.Note4:The absolute maximum junction temperature(T J max)for this device is150˚C.The maximum allowable power dissipation is dictated by T J max,thejunction-to-ambient thermal resistance(θJA),and the ambient temperature(T A),and can be calculated using the formula P D MAX=(T J max−T A)/θJA.The valuesfor maximum power dissipation will be reached only when the device is operated in a severe fault condition(e.g.,when input or output pins are driven beyond thepower supply voltages,or the power supply polarity is reversed).Obviously,such conditions should always be avoided.Note5:Human body model is100pF capacitor discharged through a1.5kΩresistor.Machine model is220pF discharged through ZERO Ohms.Note6:See the section entitled"Surface Mount"found in any post1986National Semiconductor Linear Data Book for methods of soldering surface mount devices.Note7:The analog inputs are protected as shown below.Input voltage magnitudes up to V A+300mV or to300mV below GND will not damage this device. However,errors in the conversion result can occur if any input goes above V A or below GND by more than100mV.For example,if V A is2.7V DC,ensure that−100mV≤input voltages≤2.8V DC to ensure accurate conversions.20154104Note8:To guarantee accuracy,it is required that V A be well bypassed.Note9:Typical figures are at T J=25˚C,and represent most likely parametric norms.Test limits are guaranteed to National’s AOQL(Average Outgoing Quality Level).Note10:This parameter is guaranteed by design and/or characterization and is not tested in production.DAC101S1015Specification DefinitionsDIFFERENTIAL NON-LINEARITY (DNL)is the measure of the maximum deviation from the ideal step size of 1LSB,which is V REF /1024=V A /1024.DIGITAL FEEDTHROUGH is a measure of the energy in-jected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated.It is mea-sured with a full-scale code change on the data bus.FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (3FFh)loaded into the DAC and the value of V A x 1023/1024.GAIN ERROR is the deviation from the ideal slope of the transfer function.It can be calculated from Zero and Full-Scale Errors as GE =FSE -ZE,where GE is Gain error,FSE is Full-Scale Error and ZE is Zero Error.GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes.It is specified as the area of the glitch in nanovolt-seconds.INTEGRAL NON-LINEARITY (INL)is a measure of the deviation of each individual code from a straight line through the input to output transfer function.The deviation of any given code from this straight line is measured from the center of that code value.The end point method is used.INL for this product is specified over a limited range,per the Electrical Tables.LEAST SIGNIFICANT BIT (LSB)is the bit that has the smallest value or weight of all bits in a word.This value isLSB =V REF /2nwhere V REF is the supply voltage for this product,and "n"is the DAC resolution in bits,which is 10for the DAC101S101.MAXIMUM LOAD CAPACITANCE is the maximum capaci-tance that can be driven by the DAC with output stability maintained.MONOTONICITY is the condition of being monotonic,where the DAC has an output that never decreases when the input code increases.MOST SIGNIFICANT BIT (MSB)is the bit that has the largest value or weight of all bits in a word.Its value is 1/2of V A .POWER EFFICIENCY is the ratio of the output current to the total supply current.The output current comes from the power supply.The difference between the supply and output currents,is the power consumed by the device without a load.SETTLING TIME is the time for the output to settle within 1/2LSB of the final value after the input code is updated.WAKE-UP TIME is the time for the output to settle to within 1/2LSB of the final value after the device is commanded to the active mode from any of the power down modes.ZERO CODE ERROR is the output error,or voltage,present at the DAC output after a code of 000h has been entered.D A C 101S 101 6Transfer CharacteristicTiming Diagram20154105FIGURE1.Input/Output Transfer Characteristic20154106 FIGURE2.DAC101S101TimingDAC101S1017Typical Performance Characteristicsf SCLK =30MHz,T A =25C,Input Code Range 12to 1011,unless otherwise statedDNL at V A =3.0VDNL at V A =5.0V2015415220154153INL at V A =3.0V INL at V A =5.0V2015415420154155TUE at V A =3.0V TUE at V A =5.0V2015415620154157D A C 101S 101 8Typical Performance Characteristics f SCLK =30MHz,T A =25C,Input Code Range 12to 1011,unless otherwise stated (Continued)DNL vs.V AINL vs.V A20154122201541233V DNL vs.f SCLK 5V DNL vs.f SCLK20154150201541513V DNL vs.Clock Duty Cycle 5V DNL vs.Clock Duty Cycle2015412420154125DAC101S1019Typical Performance Characteristics f SCLK =30MHz,T A =25C,Input Code Range 12to 1011,unless otherwise stated (Continued)3V DNL vs.Temperature5V DNL vs.Temperature20154126201541273V INL vs.f SCLK 5V INL vs.f SCLK20154128201541293V INL vs.Clock Duty Cycle 5V INL vs.Clock Duty Cycle2015413020154131D A C 101S 101 10Typical Performance Characteristics f SCLK =30MHz,T A =25C,Input Code Range 12to 1011,unless otherwise stated (Continued)3V INL vs.Temperature5V INL vs.Temperature2015413220154133Zero Code Error vs.f SCLKZero Code Error vs.Clock Duty Cycle2015413420154135Zero Code Error vs.TemperatureFull-Scale Error vs.f SCLK2015413620154137DAC101S10111Typical Performance Characteristics f SCLK =30MHz,T A =25C,Input Code Range 12to 1011,unless otherwise stated (Continued)Full-Scale Error vs.Clock Duty CycleFull-Scale Error vs.Temperature2015413820154139Supply Current vs.V ASupply Current vs.Temperature20154144201541455V Glitch Response Power-On Reset2015414620154147D A C 101S 101 12Typical Performance Characteristics f SCLK =30MHz,T A =25C,Input Code Range 12to 1011,unless otherwise stated (Continued)3V Wake-Up Time5V Wake-Up Time2015414820154149DAC101S101131.0Functional Description1.1DAC SECTIONThe DAC101S101is fabricated on a CMOS process with an architecture that consists of switches and a resistor string that are followed by an output buffer.The power supply serves as the reference voltage.The input coding is straight binary with an ideal output voltage of:V OUT =V A x (D /1024)where D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value between 0and 1023.1.2RESISTOR STRINGThe resistor string is shown in Figure 3.This string consists of 4096equal valued resistors with a switch at each junction of two resistors,plus a switch to ground.The code loaded into the DAC register determines which switch is closed,connecting the proper node to the amplifier.This configura-tion guarantees that the DAC is monotonic.1.3OUTPUT AMPLIFIERThe output buffer amplifier is a rail-to-rail type,providing an output voltage range of 0V to V A .All amplifiers,even rail-to-rail types,exhibit a loss of linearity as the output approaches the supply rails (0V and V A ,in this case).For this reason,linearity is specified over less than the full output range of the DAC.The output capabilities of the amplifier are described in the Electrical Tables.1.4SERIAL INTERFACEThe three-wire interface is compatible with SPI,QSPI and MICROWIRE as well as most DSPs.See the Timing Dia-gram for information on a write sequence.A write sequence begins by bringing the SYNC line low.Once SYNC is low,the data on the D IN line is clocked into the 16-bit serial input register on the falling edges of SCLK.On the 16th falling clock edge,the last data bit is clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register contents)is executed.At this point the SYNC line may be kept low orbrought high.In either case,it must be brought high for the minimum specified time before the next write sequence as a falling edge of SYNC is used to initiate the next write cycle.Since the SYNC and D IN buffers draw more current when they are high,they should be idled low between write se-quences to minimize power consumption.1.5INPUT SHIFT REGISTERThe input shift register,Figure 4,has sixteen bits.The first two bits are "don’t cares"and are followed by two bits that determine the mode of operation (normal mode or one of three power-down modes).The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK.See Timing Diagram,Figure 2.Normally,the SYNC line is kept low for at least 16falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge.However,if SYNC is brought high before the 16th falling edge,the shift register is reset and the write sequence is invalid.The DAC register is not updated and there is no change in the mode of operation or in the output voltage.1.6POWER-ON RESETThe power-on reset circuit controls the output voltage during power-up.Upon application of power the DAC register is filled with zeros and the output voltage is 0Volts and remains there until a valid write sequence is made to the DAC.1.7POWER-DOWN MODESThe DAC101S101has four modes of operation.These modes are set with two bits (DB13and DB12)in the control register.TABLE 1.Modes of OperationDB13DB12Operating Mode 00Normal Operation01Power-Down with 1k Ωto GND 10Power-Down with 100k Ωto GND 11Power-Down with Hi-ZWhen both DB13and DB12are 0,the device operates normally.For the other three possible combinations of these bits the supply current drops to its power-down level and the output is pulled down with either a 1k Ωor a 100K Ωresistor,or is in a high impedance state,as described in Table 1.The bias generator,output amplifier,the resistor string and other linear circuitry are all shut down in any of the power-down modes.However,the contents of the DAC register are unaffected when in power-down,so when coming out of power down the output voltage returns to the same voltage it20154107FIGURE 3.DAC Resistor String20154108FIGURE 4.Input Register ContentsD A C 101S 101141.0Functional Description(Continued)was before entering power down.Minimum power consump-tion is achieved in the power-down mode with SCLK dis-abled and SYNC and D IN idled low.2.0Applications InformationThe simplicity of the DAC101S101implies ease of use.However,it is important to recognize that any data converter that utilizes its supply voltage as its reference voltage will have essentially zero PSRR (Power Supply Rejection Ratio).Therefore,it is necessary to provide a noise-free supply voltage to the device.2.1DSP/MICROPROCESSOR INTERFACINGInterfacing the DAC101S101to microprocessors and DSPs is quite simple.The following guidelines are offered to has-ten the design process.2.1.1ADSP-2101/ADSP2103InterfacingFigure 5shows a serial interface between the DAC101S101and the ADSP-2101/ADSP2103.The DSP should be set to operate in the SPORT Transmit Alternate Framing Mode.It is programmed through the SPORT control register and should be configured for Internal Clock Operation,Active Low Fram-ing and 16-bit Word Length.Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.2.1.280C51/80L51InterfaceA serial interface between the DAC101S101and the 80C51/80L51microcontroller is shown in Figure 6.The SYNC signal comes from a bit-programmable pin on the microcontroller.The example shown here uses port line P3.3.This line is taken low when data is to transmitted to the DAC101S101.Since the 80C51/80L51transmits 8-bit bytes,only eight falling clock edges occur in the transmit cycle.To load data into the DAC,the P3.3line must be left low after the first eight bits are transmitted.A second write cycle is initiated to transmit the second byte of data,after which port line P3.3is brought high.The 80C51/80L51transmit routine must rec-ognize that the 80C51/80L51transmits data with the LSB first while the DAC101S101requires data with the MSB first.2.1.368HC11InterfaceA serial interface between the DAC101S101and the 68HC11microcontroller is shown in Figure 7.The SYNC line of the DAC101S101is driven from a port line (PC7in the figure),similar to the 80C51/80L51.The 68HC11should be configured with its CPOL bit as a zero and its CPHA bit as a one.This configuration causes data on the MOSI output to be valid on the falling edge of SCLK.PC7is taken low to transmit data to the DAC.The 68HC11transmits data in 8-bit bytes with eight falling clock edges.Data is transmitted with the MSB first.PC7must remain low after the first eight bits are transferred.A second write cycle is initiated to transmit the second byte of data to the DAC,after which PC7should be raised to end the write sequence.2.1.4Microwire InterfaceFigure 8shows an interface between a Microwire compatible device and the DAC101S101.Data is clocked out on the rising edges of the SCLK signal.2.2USING REFERENCES AS POWER SUPPLIESRecall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage.Since the DAC101S101consumes very little power,a refer-ence source may be used as the supply voltage.The advan-tages of using a reference source over a voltage regulator are accuracy and stability.Some low noise regulators can also be used for the power supply of the DAC101S101.Listed below are a few power supply options for the DAC101S101.2.2.1LM4130The LM4130reference,with its 0.05%accuracy over tem-perature,is a good choice as a power source for the DAC101S101.Its primary disadvantage is the lack of 3V and 5V versions.However,the 4.096V version is useful if a 0to 4.095V output range is desirable or acceptable.Bypassing the LM4130VIN pin with a 0.1µF capacitor and the VOUT pin with a 2.2µF capacitor will improve stability and reduce output noise.The LM4130comes in a space-saving 5-pin SOT23.20154109FIGURE 5.ADSP-2101/2103Interface20154110FIGURE 6.80C51/80L51Interface20154111FIGURE 7.68HC11Interface20154112FIGURE 8.Microwire InterfaceDAC101S101152.0Applications Information(Continued)2.2.2LM4050Available with accuracy of 0.44%,the LM4050shunt refer-ence is also a good choice as a power regulator for the DAC101S101.It does not come in a 3Volt version,but 4.096V and 5V versions are available.It comes in a space-saving 3-pin SOT23.The minimum resistor value in the circuit of Figure 10should be chosen such that the maximum current through the LM4050does not exceed its 15mA rating.The conditions for maximum current include the input voltage at its maximum,the LM4050voltage at its minimum,the resistor value at its minimum due to tolerance,and the DAC101S101draws zero current.The maximum resistor value must allow the LM4050to draw more than its minimum current for regula-tion plus the maximum DAC101S101current in full opera-tion.The conditions for minimum current include the input voltage at its minimum,the LM4050voltage at its maximum,the resistor value at its maximum due to tolerance,and the DAC101S101draws its maximum current.These conditions can be summarized asR(min)=(V IN (max)−V Z (min)/(I A (min)+I Z (max))andR(max)=(V IN (min)−V Z (max)/(I A (max)+I Z (min))where V Z (min)and V Z (max)are the nominal LM4050output voltages ±the LM4050output tolerance over temperature,I Z (max)is the maximum allowable current through the LM4050,I Z (min)is the minimum current required by theLM4050for proper regulation,I A (max)is the maximum DAC101S101supply current,and I A (min)is the minimum DAC101S101supply current.2.2.3LP3985The LP3985is a low noise,ultra low dropout voltage regu-lator with a 3%accuracy over temperature.It is a good choice for applications that do not require a precision refer-ence for the DAC101S101.It comes in 3.0V,3.3V and 5V versions,among others,and sports a low 30µV noise speci-fication at low frequencies.Since low frequency noise is relatively difficult to filter,this specification could be important for some applications.The LP3985comes in a space-saving 5-pin SOT23and 5-bump micro SMD packages.An input capacitance of 1.0µF without any ESR requirement is required at the LP3985input,while a 1.0µF ceramic capacitor with an ESR requirement of 5m Ωto 500m Ωis required at the output.Careful interpretation and under-standing of the capacitor specification is required to ensure correct device operation.2.2.4LP2980The LP2980is an ultra low dropout regulator with a 0.5%or 1.0%accuracy over temperature,depending upon grade.It is available in 3.0V,3.3V and 5V versions,among others.Like any low dropout regulator,the LP2980requires an output capacitor for loop stability.This output capacitor must be at least 1.0µF over temperature,but values of 2.2µF or more will provide even better performance.The ESR of this capacitor should be within the range specified in the LP2980data sheet.Surface-mount solid tantalum capacitors offer a good combination of small size and ESR.Ceramic capaci-tors are attractive due to their small size but generally have ESR values that are too low for use with the LP2980.Alumi-20154113FIGURE 9.The LM4130as a power supply20154114FIGURE 10.The LM4050as a power supply 20154115FIGURE ing the LP3985regulator20154116FIGURE ing the LP2980regulatorD A C 101S 101162.0Applications Information (Continued)num electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be too high at low temperatures.2.3BIPOLAR OPERATIONThe DAC101S101is designed for single supply operation and thus has a unipolar output.However,a bipolar output may be obtained with the circuit in Figure13.This circuit will provide an output voltage range of±5Volts.A rail-to-rail amplifier should be used if the amplifier supplies are limited to±5V.The output voltage of this circuit for any code is found to be V O=(V A x(D/1024)x((R1+R2)/R1)-V A x R2/R1) where D is the input code in decimal form.With V A=5V and R1=R2,V O=(10x D/1024)-5VA list of rail-to-rail amplifiers suitable for this application are indicated in Table2.TABLE2.Some Rail-to-Rail AmplifiersAMP PKGS Typ V OS Typ I SUPPLYLMC7111DIP-8SOT23-50.9mV25µALM7301SO-8SOT23-50.03mV620µALM8261SOT23-50.7mV1mA 2.4LAYOUT,GROUNDING,AND BYPASSINGFor best accuracy and minimum noise,the printed circuit board containing the DAC101S101should have separate analog and digital areas.The areas are defined by the locations of the analog and digital power planes.Both of these planes should be located in the same board layer. There should be a single ground plane.A single ground plane is preferred if digital return current does not flow through the analog ground area.Frequently a single ground plane design will utilize a"fencing"technique to prevent the mixing of analog and digital ground current.Separate ground planes should only be utilized when the fencing technique is inadequate.The separate ground planes must be connected in one place,preferably near the DAC101S101.Special care is required to guarantee that digital signals with fast edge rates do not pass over split ground planes.They must al-ways have a continuous return path below their traces. The DAC101S101power supply should be bypassed with a 10µF and a0.1µF capacitor as close as possible to the device with the0.1µF right at the device supply pin.The 10µF capacitor should be a tantalum type and the0.1µF capacitor should be a low ESL,low ESR type.The power supply for the DAC101S101should only be used for analog circuits.Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board.The clock and data lines should have controlled impedances.20154117FIGURE13.Bipolar OperationDAC101S10117。

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IP101单端口快速以太网收发器(中文版)

IP101单端口快速以太网收发器(中文版)

10/100M单端口快速以太网收发器特性●10／100Mbps的TX●全双工或半双工●支持自动的MDI/MDIX（介质相关交叉）功能●完全符合IEEE 802.3/802.3u●支持IEEE 802.3u自动协商●支持MII / RMII / SNI接口●IEEE 802.3全双工控制规范●支持自动省电模式●支持基线漂移（BLW）补偿●支持中断功能●支持中继模式●内置2.5V的调节器提供3.3V电源●基于DSP的PHY收发器技术●使用25MHz的晶体振荡器或50MHz振荡的ref_clk信号作为时钟源●灵活的LED显示速度、双工、链接、活动和碰撞状态●通过MDC和MDIO与其他MAC通信时支持流量控制●0.25u CMOS技术，●48引脚LQFP封装●支持无铅封装（请参阅订单信息）一般说明IP101A LF是一个IEEE 802.3/802.3u兼容的单端口10/100Mbps快速以太网收发器。

它支持自动的MDI/MDIX功能以简化网络安装和减少系统维护成本。

为了提高系统的性能，IP101A提供了一个硬件中断引脚指示链接、速度和双工状态的变化。

IP101A还提供媒体独立接口（MII）/串行网络接口（SNI）或简化媒体独立接口（RMII）连接不同类型的10/100Mbps的媒体访问控制器（MAC）。

IP101A LF设计使用5类非屏蔽双绞线电缆连接到其它局域网设备。

IP101A LF收发器是用先进的CMOS技术制造的，该芯片只需要3.3V的电源并在自动节能模式消耗非常低的功率。

IP101A LF可以实现网络用双绞线RJ-45接口适配器连接。

它也可以很容易地实现集线器、交换机、路由器、接入点。

特性总则目录修订历史接收和发送数据的路径框图引脚定义1引脚描述2寄存器描述3功能描述4串行管理界面5晶体规格6布局准则7电气特性7.1直流特性7.1.1绝对最大额定值7.1.2功率消耗7.1.3操作条件7.1.4电源电压7.2交流特性7.2.1 MII定时时序7.2.2 RMII定时时序7.2.3 SMI定时时序8订单信息9封装和机械规范接收和发送数据的路径框图图1：IP101A LF的流程图引脚配置图2：IP101A LF引脚分配注意：Register 2和register 3标识寄存器一起构成供应商模型、模型版本号和组织唯一标识符（OUI）信息。

ADC121S101_06中文资料

ADC121S101_06中文资料

ADC121S101Single Channel,0.5to 1Msps,12-Bit A/D ConverterGeneral DescriptionThe ADC121S101is a low-power,single channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface.Unlike the conventional practice of specifying per-formance at a single sample rate only,the ADC121S101is fully specified over a sample rate range of 500ksps to 1Msps.The converter is based upon a successive-approximation register architecture with an internal track-and-hold circuit.The output serial data is straight binary,and is compatible with several standards,such as SPI ™,QSPI ™,MICROWIRE,and many common DSP serial interfaces.The ADC121S101operates with a single supply that can range from +2.7V to +5.25V.Normal power consumption using a +3V or +5V supply is 2.0mW and 10mW,respec-tively.The power-down feature reduces the power consump-tion to as low as 2.6µW using a +5V supply.The ADC121S101is packaged in 6-lead LLP and SOT-23packages.Operation over the industrial temperature range of −40˚C to +125˚C is guaranteed.Featuresn Specified over a range of sample rates.n 6-lead LLP and SOT-23packages n Variable power managementn Single power supply with 2.7V -5.25V range nSPI ™/QSPI ™/MICROWIRE/DSP compatibleKey Specificationsn DNL +0.5/−0.3LSB (typ)n INL ±0.40LSB (typ)n SNR72.5dB (typ)nPower Consumption —3V Supply 2.0mW (typ)—5V Supply10mW (typ)Applicationsn Portable Systemsn Remote Data Acquisitionn Instrumentation and Control SystemsPin-Compatible Alternatives by Resolution and SpeedAll devices are fully pin and function compatible.ResolutionSpecified for Sample Rate Range of:50to 200ksps200to 500ksps 500ksps to 1Msps12-bit ADC121S021ADC121S051ADC121S10110-bit ADC101S021ADC101S051ADC101S1018-bitADC081S021ADC081S051ADC081S101Connection Diagram20145005Ordering InformationOrder Code Temperature Range Description Top Mark ADC121S101CISD −40˚C to +125˚C 6-Lead LLP PackageX1C ADC121S101CISDX −40˚C to +125˚C 6-Lead LLP Package,Tape &ReelX1C ADC121S101CIMF −40˚C to +125˚C 6-Lead SOT-23PackageX01C ADC121S101CIMF −40˚C to +125˚C6-Lead SOT-23Package,Tape &ReelX01CADC121S101EVALEvaluation BoardTRI-STATE ®is a trademark of National Semiconductor Corporation QSPI ™and SPI ™are trademarks of Motorola,Inc.April 2006ADC121S101Single Channel,0.5to 1Msps,12-Bit A/D Converter©2006National Semiconductor Corporation Block Diagram20145007Pin Descriptions and Equivalent CircuitsPin No.SymbolDescriptionANALOG I/O3V INAnalog input.This signal can range from 0V to V A .DIGITAL I/O4SCLK Digital clock input.This clock directly controls the conversion and readout processes.5SDATA Digital data output.The output samples are clocked out of this pin on falling edges of the SCLK pin.6CSChip select.On the falling edge of CS,a conversion process begins.POWER SUPPLY1V A Positive supply pin.This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1µF capacitor and a 0.1µF monolithic capacitor located within 1cm of the power pin.2GND The ground return for the supply and signals.PADGNDFor package suffix CISD(X)only,it is recommended that the center pad should be connected to ground.A D C 121S 101 2Absolute Maximum Ratings(Notes1,2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Analog Supply Voltage V A−0.3V to6.5V Voltage on Any Digital Pin to GND−0.3V to6.5V Voltage on Any Analog Pin to GND−0.3V to(V A+0.3V) Input Current at Any Pin(Note3)±10mA Package Input Current(Note3)±20mA Power Consumption at T A=25˚C See(Note4) ESD Susceptibility(Note5)Human Body Model Machine Model 3500V 300VJunction Temperature+150˚C Storage Temperature−65˚C to+150˚C Operating Ratings(Notes1,2)Operating Temperature Range−40˚C≤T A≤+125˚C V A Supply Voltage+2.7V to+5.25V Digital Input Pins Voltage Range(regardless of supply voltage)−0.3V to5.25V Analog Input Pins Voltage Range0V to V A Clock Frequency1MHz to20MHz Sample Rate up to1Msps Package Thermal ResistancePackageθJA6-lead LLP94˚C/W6-lead SOT-23265˚C/WSoldering process must comply with National Semiconduc-tor’s Reflow Temperature Profile specifications.Refer to /packaging.(Note6)ADC121S101Converter Electrical Characteristics(Notes7,9)The following specifications apply for V A=+2.7V to5.25V,GND=0V,f SCLK=10MHz to20MHz,C L=15pF,f SAMPLE=500ksps to1Msps,unless otherwise noted.Boldface limits apply for T A=-40˚C to+85˚C:all other limits T A= 25˚C unless otherwise noted.Symbol Parameter Conditions TypicalLimits(Note9)UnitsSTATIC CONVERTER CHARACTERISTICSResolution with No Missing Codes V A=+2.7v to+3.6V−40˚C≤T A≤125˚C12BitsINL Integral Non-Linearity −40˚C≤T A≤+85˚CV A=+2.7V to+3.6VSOT-23+0.4±1.0LSB(max)-0.4LSB(min)LLP+0.4+1.0LSB(max)-0.4-1.2LSB(min)T A=125˚CV A=+2.7v to+3.6VSOT-23+1.0LSB(max)-1.1LSB(min)LLP+1.0LSB(max)-1.3LSB(min)DNL Differential Non-Linearity −40˚C≤T A≤+85˚CV A=+2.7V to+3.6V+0.5+1.0LSB(max)−0.3-0.9LSB(min) T A=125˚CV A=+2.7v to+3.6V±1.0LSB(max)V OFF Offset Error −40˚C≤T A≤125˚CV A=+2.7v to+3.6V±0.1±1.2LSB(max)LSB(min)GE Gain Error −40˚C≤T A≤125˚CV A=+2.7to+3.6VSOT-23±0.20±1.2LSB(max)LLP±0.20±1.5LSB(max)DYNAMIC CONVERTER CHARACTERISTICSSINAD Signal-to-Noise Plus Distortion Ratio V A=+2.7to5.25V−40˚C≤T A≤125˚Cf IN=100kHz,−0.02dBFS7270dB(min)SNR Signal-to-Noise Ratio V A=+2.7to5.25V−40˚C≤T A≤+85˚Cf IN=100kHz,−0.02dBFS72.570.8dB(min)V A=+2.7to5.25VT A=+125˚Cf IN=100kHz,−0.02dBFS70.6ADC121S101 3ADC121S101Converter Electrical Characteristics (Notes 7,9)(Continued)The following specifications apply for V A =+2.7V to 5.25V,GND =0V,f SCLK =10MHz to 20MHz,C L =15pF,f SAMPLE =500ksps to 1Msps,unless otherwise noted.Boldface limits apply for T A =-40˚C to +85˚C :all other limits T A =25˚C unless otherwise noted.SymbolParameterConditionsTypicalLimits (Note 9)UnitsDYNAMIC CONVERTER CHARACTERISTICS THD Total Harmonic Distortion V A =+2.7to 5.25Vf IN =100kHz,−0.02dBFS −80dB (max)SFDR Spurious-Free Dynamic Range V A =+2.7to 5.25Vf IN =100kHz,−0.02dBFS 82dB (min)ENOBEffective Number of BitsV A =+2.7to 5.25Vf IN =100kHz,−0.02dBFS 11.611.3Bits (min)IMDIntermodulation Distortion,Second Order TermsV A =+5.25Vf a =103.5kHz,f b =113.5kHz −78dB Intermodulation Distortion,Third Order TermsV A =+5.25Vf a =103.5kHz,f b =113.5kHz −78dB FPBW-3dB Full Power BandwidthV A =+5V 11MHz V A =+3V8MHz ANALOG INPUT CHARACTERISTICS V IN Input Range 0to V AVI DCL DC Leakage Current ±1µA (max)C INAInput CapacitanceTrack Mode 30pF Hold Mode 4pF DIGITAL INPUT CHARACTERISTICS V IH Input High Voltage V A =+5.25V 2.4V (min)V A =+3.6V 2.1V (min)V IL Input Low Voltage V A =+5V 0.8V (max)V A =+3V 0.4V (max)I IN Input CurrentV IN =0V or V A±0.1±1µA (max)C INDDigital Input Capacitance24pF (max)DIGITAL OUTPUT CHARACTERISTICS V OH Output High Voltage I SOURCE =200µA V A −0.07V A −0.2V (min)I SOURCE =1mA V A −0.1V V OL Output Low VoltageI SINK =200µA 0.030.4V (max)I SINK =1mA0.1VI OZH ,I OZL TRI-STATE ®Leakage Current ±0.1±10µA (max)C OUTTRI-STATE ®Output Capacitance 24pF (max)Output CodingStraight (Natural)BinaryPOWER SUPPLY CHARACTERISTICS V ASupply Voltage2.7V (min)5.25V (max)I ASupply Current,Normal Mode (Operational,CS low)V A =+5.25V,f SAMPLE =1Msps 2.0 3.2mA (max)V A =+3.6V,f SAMPLE =1Msps 0.6 1.5mA (max)Supply Current,Shutdown (CS high)f SCLK =0MHz,V A =+5V,f SAMPLE =0ksps500nA f SCLK =20MHz,V A =+5V,f SAMPLE =0ksps60µAA D C 121S 101 4ADC121S101Converter Electrical Characteristics(Notes7,9)(Continued)The following specifications apply for V A=+2.7V to5.25V,GND=0V,f SCLK=10MHz to20MHz,C L=15pF,f SAMPLE=500ksps to1Msps,unless otherwise noted.Boldface limits apply for T A=-40˚C to+85˚C:all other limits T A= 25˚C unless otherwise noted.Symbol Parameter Conditions TypicalLimits(Note9)UnitsPOWER SUPPLY CHARACTERISTICSP D Power Consumption,Normal Mode(Operational,CS low)V A=+5V1016mW(max)V A=+3V 2.0 4.5mW(max)Power Consumption,Shutdown(CShigh)f SCLK=0MHz,V A=+5Vf SAMPLE=0ksps2.5µWf SCLK=20MHz,V A=+5V,f SAMPLE=0ksps300µWAC ELECTRICAL CHARACTERISTICSf SCLK Clock Frequency(Note8)10MHz(min) 20MHz(max)f S Sample Rate(Note8)500ksps(min) 1Msps(max)t CONV Conversion Time16SCLK cyclesDC SCLK Duty Cycle f SCLK=20MHz5040%(min) 60%(max)t ACQ Track/Hold Acquisition Time400ns(max) Throughput Time Acquisition Time+Conversion Time20SCLK cycles t QUIET(Note10)50ns(min) t AD Aperture Delay3nst AJ Aperture Jitter30ps ADC121S101Timing SpecificationsThe following specifications apply for V A=+2.7V to5.25V,GND=0V,f SCLK=10.0MHz to20.0MHz,C L=25pF,f SAMPLE=500ksps to1Msps,Boldface limits apply for T A=-40˚C to+85˚C;all other limits T A=25˚C.Symbol Parameter Conditions Typical Limits Units t CS Minimum CS Pulse Width10ns(min) t SU CS to SCLK Setup Time10ns(min)t EN Delay from CS Until SDATA TRI-STATE®Disabled(Note11)20ns(max)t ACC Data Access Time after SCLK Falling Edge(Note12)V A=+2.7to+3.640ns(max)V A=+4.75to+5.2520ns(max)t CL SCLK Low Pulse Width 0.4xt SCLKns(min)t CH SCLK High Pulse Width 0.4xt SCLKns(min)t H SCLK to Data Valid Hold Time V A=+2.7V to+3.6V7ns(min) V A=+4.75V to+5.25V5ns(min)t DIS SCLK Falling Edge to SDATA HighImpedance(Note13)V A=+2.7V to+3.6V25ns(max)6ns(min)V A=+4.75V to+5.25V25ns(max)5ns(min)t POWER-UP Power-Up Time from Full Power-Down1µs Note1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the listed test conditions.Note2:All voltages are measured with respect to GND=0V,unless otherwise specified.ADC121S1015ADC121S101Timing Specifications(Continued)Note 3:When the input voltage at any pin exceeds the power supply (that is,V IN <GND or V IN >V A ),the current at that pin should be limited to 10mA.The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10mA to two.The Absolute Maximum Rating specification does not apply to the V A pin.The current into the V A pin is limited by the Analog Supply Voltage specification.Note 4:The absolute maximum junction temperature (T J max)for this device is 150˚C.The maximum allowable power dissipation is dictated by T J max,the junction-to-ambient thermal resistance (θJA ),and the ambient temperature (T A ),and can be calculated using the formula P D max =(T J max −T A )/θJA .The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g.when input or output pins are driven beyond the power supply voltages,or the power supply polarity is reversed).Obviously,such conditions should always be avoided.Note 5:Human body model is 100pF capacitor discharged through a 1.5k Ωresistor.Machine model is 220pF discharged through zero ohms.Note 6:Reflow temperature profiles are different for lead-free and non-lead-free packages.Note 7:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 8:This is the frequency range over which the electrical performance is guaranteed.The device is functional over a wider range which is specified under Operating Ratings.Note 9:Data sheet min/max specification limits are guaranteed by design,test,or statistical analysis.Note 10:Minimum Quiet Time required by bus relinquish and the start of the next conversion.Note 11:Measured with the timing test circuit shown in Figure 1and defined as the time taken by the output signal to cross 1.0V.Note 12:Measured with the timing test circuit shown in Figure 1and defined as the time taken by the output signal to cross 1.0V or 2.0V.Note 13:t DIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1.The measured number is then adjusted to remove the effects of charging or discharging the output capacitance.This means that t DIS is the true bus relinquish time,independent of the bus loading.A D C 121S 101 6Timing Diagrams20145008FIGURE 1.Timing Test Circuit20145006FIGURE 2.ADC121S101Serial Timing DiagramADC121S1017Specification DefinitionsACQUISITION TIME is the time required to acquire the input voltage.That is,it is time required for the hold capacitor to charge up to the input voltage.APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion.APERTURE JITTER (APERTURE UNCERTAINTY)is the variation in aperture delay from sample to sample.Aperture jitter manifests itself as noise in the output.CONVERSION TIME is the time required,after the input voltage is acquired,for the ADC to convert the input voltage to a digital word.DIFFERENTIAL NON-LINEARITY (DNL)is the measure of the maximum deviation from the ideal step size of 1LSB.DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period.The speci-fication here refers to the SCLK.EFFECTIVE NUMBER OF BITS (ENOB,or EFFECTIVE BITS)is another method of specifying Signal-to-Noise and Distortion or SINAD.ENOB is defined as (SINAD −1.76)/6.02and says that the converter is equiva-lent to a perfect ADC of this (ENOB)number of bits.FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3dB below its low frequency value for a full scale input.GAIN ERROR is the deviation of the last code transition (111...110)to (111...111)from the ideal (V REF −1.5LSB),after adjusting for offset error.INTEGRAL NON-LINEARITY (INL)is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2LSB below the first code transition)through positive full scale (1⁄2LSB above the last code transition).The deviation of any given code from this straight line is measured from the center of that code value.INTERMODULATION DISTORTION (IMD)is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time.It is defined as the ratio of the power in the second and thirdorder intermodulation products to the sum of the power in both of the original frequencies.IMD is usually expressed in dB.MISSING CODES are those output codes that will never appear at the ADC outputs.The ADC121S101is guaranteed not to have any missing codes.OFFSET ERROR is the deviation of the first code transition (000...000)to (000...001)from the ideal (i.e.GND +0.5LSB).SIGNAL TO NOISE RATIO (SNR)is the ratio,expressed in dB,of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency,not including harmonics or d.c.SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)Is the ratio,expressed in dB,of the rms value of the input signal to the rms value of all of the other spectral compo-nents below half the clock frequency,including harmonics but excluding d.c.SPURIOUS FREE DYNAMIC RANGE (SFDR)is the differ-ence,expressed in dB,between the desired signal ampli-tude to the amplitude of the peak spurious spectral compo-nent,where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.TOTAL HARMONIC DISTORTION (THD)is the ratio,ex-pressed in dB or dBc,of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output.THD is calcu-lated aswhere A f1is the RMS power of the input frequency at the output and A f2through A f6are the RMS power in the first 5harmonic frequencies.THROUGHPUT TIME is the minimum time required between the start of two successive conversion.It is the acquisition time plus the conversion time.A D C 121S 101 8Typical Performance CharacteristicsT A =+25˚C,f SAMPLE =500ksps to 1Msps,f SCLK =10MHz to 20MHz,f IN=100kHz unless otherwise stated.DNLf SCLK =10MHzINLf SCLK=10MHz2014502020145021DNLf SCLK =20MHz INLf SCLK =20MHz2014506020145061DNL vs.Clock Frequency INL vs.Clock Frequency2014506520145066ADC121S1019Typical Performance Characteristics T A =+25˚C,f SAMPLE =500ksps to 1Msps,f SCLK =10MHz to 20MHz,f IN =100kHz unless otherwise stated.(Continued)SNR vs.Clock FrequencySINAD vs.Clock Frequency2014506320145064SFDR vs.Clock Frequency THD vs.Clock Frequency2014506720145068Spectral Response,V A =5.25Vf SCLK =10MHz Spectral Response,V A =5.25Vf SCLK =20MHz2014506920145070A D C 121S 101 10ADC121S101Typical Performance Characteristics T=+25˚C,f SAMPLE=500ksps to1Msps,Af SCLK=10MHz to20MHz,f IN=100kHz unless otherwise stated.(Continued)Power Consumption vs.Throughput,f SCLK=20MHz Array 2014505511Applications Information1.0ADC121S101OPERATIONThe ADC121S101is a successive-approximation analog-to-digital converter designed around a charge-redistribution digital-to-analog converter core.Simplified schematics of the ADC121S101in both track and hold modes are shown in Figure 3and Figure 4,respectively.In Figure 3,the device is in track mode:switch SW1connects the sampling capacitor to the input,and SW2balances the comparator inputs.The device is in this state until CS is brought low,at which point the device moves to hold mode.Figure 4shows the device in hold mode:switch SW1con-nects the sampling capacitor to ground,maintaining the sampled voltage,and switch SW2unbalances the compara-tor.The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced.When the comparator is balanced,the digital word supplied to the DAC is the digital representation of the analog input voltage.The device moves from hold mode to track mode on the 13th rising edge of SCLK.2.0USING THE ADC121S101The serial interface timing diagram for the ADC121S101is shown in Figure 2.CS is chip select,which initiates conver-sions on the ADC121S101and frames the serial data trans-fers.SCLK (serial clock)controls both the conversion pro-cess and the timing of serial data.SDATA is the serial data out pin,where a conversion result is found as a serial data stream.Basic operation of the ADC121S101begins with CS going low,which initiates a conversion process and data transfer.Subsequent rising and falling edges of SCLK will be labelled with reference to the falling edge of CS;for example,"the third falling edge of SCLK"shall refer to the third falling edge of SCLK after CS goes low.At the fall of CS,the SDATA pin comes out of TRI-STATE,and the converter moves from track mode to hold mode.The input signal is sampled and held for conversion on the fallingedge of CS.The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figure 2).The SDATA pin will be placed back into TRI-STATE after the 16th falling edge of SCLK,or at the rising edge of CS,whichever occurs first.After a conversion is completed,the quiet time t QUIET must be satisfied before bringing CS low again to begin another conversion.Sixteen SCLK cycles are required to read a complete sample from the ADC121S101.The sample bits (including leading zeroes)are clocked out on falling edges of SCLK,and are intended to be clocked in by a receiver on subse-quent falling edges of SCLK.The ADC121S101will produce three leading zero bits on SDATA,followed by twelve data bits,most significant first.If CS goes low before the rising edge of SCLK,an additional (fourth)zero bit may be captured by the next falling edge of SCLK.20145009FIGURE 3.ADC121S101in Track Mode20145010FIGURE 4.ADC121S101in Hold ModeA D C 121S 101 12Applications Information(Continued)3.0ADC121S101TRANSFER FUNCTIONThe output format of the ADC121S101is straight binary.Code transitions occur midway between successive integer LSB values.The LSB width for the ADC121S101is V A /4096.The ideal transfer characteristic is shown in Figure 5.The transition from an output code of 000000000000to a code of 000000000001is at 1/2LSB,or a voltage of V A /8192.Other code transitions occur at steps of one LSB.4.0TYPICAL APPLICATION CIRCUITA typical application of the ADC121S101is shown in Figure 6.Power is provided in this example by the National Semiconductor LP2950low-dropout voltage regulator,avail-able in a variety of fixed and adjustable output voltages.The power supply pin is bypassed with a capacitor network lo-cated close to the ADC121S101.Because the reference for the ADC121S101is the supply voltage,any noise on the supply will degrade device noise performance.To keep noise off the supply,use a dedicated linear regulator for this de-vice,or provide sufficient decoupling from other circuitry to keep noise off the ADC121S101supply pin.Because of the ADC121S101’s low power requirements,it is also possible to use a precision reference as a power supply to maximize performance.The three-wire interface is shown connected to a microprocessor or DSP .5.0ANALOG INPUTSAn equivalent circuit for the ADC121S101’s input is shown in Figure 7.Diodes D1and D2provide ESD protection for the analog inputs.At no time should the analog input go beyond (V A +300mV)or (GND −300mV),as these ESD diodes will begin conducting,which could result in erratic operation.The capacitor C1in Figure 7has a typical value of 4pF,and is mainly the package pin capacitance.Resistor R1is the on resistance of the track /hold switch,and is typically 500ohms.Capacitor C2is the ADC121S101sampling capacitor and is typically 26pF.The ADC121S101will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance.This is especially important when using the ADC121S101to sample AC signals.Also important when sampling dynamic signals is an anti-aliasing filter.6.0DIGITAL INPUTS AND OUTPUTSThe ADC121S101digital inputs (SCLK and CS)are not limited by the same maximum ratings as the analog inputs.The digital input pins are instead limited to +5.25V with respect to GND,regardless of V A ,the supply voltage.This allows the ADC121S101to be interfaced with a wide range of logic levels,independent of the supply voltage.7.0MODES OF OPERATIONThe ADC121S101has two possible modes of operation:normal mode,and shutdown mode.The ADC121S101en-ters normal mode (and a conversion process is begun)when CS is pulled low.The device will enter shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low,or will stay in normal mode if CS remains low.Once in shutdown mode,the device will stay there until CS is brought low again.By varying the ratio of time spent in the normal and shutdown modes,a system may trade-off throughput for power consumption,with a sample rate as low as zero.7.1Normal ModeThe fastest possible throughput is obtained by leaving the ADC121S101in normal mode at all times,so there are no power-up delays.To keep the device in normal mode con-tinuously,CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).If CS is brought high after the 10th falling edge,but before the 16th falling edge,the device will remain in normal mode,but the current conversion will be aborted,and SDATA will return to TRI-STATE (truncating the output word).Sixteen SCLK cycles are required to read all of a conversion word from the device.After sixteen SCLK cycles have20145011FIGURE 5.Ideal Transfer Characteristic20145013FIGURE 6.Typical Application Circuit20145014FIGURE 7.Equivalent Input CircuitADC121S10113Applications Information(Continued)elapsed,CS may be idled either high or low until the next conversion.If CS is idled low,it must be brought high again before the start of the next conversion,which begins when CS is again brought low.After sixteen SCLK cycles,SDATA returns to TRI-STATE.Another conversion may be started,after t QUIET has elapsed,by bringing CS low again.7.2Shutdown ModeShutdown mode is appropriate for applications that either do not sample continuously,or it is acceptable to trade through-put for power consumption.When the ADC121S101is in shutdown mode,all of the analog circuitry is turned off.To enter shutdown mode,a conversion must be interrupted by bringing CS high anytime between the second and tenth falling edges of SCLK,as shown in Figure 8.Once CS has been brought high in this manner,the device will enter shutdown mode;the current conversion will be aborted and SDATA will enter TRI-STATE.If CS is brought high before the second falling edge of SCLK,the device will not change mode;this is to avoid accidentally changing mode as a result of noise on the CS line.To exit shutdown mode,bring CS back low.Upon bringing CS low,the ADC121S101will begin powering up (power-up time is specified in the Timing Specifications table).This power-up delay results in the first conversion result being unusable.The second conversion performed after power-up,however,is valid,as shown in Figure 9.If CS is brought back high before the 10th falling edge of SCLK,the device will return to shutdown mode.This is done to avoid accidentally entering normal mode as a result of noise on the CS line.To exit shutdown mode and remain in normal mode,CS must be kept low until after the 10th falling edge of SCLK.The ADC121S101will be fully powered-up after 16SCLK cycles.8.0POWER MANAGEMENTThe ADC121S101takes time to power-up,either after first applying V A ,or after returning to normal mode from shut-down mode.This corresponds to one "dummy"conversion for any SCLK frequency within the specifications in this document.After this first dummy conversion,the ADC121S101will perform conversions properly.Note that the t QUIET time must still be included between the first dummy conversion and the second valid conversion.When the V A supply is first applied,the ADC121S101may power up in either of the two modes:normal or shutdown.As such,one dummy conversion should be performed after start-up,as described in the previous paragraph.The part may then be placed into either normal mode or the shutdown mode,as described in Sections 7.1and 7.2.When the ADC121S101is operated continuously in normal mode,the maximum throughput is f SCLK /20.Throughput may be traded for power consumption by running f SCLK at its maximum specified rate and performing fewer conversions per unit time,raising the ADC121S101CS line after the 10th and before the 15th fall of SCLK of each conversion.A plot of typical power consumption versus throughput is shown in the Typical Performance Curves section.To calculate the power consumption for a given throughput,multiply the frac-tion of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption.Note that the curve of power consumption vs.throughput is essentially linear.This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes.20145016FIGURE 8.Entering Shutdown Mode20145017FIGURE 9.Entering Normal ModeA D C 121S 10114。

S101

S101

NEDCS101南京南迪讯电子有限公司0.5 - 2.0GHz 砷化镓电压可控衰减器¾ 产品特性ver4.06正电压控制33dB 电压可控衰减 低直流功耗高可靠性，抗静电性能好 SOIC －8封装满足RoHS 标准¾ 产品概述S101为采用SOIC-8塑封的GaAs MMIC 电压可控衰减器，衰减量随控制电压（0-5V ）线性变化，适合应用于基站、手机以及GPS 等系统。

射频端口须外加隔直电容C BL .工作频率大于500MHz 时，C BL =100pF.¾ 25℃时典型电特性参数1 频率 最小 典型最大 单位0.5-1.0GHz 2.8 3.0 dB 插损 1.0-2.0GHz 3.3 3.6 dB 0.5-1.0GHz 28 33 dB 最大衰减量 1.0-2.0GHz28 30 dB 驻波比2.2:1 上升,下降时间 10% - 90%RF 或90% - 10% RF 0.2 μs 开关时间 50% Control to 90% / 10% RF0.2μs瞬态 In-band70 mVIP32双信道，输入功率 0dBm@ 0.9GHz 15 dBm控制电压Vc 0 Vs V 电源电压Vs4.55.0 5.5 V控制电流Ic 6 mA 电源电流Is 300 μA1. 除特殊说明外，所有的测试均在50Ω系统中完成。

2. 最坏情况VSWR vs. Control Voltage(V)F=900MHz00.511.522.5012345Control Voltage(V)V S W R¾ 典型特性曲线Attenuation vs. Temperature Normalized to 25℃ F=900MHz -2.5-2-1.5-1-0.500.511.522.5012345Control Voltage (V)A t t e n u a t i o n d e l t a (dB )¾SOIC-8 外形图¾最大额定值1项目数值Array最大RF输入功率24dBm电源电压V CC -1V，+8V控制电压V C -1V，V CC+0.5V工作温度 -40℃到+85℃存贮温度 -65℃到+150℃1. 超出此类任一限制参数工作，会造成器件永久性损坏。

海康_ds-a1016资料

海康_ds-a1016资料

760
430 x 354 x 710 （标准 8U 机箱）
1500
工作：0℃-40℃ 储藏：-20℃-70℃ 工作：20%-80%RH（无结冰、无凝露） 储藏：5%～90%RH（无结冰、无凝露）
不支持
选配支持
2 个 10M/100M/1000M 自适应以太网口（可扩展至 6 个）
单电源
冗余电源（2+1）
冗余电源（2+1）
Windows，Linux，Solaris，HP-UX，AIX，MacOS
视频流传输协议/ iSCSI / NFS / CIFS / FTP / HTTP / AFP
4GB（标配，可扩展至 16G） 48
冗余电源（3+1）
基于 Web 的 GUI，串口 CLI，支持多设备统一管理 海康存储 StorOS ，RAID 管理，存储虚拟化，网络虚拟化，监视工具，系统日志，报错处理
430 x 132 x 710 （标准 3U 机箱）
600
430 x 132 x 710 （标准 3U 机箱）
760
430 x 176 x 710 （标准 4U 机箱）
DS-A1016R、DS-A1016RS、DS-A1024R、DS-A1048R
特别说明
DS-A1016RS 是单电源，其余均是冗余电源； 支持 RAID 0、1、5、10、Hot-Spare； 2-6 个 RJ45 10/100/1000M 网口，支持网口绑定； 64 位多核处理器，高速内存 2G-16G; 支持基于 IE 浏览器的配置界面，方便易用； 支持设备运行状态的可视化管理； 可升级支持 SAS 扩展柜级联模式。
型号
尺寸(mm，宽 x 高 x 深)
功率(W，含硬盘) 环境要求 温度 湿度