L17SM209S114T;中文规格书,Datasheet资料

ATMEGA8系列规格书,Datasheet资料FeaturesHigh-performance, Low-power AtmelAVR 8-bit Microcontroller Advanced RISC Architecture–130 Powerful Instructions – Most Single-clock Cycle Execution –32 × 8 General Purpose Working Registers –Fully Static Operation–Up to 16 MIPS Throughput at 16MHz–On-chip 2-cycle MultiplierHigh Endurance Non-volatile Memory segments–8Kbytes of In-System Self-programmable Flash program memory–512Bytes EEPROM–1Kbyte Internal SRAM–Write/Erase Cycles: 10,000 Flash/100,000 EEPROM–Data retention: 20 years at 85°C/100 years at 25°C(1)–Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation–Programming Lock for Software SecurityPeripheral Features–Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode–Real Time Counter with Separate Oscillator–Three PWM Channels–8-channel ADC in TQFP and QFN/MLF packageEight Channels 10-bit Accuracy–6-channel ADC in PDIP packageSix Channels 10-bit Accuracy–Byte-oriented Two-wire Serial Interface–Programmable Serial USART–Master/Slave SPI Serial Interface–Programmable Watchdog Timer with Separate On-chip Oscillator–On-chip Analog ComparatorSpecial Microcontroller Features–Power-on Reset and Programmable Brown-out Detection–Internal Calibrated RC Oscillator–External and Internal Interrupt Sources–Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, andStandbyI/O and Packages–23 Programmable I/O Lines–28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLFOperating Voltages–2.7V - 5.5V (ATmega8L)–4.5V - 5.5V (ATmega8)Speed Grades–0 - 8MHz (ATmega8L)–0 - 16MHz (ATmega8)Power Consumption at 4Mhz, 3V, 25°C–Active: 3.6mA–Idle Mode: 1.0mA–Power-down Mode: 0.5µA 8-bit with 8KBytes In-System ProgrammableATmega8ATmega8L SummaryPinConfigurationsOverview The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption ver-sus processing speed.Block Diagram Figure 1. Block DiagramThe AVR core combines a rich instruction set with 32 general purpose working registers. All the32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.The ATmega8 provides the following features: 8 Kbytes of In-System Programmable Flash withRead-While-Write capabilities, 512 bytes of EEPROM, 1 Kbyte of SRAM, 23 general purposeI/O lines, 32 general purpose working registers, three flexible Timer/Counters with comparemodes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port,and five software selectable power saving modes. The Idle mode stops the CPU while allowingthe SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip func-tions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timercontinues to run, allowing the user to maintain a timer base while the rest of the device is sleep-ing. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronoustimer and ADC, to minimize switching noise during ADC conversions. In Standby mode, thecrystal/resonator Oscillator is running while the rest of the device is sleeping. This allows veryfast start-up combined with low-power consumption.The device is manufactured using Atmel’s high density non-volatile memory technology. TheFlash Program memory can be reprogrammed In-System through an SPI serial interface, by aconventional non-volatile memory programmer, or by an On-chip boot program running on theAVR core. The boot program can use any interface to download the application program in theApplication Flash memory. Software in the Boot Flash Section will continue to run while theApplication Flash Section is updated, providing true Read-While-Write operation. By combiningan 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the AtmelATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solutionto many embedded control applications.The ATmega8 AVR is supported with a full suite of program and system development tools,including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators,and evaluation kits.Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Minimum and Maxi-mum values will be available after the device is characterized.Pin DescriptionsVCC Digital supply voltage. GND Ground.Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/ TOSC2Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-lator amplifier and input to the internal clock operating circuit.Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier.If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 58 and “System Clock andClock Options” on page 25.Port C (PC5..PC0)Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port C pins that are externally pulled low will source current if the pull-upresistors are activated. The Port C pins are tri-stated when a reset condition becomes active,even if the clock is not running.If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-acteristics of PC6 differ from those of the other pins of Port C.If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pinfor longer than the minimum pulse length will generate a Reset, even if the clock is not running.The minimum pulse length is given in Table 15 on page 38. Shorter pulses are not guaranteed togenerate a Reset.The various special features of Port C are elaborated on page 61.Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port D pins that are externally pulled low will source current if the pull-upresistors are activated. The Port D pins are tri-stated when a reset condition becomes active,even if the clock is not running.Port D also serves the functions of various special features of the ATmega8 as listed on page63.Reset input. A low level on this pin for longer than the minimum pulse length will generate areset, even if the clock is not running. The minimum pulse length is given in Table 15 on page38. Shorter pulses are not guaranteed to generate a reset.AV CC AV CC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be externally connected to V CC, even if the ADC is not used. If the ADC is used, it should be con-nected to V CC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, V CC. AREF AREF is the analog reference pin for the A/D Converter.ADC7..6 (TQFP and QFN/MLF Package Only)In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to theA/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels.Resources A comprehensive set of development tools, application notes and datasheets are available for download on /doc/9e818e5c767f5acfa1c7cdaf.html /avr.Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.Register SummaryAddress Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page0x3F (0x5F)SREG I T H S V N Z C11 0x3E (0x5E)SPH–––––SP10SP9SP813 0x3D (0x5D)SPLSP7SP6SP5SP4SP3SP2SP1SP013 0x3C (0x5C)Reserved0x3B (0x5B)GICR INT1INT0––––IVSEL IVCE49, 67 0x3A (0x5A)GIFR INTF1INTF0––––––67 0x39 (0x59)TIMSKOCIE2TOIE2TICIE1OCIE1A OCIE1B TOIE1–TOIE072, 100, 119 0x38 (0x58)TIFR OCF2TOV2ICF1OCF1A OCF1B TOV1–TOV072, 101, 119 0x37 (0x57)SPMCR SPMIE RWWSB–RWWSRE BLBSET PGWRT PGERS SPMEN206 0x36(0x56)TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN–TWIE165 0x35 (0x55)MCUCR SESM2SM1SM0ISC11ISC10ISC01ISC0033, 66 0x34 (0x54)MCUCSR––––WDRF BORF EXTRF PORF41 0x33(0x53)TCCR0–––––CS02CS01CS0071 0x32 (0x52)TCNT0Timer/Counter0 (8 Bits)72 0x31 (0x51)OSCCAL Oscillator Calibration Register31 0x30 (0x50)SFIOR––––ACME PUD PSR2PSR1058, 74, 120, 186 0x2F (0x4F)TCCR1ACOM1A1COM1A0COM1B1COM1B0FOC1A FOC1B WGM11WGM1096 0x2E (0x4E)TCCR1B ICNC1ICES1–WGM13WGM12CS12CS11CS1098 0x2D (0x4D)TCNT1H Timer/Counter1 – Counter Register High byte99 0x2C(0x4C)TCNT1L Timer/Counter1 – Counter Register Low byte99 0x2B (0x4B)OCR1AH Timer/Counter1 – Output Compare Register A High byte99 0x2A (0x4A)OCR1AL Timer/Counter1 – Output Compare Register A Low byte99 0x29(0x49)OCR1BH Timer/Counter1 – Output Compare Register B High byte99 0x28 (0x48)OCR1BL Timer/Counter1 – Output Compare Register B Low byte99 0x27 (0x47)ICR1H Timer/Counter1 – Input Capture Register High byte100 0x26(0x46)ICR1L Timer/Counter1 – Input Capture Register Low byte100 0x25(0x45)TCCR2FOC2WGM20COM21COM20WGM21CS22CS21CS20114 0x24 (0x44)TCNT2Timer/Counter2 (8 Bits)1160x23 (0x43)OCR2Timer/Counter2 Output Compare Register116 0x22 (0x42)ASSR––––AS2TCN2UB OCR2UBTCR2UB117 0x21 (0x41)WDTCR–––WDCE WDE WDP2WDP1WDP0430x20(1) (0x40)(1)UBRRH URSEL–––UBRR[11:8]152 UCSRC URSEL UMSEL UPM1UPM0USBSUCSZ1UCSZ0UCPOL1500x1F (0x3F)EEARH–––––––EEAR820 0x1E (0x3E)EEARL EEAR7EEAR6EEAR5EEAR4EEAR3EEAR2EEAR1EEAR020 0x1D (0x3D)EEDR EEPROM Data Register20 0x1C (0x3C)EECR––––EERIE EEMWE EEWE EERE20 0x1B(0x3B)Reserved0x1A (0x3A)Reserved0x19 (0x39)Reserved0x18 (0x38)PORTB PORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB065 0x17 (0x37)DDRBDDB7DDB6DDB5DDB4DDB3DDB2DDB1DDB065 0x16 (0x36)PINBPINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB065 0x15 (0x35)PORTC–PORTC6PORTC5PORTC4PORTC3PORTC2PORTC1PORTC065 0x14 (0x34)DDRC–DDC6DDC5DDC4DDC3DDC2DDC1DDC065 0x13 (0x33)PINC–PINC6PINC5PINC4PINC3PINC2PINC1PINC065 0x12 (0x32)PORTD PORTD7PORTD6PORTD5PORTD4PORTD3PORTD2PORTD1PORTD065 0x11 (0x31)DDRDDDD7DDD6DDD5DDD4DDD3DDD2DDD1DDD065 0x10 (0x30)PINDPIND7PIND6PIND5PIND4PIND3PIND2PIND1PIND065 0x0F (0x2F)SPDR SPI Data Register127 0x0E (0x2E)SPSR SPIF WCOL–––––SPI2X126 0x0D (0x2D)SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1SPR0125 0x0C (0x2C)UDR USART I/O Data Register148 0x0B (0x2B)UCSRA RXC TXC UDRE FE DOR PE U2X MPCM148 0x0A (0x2A)UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2RXB8TXB8149 0x09 (0x29)UBRRL USART Baud Rate Register Low byte152 0x08 (0x28)ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1ACIS0186 0x07 (0x27)ADMUX REFS1REFS0ADLAR–MUX3MUX2MUX1MUX0199 0x06 (0x26)ADCSRA ADEN ADSC ADFR ADIF ADIE ADPS2ADPS1ADPS0200 0x05(0x25)ADCH ADC Data Register High byte201 0x04 (0x24)ADCL ADC Data Register Low byte201 0x03 (0x23)TWDR Two-wire Serial Interface Data Register167 0x02 (0x22)TWAR TWA6TWA5TWA4TWA3TWA2TWA1TWA0TWGCE167 Register Summary (Continued)Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page0x01 (0x21)TWSR TWS7TWS6TWS5TWS4TWS3–TWPS1TWPS0166 0x00 (0x20)TWBR Two-wire Serial Interface Bit Rate Register165 Notes: 1.Refer to the USART description (“USART” on page 129) for details on how to access UBRRH and UCSRC (“Accessing UBRRH/UCSRC Registers” on page 146)2.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written3.Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate onall bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F onlyInstruction Set SummaryMnemonics Operands Description Operation Flags#Clocks ARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add two Registers Rd ← Rd + Rr Z, C, N, V, H1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C, N, V, H1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z, C, N, V, S2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z, C, N, V, H1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z, C, N, V, H1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z, C, N, V, H1 SBCI Rd, K Subtract with Carry Constant from Reg.Rd ← Rd - K - C Z, C, N ,V, H1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z, C, N, V, S2 AND Rd, Rr Logical AND Registers Rd ← Rd ? Rr Z, N, V1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd ? K Z, N, V1OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z, N, V1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z, N, V1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z, N, V1 COM Rd One’s Complement Rd ← 0xFF ? Rd Z, C, N, V1 NEG Rd Two’s Complement Rd ← 0x00 ? Rd Z, C, N, V, H1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z, N, V1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd ? (0xFF - K)Z, N, V1 INC Rd Increment Rd ← Rd + 1Z, N, V1 DEC Rd Decrement Rd ← Rd 1 Z, N, V1 TST Rd Test for Zero or Minus Rd ← Rd ? Rd Z, N, V1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z, N, V1 SER Rd Set Register Rd ← 0xFF None1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z, C2 MULS Rd, Rr Multiply Signed R1:R0← Rd x Rr Z, C2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z, C2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1Z, C2FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1Z, C2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1Z, C2 BRANCH INSTRUCTIONSRJMP k Relative Jump PC ← PC + k + 1None2 IJMP Indirect Jump to (Z)PC ← Z None2 RCALL k Relative Subroutine Call PC ← PC + k + 1None3 ICALL Indirect Call to (Z)PC ←Z None3 RET Subroutine Return PC ← STACK None4 RETI Interrupt Return PC ← STACK I4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3None 1 / 2 / 3 CP Rd,Rr Compare Rd ? Rr Z, N, V, C, H 1 CPC Rd,Rr Compare with Carry Rd ? Rr ? C Z, N, V, C, H1 CPI Rd,K Compare Register with Immediate Rd ? K Z, N, V, C, H1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3None 1 / 2 / 3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or3None 1 / 2 / 3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1None 1 / 2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1None 1 / 2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k +1None 1 / 2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1None 1 / 2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1None 1 / 2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1None 1 / 2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1None 1 / 2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1None 1 / 2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1None 1 / 2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k +1None 1 / 2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1None 1 / 2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1None 1 / 2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ←PC + k + 1None 1 / 2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1None 1 / 2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1None 1 / 2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1None 1 / 2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1None 1 / 2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1None 1 / 2Instruction Set Summary (Continued)Mnemonics Operands Description Operation Flags#ClocksBRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1None 1 / 2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1None 1 / 2 DATA TRANSFER INSTRUCTIONSMOV Rd, Rr Move Between Registers Rd ← Rr None1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None1 LDI Rd, K Load Immediate Rd ←K None1LD Rd, X Load Indirect Rd ← (X)None2LD Rd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None2LD Rd, - X Load Indirect and Pre-Dec.X ← X - 1, Rd ← (X)None2LD Rd, Y Load Indirect Rd ← (Y)None2LD Rd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1None2LD Rd, - Y Load Indirect and Pre-Dec.Y ← Y - 1, Rd ← (Y)None2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q)None2LD Rd, Z Load Indirect Rd ← (Z)None2LD Rd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None2LD Rd, -Z Load Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)None2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z +q)None2 LDS Rd, k Load Direct from SRAM Rd ← (k)None2ST X, Rr Store Indirect(X) ← Rr None2ST X+, Rr Store Indirect and Post-Inc.(X) ← Rr, X ← X + 1None2ST- X, Rr Store Indirect and Pre-Dec.X ← X - 1, (X) ← Rr None2ST Y, Rr Store Indirect(Y) ← Rr None2ST Y+, Rr Store Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None2ST- Y, Rr Store Indirect and Pre-Dec.Y ← Y - 1, (Y) ← Rr None2 STD Y+q,Rr Store Indirect with Displacement(Y + q) ← Rr None2ST Z, Rr Store Indirect(Z) ← Rr None2ST Z+, Rr Store Indirect and Post-Inc.(Z) ← Rr, Z ← Z + 1None2ST-Z, Rr Store Indirect and Pre-Dec.Z ← Z - 1, (Z) ← Rr None2 STD Z+q,Rr Store Indirect with Displacement(Z + q) ← Rr None2 STS k, Rr Store Direct to SRAM(k) ← Rr None2 LPM Load Program Memory R0 ← (Z)None3 LPM Rd, Z Load Program Memory Rd ← (Z)None3 LPM Rd, Z+Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1None3 SPM Store Program Memory(Z) ← R1:R0None-IN Rd, P In Port Rd ←P None1 OUT P, Rr Out Port P ← Rr None1 PUSH Rr Push Register on Stack STACK ← Rr None2 POP Rd Pop Register from Stack Rd ← STACK None2 BIT AND BIT-TEST INSTRUCTIONSSBI P,b Set Bit in I/O Register I/O(P,b) ←1None2 CBI P,b Clear Bit in I/O Register I/O(P,b) ←0None2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0Z, C, N, V1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0Z, C, N, V1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)Z, C, N, V1 ROR Rd Rotate Right Through CarryRd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)Z, C, N, V1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6Z, C, N, V1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)None1 BSET s Flag Set SREG(s) ← 1SREG(s)1 BCLR s Flag Clear SREG(s) ← 0 SREG(s)1 BST Rr, b Bit Store from Register to T T ← Rr(b)T1 BLD Rd, b Bit load from T to Register Rd(b) ←T None1 SEC Set Carry C ←1C1 CLC Clear Carry C ← 0 C1 SEN Set Negative Flag N ←1N1 CLN Clear Negative Flag N ← 0 N1 SEZ Set Zero Flag Z ←1Z1 CLZ Clear Zero Flag Z ← 0 Z1 SEI Global Interrupt Enable I ←1I1 CLI Global Interrupt Disable I ← 0 I1 SES Set Signed Test Flag S ←1S1 CLS Clear Signed Test Flag S ← 0 S1 SEV Set Twos Complement Overflow.V ←1V1 CLV Clear Twos Complement Overflow V ← 0 V1 SET Set T in SREG T ←1T1Instruction Set Summary (Continued)Mnemonics Operands Description Operation Flags#ClocksCLT Clear T in SREG T ← 0 T1 SEH Set Half Carry Flag in SREG H ←1H1 CLH Clear Half Carry Flag in SREG H ← 0 H1 MCU CONTROL INSTRUCTIONSNOP No Operation None1 SLEEP Sleep(see specific descr. for Sleep function)None1Notes:1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informationand minimum quantities2.Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green3.Tape & ReelSpeed (MHz)Power Supply (V)Ordering Code (2)Package (1)Operation Range8 2.7 - 5.5A Tmega8L-8AU A Tmega8L-8AUR (3)A Tmega8L-8PU A Tmega8L-8MU A Tmega8L-8MUR (3)32A 32A 28P332M1-A32M1-A Industrial (-40°C to 85°C)16 4.5 - 5.5A Tmega8-16AU A Tmega8-16AUR (3)A Tmega8-16PU A Tmega8-16MU A Tmega8-16MUR (3)32A 32A 28P332M1-A 32M1-APackage Type32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)28P328-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)32M1-A32-pad, 5 × 5 × 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)32AErrata The revision letter in this section refers to the revision of the ATmega8 device.ATmega8 Rev. D to I, M ?First Analog Comparator conversion may be delayedInterrupts may be lost when writing the timer registers in the asynchronous timerSignature may be Erased in Serial Programming ModeCKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request1.First Analog Comparator conversion may be delayedIf the device is powered by a slow rising V CC, the first Analog Comparator conversion will take longer than expected on some devices.Problem Fix / WorkaroundWhen the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion.2.Interrupts may be lost when writing the timer registers in the asynchronous timerThe interrupt will be lost if a timer register that is synchronized to the asynchronous timer clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.Problem Fix / WorkaroundAlways check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx).3.Signature may be Erased in Serial Programming ModeIf the signature bytes are read before a chiperase command is completed, the signature may be erased causing the device ID and calibration bytes to disappear. This is critical, espe-cially, if the part is running on internal RC oscillator.Problem Fix / Workaround:Ensure that the chiperase command has exceeded before applying the next command.4.CK OPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32K HzOscillator is Used to Clock the Asynchronous Timer/Counter2When the internal RC Oscillator is used as the main clock source, it is possible to run the Timer/Counter2 asynchronously by connecting a 32KHz Oscillator between XTAL1/TOSC1 and XTAL2/TOSC2. But when the internal RC Oscillator is selected as the main clock source, the CKOPT Fuse does not control the internal capacitors on XTAL1/TOSC1 and XTAL2/TOSC2. As long as there are no capacitors connected to XTAL1/TOSC1 and XTAL2/TOSC2, safe operation of the Oscillator is not guaranteed.Problem Fix / WorkaroundUse external capacitors in the range of 20pF - 36pF on XTAL1/TOSC1 and XTAL2/TOSC2.This will be fixed in ATmega8 Rev. G where the CKOPT Fuse will control internal capacitors also when internal RC Oscillator is selected as main clock source. For ATmega8 Rev. G, CKOPT = 0 (programmed) will enable the internal capacitors on XTAL1 and XTAL2. Cus-tomers who want compatibility between Rev. G and older revisions, must ensure that CKOPT is unprogrammed (CKOPT = 1).5.Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interruptrequest.Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-ister triggers an unexpected EEPROM interrupt request.Problem Fix / WorkaroundAlways use OUT or SBI to set EERE in EECR.Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/111.Updated the datasheet according to the Atmel new Brand Style Guide.2.Updated “Ordering Information” on page 13. Added Ording Information for“Tape&Reel” devicesChanges from Rev. 2486X- 06/10 to Rev. 2486Y- 10/101.Max Rise/Fall time in Table 102 on page 239 has been corrected from 1.6ns to 1600ns.2.Note is added to “Performing Page Erase by SPM” on page 209.3.Updated/corrected several short-cuts and added some new ones.4.Updated last page according to new standard.Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/101.Updated “DC Characteristics” on page 235 with new V OL maximum value (0.9V and0.6V).Changes from Rev.2486V- 05/09 toRev. 2486W- 02/101.Updated “ADC Characteristics” on page 241 with V INT maximum value (2.9V).Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/091.Updated “Errata” on page 289.2.Updated the last page with Atmel’s new adresses.Changes from Rev.2486T- 05/08 toRev. 2486U- 08/081.Updated “DC Characteristics” on page 235 with I CC typical values.Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/081.Updated Table 98 on page 233.2.Updated “Ordering Information” on page 285.- Commercial Ordering Code removed.- No Pb-free packaging option removed.。

Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.11/46 2007-3-22ATJ2091N DatasheetVersion 1.1DeclarationCircuit diagrams and other information relating to products of Actions Semiconductor Company, Ltd. (“Actions”) are included as a means or illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been examined and is believed to be accurate, Actions makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and disclaims any responsibility for inaccuracies. Information in this document is provided solely to enable use of Actions’ products. The information presented in this document does not form part of any quotation or contract for sale. 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All sales of any Actions products are expressly conditional on your agreement to the terms and conditions of the most recently dated version of Actions’ Terms and Conditions of Sale Agreement dated before the date of your order.The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights, copyright, trademark rights, rights in trade secrets and/or know how, or any other intellectual property rights of Actions or others, however denominated, whether by express or implied representation, by estoppel, or otherwise.Information contained herein relates solely to the Actions products described herein and abrogates and supersedes, as of the release date of this publication, all previously published data and specifications relating to such products provided by Actions or by any other person purporting to distribute such information. Actions reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your Actions sales representative to obtain the latest specifications before placing your product order. Actions product may contain design defects or errors known as anomalies or errata which may cause the products functions to deviate from published specifications. Anomaly or “errata” sheets relating to currently characterized anomalies or errata are available upon request. Designers must not rely on the absence or characteristics of any features or instructions of Actions’ products marked “reserved” or “undefined.” Actions reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.Actions’ products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an OfficerCopyright© Actions Semiconductor Co., Ltd 2007. All rights reserved.Ver. 1.1 2/46 2007-3-22Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.13/46 2007-3-22 of Actions and further testing and/or modification will be fully at the risk of the customer. Copies of this document and/or other Actions product literature, as well as the Terms and Conditions of Sale Agreement, may be obtained by visiting Actions’ website at http:/ or from an authorized Actions representative. The word “ACTIONS,” the Actions’ LOGO, whether used separately and/or in combination, and the phase “ATJ2097,” are trademarks of Actions Semiconductor Company, Ltd.. Names and brands of other companies and their products that may from time to time descriptively appear in this product data sheet are the trademarks of their respective holders: no affiliation, authorization, or endorsement by such persons is claimed or implied except as may be expressly stated therein. ACTIONS DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.IN NO EVENT SHALL ACTIONS BE RELIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF ACTIONS OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER ACTIONS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR NOT.Additional SupportAdditional product and company information can be obtained by visiting the Actions website at: Table of ContentsRevision History (6)1 .Introduction (7)2. Pin Description (10)2.1 Pin Out (10)2.2 Pin Definition (10)3. Function Description (14)3.1 Functional Block Diagram (14)3.2 MCU Core (15)3.2.1 MCU System Memory Mapping (15)3.3 DSP24 Core (17)3.4 ZRAM1 and ZRAM2 (17)3.5 USB2.0 SIE (18)3.5.1 General Description (18)3.5.2 Features (19)3.5.3 USB Using Memory (20)3.6 NAND Flash Interface (20)3.7 Key Scan Interface (20)3.8 LCD Interface (21)3.9 General Purpose IO Ports (23)3.10 LOSC/RTC (23)3.11 HOSC/PLL (24)3.12 PMU/DC-DC (25)3.13 A/D, D/A and Headphone Driver (25)3.13.1 D/A Interface (25)3.13.2 A/D Interface (26)4. Electrical Characteristics (27)4.1 Absolute Maximum Ratings (27)Copyright© Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 4/46 2007-3-22Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.15/46 2007-3-22 4.2 Capacitance (27)4.3 DC Characteristics (28)4.4 AC Characteristics (29)4.4.1 AC Test Input Waveform (29)4.4.2 AC Test Output Measuring Points (29)4.4.3 Reset Parameter (30)4.4.4 Initialization Parameter (30)4.4.5 GPIO Interface Parameter (30)4.4.6 Ordinary ROM Parameter (31)4.4.7 External System Bus Parameter (33)4.4.8 Bus Operation (34)4.4.9 Serial Interface Parameter (34)4.4.10 A/D Converter Characteristics (36)4.4.11 I2S Interface Parameter (36)4.4.12 Headphone Driver Characteristics Table (36)4.4.13 LCM Driver Parameter (38)4.4.14 SPI Parameter (39)5. Ordering Information (41)5.1 Soldering Conditions (41)5.2 Precaution Against ESD For Semiconductors (41)5.3 Status Before Initialization of MOS Devices (42)6. ATJ 2091N Package Drawing (43)7. Appendix (44)Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.16/46 2007-3-22 Revision History Version Date DescriptionVer1.0 Nov. 2006 1st version created for ATJ2091NVer1.1 Mar. 2007 2nd version modified for ATJ2091N, electrical characteristics added.1 .IntroductionATJ2091N is a third generation single-chip highly-integrated digital music system solution for devices such as dedicated audio players, PDAs, and cell phones. It includes an audio decoder with a high performance DSP with embedded RAM and ROM, ADPCM record capabilities and USB interface for downloading music and uploading voice recordings. ATJ2091N also provides an interface flash memory, LED/LCD, button and switch inputs, headphones, microphone and FM radio input and control. ATJ2091N contains a high performance DSP, which can easily be programmed to support many kinds of digital audio standards such as WMA, etc. For devices like USB-Disk, ATJ2091N can act as a USB mass storage slave device to personal computer system. ATJ2091N has low power consumption to allow long battery life and an efficient flexible on-chip DC-DC converter that allows many different battery configurations, including 1xAA and 1xAAA. The built-in Sigma-Delta DAC includes a headphone driver to directly drive low impedance headphones. The ADC includes inputs for both Microphone and Analog Audio in to support voice recording and FM radio integration features. ATJ2091N provides a true “ALL-IN-ONE” solution that is ideally suited for highly optimized digital audio players.Features:z MPEG1/2/2.5 Audio Layer 1,2,3 decoder, bit rate 8-448Kbps, 8-48KHz, CBR/VBRz Support WMA Decoder, bit rate 32-384Kbps, 8-48KHzz Digital Voice Recording at ultra low 4.4 or 8Kbps w/ Actions Speech Algorithmz24 bits DSP Core with on-chip Debug Support Unit (DSU)Copyright© Actions Semiconductor Co., Ltd 2007. All rights reserved.Ver. 1.1 7/46 2007-3-22Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.18/46 2007-3-22 z On-chip DSP PM with SRAM(16K*24) ,can be switched to be MCU memory space z On-chip DSP DM with SRAM(16K*24), can be switched to be MCU memory space z Integrated MCU with DSU, the instruction set is compatible with Z80z Internal (16K-64)x8(ZRAM1),(3K+3K)(ZRAM2) and 6k ZRAM3 accessed by MCU z Internal 12Kx8 BROM build in Boot up and USB Upgrade firmwarez Internal (21K+17K)x8 TROMz Internal SRAM access time<7ns, MROM access time<16nsz External up to 3(pcs)x 32M/64M/128M/256M/512M/1G/2G/4G bytes Nand type Flashaccessed by MCU or DMAz Support 24MHz OSC with on-chip PLL for DSP and about 32KHz RC oscillator z 2-channel DMA , 1-channel CTC(Counter/Timer Controller) and interrupt controller forMCUz Energy saving dynamic power management (PMU), supporting 1xAA and 1xAAA. z Support USB 2.0 Compliance PHY+SIE, Read :7MB/S, Write: 6MB/S( Nand FlashBase )z Build in Stereo 18-bit Sigma-Delta D/Az Build in Key Scan Circuit and GPIOz Support external 8080 Series LCM driver interfacez Support FM Radio input and 32 levels volume controlz Support Stereo 18-bit Sigma-Delta A/D for Microphone/FM Input/Line Input, samplerate at 8/12/16/22/24/32/48KHzz MCU run at 48MHz(typ),F/W can program from DC up to 60MHz transparently z DSP+PM/DM Speed up to 72MIPS,while 48mips@1.4vz D/A+PA SNR :with A weight>92dB,without A weight>=88dBz A/D SNR >79dBCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.19/46 2007-3-22 z Headphone driver output 2x11Mw @16ohmz Operating Voltage: IO: 3.0v, Core: 1.8vz Standby Leakage Current: VCC:50uA@3.0V(MAX), VDD: 350uA@1.6V(MAX) z Low Power Consumption : <80mW@1.5V at typical WMA decoder solutionCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.110/46 2007-3-22 2. Pin Description2.1 Pin Out2.2 Pin DefinitionNOTE:1： PWR---Power Supply2： AI----Analog InputCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.111/46 2007-3-223： AO----Analog Output 4： O-----Output 5： I-----Input 6： BI----Bidirection 7： TBD2C, BD2C, BD2XU, SBD2X, BD2XM5----2 miliampere driver 8： BD4CM2, BD4C, BD4CU----4 miliampere driver 9: BD1XM2----1 miliampere driver 10：USCU----USCHIMITCU Pin No. Pin Name I/O Type Driver Reset Default Description 1 VCC PWR / / Power supply for USB 2UREGAO / / USB precision Resistor 3 GND PWR / / USB ground 4 USBDP A / H USB data plus 5 USBDM A / H USB data minus6 RESET- I USCU H System reset input (active low)7 PAVCC PWR / / Power supply for power amplifier8 AOUTR AO / / Int. PA right channel analog output9 AOUTL AO / / Int. PA left channel analog output 10 PAGND PWR / / Power amplifier ground11VRDAAO / / Bypass capacitor connect pin for Int. D/A Reference voltage12 MICIN AI / / Microphone pre-amplifier input 13 VMIC PWR / / Power supply for Microphone 14FMINLAI / / Left channel of FM line input 15 FMINR AI / / Right channel of FM line input 16 AGND PWR / / Analog ground 17 AVCC PWR / / power supply of Analog 18 VREFI AI / / Voltage reference input 19 AVDD PWR / / Analog Core power pin 20VDDIOPWR/ZCore power input/outputCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.112/46 2007-3-2221 VP PWR / / Power pin22 LRADC1 AI / / Low resolution A/D input 1 23 PWRMode0 AI / / POWER mode select 024 HOSCI AI / / High frequency crystal OSC input 25 HOSCO AO / / High frequency crystal OSC output 26 VCC PWR / / PAD power pin 27 BAT I / / Battery Voltage input.GPIO_B0BIZ Bit0 of General purpose I/O port B 28KEYI0 I BD2CH Bit0 of key scan circuit input 29 GPIO_C2 BI BD4CM2/ Bit2 of General purpose I/O port C GPIO_B2BIZ Bit2 of General purpose I/O port B 30 KEYI12 I BD2XUM5 H Bit1 of key scan circuit input 31LXVDDPWR// VDD DC-DC pin 32 GND PWR / / Ground 33 GND PWR / / NMOS Ground 34 LXVCC PWR / / VCC DC-DC pin35 CE2- O NF_PAD H Ext. memory chip enable 2 36 CE1- O NF_PAD H Ext. memory chip enable 1 CE3-OH Ext. memory chip enable 337GPO_A3 O BD4CU/Bit3 of General purpose Output port A GPIO_G0BIZ Bit0 of General purpose I/O port G 38CE4- O TBD2C/ Ext. memory chip enable 4 39 VDD PWR / / Digital Core power40 RB- I BD4C H Nand Type flash Ready/Busy status input.GPO_A1OL Bit1 of General purpose Output port A 41 ICECK I BD4C/Clock input of DSUGPO_A2OL Bit2 of General purpose Output port A 42 ICEDO O BD4C/ Data output of DSUGPO_A0OBD4CM2Bit0 of General purpose Output port ACopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.113/46 2007-3-2243 ICEDI I / Data input of DSU 44 ICEEN- I BD4C / DSU enable (active low) 45 ICERST- I BD4C / DSU reset (active low)GPIO_B4BIZ Bit4 of General purpose I/O port B 46KEYO0 O BD2XM5/ Bit0 of key scan circuit output GPIO_B5BIZ Bit5 of General purpose I/O port B 47KEYO1 O BD2XM5/ Bit1 of key scan circuit output 48 VCC PWR / / Digital power pad49 D7 BI NF_PAD L Bit7 of ext. memory data bus 50 D6 BI NF_PAD L Bit6 of ext. memory data bus 51 D5 BI NF_PAD L Bit5 of ext. memory data bus 52 D4 BI NF_PAD L Bit4 of ext. memory data bus 53 D3 BI NF_PAD L Bit3 of ext. memory data bus 54D2BINF_PADL Bit2 of ext. memory data bus 55 GND PWR / / Ground56 D1 BI NF_PAD L Bit1 of ext. memory data bus 57 D0 BI NF_PAD L Bit0 of ext. memory data bus 58 MWR- O NF_PAD H Ext. memory write strobe 59MRD-O NF_PAD H Ext. memory read strobe60 CLE O NF_PAD L Command latch enable for NAND flash61 ALE O NF_PAD L Address latch enable for NAND flash GPIO_C1 BI OD Bit1 of General purpose I/O port C I2C_SDAO/ I2C Serial data (Open drain) 62SIRQ- I SBD2X/ Ext. interrupt request input GPIO_C0BIOD Bit0 of General purpose I/O port C 63I2C_SCL OSBD2X / I2C serial clock (Open drain) 64 VDDPWR//Digital Core power3. Function Description3.1 Functional Block DiagramCopyright© Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 14/46 2007-3-22Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.115/46 2007-3-223.2 MCU Core3.2.1 MCU System Memory MappingEntendedMemory Space (MCU.A15=1)Internal Memory Space (MCU.A15=0)MCU 64KB Memory Space 0000H8000H FFFFHIf IA15=0 -> mapped to internal MemoryIf IA14=0, mapped to internal ZRAM （16K-64 ZRAM1）If IA14=1, mapped to internal DSP IPM/IDM when they are mapped into MCU memory space 3 extended address bits of a IO mapped register (Mapped at registered are used to decode the access to one of these memory blocks Bit 2 1 0 Accessed Block 0 0 0IPM low byteCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.116/46 2007-3-220 0 1 IPM middle byte 0 1 0 IPM high byte 0 1 1 ZRAM3 1 0 0 IDM low byte 1 0 1 IDM middle byte 1 1 0 IDM high byte 1 1 1ZRAM2 （B1+B2）Since IPM/IDM is mapped to MCU memory space per 8K block, IA13 is used toselect low/high block of 8K bytes in each 16K byte block.If IA15=1 -> Extended address bits are IO mapped at 01h and 02h for EMA15-28.EMA15-25 are output as address bus, while the EMA26-28 are used to decode CE0- ~ CE3-.CE0- is used to access boot code from ROM/MASK/NOR- type Flash.CE1- to CE3- can be configured to access ROM, or RAM or NAND-type Flash.ATJ2091N’s internal MCU MROM/SRAM memory mapping:1) (16K-64) byte ZRAM1(IA15=0,IA14=0): 0000H-3FBFH2) 6Kbyte ZRAM2 (IA15=0, IA14=1, IOReg05.[2:0]=111): 4000H-57FFH 3) (2K+256) byte URAM: 5800H-60FFH it has synchronization andasynchronism accessing mode.4) 12Kbyte BROM (IA15=1,Reg02=00h, Reg01=00h): 8000h-AFFFh 5) 21Kbyte TROM1 (IA15=1,Reg02=00h,Reg01=02h): 8000h-D3FFh 6) 17Kbyte TROM2 (IA15=1,Reg02=00h,Reg01=03h): 8000h-C400h 7) 6Kbyte ZRAM3 (IA15=0,IA14=1,IOReg05.[2:0]=011): 4000H-57FFHCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.117/46 2007-3-22ATJ2091N’s internal DSP IPM/IDM memory mapping:1) 16K x24bit IPM SRAM: 0000H-3FFFH 2) 16K x24bit IDM SRAM : 0000H-3FFFHATJ2091N’s internal DSP IPM/IDM memory mapping accessed by MCU:1) 16K x3 byte IPM SRAM: 4000H-7FFFH 2) 16K x3 byte IDM SRAM : 4000H-7FFFH(Hi/Mid/Low Byte Select and Mapping Mode controlled by IOReg05)DMA Mode Notes:1: When DMA1 and DMA2 are active, MCU will halt, and DMA1 and DMA2 have priority. 2: FLASHDMA or USB DMA is active, MCU will not halt.3.3 DSP24 CoreThis Core is a high performance, programmable Digital Signal Processor (DSP) suitable for a variety of digital audio compounding functions, such as Dolby AC-3 Surround, MPEG1 Layer3 which require large memory provided and the higher accuracy. RDSP24 is a general purpose DSP which can be appended various peripherals circuitry to implement some advanced signal processing algorithms for audio application.3.4 ZRAM1 and ZRAM2Input: A[13:0], ID[7:0], ZRAMRD-, ZRAMWR- Output: RD[7:0] (Tri-state)Speed: max read time 30 ns from ZRAMRD- going lowCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.118/46 2007-3-22Power consumption: stand by when both WR- and RD- are inactive, access current as low as possible.ZRAM2 is composed of B1 and B2, and each of them is 2k*8 byte SRAM. B1, B2 and ZRAM1(B0) can be operated independently. It has the following modes:1) MCU running at B0, while DMA[M] read B1 and DMA[N] write B2.B1 and B2 are viseversa. M=1, 2, 3, 4, 5, 6; N=1, 2, 3, 4, 5, 6; M!=N. 2) MCU running at B0+B1+B2 or B0+B1 or B0+B2. IPM and IDM Notes:Power consumption: stand by when both WR- and RD- are inactive, access current is as low as possible. PM/DM can be visited by MCU, DSP , DMA1, DMA2 and DMA5. When DSP visits low(high) bytes of 8Kbytes, MCU/DMA1,2,5 can visit high(low) bytes of 8Kbytes at the same time.3.5 USB2.0 SIE3.5.1 General DescriptionThe Actions USB2.0 device controller is fully compliant with the Universal Serial Bus 2.0 specification. In high-speed mode this device is capable of transmitting or receiving data up to 480Mbps.This high performance USB2.0 device controller integrates USB transceiver, SIE, and provides multifarious interfaces for generic MCU, RAM, ROM and DMA controller. So it is suitable for a variety of peripherals, such as: scanners, printers, mass storage devices, and digital cameras. It is designed to be a cost-effective USB total solution.Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.119/46 2007-3-223.5.2 Features¾ Fully compliant with USB Specification 2.0¾ Supports USB High Speed (480Mb/s) and Full Speed (12Mb/s) ¾ Supports Control, Bulk, Isochronous and Interrupt Transfers¾ Embedded USB high-speed Transceiver which complies with Inter UTMI ¾ Supports DMA interface (16-bit)¾ 2K bytes configurable FIFO for endpoints and provides double buffer to increasethroughput.¾ Supports USB remote wake-up feature¾ Software controlled connection to USB bus for re-enumerationCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.120/46 2007-3-223.5.3 USB Using Memory3.6 NAND Flash InterfaceATJ2091N can support NAND type flash from 32M to 4G bytes.3.7 Key Scan InterfaceKEY Scan Timing ：Cycle 1 Cycle 2KeyOut0KeyOut1KeyOut7T8TT=De-bouncing Time/8Key Scan TimingWhen key scan circuit is enabled, ATJ2091N will scan the keyboard periodically. It drives pin KEYOUTn [n=2…7] scan pulse in turn. When any key is pressed, the corresponding Keyout N will send out the scan pulse. When a key is pressed, pin Keyin N connecting the key will be found low level.There are 12 internal 8-bit registers for key value latch per scan. But only another one register (Key Scan Data Register) for MCU may access key value. Those 12 internal registers are mapped into this register, and an internal pointer is used to point to the current register to return scan data when read. Any IO write to this register will clear the internal register, and the pointer will increase by 1 and point to the next register after read is performed.3.8 LCD InterfaceIt is an ICON LCD control interface. We can operate 4*19 icons using the 10 registersCopyright© Actions Semiconductor Co., Ltd 2007. All rights reserved.Ver. 1.1 21/46 2007-3-22Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.122/46 2007-3-22from 0xc2 to 0xcb.ICON LCD 4*19OFF=V2OFF=V1ON OFF √ 32+1+1+1√√ 122√3 1.732Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.123/46 2007-3-223.9 General Purpose IO PortsATJ2091N has GPOA, GPIOB, GPIOC and GPIOG. They have different functions in different modes.GPIOF1(CE0S=H default)F2(key8*12)F3(ILCD)F4(CE0S=L default)MROM)GPO_A0 GPO_A0/ICEDI GPO_A1 GPO_A1/ICECK GPO_A2 GPO_A2/ICEDO GPO_A3 CE3-/GPOA3/MMC_CMDCE3-/GPOA3GPIO_B0 KEYI0/GPIO_B0 GPIO_B2 KEYI2/GPIO_B2KEYI2/GPIO_B2/SPI_SCKGPIO_B4 KEYO0/GPIO_B4 GPIO_B5 KEYO1/GPIO_B5 KEYO1/GPIO_B5/SPI_MOSIGPIO_C0 GPIO_C0 GPIO_C0/I2C_SCL GPIO_C1 GPIO_C1GPIO_C1/I2C_SDA/SIRQ-GPIO_C2 GPIO_C2 /MMC_SCLK GPIO_C2 GPIO_C2GPIO_G0 GPIO_G0GPIO_G0 GPIO_G0/SEG16 GPIO_G03.10 LOSC/RTCRTC is a 24-bits counter with the following functions; the clock source is LOSC/INTK32.¾ Time ¾ Alarm ¾ TimerCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.124/46 2007-3-22RTC Timer IRQ3.11 HOSC/PLLInput: A[7:0], DI[7:0], IOW-, IOR-, RESET- Output: HCK, PLLCK, CK48MHZATJ2091N supports 24Mhz crystal, and it is the system clock source.A low jitter PLL referenced to 24MHz is used to generate clock for DSP and for serial communication protocols such as USB, UART, etc. The clock used in serial communications is 48MHz. Another PLL referenced to 24MHz is used to generateCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.125/46 2007-3-2222.5792MHz for sample rate 44.1K/22.05KHz/11.025KHz and 24.576MHz for audio sequence of 48khz.3.12 PMU/DC-DCThe power management unit, PMU, includes:1. VDD (for core), VCC (for I/O) DC-DC PFM converter2. VDD regulator3. RC oscillator for one battery DC-DC startup4. IC oscillator for DC-DC controller5. Control management6. Voltage monitor7. External L & CParticular Suggestion: Both DCOP1/2 and internal NMOS are working at the beginningof power up. The unused line should be turned off after level off to reduce power consumption and interference.3.13 A/D, D/A and Headphone Driver3.13.1 D/A InterfaceATJ2091N’s internal D/A is an on-chip Sigma-Delta Modulator, a high performance D/A is composed of it and the D/A analog block referenced to 17.2. The D/A interface support 4-level play back FIFO (8 X 20-bit PCM data for L/R channel and variable sample rates, such as 48K/44.1K/32K/24K/22.05K/16K/12K/11.025K/8KHz. An on-chip PLL2 is used to generate 22.5792MHz from 24MHz to support 44.1K/22.05K/11.025KHz with 256XFS clock for over-sampling, while 24.576MHz supports 48K/32K/24K/16K/12K/8KHzCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.126/46 2007-3-22with 256XFS for over-sampling. D/A Block DiagramInternal D/A can drive earphone directly and the pin PAVCC need a bypass capacitor about 100uF to eliminate the “PENG” when D/A is powered on or off. D/A includes an analog mixer, reference to the ADDA block diagram.Power Amplifier Diagram3.13.2 A/D InterfaceThe internal microphone amplifier has gain for recording. The VMIC pin is the power supply (2.2V) for microphone.The audio A/D is a 18 bits sigma delta Analog-to-Digital Converter. Its input source can be selected from MIC amplifier or external FM or line-in, and it has two FIFO.BATTERY A/D is used for battery voltage monitoring, and the voltage range is 0.7~2.2V.LRADC1 works as line controller, and the voltage range is 0.7~2.2V. When LRADC1 PAD voltage<2.0V, it will send an interrupt request to MCU to reduce MCU’s dealing time to line controller.Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.127/46 2007-3-224. Electrical Characteristics4.1 Absolute Maximum RatingsParameter SymbolTypicalRatingUnitVDD 1.6 -0.3~2.0 V Supply voltage VCC 3.0 -0.3~3.6 V Input voltage V I -0.3~3.6 V Storage temperature T stg 25-65~150 ℃Note:1. T O = 25℃（Operating Temperature ）2. Do not short-circuit two or more output pins simultaneously.3. If even one of the above parameters exceeds the absolute maximum ratings even momentarily, the quality of the product may be degraded. The absolute maximum ratings, therefore, specify the value exceeding which the product may be physically damaged. Use the product well within these ratings.4. The specifications and conditions shown in DC Characteristics and AC characteristics are the ranges for normal operation and quality assurance of the product.4.2 CapacitanceCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.128/46 2007-3-22Parameter Symbol Condition MIN. MAX. UnitInput capacitance C I 15 pF I/O capacitanceC IOf C = 1 MHz Unmeasured pins returned to 0 V15 pFNote: T O = 25℃, VCC = 0 V.4.3 DC CharacteristicsParameter SymbolConditionMIN.TYP .MAX.UnitHigh-level outputvoltage V OHI OH = -2 mA2.4VLow-level outputvoltageV OLI OL = 2 mA0.4VHigh-level input voltage V IH 0.6*VCC VCC+0.6 VLow-level input voltage V IL -0.3 0.4*VCC V Input leakage current I LIVCC = 3.6 V, VI = VCC, 0 V +5 uA Tri-State leakagecurrentI LOVCC = 3.6 V, VI = VCC, 0 V+3 uA I drive1 GPOA0,GPOA1,GPOA24mAI drive2GPIO_B2, GPIO_B4,GPIO_B510 mAGPIO DriveI drive3 OtherGPIO 2 mASupply Current （One battery mode ）I VDDIn Full speed mode(MCU run 24MHz ininternal SRAM, DSP run 36MIPS)13.5 14.5 18 mACopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.129/46 2007-3-22In Standby mode 30 45 60 uAIn Full speed mode (MCU run 24MHz ininternal SRAM, DSPrun 36MIPS) 0.15 0.21mAI VCCIn Standby mode506070uANOTES:1. T o = -10 to +70, VDD = ℃ 1.6 V, VCC = 3.0 V2. I VDD is a total power supply current for the 1.6 V power supply. I VDD is applied to theLOGIC and PLL and OSC block.3. I VCC is a total power supply current for the 3.0 V power supply. I VCC is applied to the USB, IO and AD block.4.4 AC CharacteristicsT o = -10 to +70℃4.4.1 AC Test Input Waveform4.4.2 AC Test Output Measuring PointsAll Input Pins。