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Low Voltage, 300 MHz Quad 2:1 Mux AnalogHDTV Audio/Video SwitchADG794 Rev. BInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.FEATURESBandwidth: 300 MHzLow insertion loss and on resistance: 5 Ω typicalOn-resistance flatness: 0.7 Ω typicalSingle 3.3 V/5 V supply operationLow quiescent supply current: 1 nA typicalFast switching timest ON, 7 nst OFF, 5 nsTTL/CMOS compatibleESD protection2 kV human body model (HBM)200 V machine model (MM)1 kV field-induced charged device model (FICDM)APPLICATIONSRGB switchesHDTVDVD-RAudio/video switches FUNCTIONAL BLOCK DIAGRAMS4AS4BD1D2D3D4515-1Figure 1.GENERAL DESCRIPTIONThe ADG794 is a monolithic CMOS device comprising four2:1 multiplexers/demultiplexers with high impedance outputs. The CMOS process provides low power dissipation yet gives high switching speed and low on resistance. The on-resistance variation is less than 1.2 Ω over the input signal range.The wide bandwidth of the ADG794 (300 MHz typical), coupled with low distortion (0.18% typical), makes the part suitable for switching analog audio/video signals.The ADG794 operates from a single 3.3 V/5 V supply and is TTL logic compatible. The switches are controlled by the logic inputs IN and EN, as shown in Table 4. The EN pin allows the user to disable all switches.These switches conduct equally well in both directions when on.In the off condition, signal levels up to the supplies are blocked. The ADG794 switches exhibit break-before-make switching action. The ADG794 is available in a 16-lead QSOP. PRODUCT HIGHLIGHTS1. Wide bandwidth: 300 MHz.2. Ultralow power dissipation.3. Crosstalk: −70 dB (typical) at 10 MHz.4. Off isolation: −65 dB (typical) at 10 MHz.5. ESD protection tested as per ESD Association Standards:2 kV HBM (ANSI/ESD STM5.1-2001)200 V MM (ANSI/ESD STM5.2-1999)1 kV FICDM (ANSI/ESD STM5.3.1-1999)ADG794TABLE OF CONTENTSFeatures (1)Applications (1)Functional Block Diagram (1)General Description (1)Product Highlights (1)Revision History (2)Specifications (3)Single Supply (3)Absolute Maximum Ratings (5)ESD Caution (5)Pin Configuration and Function Descriptions (6)Terminology (7)Typical Performance Characteristics (8)Typical Application (9)Test Circuits (10)Outline Dimensions (12)Ordering Guide (12)REVISION HISTORY2/08—Rev A to Rev BChanges to Absolute Maximum Ratings Section, Table 3 (5)Updated Outline Dimensions (12)Changes to Ordering Guide..........................................................12 4/06—Rev. 0 to Rev. AChanges to Features Section (1)Changes to Product Highlights Section (1)Changes to Specifications Section (3)Changes to Typical Performance Characteristics (8)10/04—Revision 0: Initial VersionADG794SPECIFICATIONSSINGLE SUPPLYV DD = 5 V ± 10%, GND = 0 V. All specifications T MIN to T MAX, unless otherwise noted.1 Temperature range for B version is −40°C to +85°C.2 Guaranteed by design, not subject to production test.ADG794V DD = 3 V ± 10%, GND = 0 V. All specifications T MIN to T MAX, unless otherwise noted.1 Temperature range for B version is −40°C to +85°C.2 Guaranteed by design, not subject to production test.ADG794 ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted.Table 3.Parameters Ratings V DD to GND −0.3 V to +6 VAnalog, Digital Inputs1−0.3 V to V DD + 0.3 V or 30 mA,whichever occurs first Continuous Current, S or D 100 mAPeak Current, S or D 300 mA (pulsed at 1 ms,10% duty cycle maximum) Operating Temperature RangeIndustrial (B Version) −40°C to +85°CStorage Temperature Range −65°C to +150°CJunction Temperature 150°CQSOP Package, Power Dissipation 566 mWθJA Thermal Impedance 149.97°C/WLead Temperature, SolderingReflow, Peak Temperature 260(+0/−5)°CTime at Peak Temperature 20 sec to 40 sec1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditionsabove those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Only one absolute maximum rating may be applied at any one time. ESD CAUTIONADG794PIN CONFIGURATION AND FUNCTION DESCRIPTIONSS1AS1B D1D2S2B S2A IN S4A S4B S3B GND D3S3A D4V DD 05150-002Figure 2. Pin ConfigurationADG794 TERMINOLOGYV DDMost positive power supply potential.I DDPositive supply current.GNDGround (0 V) reference.SSource terminal. Can be either an input or an output.DDrain terminal. Can be either an input or an output.INLogic control input.V D (V S)Analog voltage on Terminal D and Terminal S.R ONOhmic resistance between Terminal D and Terminal S.R FLAT (ON)Flatness is defined as the difference between the maximum and minimum value of on resistance as measured.ΔR ONOn-resistance match between any two channels.I S (Off)Source leakage current with the switch off.I D (Off)Drain leakage current with the switch off.I D, I S (On)Channel leakage current with the switch on.V INLMaximum input voltage for Logic 0.V INHMinimum input voltage for Logic 1.I INL (I INH)Input current of the digital input. C S (Off)Off switch source capacitance. Measured with reference to ground.C D (Off)Off switch drain capacitance. Measured with reference to ground.C D, C S (On)On switch capacitance. Measured with reference to ground.C INDigital input capacitance.t ONDelay time between the 50% and the 90% points of the digital input and switch on condition.t OFFDelay time between the 50% and the 90% points of the digital input and switch off condition.t BBMOn or off time measured between the 80% points of both switches when switching from one to another.Charge InjectionA measure of the glitch impulse transferred from the digital input to the analog output during on/off switching.Off IsolationA measure of unwanted signal coupling through an off switch. CrosstalkA measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.−3 dB BandwidthThe frequency at which the output is attenuated by 3 dB.On ResponseThe frequency response of the on switch.Insertion LossThe loss due to the on resistance of the switch.THD + NThe ratio of the harmonic amplitudes plus the noise of a signal to the fundamental.ADG794TYPICAL PERFORMANCE CHARACTERISTICS–110–90–70–50–30–100.1100005150-003FREQUENCY (MHz)O F F I S O L A T I O N (d B)110100Figure 3. Off Isolation vs. Frequency 0–1200.1100005150-004FREQUENCY (MHz)C R O S S T A L K (d B )110100–20–40–60–80–100Figure 4. Crosstalk vs. Frequency 0–100.1100005150-015FREQUENCY (MHz)A T T E N U A T I O N (dB )110100–1–2–3–4–5–6–7–8–9Figure 5. Bandwidth4.500505150-016INPUT VOLTAGE (V)O U T P U T V O L T A G E (V ).04.03.53.02.52.01.51.00.50.5 1.01.52.0 2.53.0 3.54.0 4.5Figure 6. Output Voltage vs. Input VoltageADG794 TYPICAL APPLICATIONFigure 7. Audio/Video SwitchADG794TEST CIRCUITSVV S05150-00705150-008Figure 8. On Resistance Figure 9. Off LeakageFigure 10. On LeakageVV V OUT05150-009Figure 11. Switching TimesV V INV OUTV 05150-01Figure 12. Break-Before-Make Time Delay05150-011Figure 13. Bandwidth05150-012Figure 14. Off IsolationFigure 15. Channel-to-Channel CrosstalkS1A S1B S2A S2B S3A S3B S4A S4BFigure 16. Charge InjectionOUTLINE DIMENSIONSCOMPLIANT TO JEDEC STANDARDS MO-137-AB012808-ACONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES)ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.0.008 (0.20)Figure 17. 16-Lead Shrink Small Outline Package [QSOP](RQ-16)Dimensions shown in inches and (millimeters)ORDERING GUIDEModelTemperature Range Package DescriptionPackage Option ADG794BRQZ 1−40°C to +85°C 16-Lead Shrink Small Outline Package (QSOP) RQ-16 ADG794BRQZ-500RL71 −40°C to +85°C 16-Lead Shrink Small Outline Package (QSOP) RQ-16 ADG794BRQZ-REEL 1 −40°C to +85°C 16-Lead Shrink Small Outline Package (QSOP) RQ-16 ADG794BRQZ-REEL71−40°C to +85°C 16-Lead Shrink Small Outline Package (QSOP) RQ-161Z = RoHS Compliant Part.©2004–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05150-0-2/08(B)。

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adg命令详细解析

adg命令详细解析

adg命令详细解析一、adg命令简介adg命令是一种在计算机系统中常用的命令，用于进行一些与图形相关的操作。

通过adg命令，用户可以实现绘制图形、编辑图形、调整图形属性等功能。

本文将详细解析adg命令的用法和功能。

二、adg命令的基本语法adg命令的基本语法如下：adg [选项] [参数]三、adg命令的常用选项和参数1. -draw该选项用于指定要执行的绘图操作。

用户可以通过该选项绘制各种形状的图形，如线段、矩形、圆形等。

例如，执行以下命令可以绘制一条直线：adg -draw line 10 10 100 1002. -fill该选项用于指定图形的填充颜色。

用户可以通过该选项设置图形的填充颜色，使图形更加鲜明、美观。

例如，执行以下命令可以设置图形的填充颜色为红色：adg -fill red3. -size该选项用于指定图像的大小。

用户可以通过该选项设置图像的宽度和高度，以满足不同需求。

例如，执行以下命令可以设置图像的大小为800x600像素：adg -size 800x6004. -output该选项用于指定输出图像的文件名。

用户可以通过该选项设置输出图像的文件名和格式，以保存生成的图像。

例如，执行以下命令可以将生成的图像保存为output.png文件：adg -output output.png四、adg命令的实际应用adg命令在实际应用中具有广泛的用途，可以用于绘制各种图形、生成数据可视化图表等。

以下是adg命令的一些常见应用场景：1. 绘制统计图表adg命令可以根据给定的数据生成各种统计图表，如柱状图、折线图、饼图等。

用户可以通过指定数据和图表类型，使用adg命令绘制出符合需求的统计图表，用于数据分析和展示。

2. 制作网络拓扑图adg命令可以用于制作网络拓扑图，用户可以根据网络拓扑结构和设备连接关系，使用adg命令绘制出清晰明了的网络拓扑图，方便网络管理和故障排查。

3. 绘制流程图adg命令可以用于绘制各种流程图，如业务流程图、程序流程图等。

JTT794-2011部标过检厂家第四批(蓝斯通信)

JTT794-2011部标过检厂家第四批(蓝斯通信)


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jb7940标准

jb7940标准

jb7940标准一、引言本标准规定了jb7940型避雷器的技术要求、检验规则、安装要求、运行要求、试验方法、包装、运输和贮存等方面的内容。

本标准适用于交流电力系统中使用的jb7940型避雷器。

二、范围本标准适用于额定电压为110kv~500kv的交流电力系统中使用的jb7940型避雷器。

三、规范性引用文件下列文件对于本文件的应用是必不可少的。

凡是注日期的引用文件，仅注日期的版本适用于本文件。

凡是不注日期的引用文件，其最新版本（包括所有的修改单）适用于本文件。

gb 11032-2010 交流无间隙金属氧化物避雷器dl/t 846.1~6-2004 高压测试设备通用技术条件dl/t 596-1999 电力设备预防性试验规程四、术语和定义下列术语和定义适用于本文件。

1.避雷器：用于保护电气设备免受雷电过电压和操作过电压危害的并联器件。

2.工频参考电压：在规定的参考温度下，避雷器在工频电压下的最大持续运行电压。

3.标称放电电流：避雷器在规定条件下的最大非重复放电电流。

4.雷电冲击残压：在避雷器接通被保护设备的两个端点上测得的最大雷电冲击电压峰值。

5.操作冲击残压：避雷器在接通被保护设备的两个端点上测得的最大操作冲击电压峰值。

五、检验规则1.避雷器应按照本标准的要求进行检验，并符合相关国家和行业标准的规定。

2.避雷器的检验分为出厂检验和型式检验。

出厂检验应按照相关国家和行业标准的规定进行，并应符合本标准的要求。

型式检验应由国家认可的检测机构进行，并应符合本标准的要求。

3.避雷器的检验周期应根据其使用环境和运行情况确定，一般每年进行一次常规检验。

对于重要设备和特殊环境下的避雷器，应适当增加检验频次。

4.避雷器的检验项目应包括外观检查、绝缘电阻试验、工频参考电压试验、标称放电电流试验、雷电冲击残压试验、操作冲击残压试验等。

对于不同型号和规格的避雷器，还应根据其特性和使用要求进行其他必要的试验项目。

5.避雷器的检验结果应符合相关国家和行业标准的规定，并应满足本标准的要求。

ANALOG DEVICES AN-794 APPLICATION NOTE 数据手册

ANALOG DEVICES AN-794 APPLICATION NOTE 数据手册

AN-794APPLICATION NOTEOne Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/461-3113 • INTRODUCTIONThe AD9980 incorporates an auto-offset function. The auto-offset works by calculating the required offset set-ting to yield a given output code during clamp. When auto-offset is enabled (reg. 0x1B:5 = 1), the settings in Registers 0x0B to 0x10 are used by the auto-offset cir-cuitry as desired clamp codes (or target codes) rather than as an offset value. The circuit compares the output code after clamp (but still during the back porch ) to the target code and adjusts the offset up or down to com-pensate. In auto-offset mode, the target code is an 11-bit twos complement word, with Bit 7 of 0x0B being the sign bit for the red channel (Bit 7 of 0x0D for green; Bit 7 of 0x0F for blue).CHANGES TO REGISTER DEFINITIONSThe definition of registers 0x0B to 0x10 changes depend-ing on whether the auto-offset function is enabled ornot. The following figures describe these differences.Figure 1. AD9980 with Auto-Offset Disabled• Each set of registers consist of seven bits (binary nota-tion) that are used to adjust the offset of the ADC.Figure 2. AD9980 with Auto-Offset Enabled• Each set of registers consist of nine bits (twos com-plement notation) that are used to adjust the target code of the ADC’s output after clamp.Implementing the Auto-Offset Function on the AD9980by Del JonesBrightness AdjustmentIf auto-offset is disabled, the lower nine bits of the off-set registers control the absolute offset added to the channel. The offset control provides a +63/–64 LSB of adjustment range, with 1 LSB of offset corresponding to 1 LSB of output code.With auto-offset enabled, registers 0x0B to 0x10 now contain target codes instead of offset values. These registers can still be used to adjust brightness. The dif-ference is that when auto-offset is enabled, the exact black code output is now being adjusted so that the user knows exactly what code the black level is being set to. This is particularly useful for applications that desire to match NTSC or other video specifications that use less than full-scale code ranges. For example, if there is a requirement to only use 75% of the code range (code range of 32 to 224) for the Y input of a component video system, the Y (green) target code can be set to 128 and the gain adjusted to achieve the 224 maximum output code. When developing software to control brightness, this must be taken into consideration.T arget Code Value RestrictionsEven though there are nine bits in the target code reg-isters (eight bits plus one sign bit), there are only seven bits of actual adjustment range. Also, a target code of 0 is invalid. Therefore, the range of valid target codes is as follows:• For ground-clamped inputs –63 (1 1100 0001) to –1 (1 1111 1111) 1 (0 0000 0001) to +63 (0 0111 1111)• For midscale-clamped inputs 64 (1 0100 0000) to 191 (0 1011 1111)This should also be taken into consideration when developing software for brightness control.REV. 0AN-794USING AUTO-OFFSETTo activate the auto-offset mode, set register 0x1B, Bit 5 to 1. Next, the target code registers (0x0B to 0x10) must be programmed. The values programmed into the target code registers should be the output code desired from the AD9980 during the back porch reference time. For example, for RGB signals all three registers would normally be programmed to a very small code (4 is recommended but any code between ±63, except 0, is valid), while for YPbPr signals the green (Y) channel would normally be programmed to a very small code (4), and the blue and red channels (Pb and Pr) would normally be set to 128. For midscale-clamped inputs, any target code value between 64 and 192 is valid, although the AD9980’s offset range may not be able to reach every value. Example register settings for the auto-offset mode are shown in Table I.The ability to program a target code for each channel gives users a large degree of freedom and flexibility. While, in most cases, all channels will be set either to 4 or 128, the flexibility to select other values allows for the possibility of inserting intentional skews between channels. It also allows for the ADC range to be skewed so that voltages outside of the normal range can be digi-tized. (For example, setting the target code to 40 would allow the sync tip, which is normally below black level, to be digitized and evaluated.)T able I. Example Register Settings for Enabling Auto-OffsetRGB Auto-Offset Clamping YPbPr Auto-Offset ClampingReg. Value Description Value DescriptionRx0B 0x02 Red Offset MSB Red T arget 0x40 Red Offset MSB Red T argetRx0C 0x00 Red Offset LSB Code = +4 0x00 Red Offset LSB Code = +128dRx0D 0x02 Green Offset MSB Green T arget 0x02 Green Offset MSB Green T argetRx0E 0x00 Green Offset LSB Code = +4 0x00 Green Offset LSB Code = +4Rx0F 0x02 Blue Offset MSB Blue T arget 0x40 Blue Offset MSB Blue T argetRx10 0x00 Blue Offset LSB Code = +4 0x00 Blue Offset LSB Code = +128dRx18 **** 000* Bits 3:1 = ‘000’. T his sets all three **** 101* Bits 3:1 = ‘101’. T his sets all Red and Bluechannels to ground clamp. channels to midscale clamp and the Greenchannel to ground clamp.Rx1B **1* **** Bits 5 = ‘1’. T his enables the auto- **1* **** Bits 5 = ‘1’. T his enables the auto-offset clamping. offset clamping.Rx1B ***x x*** Bits 4:3 = ‘10’. T his sets the auto- ***x x*** Bits 4:3 = ‘10’. T his sets the auto-offset circuit to operate each 64 offset circuit to operate each 64clamps. ‘00’ = every clamp; ‘01’ = clamps. ‘00’ = every clamp; ‘01’ =16 clamps; ‘11’ = every V SYNC. 16 clamps; ‘11’ = every V SYNC.REV. 0–2––3–AN-794Clamp TimingThe internal logic for the auto-offset circuit requires from 16 to 40 data clock cycles (programmable in 8-clock steps via Bits 4:3 of Register 0x2E) to perform its function. This operation is executed immediately after the clamping signal is deactivated. Therefore, it is important to deactivate the clamp signal at least 16 to 40 (depending on 0x2E – 4:3) data clock cycles before active video. This is true whether using the AD9980’s internal clamp circuit or an external clamp signal. See Figure 3. Therefore, given these requirements, it must be ensured thatClamp Placement + Clamp Duration + Auto-OffsetEvaluation Time < Back Porch Time Or, referring to Figure 3B +C +D < AThe definition of Bits 4:3 of Register 0x2E is shown in Table II. To provide the maximum amount of clamping time, it is recommended to program these bits to 00.T able II. Auto-Offset Evaluation Time Register Bit Definition Register Bits Description 0x2E 4:3 Auto-Offset Evaluation T ime 00 = 16 clocks 01 = 24 clocks 10 = 32 clocks11 = 40 clocksRECOMMENDED PROCEDURESAuto-Offset in Continuous Update Mode 1. Set registers to enable auto-offseta.0x1B[5] = **11 1011—This enables AO with update every V SYNCb.0x20[0] = 1c.0x29[1] = 0d.0x2E[4:3] = 00—Select shortest “Evaluation Time”2.Set appropriate target code and clamp settings Auto-Offset in Hold Mode1. Set registers to enable auto-offseta.0x1B[5] = **11 1011—This enables AO with update every 64 clampsb.0x20[0] = 1c.0x29[1] = 0d.0x2E[4:3] = 00—Select shortest “Evaluation Time”2.Set appropriate target code and clamp settings 3.Let run for at least 10 V SYNC periods (~0.5 seconds)4.Set the “Hold Auto-Offset” bit (0x2C[4]) to 15.Restart at mode changea.May need updating under extreme environmental conditions in some applications�����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Figure 3. Clamp T iming RequirementsREV. 0A N 05555–0–8/05(0)–4–© 2005 Analog Devices, Inc. All rights reserved. T rademarks and registered trademarks are the property of their respective owners.。