AD7685

3 mW, 100 kSPS,14-Bit ADC in 6-Lead SOT-23AD7940 Rev.0Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESFast throughput rate: 100 kSPSSpecified for V DD of 2.5 V to 5.5 VLow power4 mW typ at 100 kSPS with 3 V supplies17 mW typ at 100 kSPS with 5 V supplies Wide input bandwidth:81 dB SINAD at 10 kHz input frequency Flexible power/serial clock speed management No pipeline delaysHigh speed serial interfaceSPI®/QSPI™/MICROWIRE™/DSP compatible Standby mode: 0.5 µA max6-Lead SOT-23 and 8-Lead MSOP packages APPLICATIONSBattery-powered systemsPersonal digital assistantsMedical instrumentsMobile communicationsInstrumentation and control systemsRemote data acquisition systemsFUNCTIONAL BLOCK DIAGRAM335--1V INSCLKSDATACSFigure 1.Table 1. 16-Bit and 14-Bit ADC (MSOP and SOT-23)Type 100 kSPS 250 kSPS 500 kSPS 16-Bit True Differential AD7684AD7687AD7688 16-Bit Pseudo Differential AD7683AD7685AD7686 16-Bit Unipolar AD768014-Bit True Differential AD7944AD7947 14-Bit Pseudo Differential AD7942AD7946 14-Bit Unipolar AD7940GENERAL DESCRIPTIONThe AD79401 is a 14-bit, fast, low power, successive approxima-tion ADC. The part operates from a single 2.50 V to 5.5 V power supply and features throughput rates up to 100 kSPS. The part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz.The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipelined delays associated with the part. The AD7940 uses advanced design techniques to achieve very low power dissipation at fast throughput rates. The reference for the part is taken internally from V DD, which allows the widest dynamic input range to the ADC. Thus, the analog input range for this part is 0 V to V DD. The conversion rate is determined by the SCLK frequency.1 Protected by U.S. Patent No. 6,681,332. This part features a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.PRODUCT HIGHLIGHTS1.First 14-bit ADC in a SOT-23 package.2.High throughput with low power consumption.3.Flexible power/serial clock speed management. The con-version rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clockspeed increase. This allows the average power consumption to be reduced when a power-down mode is used while not converting. The part also features a shutdown mode tomaximize power efficiency at lower throughput rates.Power consumption is 0.5 µA max when in shutdown.4.Reference derived from the power supply.5.No pipeline delay.AD7940Rev. 0 | Page 2 of 20TABLE OF CONTENTSSpecifications.....................................................................................3 Timing Specifications.......................................................................5 Absolute Maximum Ratings............................................................6 ESD Caution..................................................................................6 Pin Configurations and Function Descriptions...........................7 Terminology......................................................................................8 Typical Performance Characteristics.............................................9 Circuit Information........................................................................11 Converter Operation..................................................................11 Analog Input...............................................................................11 ADC Transfer Function.................................................................12 Typical Connection Diagram...................................................12 Modes of Operation.......................................................................13 Normal Mode..............................................................................13 Power-Down Mode....................................................................14 Power vs. Throughput Rate...........................................................15 Serial Interface................................................................................16 Microprocessor Interfacing...........................................................17 AD7940 to TMS320C541..........................................................17 AD7940 to ADSP-218x..............................................................17 AD7940 to DSP563xx................................................................18 Application Hints...........................................................................19 Grounding and Layout..............................................................19 Evaluating the AD7940 Performance......................................19 Outline Dimensions.......................................................................20 Ordering Guide.. (20)REVISION HISTORY6/04—Revision 0: Initial VersionAD7940Rev. 0 | Page 3 of 20SPECIFICATIONS 1V DD = 2.50 V to 5.5 V , f SCLK = 2.5 MHz, f SAMPLE = 100 kSPS, unless otherwise noted; T A = T MIN to T MAX , unless otherwise noted. Table 2.Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f IN = 10 kHz sine wave Signal-to-Noise + Distortion (SINAD)281 dB minTotal Harmonic Distortion (THD)2−98 dB typ Peak Harmonic or Spurious Noise (SFDR)2 −95 dB typIntermodulation Distortion (IMD)2Second-Order Terms −94 dB typ Third-Order Terms −100 dB typ Aperture Delay 20 ns max Aperture Jitter 30 ps typ Full Power Bandwidth 7 MHz typ @ −3 dB 2 MHz typ @ −0.1 dB DC ACCURACY Resolution 14 Bits min V DD = 2.5 V to 4.096 V 13 Bits min V DD > 4.096 VIntegral Nonlinearity 2±1 LSB max V DD = 2.5 V to 4.096 V ±2 LSB max V DD > 4.096 VOffset Error 2±6 LSB maxGain Error 2±8 LSB max ANALOG INPUT Input Voltage Ranges 0 to V DD V DC Leakage Current ±0.3 µA max Input Capacitance 30 pF typ LOGIC INPUTS Input High Voltage, V INH 2.4 V min Input Low Voltage, V INL 0.4 V max V DD = 3 V0.8 V max V DD = 5 V Input Current, I IN ±0.3 µA max Typically 10 nA, V IN = 0 V or V DDInput Capacitance, C IN 2, 310 pF max LOGIC OUTPUTS Output High Voltage, V OH V DD – 0.2 V min I SOURCE = 200 µA; V DD = 2.50 V to 5.25 V Output Low Voltage, V OL 0.4 V max I SINK = 200 µA Floating-State Leakage Current ±0.3 µA maxFloating-State Output Capacitance 2, 310 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 8 µs max 16 SCLK cycles Track-and-Hold Acquisition Time 500 ns max Full-scale step input 400 ns max Sine wave input ≤ 10 kHz Throughput Rate 100 kSPS max See the Serial Interface section POWER REQUIREMENTS V DD 2.50/5.5 V min/V max I DD Digital I/P S = 0 V or V DDNormal Mode (Static) 5.2 mA max V DD = 5.5 V; SCLK on or off 2 mA max V DD = 3.6 V; SCLK on or off Normal Mode (Operational) 4.8 mA max V DD = 5.5 V; f SAMPLE = 100 kSPS; 3.3 mA typ 1.9 mA max V DD = 3.6 V; f SAMPLE = 100 kSPS; 1.29 mA typ Full Power-Down Mode 0.5 µA max SCLK on or off. V DD = 5.5 V 0.3 µA max SCLK on or off. V DD = 3.6 VAD7940Rev. 0 | Page 4 of 20Parameter B Version Unit Test Conditions/CommentsPower Dissipation 4V DD = 5.5 V Normal Mode (Operational) 26.4 mW max V DD = 5.5 V; f SAMPLE = 100 kSPS 6.84 mW max V DD = 3.6 V; f SAMPLE = 100 kSPS Full Power-Down 2.5 µW max V DD = 5.5 V 1.08 µW max V DD = 3.6 V1 Temperature range for B Version is –40°C to +85°C. 2See the section. Terminology 3Sample tested at initial release to ensure compliance. 4See the section.Power vs. Throughput RateAD7940Rev. 0 | Page 5 of 20TIMING SPECIFICATIONSSample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD ) and timed from a voltage level of 1.6 V .V DD = 2.50 V to 5.5 V; T A = T MIN to T MAX , unless otherwise noted.1 Mark/space ratio for the SCLK input is 40/60 to 60/40.2Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.0 V. Figure 2Figure 2.3t 8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 4See the section.Power vs. Throughput Rate03305-0-0021.6VFigure 2. Load Circuit for Digital Output Timing SpecificationAD7940Rev. 0 | Page 6 of 20ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 4.Parameter RatingV DD to GND −0.3 V to +7 VAnalog Input Voltage to GND −0.3 V to V DD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 VDigital Output Voltage to GND −0.3 V to V DD + 0.3 VInput Current to Any Pin Except Supplies 1±10 mAOperating Temperature RangeCommercial (B Version) −40°C to +85°CStorage Temperature Range −65°C to +150°CJunction Temperature 150°CSOT-23 Package, Power Dissipation 450 mWθJA Thermal Impedance 229.6°C/WθJC Thermal Impedance 91.99°C/W MSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 205.9°C/W θJC Thermal Impedance 43.74°C/W Lead Temperature, Soldering Vapor Phase (60 secs) 215°C Infared (15 secs) 220°C ESD 4 kV1Transient currents of up to 100 mA will not cause SCR latch-up.Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rat-ing only; functional operation of the device at these or anyother conditions above those listed in the operational sectionsof this specification is not implied. Exposure to absolute maxi-mum rating conditions for extended periods may affect devicereliability.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.AD7940Rev. 0 | Page 7 of 20PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS03305-0-023V DD GND V IN SOT-23Figure 3. SOT-23 Pin Configuration03305-0-003NC = NO CONNECTMSOPV DD GND GND V INFigure 4. MSOP Pin ConfigurationAD7940Rev. 0 | Page 8 of 20TERMINOLOGYIntegral NonlinearityThis is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end-points of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition.Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset ErrorThis is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB.Gain ErrorThis is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., V REF − 1 LSB) after the offset error has been adjusted out.Track-and-Hold Acquisition TimeThe track-and-hold amplifier returns to track mode at the end of conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of the conversion. See the Serial Interface section for more details.Signal-to-(Noise + Distortion) RatioThis is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S /2, excluding dc). The ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given bySignal-to-(Noise + Distortion ) = (6.02 N + 1.76) dB Thus, for a 14-bit converter, this is 86.04 dB.Total Harmonic Distortion (THD)THD is the ratio of the rms sum of harmonics to the funda-mental. For the AD7940, it is defined as12625242322V V V V V V log20(dB)++++=THDwhere V 1 is the rms amplitude of the fundamental and V 2, V 3, V 4, V 5, and V 6 are the rms amplitudes of the second through the sixth harmonics.Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f S /2, excluding dc) to the rms value of the fun-damental. Normally, the value of this specification is deter-mined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion prod-ucts at sum and difference frequencies of mfa ± nfb where m , n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa −2fb).The AD7940 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.AD7940Rev. 0 | Page 9 of 20TYPICAL PERFORMANCE CHARACTERISTICSFigure 5 shows a typical FFT plot for the AD7940 at 100 kSPS sample rate and 10 kHz input frequency. Figure 6 shows the signal-to-(noise + distortion) ratio performance versus the input frequency for various supply voltages while sampling at 100 kSPS with an SCLK of 2.5 MHz. Figure 7 shows a graph of the total harmonic distortion versus the analog input frequency for various supply voltages, while Figure 8 shows a graph of the total harmonic distortion versus the analog input frequency for various source impedances (see the Analog Input section). Figure 9 and Figure 10 show the typical INL and DNL plots for the AD7940.03305-0-019(d B )–140–120–100–80–60–40–20–160010k 20k 30k 40k FREQUENCY (kHz)50k0V DD = 4.75VF SAMPLE = 100kSPS F IN = 10kHz SNR = 84.48dB SINAD = 84.35dB THD =–98.97dB SFDR =–100.84dBFigure 5. AD7940 Dynamic Performance at 100 kSPS03305-0-020S I N A D (d B )80857510INPUT FREQUENCY (kHz)10090Figure 6. AD7940 SINAD vs. Analog Input Frequencyfor Various Supply Voltages at 100 kSPS 03305-0-021T H D (d B )901008010INPUT FREQUENCY (kHz)1001108595105Figure 7. AD7940 THD vs. Analog Input Frequencyfor Various Supply Voltages at 100 kSPS03305-0-022TH D (d B )90100707510INPUT FREQUENCY (kHz)100110858095105Figure 8. AD7940 THD vs. Analog Input Frequencyfor Various Source ImpedancesAD7940Rev. 0 | Page 10 of 2003305-0-018I N L E R R O R (L S B )–0.4–0.200.20.40.60.8–0.60200040006000800010000120001400016000CODE180001.0 Figure 9. AD7940 Typical INL03305-0-017D N LE R R O R (L S B )–0.6–0.4–0.200.20.40.6–0.80200040006000800010000120001400016000CODE180000.8V DD = 3.00V TEMP = 25°CFigure 10. AD7940 Typical DNLCIRCUIT INFORMATIONThe AD7940 is a fast, low power, 14-bit, single-supply ADC. The part can be operated from a 2.50 V to 5.5 V supply. When operated at either 5 V or 3 V supply, the AD7940 is capable of throughput rates of 100 kSPS when provided with a 2.5 MHz clock. The AD7940 provides the user with an on-chip track-and-hold ADC and a serial interface housed in a tiny 6-lead SOT-23 package or in an 8-lead MSOP package, which offer the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part and also pro-vides the clock source for the successive approximation ADC. The analog input range for the AD7940 is 0 V to V DD . An external reference is not required for the ADC nor is there a reference on-chip. The reference for the AD7940 is derived from the power supply and thus gives the widest dynamic input range.The AD7940 also features a power-down option to save power between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section.CONVERTER OPERATIONThe AD7940 is a 14-bit, successive approximation ADC based around a capacitive DAC. The AD7940 can convert analog input signals in the 0 V to V DD range. Figure 11 and Figure 12 show simplified schematics of the ADC. The ADC comprises of control logic, SAR, and a capacitive DAC. Figure 11 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected V IN channel.03305-0-004V INFigure 11. ADC Acquisition PhaseWhen the ADC starts a conversion, SW2 will open and SW1 will move to Position B, causing the comparator to become unbalanced (Figure 12). The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code (see the ADC Transfer Function section). 03305-0-005V INFigure 12. ADC Conversion PhaseANALOG INPUTFigure 13 shows an equivalent circuit of the analog input struc-ture of the AD7940. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV . This will cause these diodes to become forward-biased and to start conducting current into the sub-strate. The maximum current these diodes can conduct without causing irreversible damage to the part is 10 mA. Capacitor C1 in Figure 13 is typically about 5 pF and primarily can be attrib-uted to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch (track-and-holdswitch). This resistor is typically about 25 Ω. Capacitor C2 is the ADC sampling capacitor and has a capacitance of 25 pF typi-cally. For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC low-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac per-formance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be toler-ated. The THD will increase as the source impedance increases, and performance will degrade (see Figure 8).03305-0-006V VFigure 13. Equivalent Analog Input CircuitADC TRANSFER FUNCTIONThe output coding of the AD7940 is straight binary. The de-signed code transitions occur at successive integer LSB values, i.e., 1 LSB, 2 LSBs. The LSB size is V DD /16384. The ideal transfer characteristic for the AD7940 is shown in Figure 14.03305-0-007000 (000)111 (111)ANALOG INPUT000...001000 (010)Figure 14. AD7940 Transfer CharacteristicTYPICAL CONNECTION DIAGRAMFigure 15 shows a typical connection diagram for the AD7940. V REF is taken internally from V DD and as such should be well decoupled. This provides an analog input range of 0 V to V DD . The conversion result is output in a 16-bit word. This 16-bit data stream consists of two leading zeros, followed by the 14 bits of conversion data, MSB first. For applications where power consumption is a concern, the power-down mode should be used between conversions or bursts of several conversions to improve power performance (see the Modes of Operation section).In fact, because the supply current required by the AD7940 is so low, a precision reference can be used as the supply source to the AD7940. For example, a REF19x voltage reference (REF195 for 5 V or REF193 for 3 V) or an AD780 can be used to supply the required voltage to the ADC (see Figure 15). This configura-tion is especially useful if the power supply available is quite noisy, or if the system supply voltages are at some value other than the required operating voltage of the AD7940, e.g., 15 V . The REF19x or AD780 will output a steady voltage to theAD7940. Recommended decoupling capacitors are a 100 nF low ESR ceramic (Farnell 335-1816) and a 10 µF low ESR tantalum (Farnell 197-130).03305-0-008INTERFACE5VSUPPLYFigure 15. Typical Connection DiagramDigital InputsThe digital inputs applied to the AD7940 are not limited by the maximum ratings that limit the analog inputs. Instead, the digi-tal inputs applied can go to 7 V and are not restricted by the V DD + 0.3 V limit as on the analog inputs. For example, if the AD7940 were operated with a V DD of 3 V , 5 V logic levels could be used on the digital inputs. However, it is important to note that the data output on SDATA will still have 3 V logic levels when V DD = 3 V .Another advantage of SCLK and CS not being restricted by the V DD + 0.3 V limit is the fact that power supply sequencing issues are avoided. If one of these digital inputs is applied before V DD , there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V were applied prior to V DD .MODES OF OPERATIONThe mode of operation of the AD7940 is selected by controlling the (logic) state of the CS signal during a conversion. There are two possible modes of operation, normal and power-down. The point at which CS is pulled high after the conversion has been initiated will determine whether or not the AD7940 will enter power-down mode. Similarly, if already in power-down, CS can control whether the device will return to normal operation or remain in power-down. These modes of operation are designed to provide flexible power management options. These options can optimize the power dissipation/throughput rate ratio for differing application requirements.NORMAL MODEThis mode provides the fastest throughput rate performance because the user does not have to worry about the power-up times with the AD7940 remaining fully powered all the time. Figure 16 shows the general diagram of the operation of the AD7940 in this mode. The conversion is initiated on the falling edge of asdescribed in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS . If CS is brought high any time after the 10th SCLK falling edge, but before the 16th SCLK falling edge, the part will remain powered up, but the conversion will be terminated and SDATA will go back into three-state. At least 16 serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion or may idle low until CS returns high sometime prior to the next conversion, effectively idling CS low.Once a data transfer is complete (SDATA has returned to three-state), another conversion can be initiated after the quiet time, t QUIET , has elapsed by bringing CS low again.03305-0-0091121 LEADING ZERO + CONVERSION RESULTCSSCLK16SDATAFigure 16. Normal Mode OperationPOWER-DOWN MODEThis mode is intended for use in applications where slower throughput rates are required. Either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate, and then the ADC is pow-ered down for a relatively long duration between these bursts of several conversions. When the AD7940 is in power-down, all analog circuitry is powered down.To enter power-down, the conversion process must be inter-rupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK as shown in Figure 17. Once CS has been brought high in this window of SCLKs, the part will enter power-down, theconversion that was initiated by the falling edge of CS will be terminated, and SDATA will go back into three-state. If CS is brought high before the second SCLK falling edge, the part will remain in normal mode and will not power down. This will avoid accidental power-down due to glitches on the CS line. In order to exit this mode of operation and power up the AD7940 again, a dummy conversion is performed. On the fal-ling edge of CS , the device will begin to power up and will continue to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device will be fully powered up once at least 16 SCLKs (or approximately 6 µs) have elapsed and valid data will result from the next conversion as shown in Figure 18. If CS is brought high before the 10th falling edge of SCLK, regardless of the SCLK frequency, the AD7940 will go back into power-down again. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. So although the device may begin to power-up on the falling edge of CS , it will power down again on the rising edge of CS as long as it occurs before the 10th SCLK falling edge.03305-0-010SCLKSDATATHREE-STATECSFigure 17. Entering Power-Down Mode03305-0-011SDATA SCLKCSINVALID DATA VALID DATATHE PART IS FULLY POWEREDFigure 18. Exiting Power-Down Mode。

Rev. 0Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support FET input amplifier1 pA input bias currentLow costHigh speed: 145 MHz, −3 dB bandwidth (G = +1)180 V/µs slew rate (G = +2)Low noise7 nV/√Hz (f = 10 kHz)0.6 fA/√Hz (f = 10 kHz)Wide supply voltage range: 5 V to 24 VSingle-supply and rail-to-rail outputLow offset voltage 1.5 mV maximumHigh common-mode rejection ratio: −100 dBSFDR −88 dBc @ 1 MHzLow power: 6.4 mA/amplifier typical supply current Known good die (KGD): these die are fully guaranteed to data sheet specificationsAPPLICATIONSPhotodiode preampsFiltersA/D driversLevel shiftingBuffering The AD8065-KGD-CHIP FastFET™ amplifier is a voltage feedback amplifier with a FET input offering high performance and ease of use. With a wide supply voltage range from 5 V to 24 V, and the ability to operate on single supplies, with a bandwidth of 145 MHz, the AD8065-KGD-CHIP is designed to work in a variety of applications. For added versatility, the amplifier also features a rail-to-rail output.Despite the low cost, the amplifiers provide excellent overall performance. The differential gain and phase errors of 0.02% and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz, make these amplifiers ideal for video applications. Additionally, they offer a high slew rate of 180 V/µs, excellent distortion (SFDR of −88 dBc at 1 MHz), extremely high common-mode rejection of −100 dB, and a low input offset voltage of 1.5 mV maximum under warmed up conditions. The AD8065-KGD-CHIP operates using only a 6.4 mA/amplifier typical supply current and are capable of delivering up to 30 mA of load current.The AD8065-KGD-CHIP is rated to work over the industrial temperature range of −40°C to +85°C.Additional application and technical information can be found in the AD8065 data sheet.1Protected by U.S. patent numbers 6,486,737B1; 6,518,842B11112 Specifications (3)Absolute Maximum Ratings (5)5677 Ordering Guide (7)REVISION HISTORY10/12—Revision 0: Initial VersionRev. 0 | Page 2 of 8−3 dB Bandwidth G = +1, V O = 0.2 V p-p100 145 GBD1MHzG = +2, V O = 0.2 V p-p 50 MHzG = +2, V O = 2 V p-p 42 MHz Bandwidth for 0.1 dB Flatness G = +2, V O = 0.2 V p-p 7 MHz Input Overdrive Recovery Time G = +1, −5.5 V to +5.5 V 175 ns Output Recovery Time G = −1, −5.5 V to +5.5 V 170 ns Slew Rate G = +2, V O = 4 V step 130 180 GBD1V/µs Settling Time to 0.1% G = +2, V O = 2 V step 55 nsG = +2, V O = 8 V step 205 ns NOISE/HARMONIC PERFORMANCESFDR f C = 1 MHz, G = +2, V O = 2 V p-p −88 dBcf C = 5 MHz, G = +2, V O = 2 V p-p −67 dBcf C = 1 MHz, G = +2, V O = 8 V p-p −73 dBc Third-Order Intercept f C = 10 MHz, R L = 100 Ω 24 dBm Input Voltage Noise f = 10 kHz 7 nV/√Hz Input Current Noise f = 10 kHz 0.6 fA/√Hz Differential Gain Error NTSC, G = +2, R L = 150 Ω 0.02 % Differential Phase Error NTSC, G = +2, R L = 150 Ω 0.02 Degrees DC PERFORMANCEInput Offset Voltage V CM = 0 V 0.4 1.5 Tested mV Input Offset Voltage Drift 1 17 GBD1µV/°C Input Bias Current 2 pAT MIN to T MAX25 pA Input Offset Current 1 pAT MIN to T MAX 1 pA Open-Loop Gain V O = ±3 V, R L = 1 kΩ 100 113 Tested dB INPUT CHARACTERISTICSCommon-Mode Input Impedance 1000 || 2.1 GΩ || pF Differential Input Impedance 1000 || 4.5 GΩ || pF Input Common-Mode Voltage RangeFET Input Range −5 to +1.7 −5.0 to +2.4 GBD1V Common-Mode Rejection Ratio V CM = −1 V to +1 V −85 −100 Tested dB OUTPUT CHARACTERISTICS−4.94 to +4.95 Tested V Output Voltage Swing R L = 1 kΩ −4.88 to+4.9R L = 150 Ω −4.8 to +4.7 V Output Current V O = 9 V p-p, SFDR ≥ −60 dBc,35 mAf = 500 kHzShort-Circuit Current 90 mA Capacitive Load Drive 30% overshoot G = +1 20 pF POWER SUPPLYOperating Range 5 24 Tested V Quiescent Current per Amplifier 6.4 7.2 Tested mA Power Supply Rejection Ratio V S ± 2 V −85 −100 Tested dB1 GBD = Guaranteed By Design.Rev. 0 | Page 3 of 8100 145 1Slew Rate G = +2, V O = 4 V step 130 180 GBD1V/µs DC PERFORMANCEInput Offset Voltage V CM = 0 V 0.4 1.5 Tested mV Input Offset Voltage Drift 1 17 GBD1µV/°C Input Bias Current 3 pA Input Offset Current 2 pA Open-Loop Gain V O = ±10 V 103 114 Tested dB INPUT CHARACTERISTICSInput Common-Mode Voltage RangeFET Input Range −12 to +8.5 −12.0 to +9.5 GBD1V Common-Mode Rejection Ratio V CM = −1 V to +1 V −85 −100 Tested dB OUTPUT CHARACTERISTICSOutput Voltage Swing R L = 1 kΩ −11.8 to +11.8 −11.9 to +11.9 Tested V POWER SUPPLYPower Supply Rejection Ratio V S ± 2 V −84 −93 Tested dB Quiescent Current per Amplifier 6.6 7.4 Tested mA 1 GBD = Guaranteed By Design.V S = +5 V at T A = 30°C, R L = 1 kΩ to midsupply, unless otherwise noted.Table 3.Parameter Test Conditions/Comments Min Typ Max Status Unit DYNAMIC PERFORMANCE−3 dB Bandwidth G = +1, V O = 0.2 V p-p125 155 GBD1MHz Slew Rate G = +2, V O = 2 V step 105 160 GBD1V/µs DC PERFORMANCEInput Offset Voltage V CM = 1.0 V 0.4 1.5 Tested mV Input Offset Voltage Drift 1 17 GBD1µV/°C Input Bias Current 1 pA Input Offset Current 1 pA Open-Loop Gain V O = 1 V to 4 V 100 113 Tested dB INPUT CHARACTERISTICSInput Common-Mode Voltage RangeFET Input Range 0 to 1.7 0 to 2.4 GBD1V Common-Mode Rejection Ratio V CM = 1 V to 2 V −78 −91 Tested dB OUTPUT CHARACTERISTICSOutput Voltage Swing R L = 1 kΩ 0.1 to 4.85 0.03 to 4.95 Tested V POWER SUPPLYPower Supply Rejection Ratio V S ± 2 V −78 −100 Tested dB Quiescent Current per Amplifier 6.4 7.0 Tested mA 1 GBD = Guaranteed by Design.Rev. 0 | Page 4 of 8Differential Input Voltage ±1.8 VStorage Temperature –65°C to +125°COperating Temperature Range –40°C to +105°CJunction Temperature 150°CStresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stressrating only; functional operation of the device at these or anyother conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affectdevice reliability.Rev. 0 | Page 5 of 8Rev. 0 | Page 6 of 811011-001Figure 1. AD8065 Die Pad Configuration Table 5. Pad Function DescriptionsPad No.X-Axis Y-Axis Mnemonic Description 2−485 254 −IN Inverting Input. 3−485 −172 +IN Noninverting Input. 4201 −301 −V S Negative Supply. 6343 −189 V OUTOutput. 7 485 25 +V S Positive Supply.Rev. 0 | Page 7 of 808-31-2012-AFigure 2. 6-Pad Bare Die [CHIP](C-6-5) Dimensions shown in millimetersDIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONSTable 6. Typical Die SpecificationsParameter Value UnitChip Size 1205 × 855 μmDie Size 47.4 × 33.7 MilThickness 483 μmBond Pads (Min Size) 92 × 92 μmBond Pad Composition 1% Copper Doped Aluminum %Backside Si Not Applicable Passivation Doped oxide/SiN Not ApplicableESD HBM 1000 V Table 7. Assembly RecommendationsAssembly ComponentRecommendation Die AttachAblestik 84-1LMIS R4 Bonding Method 1 mil goldORDERING GUIDEModel Temperature Range Pa c kage DescriptionPackage Option AD8065-KGD-CHIP –40°C to +85°C 6-Pad Bare Die [CHIP] C-6-5©2012 Analog Devi es, In. All rights reserved. Trademarks and Arrayregistered trademarks are the property of their respec tive owners.D11011-0-10/12(0)Rev. 0 | Page 8 of 8。

Rev.0Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment atroom temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: /zh电路笔记CN-0213连接/参考器件16位、250 kSPS PulSAR® ADC，采用MSOP/QFN封装AD7685Circuit from the Lab™实验室电路是经过测试的电路设计，用于解决常见的设计挑战，方便设计人员轻松快捷地实现系统集成。

FEATURESFast (2.4μs) 14-Bit ADCFour Simultaneously Sampled InputsFour Track/Hold Amplifiers0.35μs Track/Hold Acquisition Time2.4μs Conversion Time per ChannelHW/SW Select of Channel Sequence for ConversionSingle Supply OperationSelection of Input Ranges: ±10 V,±5 V and ±2.5 V,0 V to +5 V and 0 V to +2.5 VHigh Speed Parallel Interface Which Also AllowsInterfacing to 3 V ProcessorsLow Power, 115 mW TypPower Saving Mode, 15μW TypOvervoltage Protection on Analog InputsAPPLICATIONSAC Motor ControlUninterruptible Power SuppliesIndustrial Power Meters/MonitorsData Acquisition SystemsCommunicationsGENERAL DESCRIPTIONThe AD7865 is a fast, low power, four-channel simultaneous sampling 14-bit A/D converter that operates from a single +5V supply. The part contains a 2.4 μs successive approximation ADC, four track/hold amplifiers, 2.5 V reference, on-chip clock oscillator, signal conditioning circuitry and a high speed parallel interface. The input signals on four channels are sampled simultaneously thus preserving the relative phase information of the signals on the four analog inputs. The part accepts analog input ranges of ±10V, ±5V, ±2.5V, 0V to +2.5V and 0V to +5V. The part allows anysubset of the four channels to be converted in order to maximize the throughput rate on the selected sequence. The channels to be converted can be selected either via hardware (channel select input pins) or via software (programming the channel select register). A single conversion start signal (CONVST) simultaneously places all the track/holds into hold and initiates conversion sequence for the selected channels. The EOC signal indicates the end of each individual conversion in the selected conversion sequence. The BUSY signal indicates the end of the conversion sequence. Data is read from the part via a 14-bit parallel data bus using the standard CS and RD signals. Maximum throughput for a single channel is 350 kSPS. For all four channels the maximum throughput is 100 kSPS.PRODUCT HIGHLIGHTS1. The AD7865 features four Track/Hold amplifiers and a fast (2.4 μs) ADC allowing simultaneous sampling and then conversion of any subset of the four channels.2. The AD7865 operates from a single +5V supply and consumes only 115 mW typ, making it ideal for low power and portable applications.3. The part offers a high speed parallel interface for easy connectionto microprocessors, microcontrollers and digital signal processors.4. The part is offered in three versions with different analog input ranges. The AD7865-1 offers the standard industrial ranges of ±10V and ±5V; the AD7865-2 offers a unipolar range of 0V to +2.5V or 0V to +5V and the AD7865-3 offers the common signal processing input range of ±2.5V.5. The part features very tight aperture delay matching between the four input sample and hold amplifiers.PIN FUNCTION DESCRIPTIONS1 BUSY Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until conversion is completed on all selected channels.2 FRSTDATA First Data Output. FRSTDATA is a logic output which, when high, indicates that the Output Data Register Pointer is addressing Register 1—SeeAccessing the Output Data Registers. 3 CONVST Convert Start Input. Logic Input. A low-to-high transition on this input puts all track/holds into their hold mode and starts conversion on the selected channels. In addition, the state of the Channel Sequence Selection is also latched on the rising edge of CONVST . 4 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 5 RD Read Input. Active low logic input which is used in conjunction with CS low to enable the data outputs. Ensure the WR pin is at logic high while performing a read operation. 6 WR Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0 to DB3 into the channel select register.7 CLK IN/SL1 Conversion Clock Input/Hardware Channel Select. The function of this pin depends upon the S H /SEL input. When the S H /SEL input is high (choosing software control of the channel selection sequence), this pin assumes its CLK IN function. CLK IN is an externally applied clock (that is only necessary when INT/EXT CLK is high) this allows the user to control the conversion rate of the AD7865. Each conversion needs 16 clock cycles in order for the conversion to be completed. The clock should have a duty cycle that is no greater than 60/40. See Using an External Clock. When the S H /SEL input is low (choosing hardware control of the channel conversion sequence), this pin assumes its Hardware Channel Select function. The SL1 input determines whether Channel 1 is included in the channel conversion sequence. The selection is latched on the rising edge of CONVST . See Selecting a Conversion Sequence. 8INT /EXT CLK/SL2 Internal/External Clock/Hardware Channel Select. The function of this pin depends upon the S H /SEL input. When the S H /SEL input ishigh (choosing software control of the channel selection sequence), this pin assumes its INT/EXT CLK function. When INT/EXT CLK is at a Logic 0, the AD7865 uses its internally generated master clock. When INT/EXT CLK is at Logic 1, the master clock is generated externally to the device and applied to CLK IN. When the SH/SEL input is low (choosing hardware control of the channel conversion sequence), this pin assumes its Hardware Channel Select function. The SL2 input determines whether Channel 2 is included in the channel conversion sequence. The selection is latchedon the rising edge of CONVST. When SH/is at Logic 1 these pins have no function and can be tied to Logic 1 or Logic 0. See Selecting a Conversion Sequence. 9–10 SL3–SL4 Hardware Channel Select. When the SH/SEL input is at Logic 1, the SL3 input determines whether Channel 3 is included in the channel conversion sequence while SL4 determines whether Channel 4 is included in the channel conversion sequence. When the pin is at Logic 1, the channel is included in the conversion sequence. When the pin is at Logic 0, the channel is excluded from the conversion sequence. The selection is latched on the rising edge of CONVST. See Selecting a Conversion Sequence.11SH/SEL Hardware/Software Select Input. When this pin is at a Logic 0, the AD7865 conversion sequence selection is controlled via the SL1–SL4 input pins and runs off an internal clock. When this pin is at Logic 1, the conversion sequence is controlled via the channel select registerand allows the ADC to run with an internal or external clock. See Selecting a Conversion Sequence.12 AGND Analog Ground. General Analog Ground. This AGNDÊpin should be connected to the system’s AGND plane.13–16 VIN4x, VIN3x Analog Inputs. See Analog Input section.17 AGND Analog Ground. Analog Ground reference for the attenuator circuitry. ThisAGNDÊpin should be connected to the system’s AGND plane.18–21 VIN2x, VIN1x Analog Inputs. See Analog Input section.22 STBY Standby Mode Input. This pin is used to put the device into the power save or standby mode. The STBY input is high for normal operation and low for standby operation.23 AGND Analog Ground. General Analog Ground. This AGND pin should be connected to the system’s AGND plane.24 VREF Reference Input/Output. This pin provides access to the internal reference (+2.5 V ±20 mV) and also allows the internal reference to be overdriven by an external reference source (+2.5 V±5%). A 0.1 mF decoupling capacitor should be connected between this pin and AGND.25 A VDD Analog Positive Supply V oltage, +5.0 V ±5%. A 0.1 mF decoupling capacitor should be connected between this pin and AGND.26 AGND Analog Ground. General Analog Ground. This AGND pin should be connected to the system’s AGND plane.27–34 DB13–DB6 Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 6. Three-state TTL outputs. Output coding is twos complement for AD7865-1 and AD7865-3, and straight binary for AD7865-2.35 DVDD Positive Supply V oltage for Digital section, +5.0 V ±5%. A 0.1 mF decoupling capacitor should be connected between this pin and AGND. Both DVDD and A VDD should be externally tied together.36 VDRIVE This pin provides the positive supply voltage for the output drivers (DB0 to DB13), BUSY,EOC and FRSTDATA. It is normally tied to DVDD. VDRIVE should be decoupled with a 0.1 mF capacitor. It allows improved performance when reading during the conversion sequence. Also, the output data drivers may be powered by a 3 V ± 10% supply to facilitate interfacing to 3 V processors and DSPs.37 DGND Digital Ground. Ground reference for Digital circuitry. This DGND pin should be connected to the system’s DGND plane. The system’s DGND and AGND planes should be connected together at one point only, preferably at an AGND pin.38, 39 DB5, DB4 Data Bit 5 to Data Bit 4. Three-state TTL outputs.40–43 DB3–DB0 Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, these pins are three-state TTL outputs. The channel select register is programmed with the data on the DB0–DB3 pins with standard CS and WR signals. DB0 represents Channel 1 and DB3 represents Channel 4.44 EOC End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in a conversion sequence is indicated by a low going pulse on this line.CONVERTER DETAILSThe AD7865 is a high speed, low power, four-channel simultaneous sampling 14-bit A/D converter that operates from a single +5ÊV supply. The part contains a 2.4Êms successive approximation ADC, four track/hold amplifiers, an internal +2.5ÊV reference and a high speed parallel interface. There are four analog inputs which can be sampled simultaneously, thus preserving the relative phase information of the signals on all four analog inputs. Thereafter, conversions will be completed on the selected subset of the four channels. The part accepts an analog input range of ±10 V or ±5 V (AD7865-1), 0 V to +2.5 V or0 V to +5 V (AD7865-2) and ±2.5 V (AD7865-3). Overvoltage protection on the analog inputs for the part allows the input voltage to go to ±18 V (AD7865-1 with ±10 V input range), ±9 V (AD7865-1 with ±5 V input range), –1 V to +18 V (AD7865-2) and –4 V to +18 V (AD7865-3) without causing damage or effecting the conversion result of another channel. The AD7865 has two operating modes Reading Between Conversions and Readingafter the Conversion Sequence. These modes are discussed in more detail in the Timing and Control section.A conversion is initiated on the AD7865 by pulsing the CONVST input. On the rising edge of CONVST, all four on-chip track/holds are simultaneously placed into hold and the conversion sequence is started on all the selected channels. Channel selectionis made via the SL1–SL4 pins if SH/SEL is logic zero, or via the channel select register if SH/SEL is logic one—see Selecting a Conversion Sequence. The channel select register isprogrammed via the bidirectional data lines DB0–DB3 and a standard write operation. The selected conversion sequence is latched on the rising edge of CONVST so changing a selection will only take effect once a new conversion sequence is initiated. The BUSY output signal is triggered high on the rising edge of CONVST and will remain high for the duration of the conversion sequence. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. There is also the option of using an external clock, by tying the INT/EXT CLK pin logic high and applying an external clock to the CLKIN pin. However, the optimum throughput is obtained by using the internally generated clock— see Using an External Clock. The EOC signal indicates the end of each conversion in the conversion sequence. The BUSY signal indicates the end of the full conversion sequence and at this time all four Track and Holdsreturn to tracking mode. The conversion results can either be read at the end of the full conversion sequence (indicated by BUSY going low) or as each result becomes available (indicated by EOC going low). Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals—see Timing and Control. Conversion time for each channel of the AD7865 is 2.4μs and the track/hold acquisition time is 0.35 μs. To obtain optimum performance from the part, the read operation should not occur during a channel conversion or during the 100 ns prior to the next CONVST rising edge. This allows the part to operate at throughput rates up to 100 kHz for all four channels and achieve data sheet specifications.。