2.5V 184-pin Registered DDR-I SDRAM Modules 256MB,512MB &1GByte Modules PC1600&PC2100DescriptionThe HYS 72Dxx0x0GR are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs)organized as 32M ×72(256MB),64M ×72(512MB)and 128M ×72(1GB).The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications.All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution.This reduces capacitive loading to the system bus,but adds one cycle to the SDRAM timing.A variety of decoupling capacitors are mounted on the PC board.The DIMMs feature serial presence detect based on a serial E 2PROM device using the 2-pin I 2C protocol.The first 128bytes are programmed with configuration data and the second 128bytes are available to the customer.•184-pin Registered 8-Byte Dual-In-Line DDR-I SDRAM Module for PC and Server main memory applications •One bank 32M ×72,64M x 72,and two bank 64M x 72,128M ×72organization •JEDEC standard Double Data RateSynchronous DRAMs (DDR-I SDRAM)with a single +2.5V (±0.2V)power supply •Built with 256Mbit DDR-I SDRAMs in 66-Lead TSOPII package •Programmable Latency,Burst Length,and Wrap Sequence (Sequential &Interleave)•Auto Refresh (CBR)and Self Refresh •All inputs and outputs SSTL_2compatible •Re-drive for all input signals using register and PLL devices.•Serial Presence Detect with E 2PROM •Jedec standard MO-206form factor:133.35mm (nom.)×43.18mm (nom.)×4.00mm (max.)(6,80mm max.with stacked components)•Jedec standard reference layout:Raw Cards A,B and C •Gold plated contacts•Performance:-7-8UnitComponent Speed Grade DDR266A DDR200Module Speed GradePC2100PC1600f CK Clock Frequency (max.)@CL =2.5143125MHz f CKClock Frequency (max.)@CL =2133100MHzOrdering InformationType Compliance Code Description SDRAMTechnologyPC2100(CL=2):HYS72D32000GR-7-A PC2100R-20330-A1one bank256MB Reg.DIMM256MBit(x8) HYS72D64000GR-7-A PC2100R-20330-B1one bank512MB Reg.DIMM256Mbit(x4) HYS72D64020GR-7-A PC2100R-20330-A1two banks512MB Reg.DIMM256MBit(x8) HYS72D128020GR-7-A PC2100R-20330-C1two banks1GByte Reg.DIMM256MBit(x4)(stacked)PC1600(CL=2):HYS72D32000GR-8-A PC1600R-20220-A1one bank256MB Reg.DIMM256MBit(x8) HYS72D64000GR-8-A PC1600R-20220-B1one bank512MB Reg.DIMM256Mbit(x4) HYS72D64020GR-8-A PC1600R-20220-A1two banks512MB Reg.DIMM256MBit(x8) HYS72D128020GR-8-A PC1600R-20220-C1two banks1GByte Reg.DIMM256MBit(x4)(stacked)Note:All part numbers end with a place code(not shown),designating the silicon-die revision.Reference information available on request.Example:HYS72D32000GR-8-A,indicating Rev.A die are used for SDRAM componentsThe Compliance Code is printed on the module labels and describes the speed sort fe.“PC2100R”,the latencies(f.e.“20330”means CAS latency=2,trcd latency=3and trp latency=3)and the Raw Card used for this module.Pin Definitions and FunctionsA0-A11,A12Address Inputs(A12for256Mb&512Mb based modules)VDDPower(+2.5V)BA0,BA1Bank Selects VSSGroundD Q0-D Q63Data Input/Output VDD QI/O Driver power supplyCB0-CB7Check Bits(x72organization only)VDDIDVDD Indentification flagRAS Row Address Strobe VDDSPDEEPROM power supplyCAS Column Address Strobe VREFI/O reference supply WE Read/Write Input SCL Serial bus clockCKE0,CKE1Clock Enable SDA Serial bus data lineD Q S0-D Q S8SDRAM low data strobes SA0-SA2slave address select CK0,CK0Differential Clock Input NC no connectDM0-DM8D Q S9-D Q S17SDRAM low data mask/high data strobesDU don’t useCS0-CS1Chip Selects RESET Reset pin(forces registerinputs low)*)*)for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at the end of this datasheetAddress FormatDensity Organization MemoryBanks SDRAMs#ofSDRAMs#of row/bank/columns bitsRefresh Period Interval256MB32M x72132M x8913/2/108k64ms7.8µs 512MB64M×72164M×41813/2/118k64ms7.8µs 512MB64M x72232M x81813/2/108k64ms7.8µs 1GB128M×72264M×43613/2/118k64ms7.8µsPin ConfigurationBlock Diagram:One Bank32Mb x72DDR-I SDRAM DIMM Module HYS72D32000GR using x8organized SDRAMs on Raw Card Version ABlock Diagram:Two Bank64Mb x72DDR-I SDRAM DIMM Modules HYS72D64020GR Using x8Organized SDRAMs on Raw Card Version ABlock Diagram:One Bank64Mb x72DDR-I SDRAM DIMM Modules HYS72D64000GR Using x4Organized SDRAMs on Raw Card Version BBlock Diagram:Two Bank128Mb x72DDR-I SDRAM DIMM Modules HYS72D128020GR using x4Organized SDRAMs on Raw Card Version CAbsolute Maximum RatingsParameter Symbol Limit Values Unitmin.max.Input/Output voltage relative to VSS VIN,VOUT–0.5 3.6VPower supply voltage on VDD /VDD Qto VSSVDD,VDD Q–0.5 3.6VStorage temperature range TSTG-55+150o CPower dissipation(per SDRAM component)PD–1WData out current(short circuit)IOS–50mA Permanent device damage may occur if“Absolute Maximum Ratings”are exceeded.Functional operation should be restricted to recommended operation conditions.Exposure to higher than recommended voltage for extended periods of time affect device reliabilitySupply Voltage LevelsParameter Symbol Limit Values Unit Notesmin.nom.max.Device Supply Voltage VDD2.3 2.5 2.7V-Output Supply Voltage VDD Q2.3 2.5 2.7V1)Input Reference Voltage VREF 0.49x VDD Q0.5x VDD Q0.51x VDD QV2)Termination Voltage VTT VREF–0.04VREFVREF+0.04V3)EEPROM supply voltage VDDSPD2.3 2.53.6V1Under all conditions,VDD Q must be less than or equal to VDD2Peak to peak AC noise on VREF may not exceed±2%VREF(DC).V REF is also expected to track noise variations in VDD Q.3VTT of the transmitting device must track VREFof the receiving device.DC Operating Conditions(SSTL_2Inputs)(V DD Q=2.5V,T A=70°C,Voltage Referenced to V SS)Parameter Symbol Limit Values Unit Notesmin.max.DC Input Logic High VIH(DC)VREF+0.15VDD Q+0.3V1)DC Input Logic Low VIL(DC)–0.30VREF–0.15V–Input Leakage Current IIL–55µA1)Output Leakage Current IOL–55µA2)1)The relationship between the VDD Q of the driving device and the VREFof the receiving device is whatdetermines noise margins.However,in the case of VIH(max)(input overdrive),it is the VDD Qof the receivingdevice that is referenced.In the case where a device is implemented such that it supports SSTL_2inputs buthas no SSTL_2outputs(such as a translator),and therefore no VDD Q supply voltage connection,inputs musttolerate input overdrive to3.0V(High corner VDD Q +300mV).2)For any pin under test input of0V≤VIN≤V DD Q+0.3V.Values are shown per DDR-SDRAM component.Operating,Standby and Refresh Currents(PC1600)Operating,Standby and Refresh Currents(PC2100)Electrical Characteristics&AC Timing for DDR-I components (for reference only)(0°C≤ TA ≤ 70 °C; VDD Q=2.5V± 0.2V;VDD=2.5V± 0.2V)Electrical Characteristics&AC Timing for DDR-I components (for reference only)(0°C≤ TA ≤ 70 °C; VDD Q=2.5V± 0.2V;VDD=2.5V± 0.2V)SPD CodesPackage Outlines Raw Card A(one memory bank)Package Outlines Raw Card A(two memory banks)Package Outlines Raw Card BPackage Outlines Raw Card CAPPLICATION NOTE:Power Up and Power Management on DDR Registered DIMMs(according to JEDEC ballot JC-42.5Item1173)184-pin Double Data Rate(DDR)Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during low power mode.One feature is externally controlled via a system-generated RESET signal;the second is based on module detection of the input clocks.These enhancements permit the modules to power up with SDRAM outputs in a High-Z state(eliminating risk of high current dissipa-tions and/or dotted I/Os),and result in the powering-down of module support devices(registers and Phase-Locked Loop)when the memory is in Self-Refresh mode.The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM inputs are maintained at a valid‘low’level during power-up and self refresh.When RESET is at a low level,all the register outputs are forced to a low level,and all differential register input receivers are powered down,resulting in very low register power consumption.The pin,located on DIMM tab#10,is driven from the system as an asynchronous signal according to the attached ing this function also permits the system and DIMM clocks to be stopped during memory Self Refresh operation,while ensuring that the SDRAMs stay in Self Refresh mode.The function for RESET is as follows:As described in the table above,a low on the input ensures that the Clock Enable(CKE)signal(s)are maintained low at the SDRAM pins(CKE being one of the'Q'signals at the register output).Holding CKE low maintains a high impedance state on the SDRAM D Q,D Q S and DM outputs—where they will remain until acti-vated by a valid‘read’cycle.CKE low also maintains SDRAMs in Self Refresh mode when applicable.The DDR PLL devices automatically detect clock activity above20MHz.When an input clock frequency of20MHz or greater is detected,the PLL begins operation and initiates clock frequency lock(the minimum operat-ing frequency at which all specifications will be met is95MHz).If the clock input frequency drops below20MHz (actual detect frequency will vary by vendor),the PLL VCO(Voltage Controlled Oscillator)is stopped,outputs aremade High-Z,and the differential inputs are powered down—resulting in a total PLL current consumption of less e of this low power PLL function makes the use of the PLL RESET(or G pin)unnecessary,and it is tied inactive on the DIMM.This application note describes the required and optional system sequences associated with the DDR Regis-tered DIMM''function.It is important to note that all references to CKE refer to both CKE0and CKE1for a2-bank DIMM.Because applies to all DIMM register devices,it is therefore not possible to uniquely control CKE to one physical DIMM bank through the use of the RESET pin.Power-Up Sequence with RESET—Required1.The system sets RESET at a valid low level.This is the preferred default state during power-up.This input condition forces all register outputs to a low state independent of the condition on the register inputs(data and clock),ensuring that CKE is at a stable low-level at the DDR SDRAMs.2.The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR SDRAMs.3.Stabilization of Clocks to the SDRAMThe system must drive clocks to the application frequency(PLL operation is not assured until the input clock reaches20MHz).Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle.Once a stable clock is received at the DIMM PLL,the required PLL stabilization time(assuming power to the DIMM is stable)is100microseconds.Whena stable clock is present at the SDRAM input(driven from the PLL),the DDR SDRAM requires200µsec priorto SDRAM operation.4.The system applies valid logic levels to the data inputs of the register(address and controls at the DIMM con-nector).CKE must be maintained low and all other inputs should be driven to a known state.In general these com-mands can be determined by the system designer.One option is to apply an SDRAM‘NOP’command(with CKE low),as this is the first command defined by the JEDEC initialization sequence(ideally this would be a ‘NOP Deselect’command).A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs.5.The system switches RESET to a logic‘high’level.The SDRAM is now functional and prepared to receive commands.Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required(during this period,register inputs must remain stable).6.The system must maintain stable register inputs until normal register operation is attained.The registers have an activation time that allows their clock receivers,data input receivers,and output drivers sufficient time to be turned on and become stable.During this time the system must maintain the valid logic levels described in step5.It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE.Register activation time (t(ACT)),from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal,is specified in the register and DIMM do-umentation.7.The system can begin the JEDEC-defined DDR SDRAM power-up sequence(according to the JEDEC-pproved initialization sequence).Self Refresh Entry(RESET low,clocks powered off)—OptionalSelf Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down and the clocks are off.This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking. Self Refresh mode is an ideal time to utilize the RESET pin,as this can reduce register power consumption low deactivates register CK and CK,data input receivers,and data output drivers).1.The system applies Self Refresh entry command.(CKE→Low,CS→Low,RAS → Low,CAS→Low,WE→High)Note:The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM.After this command is issued to the SDRAM,all of the address and control and clock input conditions to the SDRAM are Don’t Cares—with the exception of CKE.2.The system sets RESET at a valid low level.This input condition forces all register outputs to a low state,independent of the condition on the registerm inputs(data and clock),and ensures that CKE,and all other control and address signals,are a stable low-level at the DDR SDRAMs.Since the RESET signal is asynchronous,setting the RESET timing in relation toa specific clock edge is not required.3.The system turns off clock inputs to the DIMM.(Optional)a.In order to reduce DIMM PLL current,the clock inputs to the DIMM are turned off,resulting in High-Z clockinputs to both the SDRAMs and the registers.This must be done after the RESET deactivate time of the reg-ister(t(INACT)).The deactivate time defines the time in which the clocks and the control and address sig-nals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM documentation.b.The system may release DIMM address and control inputs to High-Z.This can be done after the RESET deactivate time of the register.The deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied.It is highly recommended that CKE continue to remain low during this operation.4.The DIMM is in lowest power Self Refresh mode.Self Refresh Exit(RESET low,clocks powered off)—Optional1.Stabilization of Clocks to the SDRAM.The system must drive clocks to the application frequency(PLL operation is not assured until the input clock reaches~20MHz).Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle.Once a stable clock is received at the DIMM PLL,the required PLL stabilization time(assuming power to the DIMM is stable)is100microseconds.2.The system applies valid logic levels to the data inputs of the register(address and controls at the DIMM con-nector).CKE must be maintained low and all other inputs should be driven to a known state.In general these com-mands can be determined by the system designer.One option is to apply an SDRAM‘NOP’command(with CKE low),as this is the first command defined by the JEDEC Self Refresh Exit sequence(ideally this would be a‘NOP Deselect’command).A second option is to apply low levels on all of the register inputs,to be con-sistent with the state of the register outputs.3.The system switches to a logic‘high’level.The SDRAM is now functional and prepared to receive commands.Since the RESET signal is asynchronous, timing relationship to a specific clock edge is not required(during this period,register inputs must remain stable).4.The system must maintain stable register inputs until normal register operation is attained.The registers have an activation time that allows the clock receivers,input receivers,and output drivers suffi-cient time to be turned on and become stable.During this time the system must maintain the valid logic levels described in Step2.It is also a functional requirement that the registers maintain a low state at the CKE out-puts to guarantee that the DDR SDRAMs continue to receive a low level on CKE.Register activation time(t (ACT)),from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal,is specified in the register and DIMM do-umentation.5.System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.Self Refresh Entry(RESET low,clocks running)—OptionalAlthough keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an alternate operating mode for these DIMMs.1.System enters Self Refresh entry command.(CKE→Low,CS→Low,RAS→Low,CAS→Low,WE→High)Note:The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM.After this command is issued to the SDRAM,all of the address and control and clock input conditions to the SDRAM are Don’t Cares—with the exception of CKE.2.The system sets RESET at a valid low level.This input condition forces all register outputs to a low state,independent of the condition on the data and clock register inputs,and ensures that CKE is a stable low-level at the DDR SDRAMs.3.The system may release DIMM address and control inputs to High-Z.This can be done after the RESET deactivate time of the register(t(INACT)).The deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels afterlow has been applied.It is highly recommended that CKE continue to remain low during the operation.4.The DIMM is in a low power,Self Refresh mode.Self Refresh Exit(RESET low,clocks running)—Optional1.The system applies valid logic levels to the data inputs of the register(address and controls at the DIMM con-nector).CKE must be maintained low and all other inputs should be driven to a known state.In general these com-mands can be determined by the system designer.One option is to apply an SDRAM‘NOP’command(with CKE low),as this is the first command defined by the Self Refresh Exit sequence(ideally this would be a ‘NOP Deselect’command).A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs.2.The system switches to a logic'high'level.The SDRAM is now functional and prepared to receive commands.Since the signal is asynchronous, it does not need to be tied to a particular clock edge(during this period,register inputs must continue to remain stable).3.The system must maintain stable register inputs until normal register operation is attained.The registers have an activation time that allows the clock receivers,input receivers,and output drivers suffi-cient time to be turned on and become stable.During this time the system must maintain the valid logic levels described in Step1.It is also a functional requirement that the registers maintain a low state at the CKE out-puts in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE.This activation time,from asynchronous switching of from low to high,until the registers are stable and ready to accept an input signal,is t(ACT)as specified in the register and DIMM documentation.4.The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.Self Refresh Entry/Exit(RESET high,clocks running)—OptionalAs this sequence does not involve the use of the RESET function,the JEDEC standard SDRAM specification explains in detail the method for entering and exiting Self Refresh for this case.Self Refresh Entry(RESET high,clocks powered off)—Not PermissibleIn order to maintain a valid low level on the register output,it is required that either the clocks be running and the system drive a low level on CKE,or the clocks are powered off and RESET is asserted low according to thesequence defined in this application not e.In the case where remains high and the clocks are powered off,the PLL drives a High-Z clock input into the register clock input.Without the low level on RESET an unknown DIMM state will result.。
16-CHANNEL TRUE DIVERSITY UHF WIRELESS SYSTEMOWNER'S MANUALCopyright 2013, Samson Technologies Corp. v2Samson Technologies Corp.45 Gilpin AveHauppauge, NY 11788Important Safety InformationCAUTION: TO REDUCE THE RISK OF ELECTRIC SHOCK, DO NOTREMOVE COVER (OR BACK). NO USER-SERVICEABLE PARTS IN-SIDE. REFER SERVICING TO QUALIFIED SERVICE PERSONNEL.If you want to dispose this product, do not mix it with general household waste. There is aseparate collection system for used electronic products in accordance with legislation thatrequires proper treatment, recovery and recycling.Private household in the 25 member states of the EU, in Switzerland and Norway may return their used electronic products free of charge to designated collection facilities or to a retailer (if you purchase a similar new one).For Countries not mentioned above, please contact your local authorities for a correct method of disposal.By doing so you will ensure that your disposed product undergoes the necessary treatment, recovery and recycling and thus prevent potential negative effects on the environment and human health.ATTENTIONRISQUE D’ÉLECTROCUTION !NE PAS OUVRIR !WARNINGTO PREVENT FIRE OR SHOCK HAZARD. DO NOT USE THIS PLUG WITH AN EXTENSION CORD, RECEPTACLE OR OTHER OUTLET UNLESS THE BLADES CAN BE FULLY INSERT-ED TO PREVENT BLADE EXPOSURE. TO PREVENT FIRE OR SHOCK HAZARD. DO NOT EXPOSE THIS APPLIANCE TO RAIN OR MOISTURE. TO PREVENT ELECTRICAL SHOCK, MATCH WIDE BLADE PLUG TO WIDE SLOT AND FULLY INSERT.Important Safety Information1. Read these instructions.2. Keep these instructions.3. Heed all warnings.4. Follow all instructions.5. Do not use this apparatus near water.6. Clean only with dry cloth.7. Do not block any ventilation open-ings. Install in accordance with the manufacturer’s instructions.8. Do not install near any heat sourc-es such as radiators, heat registers, stoves, or other apparatus (includ-ing amplifiers) that produce heat.9. Do not defeat the safety purpose of the polarized or grounding type plug. A polarized plug has two blades with one wider than the other. A grounding type plug hastwo blades and a third ground-ing prong. The wide blade or the third prong are provided for your safety. If the provided plug does not fit into your outlet, consult an electrician for replacement of the obsolete outlet.10. Protect the power cord from being walked on or pinched particularly at the plugs, convenience recep-tacles, and at the point where theyexit from the apparatus.11. Only use attachments/accessoriesspecified by the manufacturer.12. Use only with the cart, stand,the apparatus. When a cart isused, use caution when movingthe cart/apparatus combinationto avoid injury from tip-over.13. Unplug the apparatus during light-ening storms, or when unused for long periods of time. 14. Refer all servicing to qualified per-sonnel. Service is required whenthe apparatus has been damaged in any way, such as power supply cord or plug is damaged, liquid has been spilled or objects havefallen into the apparatus has been exposed to rain or moisture, does not operate normally, or has been dropped.15. This appliance shall not beexposed to dripping or splashing water and that no object filled with liquid such as vases shall be placed on the apparatus.16. Caution-to prevent electrical shock, match wide blade plug wide slot fully insert.17. Please keep a good ventilation en-vironment around the entire unit.18. The direct plug-in adapter is used as disconnect device, the discon-nect device shall remain readily operable.19. Batteries (battery pack or batteriesinstalled) shall not be exposed to excessive heat such as sunshine, fire or the like.Table of ContentsIntroduction (6)System Features (7)System Components (7)Guided Tour - CR88 Receiver . . . . . . . . . . . . . . . . . . 8Guided Tour - CB88 Belt Pack Transmitter . . . . . . . . . . . .10Guided Tour - CH88 Handheld Transmitter . . . . . . . . . . . .12Quick Start - Single System Setup . . . . . . . . . . . . . . . .13Quick Start - Multiple System Setup . . . . . . . . . . . . . . .17Rack Mounting . . . . . . . . . . . . . . . . . . . . . . . . .19Concert 88 Channel Plans . . . . . . . . . . . . . . . . . . . .20Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . .21Specifications (22)5 Concert 88 Wireless SystemIntroductionCongratulations on purchasing the Samson Concert 88 wireless system. The Concert 88 is the ideal solution for the active performer who needs a reliable, great sounding system for wireless applications. Featuring simple operation, with 16 available chan-nels and infrared set for the transmitter channel, the Concert 88 can quickly be up and running out of the box. The Concert 88 system ensures clear, interruption-free performance by combining tone-key with auto-mute. This configuration allows only the transmitter’s audio to pass through the receiver, and mutes the output if there is any interference.The Concert 88 comes in four configurations. The vocal handheld system includes the CH88 handheld transmitter and Q6 dynamic microphone capsule. The CB88 belt pack system can be configured with either the HS5 headset microphone, LM5 lavalier microphone, or a ¼" instrument cable. For travel or permanent installation, the Concert 88 includes a standard 19" rackmount kit.In these pages, you’ll find a detailed description of the features of the Concert 88 wireless system, as well as a guided tour through its control panel, step-by-step instructions for its setup and use, and full specifications. If your wireless system was purchased in the United States, you’ll also find a warranty card enclosed—don’t forget to fill it out and mail it in so that you can receive online technical support and so that we can send you updated information about this and other Samson products in the future. Also, be sure to check out our website () for com-plete information about our full product line.We recommend you keep the following records for reference, as well as a copy of your sales receipt.Receiver Serial number: _________________________________________ Transmitter Serial number: ______________________________________Date of purchase: ______________________________________________Dealer name: __________________________________________________With proper care and maintenance, your Concert 88 wireless system will operate trouble-free for many years. Should your wireless system ever require servicing, a Return Authorization (RA) number must be obtained before shipping your unit to Samson. Without this number, the unit will not be accepted. Please call Samsonat 1-800-3SAMSON (1-800-372-6766) for an RA number prior to shipping your unit. Please retain the original packing materials and, if possible, return the unit in its original carton. If your Concert 88 system was purchased outside of the United States, contact your local distributor for warranty details and service information.67Concert 88 Wireless System System ComponentsSystem FeaturesAll systemsCR88 receiverPower Supply¼" to ¼" audio cableRack Accessories Long rack ear, short rack ear, two receiver adaptor Owner's ManualHandheld systemCH88 handheld transmitter with Q6 dynamic microphone capsuleHeadset systemCB88 belt pack transmitterHS5 headset microphone with mini-XLR connectorLavalier SystemCB88 belt pack transmitterLM5 lavalier microphone with mini-XLR connectorTie clipInstrument SystemCB88 belt pack transmitter¼" to mini-XLR instrument cable•Professional wireless system for use in both live sound and sound contracting applications •True diversity technology maximizes active range (up to 300 feet) and reduces potential interference •16 available channels operating in the UHF band designed for maximum system compatibility in the same location without interference • The CR88 receiver is a half-rack unit that can be used freestanding or can be mounted in any standard 19" rack using the included rack kit, making it easy to integrate into any traveling or fixed installation audio system• Tone-key and auto-mute ensures clear, interruption-free performance allowing only the transmitter’s audio to pass through the receiver, and mutes the output if there is any interference• Up to 300-foot range (line-of-sight)•Up to eight hours of battery life, using two standard AA batteriesGuided Tour - CR88 Receiver1. Antennas - The antenna mountings allow full rotation for optimum placement. Innormal operation, both antennas should be placed in a vertical position. Both antennas can be folded inward for convenience when transporting the CR88. 2. VOLUME Control - This knob sets the level of the audio signal being outputthrough both the balanced and unbalanced output jacks on the rear panel.Reference level is obtained when the knob is turned fully clockwise (to its “10”setting).3. READY Indicator - This indicator lights green when the CR88 is receiving RF sig-nal and the system is ready to use.4. PEAK Indicator - This indicator lights red when the transmitted audio signal isoverloaded.5. LED Display - The 7-segment LED display shows the receiver's current operatingchannel. The CR88 channels are indicated by 0-9 and A-F.6. IR Transmitter - During “IR SET” an infrared light is used to set the transmitterchannel.7. SELECT Button - Press this button to cycle through the receiver's operating chan-nels. Press and hold this button to send the channel information to the transmit-ter via infrared transmission.8. POWER Switch - Use this to turn the CR88 power on and off.89Concert 88 Wireless SystemGuided Tour - CR88 Receiver1. DC Input - Connect the supplied power adapter here, using the strain relief asshown in the illustration below. WARNING: Do not substitute any other kind of power adapter. Doing so can cause severe damage to the CR88 and will void your warranty.2. BALANCED OUTPUT - Use this electronically balanced low impedance (600 Ohm)XLR jack when connecting the CR88 to professional (+4dBu) audio equipment. Pin wiring is as follows: Pin 1 ground, Pin 2 high (hot), and Pin 3 low (cold).3. UNBALANCED OUTPUT - Use this unbalanced high impedance (5K Ohm) ¼" jackwhen connecting the CR88 to consumer (-10dBV) audio equipment. Wiring is as follows: tip hot, sleeve ground.Guided Tour - CB88 Belt Pack Transmitter1. Input Connector - Connect the input device via the mini-XLR connector. The CB88is supplied with either a lavalier, headset microphone or ¼" instrument cable. 2. Status Indicator - This LED displays the operation mode:GREEN Normal OperationRED MuteFlashing GREEN Low Battery3. Power/Mute Switch - Press and hold to turn the unit on or off. Press and releaseto mute or unmute the transmitter.4. Belt Clip - Use this clip to fasten the CB88 transmitter to a belt or guitar strap.5. Battery Cover Release - Push in both sides and pull back to open the CB88 bat-tery cover.6. Antenna - This permanently attached transmitter antenna should be fully extend-ed during normal operation.1011Concert 88 Wireless System 7. Input GAIN Control - This control adjusts the transmitter input sensitivity to workwith microphone and instruments inputs. For optimal performance, using the included screwdriver, set the input GAIN control to where you see the CR88 PEAK indicator start to light under high levels, then turn down slowly until the PEAK light stops lighting. 8. Battery Holder - Insert two standard AA (LR6) batteries here, being sure toobserve the plus and minus polarity markings shown. Although rechargeableNi-Cad batteries can be used, they do not supply adequate current for more than four hours. WARNING: Do not insert the batteries backwards; doing so can cause severe damage to the CB88 and will void your warranty.9. IR Lens - This window is used to capture the infrared signal sent from the CR88during the IR SET to channelize the transmitter.10. Plastic Screwdriver - Designed for use in adjusting the CB88 input GAIN control(See #7 Input GAIN Control).Guided Tour - CB88 Belt Pack TransmitterGuided Tour - CH88 Handheld Transmitter1. Status Indicator - This LED displays the Array operation mode:GREEN Normal OperationRED MuteFlashing GREEN Low Battery2. Power/Mute Switch - Press and hold toturn the unit on or off. Press and releaseto mute or unmute the transmitter.3. Battery Cover - Unscrew the battery covercompartment.4. Battery Holder - Open the battery holderby pressing the tab and lifting the cover.Insert two standard AA (LR6) batterieshere, being sure to observe the plus andrechargeable Ni-Cad batteries can beused, they do not supply adequate cur-Do not insert the batteries backwards;CH88 and will void your warranty.5. Input GAIN Control - This control adjuststhe transmitter input sensitivity. Foroptimal performance, using the includedscrewdriver, set the input GAIN control to where you see the CR88 PEAK indica-tor start to light under high levels, then turn down until the PEAK light stops lighting.6. IR Lens - This window is used to capture the infrared signal sent from the CR88during the IR SET to channelize the transmitter. The battery cover must be open and the IR Lens facing towards the receiver to load the selected channel.7. Plastic Screwdriver - Designed for use in adjusting the CB88 input GAIN control(See #5 Input GAIN Control HH).12Quick Start - Single System SetupIn order for your wireless system to work correctly, both the receiver and transmitter must be set to the same channel.Follow this basic procedure for setting up and using your Concert 88 wireless system:Physically place the CR88 receiver where it will be used, and extend the anten-nas vertically. The general rule of thumb is to maintain “line of sight” between the receiver and transmitter so that the person using or wearing the transmitter can see the receiver.With the Power switch on and the CR88 power off, connect the included powers Select button to change channelQuick Start - Single System SetupWhen using multiple systems, each system must be set to a different operating channel. Transmitter and receiver pairs must be on the same channel plan in order to worktogether (See "Concert 88 Channel Plans" on page 20).When setting an additional transmitter, make sure to close all other transmitter bat-9. Press and h 8. Press button on transmitter to turn onThe CR88 receiver can be installed into a standard 19” rack for transport or per-manent installation using the included rack ears. Follow the simple steps below to mount the CR88:Attach the included rack ears by sliding each rack ear into the groove on either side of the CR88 until they lock into place, and the receiver flush with the front panel.Position the CR88 receiver into an available rack space and slide in until the rack ears are touching the rails of the rack case and are aligned with the rack rail holes.Mount the receiver into the rack using the appropriate size rack screws (not includ-ed). To ensure equal tension and balance when installing the receiver, you should secure screws in a crisscross pattern of opposite corners: top left -> bottom right -> top right -> bottom left.In order to mount two CR88 receiv-ers in one rack space, the system includes a center connection piece. Slide the center connection piece into the groove of each receiver and attach the short rack ears to each receiver. Mount the receivers into the rack using the crisscross pattern described above.Rack MountingGroup C 638-662 MHzGroup D542-566 MHzGroup F*863-865 MHzGroup G*606-630 MHzCh Freq Ch Freq Ch Freq Ch Freq0638.1250542.1250863.050 0606.125 1639.6251543.6251863.250 1607.625 2641.0502545.052863.550 2609.053642.4253546.4253863.750 3610.425 4642.9004546.9004864.050 4610.900 5645.5255549.5255864.250 5613.525 6647.1006551.1006864.550 6615.100 7648.4757552.4757864.750 7616.475 8650.0008554.0008864.950 8618.000 9652.0759556.0759620.075 A654.975A558.975A622.975 B655.975B559.975B623.975 C657.050C561.050C625.050 D658.975D562.975D626.975 E660.425E564.425E628.425 F661.975F565.975F629.975 Concert 88 Channel Plans* Not for use in the USA and Canada. For questions regarding available channels in your area contact your local Samson distributor.20Troubleshooting Issue SolutionsNo Audio Make sure that the transmitter and receiver are both powered on.Ensure the transmitter’s batteries are installed correctly. Check that the transmitter is not muted.Confirm that the CR88 adaptor is correctly connected and plugged into an electrical outlet.Turn on the CR88 receiver.Make sure the CR88 audio output connections are se-curely connected.Ensure that the receiver and transmitter are in line of sight with one another.Check the receiver and audio input device level controls. Ensure that the transmitter and receiver are set to the same operating channel. If unsure, reset the channel by performing an IR set.Distorted Audio The receiver output level or audio input device level may be too high.Check the transmitters batteries, and replace if low.The input gain on the transmitter (CB88) or audio source level may be too high.Audio Dropout The transmitter may be too far away from the receiver. Move it closer to the receiver, or reposition the antennas. Remove any sources that may cause RF interference such as cell phones, cordless phones, lighting equipment, com-puters, metal structures, etc.Receiver will not power on Check the adaptor to ensure it is properly connected and plugged into an outlet providing power.Transmitter will notpower on (LED lightsRED)Replace the transmitter batteries.Unwanted noise or interference If using multiple systems, make sure none of the systems are operating on the same channel. If the problem per-sists, change one or all of the systems channels.21Concert 88 Wireless SystemSpecifications SystemWorking Range 300' (100m) line of sightAudio Frequency Response 50 Hz - 15 kHzT.H.D. (Overall) <1% (@AF 1 kHz, RF 46 dBu) Dynamic Range >100 dB A-weightedSignal to Noise >90 dBOperating Temperature –10°C (14°F) to +60°C (+140°F) Tone Key Frequency 32.768 kHzCB88 Belt pack TransmitterInput Connector Mini-XLR (P3)Input Impedance 1MΩInput Gain Range 38 dBRF Power 10 mW EIRPPower Requirements Two AA (LR6) alkaline batteries Battery Life 8 hoursDimensions (HxLxD) 3.75" x 2.44" x 0.75"96mm x 62mm x 18.5mmWeight 0.2 lb / 93 gCH88 Handheld TransmitterMicrophone Element Q6 DynamicInput Gain Range 28 dBRF Power 10 mW EIRPPower Requirements Two AA (LR6) alkaline batteries Battery Life 8 hoursDimensions (HxØ) 10.23" x 2.1"260mm x 54mmWeight 0.48 lb / 218 gCR88 ReceiverAudio Output Level - Unbalanced +14 dBuAudio Output Level - Balanced +9 dBuAudio Output Impedance - Unbalanced 810 OhmsAudio Output Impedance - Balanced 240 OhmsSensitivity -100 dBm / 30 dB sinadImage Rejection >50 dBOperating Voltage 15 VDC 200mADimensions (LxWxH) 8.25" x 4.9" x 1.75"210mm x 125mm x 44mmWeight 0.85 lb / 388 gAt Samson, we are continually improving our products, therefore specifications and images are subject to change without notice.22This device complies with RSS-210 of Industry & Science Canada.Operation is subject to the following two conditions:(1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation.Hereby, Samson Technologies Corp., declares that this CR88, CH88, CB88 is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC. The declaration of conformity may be consulted at/site_media/support/R&TTE_DOC/CONCERT_88_R&TTE_DOC.pdfSamson Technologies45 Gilpin AvenueHauppauge, New York 11788-8816 Phone: 1-800-3-SAMSON (1-800-372-6766)Fax: 631-784-2201。
