GMS升级方案V1.0.1

密级状态：绝密( ) 秘密( ) 内部( ) 公开( √ )文件状态: [ ] 草稿[ √ ] 正式发布[ ] 正在修改文件标识:RK-KF-YF-279当前版本:V1.1.5作者:吴良清完成日期:2021-08-31审核:陈海燕审核日期:2021-08-31title: Rockchip_Developer_Guide_Android11_SDK_V0.0.2_CNdescription: Android11开发指南published: truedate: 2021-07-13T06:21:56.250Ztags: sdkRockchip Android 11.0 SDK开发指南版本号作者修改日期修改说明备注V0.0.1吴良清2020-12-25发布RK3566/RK3568 Alpha版本V0.0.2卞金晨2021-01-06发布PX30/RK3326 Beta版本V1.0.0吴良清2021-01-29增加RK3566/RK3568 EVB板编译方法V1.1.0吴良清2021-02-23发布RK3399 Alpha版本V1.1.1吴良清2021-03-09修改单独编译kernel的说明V1.1.2吴良清2021-05-12支持RK3288W芯片平台V1.1.3吴良清2021-05-23增加常见问题说明V1.1.4吴良清2021-07-12支持RK3566 BOX产品形态，支持RK3328 BOX产品形态，增加repo服务器搭建及常见问题说明V1.1.5吴良清2021-08-31增加常见问题说明文档问题反馈：******************免责声明本文档按“现状”提供，瑞芯微电子股份有限公司（“本公司”，下同）不对本文档的任何陈述、信息和内容的准确性、可靠性、完整性、适销性、特定目的性和非侵权性提供任何明示或暗示的声明或保证。

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由于产品版本升级或其他原因，本文档将可能在未经任何通知的情况下，不定期进行更新或修改。

福州瑞芯微电子有限公司密级状态：绝密()秘密()内部(√)公开()RK平台Android7.1_GMS_产品测试环境搭建（系统产品一部）文件状态：[]正在修改[√]正式发布当前版本：V1.0作者：xzj完成日期：2017-05-15审核：完成日期：2017-05-15福州瑞芯微电子有限公司Fuzhou Rockchips Semiconductor Co.,Ltd(版本所有,翻版必究)版本号作者修改日期修改说明备注V1.0xzj2017-03-10初始版本，加入公共补丁以及KR312x补丁V1.7xzj2017-05-15适配对外更新0512,对应CTSR5版本目录1简述 (3)2测试命令 (3)3产品编译 (4)4ANDROID7.1CTS (5)4.1简述 (5)4.2A NDROID7.1CTS环境设置 (5)4.2.1CTS代码集成DRM、GMS包 (5)4.2.2CTS代码配置 (6)4.2.3CTS固件生成（KEY签名） (7)4.2.4CTS固件签名 (7)4.2.5机器序列号 (8)4.2.6机器配置 (9)4.2.7FRP功能 (9)4.3CTS/GTS测试可豁免测试项 (9)4.4CTS、GTS测试不过项补丁 (11)4.4.17.1CTS/GTS测试共性问题 (11)4.4.2CTS312xSDK测试特有问题 (18)4.4.3CTS3288SDK测试特有问题 (20)4.4.43368SDK CTS测试特有问题 (20)4.4.53188SDK CTS测试特有问题 (21)4.5CTS V ERIFIER测试不过项补丁 (21)4.5.1有关CV中Audio相关测试的说明 (23)4.6XTS4.1R2测试不过项补丁 (27)1简述本文档主要是简单介绍下Android7.1R5RK平台上过GMS的一些环境搭建及部分目前测试不过项的补丁，若有存在其他问题，欢迎反馈，我们会尽快进行补充。

DEC. 1998Ver. 3.0 8-BIT SINGLE-CHIP MICROCONTROLLERSGMS90 SeriesDATA SHEETVersion 3.0Published byMCU Application Team©1998 LG Semicon Co., Ltd. All right reserved.Additional information of this manual may be served by LG Semicon offices in Korea or Distributors and Rep-resentatives listed at address directory.LG Semicon reserves the right to make changes to any information here in at any time without notice.The information, diagrams and other data in this manual are correct and reliable; however, LG Semicon Co., Ltd. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.GMS90 SeriesDec. 1998 Ver 3.0Device Naming StructureGMS90X5X Frequency Package Type Blank:24:40:12MHz 24MHz 40MHz Blank:PL:Q:40PDIP 44PLCC 44MQFP ROM Code serial No.ROM size 1:2:4:4k bytes 8k bytes 16k bytes 6:8:24k bytes 32k bytes Operating Voltage C:L:4.25~5.5V 2.7~3.6VL G S e m i c o n M C U- GBXXX XX XXGMS97X5X FrequencyPackage Type Blank:H:12/24(5V),12MHz(3V)33MHz Blank:PL:Q:40PDIP 44PLCC 44MQFPROM size 1:2:4:4k bytes 8k bytes 16k bytes 6:8:24k bytes 32k bytes Operating Voltage C:L:4.25~5.5V 2.7~3.6VL G S e m i c o n M C UXXX M a s k R O M v e r s i o nO T P v e r s i o nGMS90 SeriesDec. 1998 Ver 3.0GMS90 Series Selection GuideNote: The ROM version products in this data book will be applied to new masking version. (From Dec., 1998)In case that you have old products, please refer to previous data book (prior to this).Operating Voltage (V)ROM size (bytes)RAM size (bytes)Device Name Operating Frequency (MHz)MASKOTP4.25~5.5ROM-less128256GMS90C31GMS90C3212/24/4012/24/404K 8K 16K 24K 32K-----128256256256256GMS90C51GMS90C52GMS90C54GMS90C56GMS90C5812/24/4012/24/4012/24/4012/24/4012/24/40----------4K 4K 8K 8K 16K 16K 24K 24K 32K 32K 128128256256256256256256256256GMS97C51GMS97C51H GMS97C52GMS97C52H GMS97C54GMS97C54H GMS97C56GMS97C56H GMS97C58GMS97C58H 12/243312/243312/243312/243312/24332.7~3.6ROM-less128256GMS90L31GMS90L3212/1612/164K 8K 16K 24K 32K -----128256256256256GMS90L51GMS90L52GMS90L54GMS90L56GMS90L5812/1612/1612/1612/1612/16-----4K 8K 16K 24K 32K128256256256256GMS97L51GMS97L52GMS97L54GMS97L56GMS97L581212121212GMS90 SeriesDec. 1998 Ver 3.01GMS90C31/51, 97C51GMS90L31/51, 97L51 (Low voltage versions)•Fully compatible to standard MCS-51 microcontroller•Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)•4K × 8 (EP)ROM •128 × 8 RAM•64K external program memory space •64K external data memory space •Four 8-bit ports•Two 16-bit Timers / Counters •USART•Five interrupt sources, two priority levels •Power saving Idle and power down mode•Quick pulse programming algorithm (in the OTP devices)•2-level program memory lock (in the OTP devices)•2.7Volt low voltage version available •P-DIP-40, P-LCC-44, P-MQFP-44 packageBlock DiagramRAM 128 × 8PORT 0PORT 1PORT 3PORT 28-BIT USARTROM / EPROM4K × 8CPUT 0T 1I/OI/O I/O I/OGMS90 Series2Dec. 1998 Ver 3.0GMS90C32/52, 97C52GMS90L32/52, 97L52 (Low voltage versions)•Fully compatible to standard MCS-51 microcontroller•Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)•8K × 8 (EP)ROM •256 × 8 RAM•64K external program memory space •64K external data memory space •Four 8-bit ports•Three 16-bit Timers / Counters (Timer2 with up/down counter feature)•USART•Six interrupt sources, two priority levels •Power saving Idle and power down mode•Quick pulse programming algorithm (in the OTP devices)•2-level program memory lock (in the OTP devices)•2.7Volt low voltage version available •P-DIP-40, P-LCC-44, P-MQFP-44 packageBlock DiagramRAM 256 × 8PORT 0PORT 1PORT 3PORT 28-BIT USARTROM / EPROM8K × 8CPUT 0T 1I/OI/O I/O I/OT 2GMS90 SeriesDec. 1998 Ver 3.03GMS90C54/56/58, 97C54/56/58GMS90L54/56/58, 97L54/56/58 (Low voltage versions)•Fully compatible to standard MCS-51 microcontroller•Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)•16K/24K/32K bytes (EP)ROM •256 × 8 RAM•64K external program memory space •64K external data memory space •Four 8-bit ports•Three 16-bit Timers / Counters (Timer2 with up/down counter feature)•USART•One clock output port•Programmable ALE pin enable / disable •Six interrupt sources, two priority levels •Power saving Idle and power down mode•Quick pulse programming algorithm (in the OTP devices)•2-level program memory lock (in the OTP devices)•2.7Volt low voltage version available •P-DIP-40, P-LCC-44, P-MQFP-44 packageBlock DiagramRAM 256 × 8PORT 0PORT 1PORT 3PORT 28-BIT USARTROM / EPROM GMS9XX54: 16K × 8CPUT 0T 1I/OI/O I/OI/OT 2GMS9XX56: 24K × 8GMS9XX58: 32K × 8GMS90 Series4Dec. 1998 Ver 3.0PIN CONFIGURATION44-PLCC Pin Configuration (top view)P0.4 / AD4P0.5 / AD5P0.6 / AD6P0.7 / AD7EA / V PP N.C.*ALE / PROG PSEN P2.7 / A15P2.6 / A14P2.5 / A13P1.5P1.6P1.7RESET RxD / P3.0N.C.*TxD / P3.1INT0 / P3.2INT1 / P3.3T0 / P3.4T1 / P3.5W R / P 3.6R D / P 3.7X T A L 2X T A L 1V S SN .C .*P 2.0 / A 8P 2.1 / A 9P 2.2 / A 10P 2.3 / A 11P 2.4 / A 12P 1.4P 1.3P 1.2P 1.1 / T 2E XP 1.0 / T 2N .C .*V C CP 0.0 / A D 0P 0.1 / A D 1P 0.2 / A D 2P 0.3 / A D 36543214443424140181920212223242526272839383736353433323130297891011121314151617INDEX CORNERN.C.: Do not connect.GMS90 SeriesDec. 1998 Ver 3.0540-PDIP Pin Configuration (top view)P0.4 / AD4P0.5 / AD5P0.6 / AD6P0.7 / AD7EA / V PP ALE / PROG PSEN P2.7 / A15P2.6 / A14P2.5 / A133938373635343332313029282726252423222140P2.4 / A12P2.3 / A11P2.2 / A10P2.1 / A9P2.0 / A8P0.0 / AD0P0.1 / AD1P0.2 / AD2P0.3 / AD3V CC T2EX / P1.1P1.2P1.3P1.4T2 / P1.0P1.5P1.6P1.7RESET RxD / P3.0TxD / P3.1INT0 / P3.2INT1 / P3.3T0 / P3.4T1 / P3.5WR / P3.6RD / P3.7XTAL2XTAL1V SS2345678910111213141516171819201GMS90 Series6Dec. 1998 Ver 3.044-MQFP Pin Configuration (top view)P0.4 / AD4P0.5 / AD5P0.6 / AD6P0.7 / AD7EA / V PP N.C.*ALE / PROG PSEN P2.7 / A15P2.6 / A14P2.5 / A13P1.5P1.6P1.7RESET RxD / P3.0N.C.*TxD / P3.1INT0 / P3.2INT1 / P3.3T0 / P3.4T1 / P3.5W R / P 3.6R D / P 3.7X T A L 2X T A L 1V S SN .C .*P 2.0 / A 8P 2.1 / A 9P 2.2 / A 10P 2.3 / A 11P 2.4 / A 12P 1.4P 1.3P 1.2P 1.1 / T 2E XP 1.0 / T 2N .C .*V C CP 0.0 / A D 0P 0.1 / A D 1P 0.2 / A D 2P 0.3 / A D 34443424140393837363534121314151617181920212233323130292827262524231234567891011N.C.: Do not connect.GMS90 SeriesDec. 1998 Ver 3.07GMS90 Series8Dec. 1998 Ver 3.0PIN DEFINITIONS AND FUNCTIONSSymbol Pin NumberInput/Output FunctionPLCC-44PDIP-40MQFP-44P1.0-P1.72-92321-812140-44, 1-3404140I/OPort1Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the pulls-ups (I IL , in the DC characteristics). Pins P1.0and P1.1 also. Port1 also receives the low-order address byte during program memory verification.Port1 also serves alternate functions of Timer 2.P1.0 / T2 :Timer/counter 2 external count input P1.1 / T2EX :Timer/counter 2 trigger inputIn GMS9XC54/56/58:P1.0 / T2, Clock Out : Timer/counter 2 external countinput, Clock OutP3.0-P3.711,13-1910-175, 7-13I/OPort 3Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 3 pins that are externally pulled low will source current because of the pulls-ups (I IL , in the DC characteristics). Port 3 also serves the special features of the 80C51 family, as listed below.11131415161718191011121314151617578910111213P3.0 / RxDP3.1 / TxDP3.2 /INT0P3.3 / INT1P3.4 /T0P3.5 /T1P3.6 / WRP3.7 /RDreceiver data input (asynchronous) or data input output(synchronous) of serial interface 0transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0interrupt 0 input/timer 0 gate control interrupt 1 input/timer 1 gate control counter 0 input counter 1 inputthe write control signal latches the data byte from port 0 into the external data memorythe read control signal enables the external data memory to port 0XTAL2201814OXTAL2Output of the inverting oscillator amplifier.GMS90 SeriesDec. 1998 Ver 3.09XTAL1211915IXTAL1Input to the inverting oscillator amplifier and input to the internal clock generator circuits.To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop.Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed.P2.0-P2.724-3121-2818-25I/OPort 2Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 2 pins that are externally pulled low will source current because of the pulls-ups (I IL , in the DC characteristics).Port 2emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2special function register.PSEN 322926OThe Program Store EnableThe read strobe to external program memory when the device is executing code from the external program memory. PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.PSEN is not activated during fetches from internal program memory.RESET 1094IRESETA high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to V SS permits power-on reset using only an external capacitor to V CC .Symbol Pin NumberInput/Output FunctionPLCC-44PDIP-40MQFP-44GMS90 Series10Dec. 1998 Ver 3.0ALE /PROG333027OThe Address Latch Enable / Program pulseOutput pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming.In GMS9XC54/56/58:If desired, ALE operation can be disabled by setting bit 0 of SFR location 8E H . With this bit set, the pin is weakly pulled high. The ALE disable feature will be terminated by reset. Setting the ALE-disable bit has no affect if the microcontroller is in external execution mode.EA / V PP 353129IExternal Access Enable / Program Supply Voltage EA must be external held low to enable the device to fetch code from external program memory locations 0000H to FFFF H . If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than its internal memory size. This pin also receives the 12.75V programming supply voltage (V PP ) during EPROM programming.Note;however, that if any of the Lock bits are programmed, EA will be internally latched on reset.P0.0-P0.736-4332-3930-37I/OPort 0Port 0 is an 8-bit open-drain bidirectional I/O port.Port 0 pins that have 1s written to them float and can be used as high-impedance inputs.Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the GMS97X5X. External pull-up resistors are required during program verification.V SS 222016-Circuit ground potentialV CC 444038-Supply terminal for all operating modes N.C.1,1223,34-6,1728,39-No connectionSymbol Pin NumberInput/Output FunctionPLCC-44PDIP-40MQFP-44GMS90 SeriesDec. 1998 Ver 3.011FUNCTIONAL DESCRIPTIONThe GMS90 series is fully compatible to the standard 8051 microcontroller family.It is compatible with the general 8051 family. While maintaining all architectural and operational characteristics of the general 8051 family.Figure 1 shows a block diagram of the GMS90 seriesFigure 1. Block Diagram of the GMS90 seriesGMS90 Series12Dec. 1998 Ver 3.0CPUThe GMS90 series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12MHz crystal, 58% of the instructions are executed in 1.0µs (40MHz: 300ns).Special Function Register PSWReset value of PSW is 00H .BitFunctionCY Carry FlagAC Auxiliary Carry Flag (for BCD operations)F0General Purpose FlagRS10011RS00101Register Bank select control bitsBank 0 selected, data address 00H - 07H Bank 1 selected, data address 08H - 0F H Bank 2 selected, data address 10H - 17H Bank 3 selected, data address 18H - 1F H OV Overflow Flag F1General Purpose FlagPParity FlagSet/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.CY AC F0RS1RS0OV F1P 7654321LSBMSB Bit No.Addr. D0HPSWGMS90 SeriesDec. 1998 Ver 3.013SPECIAL FUNCTION REGISTERSAll registers, except the program counter and the four general purpose register banks, reside in the special func-tion register area.The 28 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area.All SFRs are listed in Table 1, Table 1, and Table 3.In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the functional blocks of the GMS90 series. Table 3 illustrates the contents of the SFRs.Table 1. Special Function Registers in Numeric Order of their AddressesAddress Register Contents afterReset Address Register Contents afterReset80H 81H 82H 83H 84H 85H 86H 87H P0 1)SP DPL DPH reserved reserved reserved PCON 1)Bit-addressable Special Function Register.FFH 07H 00H 00H XXH 2)XXH 2)XXH 2)0XX0000B 2)2)X means that the value is indeterminate and the location is reserved.90H 91H 92H 93H 94H 95H 96H 97H P1 1)reserved reserved reserved reserved reserved reserved reserved FF H 00H XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)88H 89H 8AH 8BH 8CH 8DH 8EH 3)8FH3)The GMS9XX54/56/58 have the AUXR0 register at address 8E H .TCON 1)TMOD TL0TL1TH0TH1 3)reserved00H 00H 00H 00H 00H 00H 3)XXH 2)98H 99H 9AH 9BH 9CH 9DH 9EH 9FHSCON 1)SBUF reserved reserved reserved reserved reserved reserved00H XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)8E HreservedXXXXXXX0B 2)8E HAUXR0GMS9XX51/52GMS9XX54/56/58XXXXXXXX B 2)GMS90 Series14Dec. 1998 Ver 3.0Table 1. Special Function Registers in Numeric Order of their Addresses (cont’d)Address Register Contents afterResetAddress Register Contents afterResetA0H A1H A2H A3H A4H A5H A6H A7H P2 1)reserved reserved reserved reserved reserved reserved reserved FFH XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)C8H C9H 3)CAH CBH CCH CDH CEH CFH T2CON 1)T2MOD RC2L RC2H TL2TH2reserved reserved 00H 3)00H 00H 00H 00H XXH 2)XXH 2)A8H A9H AAH ABH ACH ADH AEH AFH IE 1)reserved reserved reserved reserved reserved reserved reserved 0X000000B 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)D0H D1H D2H D3H D4H D5H D6H D7H PSW 1)reserved reserved reserved reserved reserved reserved reserved 00H XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)B0H B1H B2H B3H B4H B5H B6H B7H P3 1)reserved reserved reserved reserved reserved reserved reserved FFH XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)D8H D9H DAH DBH DCH DDH DEH DFH reserved reserved reserved reserved reserved reserved reserved reserved XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)B8H B9H BAH BBH BCH BDH BEH BFH IP 1)reserved reserved reserved reserved reserved reserved reserved XX000000B 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)E0H E1H E2H E3H E4H E5H E6H E7H ACC 1)reserved reserved reserved reserved reserved reserved reserved 00H XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)C0H C1H C2H C3H C4H C5H C6H C7Hreserved reserved reserved reserved reserved reserved reserved reservedXX H XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)E8H E9H EAH EBH ECH EDH EEH EFHreserved reserved reserved reserved reserved reserved reserved reservedXXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)GMS90 SeriesDec. 1998 Ver 3.015F0H F1H F2H F3H F4H F5H F6H F7HB 1)reserved reserved reserved reserved reserved reserved reserved00H XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)F8H F9H FAH FBH FCH FDH FEH FFHreserved reserved reserved reserved reserved reserved reserved reservedXXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)XXH 2)1)Bit-addressable Special Function Register.2)X means that the value is indeterminate and the location is reserved.3)Address C9H is configured as below.Table 1. Special Function Registers in Numeric Order of their Addresses (cont’d)Address Register Contents afterResetAddress Register Contents afterResetC9HreservedXXXXXX00B 2)XXXXXXX0B 2)C9HT2MODGMS9XX51/52GMS9XX54/56/58GMS90 Series16Dec. 1998 Ver 3.0Table 2. Special Function Registers - Functional BlocksBlock Symbol NameAddress Contents after Reset CPUACC B DPH DPL PSW SP AccumulatorB-RegisterData Pointer, High Byte Data Pointer, Low ByteProgram Status Word Register Stack PointerE0H 1)F0H 1)83H 82H D0H 1)81H 1)Bit-addressable Special Function register00H 00H 00H 00H 00H 07HInterrupt SystemIE IP Interrupt Enable Register Interrupt Priority Register A8H 1)B8H 1)0X000000B 2)XX000000B 2)2)X means that the value is indeterminate and the location is reservedPortsP0P1P2P3Port 0Port 1Port 2Port 380H 1)90H 1)A0H 1)B0H 1)FFH FFH FFH FFHSerial ChannelsPCON 3)SBUF SCON 3)This special function register is listed repeatedly since some bit of it also belong to other functional blocks Power Control Register Serial Channel Buffer Reg.Serial Channel 0 Control Reg.87H 99H 98H 1)0XXX0000B 2)XXH 2)00H Timer 0/ Timer 1TCON TH0TH1TL0TL1TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register88H 1)8CH 8DH 8AH 8BH 89H 00H 00H 00H 00H 00H 00HTimer 2T2CON T2MOD RC2H RC2L TH2TL2AUXR0 4)4)The AUXR0 is in the GMS9XX54/56/58 only.Timer 2 Control Register Timer 2 Mode RegisterTimer 2 Reload Capture Reg., High Byte Timer 2 Reload Capture Reg., Low Byte Timer 2, High Byte Timer 2, Low Byte Aux. Register 0C8H 1)C9H CBH CAH CDH CCH 8EH 00H 00H 00H 00H 00H 00HXXXXXXX0B 2)Power Saving ModesPCON3)Power Control Register87H0XXX0000B 2)GMS90 SeriesDec. 1998 Ver 3.017† indicates resident in the GMS9XX54/56/58, not in 9XX51/52.Table 3. Contents of SFRs, SFRs in Numeric OrderAddress Register Bit 765432180H P081H SP 82H DPL 83H DPH 87H PCON SM OD ---GF1GF0PDE IDLE 88H TCON TF1TR1TF0TR0IE1IT1IE0IT089H TMOD GATEC/TM1MTGATEC/TM1M08AH TL08BH TL18CH TH08DH TH18EH AUXR0 †-------A0 †90H P198H SCON SM0SM1SM2RENTB8RB8TIRI99H SBUF A0H P2A8H IE EA-ET2ESET1EX1ET0EX0B0H P3B8HIP--PT2PSPT1PX1PT0PX0SFR bit and byte addressable SFR not bit addressable- : this bit location is reservedGMS90 Series18Dec. 1998 Ver 3.0† indicates resident in the GMS9XX54/56/58, not in 9XX51/52.Table 3. Contents of SFRs, SFRs in Numeric Order (cont’d)Address Register Bit 7654321C8H T2CON TF2EXF2RCLK TCLK EXEN2TR2C/T2CP/RL2C9H T2MOD ------T2OE †DCENCAH RC2L CBH RC2H CCH TL2CDH TH2D0H PSW CYACF0RS1RS0OVF1PE0H ACC F0HBSFR bit and byte addressable SFR not bit addressable- : this bit location is reservedGMS90 SeriesDec. 1998 Ver 3.019TIMER / COUNTER 0 AND 1Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:In the "timer" function (C/T = "0") the register is incremented every machine cycle. Therefore the count rate is f OSC /12.In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding exter-nal input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is f OSC /24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 2 illustrates the input clock logic.Figure 2. Timer/Counter 0 and 1 Input Clock LogicTable 4. Timer/Counter 0 and 1 Operating ModesModeDescriptionTMODInput ClockGateC/TM1M0internalexternal (Max.)08-bit timer/counter with a divide-by-32 prescaler X X 00f OSC ÷(12×32)f OSC ÷(24×32)116-bit timer/counter X X 01f OSC ÷12f OSC ÷2428-bit timer/counter with 8-bit auto-reloadXX1f OSC ÷12f OSC ÷243Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stopsX X 11f OSC ÷12f OSC ÷24f OSC ÷ 12TMOD f OSC ÷ 12P3.4/T0P3.5/T1Max. f OSC /24C/T =1≥1TCON TR0 / 1TMODGate &P3.2 / INT0P3.3 / INT1Timer 0/1Input Clock1GMS90 Series20Dec. 1998 Ver 3.0TIMER 2Timer 2 is a 16-bit timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in Table 5.Note: ↓Table 5. Timer/Counter 2 Operating ModesMode T2CONT2MO DT2CON P1.1/T2EX RemarksInput ClockRCLK orTCLKCP/RL2TR2DCEN EXEN2internalexternal (P1.0/T2)16-bit Auto-Reload000000001111001101X X X ↓01reload upon over-flowreload trigger (fall-ing edge)Down counting Up counting f OSC ÷ 12Max.f OSC ÷2416-bit Capture1111XX 01X↓16 bit Timer/ Coun-ter (only up-count-ing)capture TH2,TL2 → RC2H,RC2L f OSC ÷ 12Max.f OSC ÷ 24Baud Rate Generator11XX 11XX 01X↓no overflowinterrupt request (TF2)extra external inter-rupt ("Timer 2")f OSC ÷ 12Max.f OSC ÷ 24Off X XXXXTimer 2 stops--GMS90 SeriesDec. 1998 Ver 3.021SERIAL INTERFACE (USART)The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes)as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 7.Table 6. USART Operating Modes ModeSCON BaudrateDescriptionSM0SM10Serial data enters and exits through RxD.TxD outputs the shift clock. 8-bit are transmit-ted/received (LSB first)101Timer 1/2 overflow rate8-bit UART10 bits are transmitted (through TxD) or received (RxD)210or 9-bit UART11 bits are transmitted (TxD) or received (RxD)311Timer 1/2 overflow rate9-bit UARTLike mode 2 except the variable baud rateTable 7. Formulas for Calculating Baud ratesBaud Ratederived fromInterface ModeBaudrateOscillator2Timer 1 (16-bit timer)(8-bit timer with 8-bit auto reload)1,31,3Timer 21,3f OSC 12------------f OSC 32------------f OSC 64------------f OSC 12------------2SMOD64------------------f OSC ×2SMOD32------------------Timer 1 overflow ()×2SMOD 32------------------f OSC 12256TH1()–[]×--------------------------------------------------×f OSC3265536RC2H RC2L ,()–[]×---------------------------------------------------------------------------------GMS90 Series22Dec. 1998 Ver 3.0INTERRUPT SYSTEMThe GMS90 series provides 5 (4K bytes ROM version) or 6 (above 8K bytes ROM version) interrupt sources with two priority levels. Figure 3 gives a general overview of the interrupt sources and illustrates the request and control flags.Figure 3. Interrupt Request SourcesPT0IP.1PT1IP.3PT2IP.5PS IP.4PX0IP.0PX1IP.2EA IE.7ET0IE.1ET1IE.3ET2IE.5ES IE.4EX0IE.0EX1IE.2TF0TCON.5TF1TCON.7≥1TF2T2CON.7EXF2T2CON.6≥1RI SCON.0TI SCON.1IE0TCON.1IE1TCON.3IT0TCON.0IT1TCON.2P3.2/INT0P3.3/INT1EXEN2T2CON.3P1.1/T2EXTimer 2 OverflowTimer 0 OverflowTimer 1 Overflow: Low level triggered : Falling edge triggeredLow PriorityHigh PriorityUARTGMS90 SeriesDec. 1998 Ver 3.023A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority in-terrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.If two requests of different priority level are received simultaneously, the request of higher priority is serviced.If requests of the same priority are received simultaneously, an internal polling sequence determines which re-quest is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9.Table 8. Interrupt Sources and their Corresponding Interrupt VectorsSource (Request Flags)VectorsVector AddressRESET IE0TF0IE1TF1RI + TITF2 + EXF2RESETExternal interrupt 0Timer 0 interrupt External interrupt 1Timer 1 interrupt Serial port interrupt Timer 2 interrupt0000H 0003H 000BH 0013H 001BH 0023H 002BHTable 9. Interrupt Priority-Within-LevelInterrupt SourcePriority External Interrupt 0Timer 0 Interrupt External Interrupt 1Timer 1 Interrupt Serial Channel Timer 2 InterruptIE0TF0IE1TF1RI + TITF2 + EXF2High ↓↓↓↓LowGMS90 Series24Dec. 1998 Ver 3.0Power Saving ModesTwo power down modes are available, the Idle Mode and Power Down Mode.The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence.Table 10 gives a general overview of the power saving modes.In the Power Down mode of operation, V CC can be reduced to minimize power consumption. It must be ensured,however, that V CC is not reduced before the Power Down mode is invoked, and that V CC is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down mode also restarts the oscillator. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset).Table 10. Power Saving Modes OverviewMode Entering Instruction Example Leaving by RemarksIdle modeORL PCON, #01H- Enabled interrupt - Hardware ResetCPU is gated offCPU status registers maintain their data.Peripherals are activePower-Down mode ORL PCON, #02H Hardware ResetOscillator is stopped, contents of on-chip RAM and SFR’s are maintained (leaving Power Down Mode means redefinition of SFR contents).。

*****客户NBU升级方案文档属性文档变更目录第一章项目背景与范围............................................................................................................................... - 5 -§1.1项目背景 . (5)§1.2范围 (5)第二章项目实施计划 .................................................................................................................................. - 8 -§2.1资源安排 . (8)§2.1.1人员资源安排 ................................................................................................................................ - 8 -§2.1.2软件资源 ........................................................................................................................................ - 9 -§2.2实施计划 . (9)第三章备份升级 .......................................................................................................................................... - 9 -§3.1升级前的准备 .. (9)§3.1.1预测升级期间备份作业 ................................................................................................................ - 9 -§3.1.2创建备份测试数据 ........................................................................................................................ - 9 -§3.1.3禁用Opscenter数据收集 ............................................................................................................ - 10 -§3.1.4 Catalog备份.................................................................................................................................. - 10 -§3.1.5 Disable media server ...................................................................................................................... - 10 -§3.1.6禁止新作业发起 .......................................................................................................................... - 10 -§3.1.7确认所有的作业已经完成 .......................................................................................................... - 10 -§3.1.8关闭NBU ...................................................................................................................................... - 10 -§3.1.9 EMM数据库一致性检查.............................................................................................................. - 10 -§3.1.10清理日志 .................................................................................................................................... - 11 -§3.1.11备份openv目录程序................................................................................................................. - 11 -§3.2升级MASTER S ERVER 软件 (11)§3.2.1升级NBU7.7 ................................................................................................................................. - 11 -§3.2.2检查install log .............................................................................................................................. - 12 -§3.2.3清除host_cache ........................................................................................................................... - 12 -§3.2.4激活备份策略 .............................................................................................................................. - 12 -§3.2.5激活media server ........................................................................................................................ - 12 -§3.2.6启用Opscenter数据收集 ............................................................................................................ - 12 -第四章回退步骤 .........................................................................................................................................- 13 -§4.1.1卸载NBU7.7 ................................................................................................................................. - 13 -§4.1.2安装NBU7.6 ................................................................................................................................. - 13 -§4.1.3检查install log .............................................................................................................................. - 13 -§4.1.4升级NBU7.6.0.4 ........................................................................................................................... - 14 -第五章介质服务器退网..............................................................................................................................- 14 -§5.1环境准备检查 (14)§5.2备份策略操作 (14)§5.2.1备份策略 ...................................................................................................................................... - 14 -§5.2.2 Vault配置...................................................................................................................................... - 15 -§5.3退网操作 .. (15)§5.3.1 Offline Media Server ...................................................................................................................... - 15 -§5.3.2 Media Server对应image .............................................................................................................. - 15 -§5.3.3修改Media Owner ....................................................................................................................... - 15 -§5.3.4配置恢复替代服务器 .................................................................................................................. - 15 -§5.3.5删除Media Server相关的设备 ................................................................................................... - 15 -§5.3.6删除media server ........................................................................................................................ - 16 -第六章升级CLIENT ....................................................................................................................................- 16 -§6.1升级前的准备 (16)§6.2升级W INDOWS客户端 (16)§6.3升级U NIX客户端 (17)§6.3.1准备工作 ...................................................................................................................................... - 17 -§6.3.2生成并sftp安装介质到客户端 .................................................................................................. - 17 -§6.3.3升级客户端软件 .......................................................................................................................... - 17 -§6.4升级验证 .. (17)§6.5回退方案 (17)§6.5.1项目进度计划 .............................................................................................................................. - 17 -第一章项目背景与范围§1.1项目背景由于7.6.0.3版本的不稳定性与s软件安装错误，现需要对大地保险备份系统进行改造升级，升级master与客户端改造。

FortiOS升级手册© Copyright 2006 美国飞塔有限公司版权所有。

本手册中所包含的任何文字、例子、图表和插图，未经美国飞塔有限公司的许可，不得因任何用途以电子、机械、人工、光学或其它任何手段翻印、传播或发布。

注册商标动态威胁防御系统（DTPS）, APSecure, FortiASIC, FortiBIOS, FortiBridge, FortiClient, FortiGate,FortiGate统一威胁管理系统, FortiGuard, FortiGuard-Antispam, FortiGuard-Antivirus, FortiGuard-Intrusion, FortiGuard-Web, FortiLog, FortiManager, Fortinet, FortiOS, FortiPartner, FortiProtect, FortiReporter, FortiResponse, FortiShield, FortiVoIP和FortiWiFi均是飞塔有限公司的注册商标（包括在美国和在其他国家的飞塔有限公司）。

本手册中提及的公司和产品由他们各自的所有者拥有其商标或注册商标。

服从规范FCC Class A Part 15 CSA/CUS注意：如果您安装的电池型号有误，可能会导致爆炸。

请根据使用说明中的规定处理废旧电池。

目录目录 (1)介绍 (9)Fortinet公司技术文档 (9)技术文档CD (9)Fortinet 知识库 (9)Fortinet 技术文档的建议与意见 (10)客户服务与技术支持 (10)设备注册 (10)升级说明 (11)配置文件备份 (11)安装向导 (11)FortiLog设备名称的更改 (11)LCD显示信息更改 (11)基于web管理器更改 (12)基于web管理器的功能变化 (13)CLI命令的更改 (13)FortiUSB支持 (13)公知信息 (14)系统设置 (14)防火墙 (15)高可用性（HA） (16)反病毒 (17)反垃圾邮件 (17)VPN (17)即时消息通信 (18)P2P (19)网页过滤 (19)FortiFuard web过滤 (19)虚拟域 (20)日志与报告 (20)新增功能与功能的更改 (21)系统设置 (21)状态 (21)会话 (22)网络 (22)配置 (22)管理员 (22)维护 (22)虚拟域 (24)路由表 (25)静态路由 (25)动态路由 (25)监控器 (25)防火墙 (26)策略 (26)地址 (26)服务 (26)虚拟IP (26)内容包括列表 (26)VPN (26)IPSec (27)SSL (27)证书 (27)用户 (27)LDAP (28)Windows AD (28)用户组 (28)反病毒防护 (28)文件模式 (28)隔离 (28)配置 (29)入侵防护（IPS） (29)特征 (29)异常 (29)协议解码器 (29)Web过滤 (30)内容屏蔽 (30)URL过滤 (30)Web过滤 (30)反垃圾邮件（之前名为“垃圾邮件过滤”） (31)禁忌词汇 (31)黑/白名单 (31)IM/P2P (32)统计表 (32)用户 (32)日志与报告 (32)日志配置 (33)日志访问 (33)报告 (34)HA (34)升级HA群集 (34)SNMP MIB与陷阱 (35)SNMP陷阱 (35)MIB文件名称 (35)FortiOS 3.0 MR2 (36)升级说明 (36)LCD显示更改 (36)FortiGuard状态显示图标 (37)FortiUSB支持 (37)新增功能与功能的更改 (37)系统设置 (37)路由 (38)防火墙 (39)VPN (40)用户 (40)Web过滤 (40)日志与报告 (40)报告配置 (41)报告访问 (41)HA (41)SNMP MIB与陷阱更改 (41)公知信息 (41)基于web的管理器 (41)系统设置 (42)系统设置（FortiWiFi-60A/AM） (42)防火墙 (43)高可用性（HA） (43)VPN (43)即时信息与P2P (44)IPS (44)Web过滤 (44)虚拟域 (44)反垃圾邮件 (45)日志与报告 (45)FortiOS 3.0MR3 (45)新增功能与更改的功能 (46)FortiOS3.0MR3中CLI操作的更改 (46)系统设置 (46)CLI控制台 (48)在FortiOS 3.0MR3中创建列表 (50)FortiGate-5050与FortiGate-5140设备的机架管理 (50)防火墙 (50)策略 (51)内容保护列表 (52)FortiClient检测防火墙策略 (52)RADIUS (52)VPN (53)SSL-VPN (53)反垃圾邮件 (54)IM/P2P (54)日志与报告 (54)内容存档 (54)HA (54)公知信息 (55)基于web的管理器 (55)虚拟域 (55)路由 (55)防火墙 (55)即时消息 (56)P2P (57)IPS (57)日志与报告 (57)解决方法 (58)FortiOS 3.0MR4 (59)新增功能与功能更改 (59)系统设置 (59)网络接口 (60)访问控制列表 (61)拓扑结构 (61)多个DHCP服务器的IP-MAC绑定 (63)硬盘健康状态监控（HDD） (63)命令行接口 (63)FortiGuard-web过滤与反垃圾邮件服务 (63)VDOM (64)路由 (64)防火墙 (64)策略 (65)VPN (65)入侵防护 (66)Web过滤 (67)IM、P2P与V oIP (67)日志与报告 (67)报告配置 (68)高可用性（HA） (68)公知信息 (69)基于web的管理器 (69)系统设置 (69)虚拟域 (69)高可用性（HA） (70)防火墙 (70)VPN (70)IPS (71)Web过滤 (71)即时消息（IM） (71)P2P (72)日志与报告 (72)更改固件版本 (73)备份配置 (73)使用基于web的管理器备份配置 (73)使用CLI备份配置文件 (74)升级FortiGate设备 (74)升级到FortiOS3.0 (74)使用基于web的管理器升级 (74)使用CLI升级 (75)校验升级 (76)返回到FortiOS2.80MR11 (76)备份FortiOS3.0配置 (76)将配置备份到PC (76)备份到FortiUSB Key (76)使用基于web的管理器恢复到FortiOS2.80MR11 (77)使用基于web的管理器恢复到FortiOS2.80MR11 (77)校验恢复 (78)使用CLI恢复到FortiOS2.80MR11 (78)使用CLI恢复到FortiOS2.80MR11 (78)恢复配置 (79)使用基于web的管理器恢复配置设置 (79)从FortiOS3.0MR1升级到FortiOS3.0MR2 (80)备份配置 (80)使用基于web的管理器备份当前配置 (80)使用CLI备份当前配置 (80)使用FortiUSB Key备份当前配置文件 (80)升级到FortiOS3.0MR2 (81)使用基于web的管理器升级 (81)使用CLI升级 (81)恢复到FortiOS3.0MR1 (82)备份配置 (82)将FortiOS3.0MR2的配置文件备份到PC (82)将当前配置备份到FortiUSB Key (82)恢复到FortiOS3.0MR1 (83)使用基于web的管理器恢复到FortiOS3.0 MR1 (83)使用CLI恢复到FortiOS3.0MR1 (83)恢复FortiOS3.0MR1配置 (84)使用基于web的管理器恢复配置设置 (84)使用CLI恢复FortiOS 3.0MR1的配置设置 (84)使用FortiUSB恢复设置 (85)有关FortiOS2.80MR11的升级 (85)从FortiOS2.80MR11升级到FortiOS 3.0MR1 (86)IPS组 (86)VPN防火墙策略 (86)PING发生器 (86)未被使用的IPSec VPN (86)FortiGuard web过滤替代信息字符串 (86)Web过滤与垃圾邮件过滤列表 (87)Active X, Cookie, 与Java Apple过滤 (87)没有配置“设备设置”的静态路由 (87)有关从FortiOS2.80MR11升级到FortiOS 3.0MR2 (87)日志过滤更改 (87)VDOM许可 (88)VDOM配置中IPSec手工密钥 (88)报警邮件替代信息 (88)报警邮件过滤 (88)区域中的防火墙策略 (88)有关从FortiOS2.80MR11升级到FortiOS3.0MR4 (88)管理用户 (89)策略路由 (89)WLAN接口下的VLAN (89)日志硬盘设置 (89)有关升级到FortiOS3.0MR2 (89)有关FortiOS3.0MR3升级 (89)介绍FortiNet公司在研发与更新其FortiGate防火墙设置的同时，一直注重开发、测试与优化FortiGate设备的操作系统。

广东海洋大学体育馆管理系统需求规格编号：GMS—SRS版本:1.1变更记录体育馆管理系统需求分析1 主要业务流程1.1场地申请管理员负责处理由学生提出的场地申请，审核其申请是否符合条件，如果不符合，则退回申请让学生修改，而如果已经符合，则批准申请并提交申请数据。

场地申请流程如下：1.2场地预约学生登录系统提出场地预约申请，管理员审核其申请是否符合条件，如果不符合，则退回申请让学生修改，而如果已经符合，则批准申请并提交申请数据。

场地预约流程如下：1.3器材租借申请管理员负责处理由学生提出的器材租借申请，审核其申请是否符合条件，如果不符合，则退回申请让学生修改，而如果已经符合，则批准申请并提交申请租借数据。

器材租借申请流程如下：体育馆管理系统需求分析体育馆管理系统需求分析2 系统角色GMS 用来对广东海洋大学体育馆进行管理，主要功能包括场地管理员人员管理、场地使用管理、体育赛事管理、器材管理、日常教务管理、营业统计报表。

GMS 包括四种角色（Actor ）： 1.管理员（Manager ）manager 指的是GMS 中不具有管理、更改职能的用户，但能够管理场地和器材，以及赛事的用户。

2．超级管理员（SuperMan ）超级管理员除了具有普通用户的功能能外，负责创建体育馆组织结构，导入管理员信息。

体育馆管理系统需求分析3．教师（Teacher）教师除了具有普通用户功能外，还可以对自己日常教务经行安排。

4．普通用户（User）普通用户指的是GMS中不具有管理、审批职能的用户，仅能够查看本人相关信息，进行场地预约，申请场地、赛事。

Teacher体育馆管理系统需求分析3 系统总任务模型GYM 任务模型4缩写表体育馆管理系统需求分析5 功能性需求任务描述5.1 人员管理模块5.1.1 添加场地管理员用户需求编号：GMS- AM-1需求描述：超级管理员登录系统后，添加场地管理员用户。

GMS- AM -1-1 添加场地管理员用户时，可以输入新场地管理员的用户名、密码、性别、联系方式等相关描述GMS- AM -1-2 添加场地管理员的信息都是必写的，如果某一项没有填写，要给出提示信息。

**有限公司K/3 系统升级项目方案创建日期：2012-11-5确认日期：当前版本：目录一、项目背景................................................................................................. 错误！未定义书签。

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三、项目方案与计划..................................................................................... 错误！未定义书签。

四、价值分析................................................................................................. 错误！未定义书签。

一、项目背景**有限公司（以下简称**公司）是从事工业自动化领域系列产品的研发、生产、销售和承接自动化工程及技术服务等。

**公司于2006年开始使用K/3软件，K/3系统经过多年使用，功能模块从财务、供应链到生产不断增加，应用程度也不断增加变得复杂。

**公司目前使用的是K/3 V10.3版本，随着业务的不断增长，已经不能满足业务需求，账套数据量也越来越大，对现有系统有以下问题急需解决：1. 随着账套数据量越来越大，K/3系统以及数据的安全隐患增加，K/3系统使用性能下降，信息部承担很大的系统及数据风险，最终用户的使用体验很差；护的工作，对最新的客户端操作系统、服务器操作系统及数据库已经不支持。

比如，最新的Windows 2008操作系统，SQL Server 2008数据库；3. 按照事业部核算，并账、并表等新版本需求；4. 各地分公司数据集中部署，建立集团数据中心需求；基于以上的问题，将客户升级到K/3 WISE V13.0版本，能够获得最新的金蝶软件应用，降低目前运行的风险以及客户的管理成本，支撑企业不断发展需要，帮助客户获取更多管理价值和应用功能。