DDR3 implementation challenges
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DDRx SDRAM IO
How Prism Handles These Challenges
Adopt a holistic approach
– Allows global optimization of complete solution
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DDR3 vs. DDR2 Physical Differences
DDR2
DDR3
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DDR2 vs. DDR3 Electrical Differences
DDR2 SSTL2 IO @ 1.8V 400 – 1033* Mbps Single/Differential DQS No Reset On-Chip Driver Calibration Option No Leveling Prefetch = 4 DDR3 SSTL2 IO @ 1.5V 800 – 2133* Mbps Differential DQS True Reset On-Chip Driver Calibration Required Using ZQ Pin Read & Write Leveling Prefetch = 8
FIRST TIME RIGHT!
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Examples of Success
DDR2 eye at 667 Mbps
DDR3 eye at 1333 Mbps
Courtesy of MetaRAM
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Clock Generation and Distribution
1.6 GHz 2x clock for DDR1600 with a wide tuning range Requires custom/semi-custom approach and up-front planning ASIC style distribution not precise enough
2009
The Interconnect IP Company
Content
Prism Circuits Overview Prism History With DDR Differences Between DDR2 and DDR3 DDR3 PHY Implementation Challenges Summary
Net effect is reduced eye opening!
∆L ∆C LC model (DDR) ∆R ∆L ∆C RLC model (DDR2) ∆R ∆L ∆C ∆G
RLCG model (DDR3)
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IO Design
Burden of off-chip signaling pushed to IO design SSTL15 design is therefore even more important Requires more accurate modeling of DDR channel Lots of signal integrity analysis and validation
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DDRx SDRAM IO
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Off Chip Signaling
Board characteristics have not improved
But higher slew rates from DDR2 to DDR3
– Translates to more reflections due to discontinuities – Implies higher SSO noise resulting in more IO timing uncertainty
Fly-by-routing of address routing in DIMMs causes multiple sub-domains within PHY Mesochronous clock domain crossing without flow control Aggregating 8-byte data slices into a synchronized 64-bit slice
Rules have changed for DDR3 Gbit+ baud rates
– Cannot achieve high speed on PHY without additional intelligence – Memory Controller needs to share some smarts with the PHY while speeding up – The line between the two is now softer
In-house design of clock macros, DDR FFs Borrow heavily from SerDes expertise
– High-precision Delay Lines and Phase Interpolators – Signal integrity analysis and simulation
PLL
1/D2
1/NF
PFD
CP
LPF
VCO
1/D1
1/FB
1/D2
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DLL Design
Must be capable of good granularity at high speed At 1600MT/s, data eye of 625ps requires single digit DQS calibration step size Needs to support a wide frequency range
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DFI Compliant DDR3/2 Combo PHY
DOMAIN CROSSING and HIGH SPEED MIXED SIGNAL SUBLAYER CONTROL WRITE READ UPDATE Denali Memory Controller STATUS TRAINING PRISM
Prism’s DDR History
45nm
DDR3/2
1600MT/s Fujitsu
65nm
DDR3/2
1600MT/s Fujitsu
DDR3/2
1600MT/s TSMC
90nm
130nm
1600MT/s TSMC
DDR3
180nm
800MT/s TSMC
DDR2
2006
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2007
2008
Content
Prism Circuits Overview Prism History With DDR Differences Between DDR2 and DDR3 DDR3 PHY Implementation Challenges Summary
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Corporate Overview
Prism Circuits delivers interconnect IP for high performance, low power wired multi-gigabit interfaces Strong Mixed-Signal team with demonstrated expertise
SDLL
DQS
Read Training
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பைடு நூலகம்
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Integration Challenges
DDR3 Memory Controller
DDR3 PHY
Controller-PHY Interface Is Very Important!
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Serial Interfaces
– Multiple SerDes IP
• PCIe Gen1 & Gen2 (65nm, 45nm) • XAUI 3.125 & 6.25 (65nm, 45nm) • 10G KR (65nm, 45nm)
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Deciding The Boundary
Traditional methods of abstraction
– Make the Memory Controller smart with lower clock rates – Make the PHY fast with reduced complexity
DDR3 PHY Implementation Challenges
Mahmud Hassan Principal Architect Prism Circuits, Inc.
The Interconnect IP Company
Content
Prism Circuits Overview Prism History With DDR Differences Between DDR2 and DDR3 DDR3 PHY Implementation Challenges Summary
