vp7615中文资料_数据手册_IC数据表

The VP7615 iCamHost™ Processor chip can decodethe signals from a variety of iVision™ compatible digital videocameras (such as Silicon Vision’s iCam™) and process themfor use in a host computer system. Digital cameras can offerreal cost and performance gains in applications which requirea digital video input, and iVision technology realises boththese benefits. In a typical analog camera the digitisedoutput from the CCD imager is normally encoded into ananalog composite video signal which then has to be re-digitised at the input to the host system. By employing theiVision approach the output from the camera is maintained asa digital signal, but in a format which allows for a low cost 9-wire connection to the host. Eliminating the unnecessaryconversion to an analog signal and back again not only savescost, but also avoids any possible degradation of imagequality. Other benefits include direct control of the camerafrom the host and the ability to power the camera from thehost system so saving the cost of a separate power supply.The VP7615 supports two software selectable CamPort™interface ports, either of which can receive the digital videofrom an iVision™ compatible digital video camera. Theoutput is a standard colour digital video signal, similar tostandard composite analog-digital decoder chips such as thePhilips SAA7110 and SAA7111. All iCamHost™ operatingmodes are controlled by the host PC via an I2C interface.Hardware I/O controls include output enable and I2C addressoffset.

NOTE: iCamTM, CamPort™ and iCamHost™ aretrademarks of Silicon Vision, Inc., Fremont, CA

ORDERING INFORMATIONVP7615 CG FP1NFEATURESIAccommodates different camera configurations based ona variety of CCD imager resolutionsIRequires only a small, low-cost 9 pin mini-DIN to connectto cameraIReceives the image signal from the camera in digital format a frame rate determined by the hostIDecodes all necessary synchronisation and clock signalsfrom the digital data streamIProgrammable gamma correction curve in RGBcolourspaceIProgrammable colour-separation matrixICollects image status data within user-defined rectangulargated zone of CCD sensorIProgrammable horizontal and vertical aperture correctionIPin-strap selectable output format in 16 bit YUV 4:2:2 or 8bit CCIR 656 YUV 4:2:2ITest pattern generator for SMPTE colourbarsIBypass mode to output unprocessed 8 bit CCD pixelsamples in the luminance channelIDual iCamPort™ camera input ports, software selectableICompletely iVision™ CompatibleIEight general purpose I/O pins for board level configurationcontrol and/or statusIProgrammable polarity for HSYNC, VSYNC, HACT &VACT control outputsIChip pinout is backwards compatible with VP7610VP7615

Colour Digital Video Camera Decoder ICAdvance Information

Supersedes February 1997 edition, DS4602 - 2.4DS4602 - 3.1 August 1997

2VP7615

Fig.1 Functional Block Diagram

DEMUX & SYNC RECOVERY

RAM CONTROL5

5CAMPORT ACAMPORT B

TWO HORIZONTAL LINE DELAY FIFO RAM

PIXELSEPARATOR

CONVERTER APERTURECORRECTION

GAMMACORRECTIONCMYG

RGB

UVYCONVERSION

CHROMINANCESUB-SAMPLINGAND FILTERING

OUTPUTFORMATTERCHROMINANCE& LUMINANCE METRICSSERIAL BUSCONTROLLERI2C CLK,DATAADDRESS OFFSET23CTRL

CTRLCTRL

CTRL

CTRLCTRLCTRLTO SERIAL BUS CONTROLLER MODULE

OUTPUT ENABLE

8 BIT CCIR656/16 BIT CCIR601VSYNC,HSYNC, VACT, HACTBFLAG,FIELDCLK1X,CLK2X

COLOUR MATRIX

COLOURSPACE

3VP7615

THEORY OF OPERATION

General OverviewThe VP7615 iCamHost™ is a fully synchronous real-timepipeline pixel processor for converting digitized CCDphotosite samples into co-sited, colour calibrated, gammacorrected and aperture corrected digital video in an industry-conventional format similar to analog video decoders. TheVP7615 supports the full iVision™ Command Set for controlof camera head functions such as frame rate, resolution,exposure and colour depth via the CamPort™ Interface.Access to all registers and functions is provided by an I2C statemachine.

Demux and sync recoveryThe incoming CCD photosite bytes come in a single nibble ata time in a “big-endian” fashion from one of two CamPort™s.These nibbles are clocked in via a separate pixel clock signal.The formatting signals such as start of active video, end ofactive video, and start of new frame are all encoded into thenibble stream. The output is an 8 bit byte of CCD sample foreach pixel clock, as well as separate horizontal and verticalsync signals.

RAM control & 2H line delay FIFO RAMSince the iCamHost™ assumes an interlaced scanning CCDwith a CMYG colour mosaic format, the colour content isderived from different locations around where the output videopixel is desired. Specifically, the first line from the CCDcontains “red-like” colour content, alternating with thefollowing line containing “blue-like” colour content. The thirdline is real-time, and the first opportunity to output properly co-sited luminance and chrominance as though the colour pixelswere superimposed upon themselves, all on the second line.