MCF54455_0812中文资料
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Freescale SemiconductorData Sheet: Advance InformationDocument Number: MCF54455Rev. 3, 12/2008This document contains information on a new product. Specifications and information herein are subject to change without notice.MCF54455Features•Version 4 ColdFire ® Core with MMU and EMAC •Up to 410 Dhrystone 2.1 MIPS @ 266 MHz•16-KBytes instruction cache and 16-KBytes data cache •32-KBytes internal SRAM•Support for booting from SPI-compatible flash, EEPROM, and FRAM devices•Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus masters •16-channel DMA controller•16-bit 133-MHz DDR/mobile-DDR/DDR2 controller •USB 2.0 On-the-Go controller with ULPI support•32-bit PCI controller @ 66MHz•ATA/ATAPI controller • 2 10/100 Ethernet MACs•Coprocessor for acceleration of the DES, 3DES, AES, MD5, and SHA-1 algorithms •Random number generator•Synchronous serial interface (SSI)• 4 periodic interrupt timers (PIT)• 4 32-bit timers with DMA support•DMA-supported serial peripheral interface (DSPI)• 3 UARTs•I 2C bus interfaceMCF5445x ColdFire ®Microprocessor Data SheetTable of Contents1MCF5445x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4 2Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . .53.1Analog Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . .53.2Oscillator Power Filtering . . . . . . . . . . . . . . . . . . . . . . . .63.3Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .63.3.1Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . .73.3.2Power-Down Sequence. . . . . . . . . . . . . . . . . . . .7 4Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .74.1Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74.2Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .154.3Pinout—360 TEPBGA. . . . . . . . . . . . . . . . . . . . . . . . . .16 5Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .175.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .175.2Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .185.3ESD Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195.4DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .195.5ClockTiming Specifications. . . . . . . . . . . . . . . . . . . . . .205.6Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . .225.7FlexBus Timing Specifications . . . . . . . . . . . . . . . . . . .235.8SDRAM AC Timing Characteristics. . . . . . . . . . . . . . . .255.9PCI Bus Timing Specifications . . . . . . . . . . . . . . . . . . 275.9.1Overshoot and Undershoot . . . . . . . . . . . . . . . 285.10ULPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 295.11SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 305.12I2C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 325.13Fast Ethernet Timing Specifications . . . . . . . . . . . . . . 335.13.1Receive Signal Timing Specifications . . . . . . . 335.13.2T ransmit Signal Timing Specifications . . . . . . . 345.13.3Asynchronous Input Signal Timing Specifications345.13.4MII Serial Management Timing Specifications. 355.1432-Bit Timer Module Timing Specifications. . . . . . . . . 355.15AT A Interface Timing Specifications. . . . . . . . . . . . . . . 365.16DSPI Timing Specifications. . . . . . . . . . . . . . . . . . . . . 365.17SBF Timing Specifications. . . . . . . . . . . . . . . . . . . . . . 385.18General Purpose I/O Timing Specifications. . . . . . . . . 395.19JT AG and Boundary Scan Timing. . . . . . . . . . . . . . . . 405.20Debug AC Timing Specifications. . . . . . . . . . . . . . . . . 42 6Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46LEGENDATA– Advanced T echnology Attachment Controller BDM– Background debug moduleCAU– Cryptography acceleration unitDSPI– DMA serial peripheral interfaceeDMA– Enhanced direct memory accessEMAC– Enchance multiply-accumulate unitEPORT– Edge port moduleFEC– Fast Ethernet ControllerGPIO– General Purpose Input/Output ModuleI2C– Inter-Intergrated Circuit INTC– Interrupt controllerJTAG– Joint T est Action Group interfaceMMU– Memory management unitPCI– Peripheral Component InterconnectPIT– Programmable interrupt timersPLL– Phase locked loop moduleRNG– Random Number GeneratorRTC– Real time clockSSI– Synchronous Serial InterfaceUSB OTG– Universal Serial Bus On-the-Go controllerFigure1. MCF54455 Block DiagramMCF5445x Family Comparison1MCF5445x Family ComparisonThe following table compares the various device derivatives available within the MCF5445x family.Table1. MCF5445x Family ConfigurationsModule MCF54450MCF54451MCF54452MCF54453MCF54454MCF54455 ColdFire Version 4 Core with EMAC••••••(Enhanced Multiply-Accumulate Unit)Core (System) Clock up to 240MHz up to 266MHzPeripheral Bus Clockup to 120MHz up to 133MHz(Core clock ÷ 2)External Bus Clockup to 60MHz up to 66MHz(Core clock ÷ 4)Performance (Dhrystone/2.1 MIPS)up to 370up to 410Independent Data/Instruction Cache16KBytes eachStatic RAM (SRAM)32KBytesPCI Controller••••••Cryptography Acceleration Unit (CAU)—•—•—•A TA Controller————••DDR SDRAM Controller••••••FlexBus External Interface••••••USB2.0On-the-Go••••••UTMI+Low Pin Interface(ULPI)••••••Synchronous Serial Interface (SSI)••••••Fast EC)112222thernet Controller(FEUARTs333333I2C••••••DSPI••••••Real Time Clock••••••32-bit DMA Timers444444Watchdog Timer(WDT)••••••Periodic Interrupt Timers(PIT)444444Edge Port Module (EPORT)••••••Interrupt Controllers(INTC)22222216-channel Direct Memory Access(DMA)••••••General Purpose I/O Module(GPIO)••••••JTAG — IEEE® 1149.1 Test Access Port••••••Package256 MAPBGA360 TEPBGAOrdering Information2Ordering Information3Hardware Design Considerations3.1Analog Power FilteringTo further enhance noise isolation, an external filter is strongly recommended for the analog V DD pins (VDD_A_PLL,VDD_RTC). The filter shown in Figure 2 should be connected between the board IV DD and the analog pins. The resistor and capacitors should be placed as close to the dedicated analog V DD pin as possible. The 10-Ω resistor in the given filter is required. Do not implement the filter circuit using only capacitors. The analog power pins draw very little current. Concerns regarding voltage loss across the 10-ohm resistor are not valid.Figure 2. System Analog V DD Power FilterTable 2. Orderable Part NumbersFreescale PartNumber DescriptionPackageSpeed Temperature MCF54450VM180MCF54450 Microprocessor256 MAPBGA180 MHz0° to +70° C MCF54450VM240240 MHz MCF54451CVM180MCF54451 Microprocessor180 MHz –40° to +85° C MCF54451VM240240 MHz 0° to +70° C MCF54452CVR200MCF54452 Microprocessor360 TEPBGA200 MHz –40° to +85° C MCF54452VR266266 MHz 0° to +70° C MCF54453CVR200MCF54453 Microprocessor200 MHz–40° to +85° C MCF54453VR266266 MHz 0° to +70° C MCF54454CVR200MCF54454 Microprocessor200 MHz –40° to +85° C MCF54454VR266266 MHz 0° to +70° C MCF54455CVR200MCF54455 Microprocessor200 MHz –40° to +85° C MCF54455VR266266 MHz0° to +70° CBoard IV DD10 Ω0.1 µFAnalog V DD Pin10 µFGNDHardware Design Considerations3.2Oscillator Power FilteringFigure 3 shows an example for isolating the oscillator power supply from the I/O supply (EVDD) and ground.Figure 3. Oscillator Power Filter3.3Supply Voltage SequencingFigure 4 shows situations in sequencing the I/O V DD (EV DD ), SDRAM V DD (SDV DD ), PLL V DD (PV DD ), and internal logic/core V DD (IV DD ).Figure 4. Supply Voltage Sequencing and Separation CautionsThe relationship between SDV DD and EV DD is non-critical during power-up and power-down sequences. SDV DD (2.5V or 1.8V) and EV DD are specified relative to IV DD .VDD_OSC10 Ω0.1 µF EVDD Pin1 µFGNDVSS_OSC100 MHzEV DD (3.3V)IV DD , PV DDTime3.3V1.5VD C P o w e r S u p p l y V o l t a g eNotes:1Input voltage must not be greater than the supply voltage (EV DD , SDV DD , IV DD , or PV DD ) by more than 0.5V at any time, including during power-up.2Use 50V/millisecond or slower rise time for all supplies.2.5V Supplies StableSDV DD (2.5V — DDR)1.8V SDV DD (1.8V — DDR2)Pin Assignments and Reset States 3.3.1Power-Up SequenceIf EV DD/SDV DD are powered up with the IV DD at 0V, the sense circuits in the I/O pads cause all pad output drivers connected to the EV DD/SDV DD to be in a high impedance state. There is no limit on how long after EV DD/SDV DD powers up before IV DD must power up. The rise times on the power supplies should be slower than 50V/millisecond to avoid turning on the internal ESD protection clamp diodes.3.3.2Power-Down SequenceIf IV DD/PV DD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after IV DD and PV DD power down before EV DD or SDV DD must power down. There are no requirements for the fall times of the power supplies.4Pin Assignments and Reset States4.1Signal MultiplexingThe following table lists all the MCF5445x pins grouped by function. The Dir column is the direction for the primary function of the pin only. Refer to Section4, “Pin Assignments and Reset States,” for package diagrams. For a more detailed discussion of the MCF5445x signals, consult the MCF54455Reference Manual (MCF54455RM).NOTEIn this table and throughout this document, a single signal within a group is designatedwithout square brackets (i.e., FB_AD23), while designations for multiple signals within agroup use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the twobracketed numbers when these numbers are separated by a colon.NOTEThe primary functionality of a pin is not necessarily its default functionality. Most pins thatare muxed with GPIO default to their GPIO functionality. See Table3 for a list of theexceptions.Table3. Special-Case Default Signal FunctionalityPin256 MAPBGA360 TEPBGAFB_AD[31:0]FB_AD[31:0] except when serial boot selects 0-bitboot port size.FB_BE/BWE[3:0]FB_BE/BWE[3:0]FB_CS[3:1]FB_CS[3:1]FB_OE FB_OEFB_R/W FB_R/WFB_T A FB_T AFB_TS FB_TSPin Assignments and Reset StatesPCI_GNT[3:0]GPIO PCI_GNT[3:0]PCI_REQ[3:0]GPIO PCI_REQ[3:0]IRQ1GPIO PCI_INTA andconfigured as an agent.A TA_RESETGPIOA TA resetTable 4. MCF5445x Signal Information and MuxingSignal Name GPIO Alternate 1Alternate 2P u l l -u p (U )1P u l l -d o w n (D )D i r e c t i o n 2V o l t a g e D o m a i nMCF54450MCF54451256 MAPBGA MCF54452MCF54453MCF54454MCF54455360 TEPBGAResetRESET ———U I EVDD L4Y18RSTOUT————OEVDDM15B17ClockEXTAL/PCI_CLK————I EVDD M16A16XT AL———U 3OEVDDL16A17Mode SelectionBOOTMOD[1:0]————I EVDD M5, M7AB17, AB21FlexBusFB_AD[31:24]PFBADH[7:0]4FB_D[31:24]——I/OEVDDA14, A13, D12, C12, B12, A12, D11, C11J2, K4, J1, K1–3,L1, L4FB_AD[23:16]PFBADMH[7:0]4FB_D[23:16]——I/O EVDDB11, A11, D10, C10, B10, A10, D9,C9L2, L3, M1–4,N1–2FB_AD[15:8]PFBADML[7:0]4FB_D[15:8]——I/O EVDD B9, A9, D8, C8, B8,A8, D7, C7P1–2, R1–3, P4,T1–2FB_AD[7:0]PFBADL[7:0]4FB_D[7:0]——I/O EVDD B7, A7, D6, C6, B6, A6, D5, C5T3–4, U1–3, V1–2,W1FB_BE/BWE[3:2]PBE[3:2]FB_TSIZ[1:0]——O EVDD B5, A5Y1, W2FB_BE/BWE[1:0]PBE[1:0]———O EVDD B4, A4W3, Y2FB_CLK ————O EVDD B13J3FB_CS[3:1]PCS[3:1]———O EVDD C2, D4, C3W5, AA4, AB3FB_CS0————O EVDD C4Y4FB_OE PFBCTL3———O EVDD A2AA1FB_R/W PFBCTL2———O EVDD B2AA3FB_T APFBCTL1——UIEVDDB1AB2Table 3. Special-Case Default Signal Functionality (continued)Pin 256 MAPBGA360 TEPBGAPin Assignments and Reset StatesFB_TS PFBCTL0FB_ALE FB_TBST—O EVDDA3Y3PCI Controller 5PCI_AD[31:24]—FB_A[31:24]——I/OEVDD —C11, D11, A10, B10, J4, G2, G3,F1PCI_AD[23:0]—FB_A[23:0]——I/O EVDDK14–13, J15–13, H13–15, G15–13, F14–13, E15–13, D16, B16, C15, B15, C14, D15, C16, D14D12, C12, B12, A11, B11, B9, D9, D10, A8, B8, A5, B5, A4, A3, B3, D4, D3, E 3–E 1, F3, C2, D2, C1PCI_CBE[3:0]————I/O EVDD —G4, E4, D1, B1PCI_DEVSEL ————O EVDD —F2PCI_FRAME ————I/O EVDD —B2PCI_GNT3PPCI7A T A_DMACK——O EVDD —B7PCI_GNT[2:1]PPCI[6:5]———O EVDD —C8, C9PCI_GNT0/PCI_EXTREQ PPCI4———OEVDD—A9PCI_IDSEL ————I EVDD —D5PCI_IRDY ————I/O EVDD —C3PCI_P AR ————I/O EVDD —C4PCI_PERR ————I/O EVDD —B4PCI_REQ3PPCI3A TA_INTRQ——I EVDD —C7PCI_REQ[2:1]PPCI[2:1]———I EVDD —D7, C5PCI_REQ0/PCI_EXTGNT PPCI0———IEVDD—A2PCI_RST ————O EVDD —B6PCI_SERR ————I/O EVDD —A6PCI_STOP ————I/O EVDD —A7PCI_TRDY————I/OEVDD—C10SDRAM ControllerSD_A[13:0]————O SDVDDR1, P1, N2, P2, R2, T2, M4, N3, P3, R3, T3, T4, R4, N4V22, U20–22, T19–22, R20–22, N19, P20–21SD_BA[1:0]————O SDVDD P4, T5P22, P19SD_CAS ————O SDVDD T6L19SD_CKE————OSDVDDN5N22Table 4. MCF5445x Signal Information and Muxing (continued)Signal Name GPIO Alternate 1Alternate 2P u l l -u p (U )1P u l l -d o w n (D )D i r e c t i o n 2V o l t a g e D o m a i nMCF54450MCF54451256 MAPBGA MCF54452MCF54453MCF54454MCF54455360 TEPBGAPin Assignments and Reset StatesSD_CLK ————O SDVDD T9L22SD_CLK ————O SDVDD T8M22SD_CS[1:0]————O SDVDDP6, R6L20, M20SD_D[31:16]————I/O SDVDD N6, T7, N7, P7, R7, R8, P8, N8, N9, T10, R10, P10, N10, T11, R11, P11L21, K22, K21,K20, J20, J19, J21, J22, H20, G22, G21, G20, G19,F22, F21, F20SD_DM[3:2]————O SDVDD P9, N12H21, E21SD_DQS[3:2]————O SDVDD R9, N11H22, E22SD_RAS ————O SDVDD P5N21SD_VREF ————I SDVDD M8M21SD_WE————OSDVDDR5N20External Interrupts Port 6IRQ7PIRQ7———I EVDD L1ABB13IRQ4PIRQ4—SSI_CLKIN—I EVDD L2ABB13IRQ3PIRQ3———I EVDD L3AB14IRQ1PIRQ1PCI_INTA——IEVDDF15C6FEC0FEC0_MDC PFECI2C3———O EVDD F3AB8FEC0_MDIO PFECI2C2———I/O EVDD F2Y7FEC0_COL PFEC0H4—ULPI_DA T A7—I EVDD E1AB7FEC0_CRS PFEC0H0—ULPI_DA T A6—I EVDD F1AA7FEC0_RXCLK PFEC0H3—ULPI_DA T A1—I EVDD G1AA8FEC0_RXDV PFEC0H2FEC0_RMII_CRS_DV——IEVDDG2Y8FEC0_RXD[3:2]PFEC0L[3:2]—ULPI_DA TA[5:4]—I EVDD G3, G4AB9, Y9FEC0_RXD1PFEC0L1FEC0_RMII_RXD1——I EVDD H1W9FEC0_RXD0PFEC0H1FEC0_RMII_RXD0——I EVDD H2AB10FEC0_RXER PFEC0L0FEC0_RMII_RXER ——I EVDD H3AA10FEC0_TXCLK PFEC0H7FEC0_RMII_REF_CLK——IEVDDH4Y10FEC0_TXD[3:2]PFEC0L[7:6]—ULPI_DA TA[3:2]—O EVDD J1, J2W10, AB11FEC0_TXD1PFEC0L5FEC0_RMII_TXD1——OEVDDJ3AA11Table 4. MCF5445x Signal Information and Muxing (continued)Signal Name GPIO Alternate 1Alternate 2P u l l -u p (U )1P u l l -d o w n (D )D i r e c t i o n 2V o l t a g e D o m a i nMCF54450MCF54451256 MAPBGA MCF54452MCF54453MCF54454MCF54455360 TEPBGAPin Assignments and Reset StatesFEC0_TXD0PFEC0H5FEC0_RMII_TXD0——O EVDD J4Y11FEC0_TXEN PFEC0H6FEC0_RMII_TXEN——O EVDD K1W11FEC0_TXERPFEC0L4—ULPI_DA T A0—O EVDDK2AB12FEC1FEC1_MDC PFECI2C5—ATA_DIOR —O EVDD —W20FEC1_MDIO PFECI2C4—A T A_DIOW —I/O EVDD —Y22FEC1_COL PFEC1H4—A T A_DA T A7—I EVDD —AB18FEC1_CRS PFEC1H0—A T A_DA T A6—I EVDD —AA18FEC1_RXCLK PFEC1H3—A T A_DA T A5—I EVDD —W14FEC1_RXDV PFEC1H2FEC1_RMII_CRS_DVATA_DA TA15—IEVDD—AB15FEC1_RXD[3:2]PFEC1L[3:2]—A T A_DA T A[4:3]—I EVDD —AA15, Y15FEC1_RXD1PFEC1L1FEC1_RMII_RXD1ATA_DA TA14—I EVDD —AA17FEC1_RXD0PFEC1H1FEC1_RMII_RXD0ATA_DA TA13—I EVDD —Y17FEC1_RXER PFEC1L0FEC1_RMII_RXER ATA_DA TA12—I EVDD —W17FEC1_TXCLK PFEC1H7FEC1_RMII_REF_CLKATA_DA TA11—IEVDD—AB19FEC1_TXD[3:2]PFEC1L[7:6]—A T A_DA T A[2:1]—O EVDD —Y19, W18FEC1_TXD1PFEC1L5FEC1_RMII_TXD1ATA_DA TA10—O EVDD —AA19FEC1_TXD0PFEC1H5FEC1_RMII_TXD0A T A_DA T A9—O EVDD —Y20FEC1_TXEN PFEC1H6FEC1_RMII_TXENA T A_DA T A8—O EVDD —AA21FEC1_TXERPFEC1L4—A T A_DA T A0—OEVDD—AA22USB On-the-GoUSB_DM ————O USB VDD F16A14USB_DP ————O USB VDD E16A15USB_VBUS_EN PUSB1USB_PULLUPULPI_NXT —O USB VDD E5AA2USB_VBUS_OCPUSB0—ULPI_STP UD 7IUSB VDDB3V4ATAATA_BUFFER_EN PATAH5———O EVDD —Y13A T A_CS[1:0]P A TAH[4:3]———OEVDD—W21, W22Table 4. MCF5445x Signal Information and Muxing (continued)Signal Name GPIO Alternate 1Alternate 2P u l l -u p (U )1P u l l -d o w n (D )D i r e c t i o n 2V o l t a g e D o m a i nMCF54450MCF54451256 MAPBGA MCF54452MCF54453MCF54454MCF54455360 TEPBGAPin Assignments and Reset StatesA T A_DA[2:0]P A TAH[2:0]———O EVDD —V19–21A T A_RESET P A T AL2———O EVDD —W13A T A_DMARQ P A T AL1———I EVDD —AA14ATA_IORDYP A T AL0———I EVDD—Y14Real Time ClockEXTAL32K ————I EVDD J16A13XTAL32K————OEVDDH16A12SSISSI_MCLK PSSI4———O EVDD T13D20SSI_BCLK PSSI3U1CTS ——I/O EVDD R13E19SSI_FS PSSI2U1RTS ——I/O EVDD P12E20SSI_RXD PSSI1U1RXD —UD I EVDD T12D21SSI_TXDPSSI0U1TXD—UDOEVDDR12D22I 2CI2C_SCL PFECI2C1—U2TXD U I/O EVDD K3AA12I2C_SDAPFECI2C0—U2RXD UI/OEVDDK4Y12DMADACK1PDMA3—ULPI_DIR —O EVDD M14C17DREQ1PDMA2—USB_CLKINU I EVDD P16C18DACK0PDMA1DSPI_PCS3——O EVDD N15A18DREQ0PDMA0——UIEVDDN16B18DSPIDSPI_PCS5/PCSS PDSPI6———O EVDD N14D18DSPI_PCS2PDSPI5———O EVDD L13A19DSPI_PCS1PDSPI4SBF_CS ——O EVDD P14B20DSPI_PCS0/SS PDSPI3——U I/O EVDD R16D17DSPI_SCK PDSPI2SBF_CK ——I/O EVDD R15A20DSPI_SIN PDSPI1SBF_DI —8I EVDD P15B19DSPI_SOUTPDSPI0SBF_DO——OEVDDN13C20Table 4. MCF5445x Signal Information and Muxing (continued)Signal Name GPIO Alternate 1Alternate 2P u l l -u p (U )1P u l l -d o w n (D )D i r e c t i o n 2V o l t a g e D o m a i nMCF54450MCF54451256 MAPBGA MCF54452MCF54453MCF54454MCF54455360 TEPBGAPin Assignments and Reset StatesUARTsU1CTS PUART7———I EVDD —V3U1RTS PUART6———O EVDD —U4U1RXD PUART5———I EVDD —P3U1TXD PUART4———O EVDD —N3U0CTS PUART3———I EVDD M3Y16U0RTS PUART2———O EVDD M2AA16U0RXD PUART1———I EVDD N1AB16U0TXDPUART0———OEVDDM1W15Note:The UART1 and UART 2 signals are multiplexed on the DMA timers and I2C pins.DMA TimersDT3IN PTIMER3DT3OUT U2RXD —I EVDD C13H2DT2IN PTIMER2DT2OUT U2TXD —I EVDD D13H1DT1IN PTIMER1DT1OUT U2CTS —I EVDD B14H3DT0INPTIMER0DT0OUTU2RTS —IEVDDA15G1BDM/JTAG 9PSTDDA TA[7:0]————O EVDDE2, D1, F4, E3, D2, C1, E4, D3AA6, AB6, AB5,W6, Y6, AA5, AB4,Y5JTAG_EN ———D I EVDD M11C21PSTCLK —TCLK ——I EVDD P13C22DSI —TDI —U I EVDD T15C19DSO —TDO ——O EVDD T14A21BKPT —TMS —U I EVDD R14B21DSCLK—TRST—UIEVDDM13B22TestTEST ———D I EVDD M6AB20PLLTEST————OEVDDK16D15Table 4. MCF5445x Signal Information and Muxing (continued)Signal Name GPIO Alternate 1Alternate 2P u l l -u p (U )1P u l l -d o w n (D )D i r e c t i o n 2V o l t a g e D o m a i nMCF54450MCF54451256 MAPBGA MCF54452MCF54453MCF54454MCF54455360 TEPBGAPin Assignments and Reset StatesPower SuppliesIVDD——————E6–12, F5, F12D6, D8, D14, F4, H4, N4, R4, W4, W7, W8, W12, W16, W19EVDD ——————G5, G12, H5, H12, J5, J12, K5, K12, L5–6, L12D13, D19, G8, G11, G14, G16, J7,J16, L7, L16, N16,P7, R16, T8, T12,T14, T16SD_VDD ——————L7–11, M9, M10F19, H19, K19, M19, R19, U19VDD_OSC ——————L14B16VDD_A_PLL ——————K15C14VDD_RTC ——————M12C13VSS——————A1, A16, F6–11, G6–11, H6–11, J6–11, K6–11, T1, T16A1, A22, B14, G7, G9–10, G12–13, G15, H7, H16,J9–14, K7, K9–14,K16, L9–14, M7, M9–M14, M16, N9–14, P9–14, P16, R7, T7, T9–11, T13, T15, AB1, AB22VSS_OSC——————L15C161Pull-ups are generally only enabled on pins with their primary function, except as noted.2Refers to pin’s primary function.3Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).4Serial boot must select 0-bit boot port size to enable the GPIO mode on these pins.5When the PCI is enabled, all PCI bus pins come up configured as such. This includes the PCI_GNT and PCI_REQ lines, which have as a PCI host.and IRQ1/PCI_INT A come up as GPIO.6GPIO functionality is determined by the edge port module. The pin multiplexing and control module is only responsible for assigning the alternate functions.7Depends on programmed polarity of the USB_VBUS_OC signal.8Pull-up when the serial boot facility (SBF) controls the pin9If JTAG_EN is asserted, these pins default to Alternate 1 (JT AG) functionality. The pin multiplexing and control module is not responsible for assigning these pins.Table 4. MCF5445x Signal Information and Muxing (continued)Signal Name GPIO Alternate 1Alternate 2P u l l -u p (U )1P u l l -d o w n (D )D i r e c t i o n 2V o l t a g e D o m a i n MCF54450MCF54451256 MAPBGA MCF54452MCF54453MCF54454MCF54455360 TEPBGAPin Assignments and Reset States4.2Pinout—256 MAPBGAThe pinout for the MCF54450 and MCF54451 packages are shown below.Figure 5. MCF54450 and MCF54451 Pinout (256 MAPBGA)12345678910111213141516AVSSFB_OEFB_TSFB_BE/BWE0FB_BE/BWE2FB_AD 2FB_AD 6FB_AD 10FB_AD 14FB_AD 18FB_AD 22FB_AD 26FB_AD 30FB_AD 31T0INVSSAB FB_TAFB_R/W USB_VBUS_OCFB_BE/BWE1FB_BE/BWE3FB_AD 3FB_AD 7FB_AD 11FB_AD 15FB_AD 19FB_AD 23FB_AD 27FB_CLKT1INPCI_AD 4PCI_AD6BC PST DDATA2FB_CS3FB_CS1FB_CS0FB_AD0FB_AD 4FB_AD 8FB_AD 12FB_AD 16FB_AD 20FB_AD 24FB_AD 28T3IN PCI_AD 3PCI_AD 5PCI_AD1CDPST DDATA6PST DDATA3PST DDATA0FB_CS2FB_AD1FB_AD 5FB_AD 9FB_AD 13FB_AD 17FB_AD 21FB_AD 25FB_AD 29T2INPCI_AD 0PCI_AD 2PCI_AD7DEFEC0_COL PST DDATA7PST DDATA4PSTDDA TA1USB_VBUS_EN IVDDIVDDIVDDIVDDIVDDIVDDIVDDPCI_AD 8PCI_AD 9PCI_AD10USB_DP EF FEC0_CRS FEC0_MDIO FEC0_MDC PST DDA TA5IVDD VSS VSS VSS VSS VSS VSS IVDD PCI_AD 11PCI_AD 12IRQ_1USB_DM F G FEC0_RXCLK FEC0_RXDV FEC0_RXD3FEC0_RXD2EVDD VSS VSS VSS VSS VSS VSS EVDD PCI_AD 13PCI_AD 14PCI_AD 15NC G H FEC0_RXD1FEC0_RXD0FEC0_RXER FEC0_TXCLK EVDD VSS VSS VSS VSS VSS VSS EVDD PCI_AD 18PCI_AD 17PCI_AD 16XTAL 32K H J FEC0_TXD3FEC0_TXD2FEC0_TXD1FEC0_TXD0EVDD VSS VSS VSS VSS VSS VSS EVDD PCI_AD 19PCI_AD 20PCI_AD 21EXTAL 32K J K FEC0_TXEN FEC0_TXER I2C_SCL I2C_SDA EVDD VSS VSS VSS VSS VSS VSS EVDD PCI_AD 22PCI_AD 23VDD_A _PLL PLL TEST K LIRQ_7IRQ_4IRQ_3RESET EVDD EVDD SDVDD SDVDD SDVDD SDVDD SDVDD EVDD DSPI_PCS2VDD_OSC VSS_OSC XTALLM U0TXD U0RTSU0CTSSD_A7BOOT MOD1TESTBOOTMOD0SD_VREFSDVDDSDVDDJTAG_EN VDD_RTC TRST DACK1RST OUT EXTAL M N U0RXD SD_A11SD_A6SD_A0SD_CKE SD_D31SD_D29SD_D24SD_D23SD_D19SD_DQS2SD_DM2DSPI_SOUT DSPI_PCS5DACK0DREQ0N P SD_A12SD_A10SD_A5SD_BA1SD_RAS SD_CS1SD_D28SD_D25SD_DM3SD_D20SD_D16SSI_FSTCLK DSPI_PCS1DSPI_SIN DREQ1P R SD_A13SD_A9SD_A4SD_A1SD_WESD_CS0SD_D27SD_D26SD_DQS3SD_D21SD_D17SSI_TXD SSI_BCLK TMS DSPI_SCK DSPI_PCS0R TVSS SD_A8SD_A3SD_A2SD_BA0SD_CAS SD_D30SD_CLK SD_CLK SD_D22SD_D18SSI_RXD SSI_MCLK TDO TDI VSS T12345678910111213141516Pin Assignments and Reset States4.3Pinout—360 TEPBGAThe pinout for the MCF54452, MCF54453, MCF54454, and MCF54455 packages are shown below.Figure 6. MCF54452, MCF54453, MCF54454, and MCF54455 Pinout (360 TEPBGA)12345678910111213141516171819202122AGND PCI_REQ0PCI_AD10PCI_AD11PCI_AD13PCI_SERR PCI_STOP PCI_AD15PCI_GNT0PCI_AD29PCI_AD20XTAL 32K EXTAL 32K USB_DM USB_DP EXTAL XTAL DACK0DSPI_PCS2DSPI_SCK TDOGNDAB PCI_CBE0PCI_FRAME PCI_AD9PCI_PERR PCI_AD12PCI_RST PCI_GNT3PCI_AD14PCI_AD18PCI_AD28PCI_AD19PCI_AD21NC GND NCVDD_OSC RST OUT DREQ0DSPI_SIN DSPI_PCS1TMS TRST BC PCI_AD0PCI_AD2PCI_IRDY PCI_P AR PCI_REQ1IRQ1PCI_REQ3PCI_GNT2PCI_GNT1PCI_TRDY PCI_AD31PCI_AD22VDD_RTC VDD_A_PLL NC VSS_OSC DACK1DREQ1TDIDSPI_SOUT JTAG_EN TCLK CD PCI_CBE1PCI_AD1PCI_AD7PCI_AD8PCI_IDSELIVDD PCI_REQ2IVDDPCI_AD17PCI_AD16PCI_AD30PCI_AD23EVDDIVDDPLL TESTNCDSPI_PCS0DSPI_PCS5EVDD SSI_MCLK SSI_RXD SSI_TXD DE PCI_AD4PCI_AD5PCI_AD6PCI_CBE2SSI_BCLK SSI_FSSD_DM2SD_DQS2EF PCI_AD24PCI_DE VSEL PCI_AD3IVDD SDVDDSD_D16SD_D17SD_D18FG T0INPCI_AD26PCI_AD25PCI_CBE3GND EVDD GND GND EVDD GND GND EVDD GND EVDD SD_D19SD_D20SD_D21SD_D22GH T2IN T3IN T1INIVDD GND GND SDVDD SD_D23SD_DM3SD_DQS3HJ FB_AD 29FB_AD 31FB_CLK PCI_AD27EVDD GND GND GND GND GND GND EVDD SD_D26SD_D27SD_D25SD_D24JK FB_AD 28FB_AD 27FB_AD 26FB_AD 30GND GND GND GND GND GND GND GND SDVDD SD_D28SD_D29SD_D30KL FB_AD 25FB_AD 23FB_AD 22FB_AD 24EVDD GND GND GND GND GND GND EVDD SD_CAS SD_CS1SD_D31SD_CLK LM FB_AD 21FB_AD 20FB_AD 19FB_AD 18GND GND GND GND GND GND GND GND SDVDDSD_CS0SD_VREF SD_CLK MN FB_AD 17FB_AD 16U1TXDIVDD GND GND GND GND GND GND GND EVDD SD_A2SD_WESD_RAS SD_CKE NP FB_AD 15FB_AD 14U1RXD FB_AD 10EVDD GND GND GND GND GND GND GND SD_BA0SD_A1SD_A0SD_BA1PR FB_AD 13FB_AD 12FB_AD 11IVDD GND EVDD SDVDDSD_A5SD_A4SD_A3RT FB_AD 9FB_AD 8FB_AD 7FB_AD 6GND EVDD GND GND GND EVDD GND EVDD GND EVDD SD_A9SD_A8SD_A7SD_A6TU FB_AD 5FB_AD 4FB_AD 3U1RTS SDVDD SD_A12SD_A11SD_A10UV FB_AD 2FB_AD 1U1CTSUSB_VBUS_OC AT A_DA2ATA_DA1A TA_DA0SD_A13VWFB_AD 0FB_BE/BWE2FB_BE/BWE1IVDDFB_CS3PST DDAT A4IVDDIVDDFEC0_RXD1FEC0_TXD3FEC0_TXEN IVDDATA_RESET FEC1_RXCLK U0TXDIVDDFEC1_RXER FEC1_TXD2IVDDFEC1_MDC A TA_CS1A TA_CS0WY FB_BE/BWE3FB_BE/BWE0FB_TS FB_CS0PST DDA TA0PST DDAT A3FEC0_MDIO FEC0_RXDV FEC0_RXD2FEC0_TXCLKFEC0_TXD0I2C_SDA AT A_BU FFER_ENA TA_IORDYFEC1_RXD2U0CTS FEC1_RXD0RESETFEC1_TXD3FEC1_TXD0NC FEC1_MDIOYAA FB_OE USB_VBUS_EN FB_R/W FB_CS2PST DDA TA2PST DDAT A7FEC0_CRS FEC0_RXCLK NCFEC0_RXER FEC0_TXD1I2C_SCL IRQ4A TA_DMARQ FEC1_RXD3U0RTSFEC1_RXD1FEC1_CRS FEC1_TXD1NCFEC1_TXEN FEC1_TXERAAAB GND FB_T A FB_CS1PST DDATA1PST DDA TA5PST DDAT A6FEC0_COL FEC0_MDC FEC0_RXD3FEC0_RXD0FEC0_TXD2FEC0_TXER IRQ7IRQ3FEC1_RXDV U0RXD BOOT MOD1FEC1_COL FEC1_TXCLK TEST BOOT MOD0GND AB12345678910111213141516171819202122。