Systolic Arrays & VLIW.ppt

Google Pixel 6 Pro 128GBGoogle Tensor Application Processor PoP(Tensor AP + Micron 12 GB LPDDR5 MT62F1536M64D8CH-031 WT:A)Kioxia 128 GB NAND Flash MemorySamsung SHANNON A5123 5G ModemSamsung SHANNON 5511 RF TransceiverMaxim MAX77759A PMICSTMicroelectronics NFC Controller ST54KMaxim MAX20339EWB Surge protection ICNXP PCA9468 Battery Charger ICSTMicroelectronics MCU ST33J2M0Google H1D3M Titan M security processorSamsung Exynos SM 5800 Supply Modulator (2 pcs)Cirrus Logic CS35L41B Audio Amplifier (2 pcs)Cirrus Logic CS40L25 Audio Amplifier HapticBroadcom BCM47765 GNSS Receiver ICFigure 1. Google Pixel 6 Pro Board ShotSkyworks SKY53737 FEMSkyworks SKY58260-11 FEMSamsung Exynos SM 5800 Supply ModulatorQorvo QM77080 FEMSkyworks SKY53738 FEM (3 pcs)Skyworks SKY77652-31 PAMSamsung Shannon 5311A PMICIDT P9412 Wireless Charing Receiver ICSamsung PMIC S2MPG10Samsung PMIC S2MPG11Unknown, Wi-Fi/BT Module (likely)Figure 2. Google Pixel 6 Pro Board ShotGoogle Tensor Application ProcessorGoogle’s semi-custom application processor is all about AI. Google built a custom deep learning accelerator (DLA) to challenge Qualcomm and Samsung in inferencing. The custom DLA features 16 (4x4) instantiations of systo lic arrays that outscore both Qualcomm and Samsung on ETH Zurich’s AI-Benchmark. While impressive, AI-Benchmark only tells half the story since it heavily relies on FP16 for inferencing. Most mobile AI network designers like to use INT8 for their layers because of the increased energy efficiency and comparable accuracy. For INT8 processing, the Pixel’s DLA lags both Qualcomm and Samsung in object detection, image segmentation, and image classification according to MLPerf 1.0.1 results.Figure 3. Google Deep Learning Accelerator (DLA)TechInsights' lab team has done a great job in getting the Google Tensor processor die photos quickly. The Tensor die has a die size (seal) of 10.38mm x 10.43mm = 108.26mm2 and is fabbed on Samsung's5nm process node technology. The following images show die marks and the die photo.Figure 4. Google Tensor Die MarkingsFigure 5. Google Tensor Package MarkingsThe die mark “S5P9845” conforms to the traditional Samsung Exynos processor naming rule, where the Exynos 990 Application Processor has the die marks of S5E9830, the Exynos 2100 5G SoC has die marks of S5E9840, and the Exynos 1080 5G SoC has S5E9815.We have heard of possible ties between the Google Tensor and Samsung Exynos processors, and our analysis of the Tensor die continues. It does appear that the foundry supplier for the Tensor die is Samsung. We will confirm the process node soon, which we ex pect is in Samsung’s 5LPE.Figure 6. Google Tensor Die PhotoSecurityGoogle designed the Titan M2, which is a custom RISC-V controller, to support Android Strongbox, securely generating keys, storing passwords, and protecting PINs. The company tested and certified its Titan chip through an external evaluation lab, achieving AVA_VAN.5 certification—one of the highest levels for smartphones.Mobile RF Components in the Google Pixel 6 ProOn the mobile RF front, the Pixel 6 brings about some key new developments:∙Google / Samsung ties in the Tensor: Now that we have spent some time examining the Google Tensor SoC, we have analyzed the device tree file system of the Linux kernel for Google Pixel 6, and it shows that some blocks of the Google GS101 Tensor processor are shared with Samsung’s Exynos.∙ A first for the US market: Samsung has developed a full 5G radio solution, which is included in the Pixel 6, making this the first major 5G phone in the US that does not include a Qualcommmodem.Looking forward, we note that Oppo is looking to develop their own SoC solutions for higher end phones - is Qualcomm’s dominance in this space diminishing?UWB ConnectivityConfirmed: the Google Pixel 6 Pro supports UWB connectivity, operating between 6489.6 MHz and 7987.2 MHz. Similar to the Galaxy S21 Ultra UWB design, the Google Pixel 6 Pro has multiple UWB patch antennas. However, in Google Pixel 6 Pro, only one antenna is used to transmit, whereas in the Galaxy S21 Ultra, two UWB antennas are used to send UWB signals.Although the Google Pixel 6 Pro design has similar components to the Samsung Galaxy S20 and Galaxy S21 Ultra, the Teardown team identified a new Qorvo UWB component instead of the same NXP SR100T that was found in the Samsung Galaxy S21 Ultra.WiFi 6EAnother point of similarity between the Google Pixel 6 Pro and the Samsung Galaxy S21 Ultra: the Pixel supports WiFi 6. This, however, is not just a protocol advancement - it requires new hardware designs. So far, we can confirm that the WiFi 6E modules from both phones include the Broadcom WiFi 6E SoC.Samsung Design WinsWith the exception of the Google Tensor Application Processor - which is now in our , the phone's key components are from Samsung, including: Samsung SHANNON A5123 5G Modem, Samsung SHANNON 5511 RF Transceiver, SHANNON 5800 Envelope Tracker IC, Samsung SHANNON 5311A PMIC, And more! The Samsung SHANNON A5123 5G Modem is not new to us. We originally found it in the Galaxy S20 Ultra in early 2020, where it paired with the Samsung Exynos 990 Application Processor as a standalone 5G Modem.As we have confirmed that there is a standalone Samsung 5G Modem in the Pixel 6 Pro, it stands to reason that the Google Tensor is an Application Processor without integrated Modem functionality, but we have not seen the die photos yet - we will confirm when we do.The Samsung SHANNON 5511 RF Transceiver is not new to us either. We originally found it in Samsung Exynos 1080 and 2100 5G SoC platform smartphones, such as Vivo X60 and Samsung Galaxy S21 series in early 2021.Additional Design WinsIn Memory, the Google Pixel 6 Pro we have torn down has a Micron 12 GB LPDDR5 which should have 8 pieces die of Micron’s 1y nm 12 Gb LPDDR5.KIOXIA has won the NAND Flash slot.There is a standalone GNSS Receiver IC from Broadcom. The BCM47765 is the company’s second generation Dual-Frequency (L1+L5) GNSS chip. TechInsights has analyzed the first generationBCM47755.The Pixel 6 Pro supports NFC and Wi-Fi/BT functions too. We have identified two likely modules and will confirm them through further analysis.STMicroelectronics keeps the NFC slot design win with the same die that we have seen in the Google Pixel 4 and Pixel 4 XL. We have confirmed that inside the wireless combo IC module is the Broadcom BCM4389 Wi-Fi 6E and Bluetooth 5 wireless combo SoC, which we first saw in the Samsung Galaxy S21 Ultra 5G phone.Google Pixel 6 Pro US Model GA03149-USWe have now done a quick tear down on a Google Pixel 6 Pro GA03149-US, a United States model of the phone that supports 5G mmWave and Sub-6.Comparison with the Canadian model we have been examining shows that the US model has a Samsung mmWave RF Transceiver Exynos RF 5710. So Samsung is the second silicon supplier of the 5G NR mmWave cellular chipsets, alongside Qualcomm. TechInsights will be creating a series of reverse engineering reports on the Exynos RF 5710 for our Mobile RF Analysis subscribers.We have also found a Murata mmWave Module SS1707051 found in the US phone. We are currently working to identify the die inside.Figure 7. Samsung mmWave RF Transceiver Exynos RF 5710Figure 8. Dual mmWave antenna module from Murata。

Lecture 6MR Angiography (MRA) Techniques and ApplicationsChen Lin (林辰)Indiana University School of Medicine & Clarian Health Partners Outline•The background•The principleand techniques•The challengesand solutions•The applicationsHuman Vascular System•Intra cranial•Carotid•Aortic•Coronary•Pulmonary•Abdominal•Renal•PeripheralVascular Abnormities •Stenosis•Aneurysm•Arterial Venous Malformation (AVM)•Thrombus•Plaque•Internal bleeding•…Properties of the Blood•Flow–Velocity: 100 –150 cm/sec in abdominal aorta; 10 –20 cm/sec in peripheral arteries–Pulsatile: Peak arterial flow @ 150 –200 ms afterventricular contraction•T1–~ 1200ms @ 1.5T, ~ 1500ms @ 3T•T2–~ 250ms for arterial blood, ~ 30ms for venous bloodMR Angiography Techniques•Contrast Enhanced MRA (CE‐MRA)–High contrast to noise ratio–No flow induced de‐phasing and signal lost–Fast acquisition ‐> Dynamic imaging–Acquisition timing is important–Gd related NSF is a concern•Non‐Enhanced MRA (NE‐MRA)–Quantitative–Prone to artifacts–Different techniques specific to regionGd Contrast Enhanced MRA•Became popular during 1995‐1999.•Gd contrast agents decrease T 1and increase CNR of blood and soft tissue.•With fast 3D sequences, allow high resolution and coverage of large VOI.•Short acquisition times allow breath ‐holding for visualization of abdominal vasculature.Basic CE ‐MRA Technique•0.1‐0.2 mM/kg (20‐40ml) of Gd contrast injected at 2‐3 ml/sec •Flush with 20‐30ml of saline•3D spoiled gradient echo based sequence •Min. TE and Min. TR0.8 x 0.9 x 0.6 mm 3CE ‐MRA Considerations•Amount of Gd Contrast•Proper acquisition window and timing–Bolus Timing –View Ordering•Improve resolution with partial k ‐space acquisition–Partial Echo, Partial Fourier, Parallel imaging, Radial sampling•Time resolved MRA with view sharing–Key ‐hole, TRICKS/TWIST•Multi ‐station bolus chasing and continuous moving table acquisitionAmount of Contrast•pulmonary arteries 0.1 mmol/kg•aorta0.1 ‐0.2 mmol/kg •renal arteries 0.1 ‐0.2 mmol/kg •portal vein0.2 mmol/kg •peripheral arteries0.3 mmol/kgGd: 20ml Gd: 40mlCourtesy of M. Prince, Cornell, NYArterial and Venous Phases ArteryVeinTime12 sec 18 sec 24 sec 30 sec0 sec CE ‐MRA Acquisition TimingArteryVeinTimePatient Specific DelayRecessed Elliptical Centric View Order•Fluoro Triggering : Realtime 2D scan of ~1 fps)•Test Bolus: 2D fast scan with small doseTime to k ‐space CenterHi ‐res CE ‐MRA of Carotid Artery CE ‐MRADSAAcceleration by Parallel ImagingWithout SENSEWith SENSETime ‐resolved CE ‐MRA (tMRA)ArteryVeinTimetMRA with iPAT=4P.Finn et al., UCLA, Los Angeles, USA1 volume per secHigh Resolution and Large FOV tMRA P.Finn et al., UCLA, Los Angeles, USAMIPAcceleration by Sharing of k ‐space Data•Divide k ‐space into central and peripheral regions.•Sample central k ‐space points more frequently than peripheral points •No lose of SNR.•Increase frame rate, by temporal base remains same (temporal interpolation).TWISTAcceleration by Under ‐sampling T. Gu American Journal of Neuroradiology 26:743‐749VIPR (Vastly under ‐sampled Isotropic PRojection)VIPR Pulmonary tMRA7.5 s 11 s 14.5 s21.5 s 18 s 25 s35.5 s32 s28.5 s11 averaged time frames (7.5 s to 44 s, 37 s total)9150 projectionsT i me 4D (Spatial & Temporal) Information 3D Gd MRA: 87 sec1st station: reverse centric k ‐space acquisition2nd & 3rd stations: centric k ‐space acquisitionBolus Chase peripheral MRA (Run ‐off)Vogt, F. M. et al. Radiology 2007Continuous Moving Table MRA University Munich (LMU)Whole (Body) MRA with Coil ArraysNon‐Enhanced MRA (NE‐MRA)•Time of Flight (TOF)–3D TOF intracranial arterial–2D TOF Carotid and peripheral•Balanced SSFP (bFFE/TrueFISP/FIESTA)–Coronary, Renal•3D Half Fourier FSE–Abdominal, Peripheral•Phase Contrast (PC)Miyazaki, M. et al. Radiology2008;248:20-43Time of Flight (TOF) MRA The Principle of TOFNo Flow Slow Flow Fast FlowMax. SaturationPartial SaturationNo Saturation ImagingSliceThe effective T1is reduced due to in‐flowElimination of Venous Signal Arterial FlowVariable FAExcitation(TONE)Venous FlowTrackingSaturationBandCan be used to identify vessels feeding a given territoryTOF MRA Optimization•Orienting the slice/slab perpendicular to thedirection of flow.•Variation of flip angle across slice profile.•Background tissue suppress with MT.•Fat saturation.•Cardiac gating to reduce pulsatile flow artifact.•Use zero‐fill of k‐space (ZIP) to spatial interpolation.•Acceleration (more applicable at high field)3DTOF MRA with MT at 3.0TDefault 3DTOF3DTOF with ECR MT3DTOF (12:06)3DTOFEC (7:11)3DTOFEC + SENSE(3:41)Accelerated 3D TOF MRA at 3.0T: MT Region2D versus 3D for TOF MRA2D•Less saturation, moresensitive to slow flow•Better contrastbetween blood andstationary tissue3D•Better resolution in slabdirection•More efficientacquisition, greater SNRMultiple Overlapping Thin Slab Acquisition(MOTSA)1.5 T3.0TDSA??The Advantage of High FieldAneurysm (2.8 mm) of the Middle Cerebral ArteryHigher SNR + Longer T1 + MT still possibleFinn, J. P. et al. Radiology 2006;241:338-354Balanced SSFP MRASSFP SequencesG sliceG phaseG readTRααTR−ααG sliceG phaseG readSSFP(FLASH)Balanced SSFP(TrueFISP)Balanced SSFP•T2/T1 Contrast•Flow Compensated•High SNR•Fast Acquisitiono Susceptible to off‐resonance artifactso High SARFinn, J. P. et al. Radiology 2006;241:338-3543D TrueFISP with NAV and FS Finn, J. P. et al. Radiology 2006;241:338-3543D bSSFP of Coronary ArteryLADbSSFP versus CE MRA for Renal ArteryABC DMaki, J. H. et al. Am. J. Roentgenol. 2007;188:W540-W546Navigator Trigger SSFPCE ‐MRAECG FSE MRA (Native)•3D HASTE acquisition in high resolution •Arterial and venous phase separableDr. Vivian Lee et al., NYU, USA,Jian Xu, Siemens, Alto Stemmer, SiemensDelay 1ECGRF EchoIR pulseDelay 2slice 1slice 1Systolic triggering90o 180o 180o 180o 180o 180oDiastolic triggerin gDelay 1Delay 2slice 2slice 2Dual ‐Phase FSE AcquisitionSystolic triggeringDiastolic triggerin gVelocity ContrastDiastolicSystolic‐=Courtesy of LMU, Munich, GermanyNATIVE versus CE for Peripheral MRANative versus CE MRA for Aortic ArterySource ImageMIPPhase Contrast MRA Motion Dependent Phase DifferenceGφBipolar GradientStationary spinsMoving spinsΔφ= γΑτVτAAZY XM XYttRe-phased Magnitude Phase|M1|magnitude of flow compensated signal |M2 –M1|magnitude of signal difference φ2‐φ1phase angle of signal difference flow bright background visibleflow brightbackground suppressedforward flow bright reverse flow black background mid ‐grayPhase Contrast AcquisitionNeed to acquire two images: 1) w/o flow encoding and 2) flow encodedECGAcq WindowAcq WindowEchoess1 = flow compensated (as reference)s2 = flow encodeds1s2s1s2s1s2s1s2s1s2s1s2s1s2s1s2s1s2s1s2Synchronizes with cardiac cycle (typically with retrospective gating)Synchronized and Interleaved Acquisitions for Pulsatile FlowVENC optimalVENC OptimizationVENC too large Poor ContrastVENC too smallAliasing-180+180+200-200+180-180+170-170+180-180+90-90VENC OptimizationPulmonary Artery70-130Aorta100 –175 Carotid Artery80 –120 External Iliac Artery 81 –120 Carotid Syphon55Common Femoral Artery 115Basilar Artery40Superficial Femoral Artery 90Vertebral Artery 40Popliteal Artery 70Sagittal Sinus Vein 10Peripheral Veins5 –10In ‐Plane Sagittal AortaThru ‐Plane Axial AortaVelocity Encoding Direction3D Phase ‐Contrast MRA of Renal CirculationCoronal, Gd enhanced TR/TE = 7/1.4 ms 40o flip, false renal stenosis (False Positive)Coronal, 3D PC TR/TE = 33/6 ms20o flipPC MRA•Requires multiple acquisitions (one reference and one for each flow encoding directions). Long scan time.•Good background suppression from subtraction.•No saturation problem, sensitive for slow flow provided there is adequate SNR and long T2*.•Can be quantitative: Flow velocity ~ φ2 ‐φ1Flow Measurement with PC ‐MRI•Typically uses 2DFT phase contrast method.•Slice positioned perpendicular to axis of vessel.•ROI drawn to delineate vessel lumen–Average value in ROI is mean velocity –Area of ROI is vessel cross ‐sectional area•Flow = Mean velocity * Area.•For pulsatile flow, multi ‐phase cine required.Aorta Measuring Pulsatile Flow with PC MRICSFFinn, J. P. et al. Radiology 2006;241:338-354Normal aortic valveVelocityFlowFinn, J. P. et al. Radiology 2006;241:338-354Aortic Value Stenosis VelocityFlow Summary•Contrast enhanced MRA provides high SNR, however, acquisition timing is critical if time resolved MRA is not used.•More non contrast enhanced MRA have become available. However, they tend to be application specific.•Quantitative measurement of flow velocity and flow rate is possible with PC MRA.Thank You!。

oracle高级分析函数使用实例2014年11月26日10:26:55∙标签：∙oracle∙1744ORACLE的分析函数，发现大家写SQL的时候有些功能写的比较麻烦或者不知道复杂的功能怎么通过SQL实现，ORACLE自带的分析函数有很多相应的功能：它是Oracle分析函数专门针对类似于"经营总额"、"找出一组中的百分之多少" 或"计算排名前几位"等问题设计的。

分析函数运行效率高，使用方便。

分析函数是基于一组行来计算的。

这不同于聚集函数且广泛应用于OLAP环境中。

Oracle从8.1.6开始提供分析函数，分析函数用于计算基于组的某种聚合值，它和聚合函数的不同之处是对于每个组返回多行，而聚合函数对于每个组只返回一行。

语法：<analytic-function>(<argument>,<argument>,...)over(<query-partition-clause><order-by-clause><windowing-clause>)其中：1 over是关键字，用于标识分析函数。

2 <analytic-function>是指定的分析函数的名字。

Oracle分析函数很多。

3 <argument>为参数，分析函数可以选取0-3个参数。

4 分区子句<query-partition-clause>的格式为：partition by<value_exp>[,value_expr]...关键字partition by子句根据由分区表达式的条件逻辑地将单个结果集分成N组。

这里的"分区partition"和"组group"都是同义词。

5 排序子句order-by-clause指定数据是如何存在分区内的。

波束形成器的fpga实现英文回答。

Beamformer FPGA Implementation.A beamformer is a signal processing technique that combines multiple signals to form a single, enhanced signal. This can be used to improve the signal-to-noise ratio (SNR) of a signal, or to steer the beam in a specific direction.Beamformers can be implemented in hardware using FPGAs (Field Programmable Gate Arrays). FPGAs are programmable logic devices that can be configured to perform a wide variety of tasks. This makes them ideal for implementing beamformers, which can be complex and require high-performance processing.There are many different ways to implement a beamformer on an FPGA. One common approach is to use a tapped delayline (TDL) architecture. In this architecture, each inputsignal is delayed by a different amount, and then the delayed signals are summed together to form the output signal. The delays are typically controlled by a set of coefficients, which are stored in memory.Another approach to implementing a beamformer on an FPGA is to use a systolic array architecture. In this architecture, the input signals are processed in a series of stages, each of which performs a specific operation. The stages are typically connected in a pipeline, so that the output of one stage is the input to the next stage.The choice of which architecture to use depends on the specific requirements of the application. TDL architectures are typically more efficient for small beamformers, while systolic array architectures are more efficient for large beamformers.FPGAs are a powerful and versatile platform for implementing beamformers. They offer high performance, low power consumption, and small size, making them ideal for a wide range of applications.中文回答。

TCL脚本语言学习（1）当输入的命令较长时，可以使用反斜线 \ 将一行命令分割为几行,例如：set target_library \/home/fzz/synopsys/library/slow.db上面的命令等价于set target_library /home/fzz/synopsys/library/slow.db（2）缩略语命令：Synopsys的命令可以缩略到非含糊的形式，但是在脚本文件中应该少使用缩略命令，因为脚本文件在某些Synopsys的工具或者TCL中的命令易于发生变化，这种变化因为缩略而变得含糊。

（3）可以使用Synopsys中的“history”命令列举或者执行出先前使用过所有命令，例如：dc_shell> history info 5该命令将列举出最近执行过的5跳指令dc_shell> history redo 4该命令将执行在当前 dc_shell中执行过的命令中的第4条指令，这里面redo 后面的数据如不是有效的，则将重复执行最后输入的命令。

例如dc_shell> history redo -4, -4 无效，将重复执行最后输入的有效指令也可以采用快捷键的方式，输入“!!”命令，重新执行命令。

例如：dc_shell> !!set target_library /home/fzz/synopsys/library/slow.db/home/fzz/synopsys/library/slow.db能够重复执行某条指令可以使用Dc_shell> !5(4)以命令行方式获得help使用-help 命令获得帮助Dc_shell> echo –help同样可以使用for命令获得help的所有命令，输入方式如下：dc_shell> help for*也可以获得特殊的命令组的所有命令的列表，通过输入命令集合的名字，例如：dc_shell> help procedures使用man命令也可以使用man命令获取Synopsys中获得帮助的相应命令，例如：dc_shell > man query_objects(5)Command Status命令状态时命令返回值，所有的命令都返回一个一个字符串或者 null，默认时命令状态值返回控制窗口，例如：dc_shell >set total_cells 0 ,这里定义了一个新的变量dc_shell >incr total_cells(6)Quoting 引用使用quoting disable一些特殊字符的含义（例如:[],$ and ;）dc_shell> set a 5; set b 1010dc_shell> echo {[expr $b - $a]} evaluates to [expr $b - $a][expr $b - $a] evaluates to 5双引号标示特殊的较弱的quoting，使用举例如下：dc_shell> Set A 10; set B 44dc_shell> ech o “A is $A; B is $B.\nNet is [expr $A - $B].”chapter 2 Tcl基础Variables变量dc_shell> set buf_name 1si_10K/B1I1si_10K/B1Idc_shell> set a 11dc_shell> set b 2.5Tcl中所有的变量都是字符串，Tcl不识别变量是整数或者实数的变量dc_shell> set b 1010dc_shell> incr b11dc_shell> incr b -65Incr的默认增加值是1，如果增加的不是整数值，那么则会报错，例如：dc_shell> set b 2.42.4dc_shell> incr bError …为了查找一个变量是否存在，可以使用tcl的info exists命令，例如说，为了查看变量total_cells是否存在，键入：dc_shell> info exists total_cells如果变量存在，则info exists返回1，否则，返回0。

习题一1.什么是程序存储工作方式？答：计算机的工作方式——存储程序工作方式。

即事先编写程序，再由计算机把这些信息存储起来，然后连续地、快速地执行程序，从而完成各种运算过程。

2.采用数字化方法表示信息有哪些优点？用数字化方法表示信息的优点：（1）抗干扰能力强, 可靠性高。

（2）依靠多位数字的组合，在表示数值时可获得很宽的表示范围以及很高的精度。

（3）数字化的信息可以存储、信息传送也比较容易实现。

（4）可表示的信息类型与范围及其广泛，几乎没有限制。

（5）能用逻辑代数等数字逻辑技术进行信息处理，这就形成了计算机硬件设计的基础。

3.如果有7×9点阵显示出字符A的图像，请用9个七位二进制代码表示A的点阵信息。

4.数字计算机的主要特点是什么？1.（1）能在程序控制下自动连续地工作；（2|）运算速度快；（3）运算精度高；（4）具有很强的信息存储能力；（5）通用性强，应用领域及其广泛。

5.衡量计算机性能的基本指标有哪些？答：衡量计算机性能的基本指标：（1）基本字长——参加一次运算的数的位数；（2）数据通路宽度——数据总线一次能并行传送的位数；（3）运算速度——可用①CPU的时钟频率与主频，②每秒平均执行指令数，③典型四则运算的时间来表示。

（4）主存储器容量——可用字节数或单元数（字数）×位数来表示。

（5）外存容量——常用字节数表示。

（6）配备的外围设备及其性能。

（7）系统软件配置。

7.系统软件一般包括哪些部分？列举你所熟悉的三种系统软件。

系统软件一般包括操作系统，编译程序、解释程序、各种软件平台等。

例如WINDOWS98操作系统，C语言编译程序等，数据库管理系统。

8.对源程序的处理有哪两种基本方式？对源程序的处理通常有两种处理方式：解释方式和编译方式。

习题二1.将二进制数(101010.01)2转换为十进制数及BCD码。

解：(101010.01)2 = (42.25)10 = (01000010.00100101)BCD2.将八近制数(37.2)8转换为十进制数及BCD码.解:(37.2)8 = (31.25)10 =(011001.010101)BCD3.将十六进制熟(AC.E)转换为十进制数及BCD码.解: (AC.E)16 =(174.875)10 = (000101110100.100001110101)BCD4.将十进制数(75.34)10转换为8位二进制数及八进制数、十六进制数。

VSP Lecture5 -Systolic Array (cwliu@.tw)5-15012: VLSI Signal ProcessingLecture 5 Systolic Array ArchitectureVSP Lecture5 -Systolic Array (cwliu@.tw)5-2Techniques for VLSI Systems •Algorithm Strength Reduction –Fast algorithm •Using polyphase filter bank to realize long-length taps linear phase filter •Using FFT instead of DFT •Fast convolution algorithm–Tradeoff between performance and complexity •Fast TrackbackViterbi algorithm (for convolutonal code, Turbo code)•Detect first and followed by BM algorithm for Reed-Solomon Code •Using CORDIC machine instead of complex multiplier•Memory management –Memory bank, Register File –Local buffer (cache, or FIFO…)–Multiple-port memory is replaced by multiple single-port memory bank •Power Management –Resource allocation –Using finite-state machine (FSM) to well timing and flow control, through enable/disable signals, in order to time-share the same PE –Clock gating, Data gating–Power-aware, Energy-aware design•Low-power circuit design technologyVSP Lecture5 -Systolic Array (cwliu@.tw)5-3Convolutinal CodeEncoderTrellis diagram (or dependent graph)VSP Lecture5 -Systolic Array (cwliu@.tw)5-4Mapping Algorithmsonto Array Structures •Localized operations, intensive computations, and matrix operations are features of many DSP algorithms.•Derive a maximal concurrency by using both pipelining and parallel processing –How is the inherent concurrency?–How is the array processor design dependent on the algorithm?–How is the algorithm best implemented in the array processor?•Dependence graph (DG)–By tracing the associated space-time index space and using proper arcs to display the dependencies –It exhibits the full dependencies incurred in the execution of a specific algorithm•Interconnection network •SystolicArray–Modularity, regularity, local interconnectionVSP Lecture5 -Systolic Array (cwliu@.tw)5-5History and Motivation•Introduced by HT Kung and Leiserson, 1978•Designs for matrix computations•Illustrated by snapshots of operation •Motivations –Improve performance of special-purpose systems (e.g. maximize processing permemory access)–Reduce design and implementation costsVSP Lecture5 -Systolic Array (cwliu@.tw)5-6What is a Systolic Architecture • A network of processing elements (PEs) that computes and rhythmically passes data through it •Multiple PEs to maximize processing per memory access Ordinary system100 ns 100 ns10 MOPS 40 MOPSExampleSystolic FIR filter Least-Square Algorithm VSP Lecture5 -Systolic Array (cwliu@.tw)5-7Array Structure Examples1D array2D array3D arrayVSP Lecture5 -Systolic Array (cwliu@.tw)5-8VSP Lecture5 -Systolic Array (cwliu@.tw)5-9Why Systolic Array •A new class of pipelined array architectures •Benefits –Simple and regular design (cost-effective)–Concurrency and communication –Modular and expandable•Drawbacks –Not all algorithms can be implemented using a systolic architecture–Cost in hardware and area –Cost in latencyVSP Lecture5 -Systolic Array (cwliu@.tw)5-10Systolic Fundamentals •Systolic architecture are designed by using linear mapping techniques on regular dependence graph (DG)•Regular Dependence Graph: the presence of an edge in a certain direction at any node in the DG represents presence of an edge in the same direction at all nodes in the DG •DG corresponds to space representation Æno time instance is assigned to any computation •Systolic architectures have a space -time representation where each node is mapped to a certain processing element (PE) and is scheduled at a particular time instance.•Systolic design methodology maps an N-dimensional DG to a lower dimensional systolic architectureVSP Lecture5 -Systolic Array (cwliu@.tw)5-11Regular Dependence Graph •Space representation for FIR filter(0,1)T(1,0)T(1,-1)Ty(n)=w 0x(n)+w 1x(n-1)+w 2x(n-2)VSP Lecture5 -Systolic Array (cwliu@.tw)5-12Definitions•Projection vector (also called iteration vector)–Two nodes that are displaced by d or multiples of d are executed by the same processor •Schedulingvector–Any node with index I would be executed at time s T I •Processor space vector –Any node with index I T =(i,j) would be executed byprocessor ⎟⎟⎠⎞⎜⎜⎝⎛=21d d d ),(21s s T =s ),(21p p T =p ⎥⎦⎤⎢⎣⎡=j i p p T ),(21I pVSP Lecture5 -Systolic Array (cwliu@.tw)5-13Systolic Design Methodology•Many systolic architectures can be designed for a given algorithm by selecting different projection, processor space, and scheduling vectors.•Feasibility constraints –If point I A and point I B differ by d , d = I A -I B , i.e. theyare lying on the same direction along projection vector, they must be executed by the same processor. That is, p TI A =p T I B or p T d =0–If point I A and point I Bare mapped to the sameprocessor, i.e. I A -I B =d , they cannot be executed at thesame time. That is, s T I A s TI B or s T d 0–If an edgee exists in DG, then an edge p T e is introducedin the systolic array with s T e delay VSP Lecture5 -Systolic Array (cwliu@.tw)5-14Array Architecture Design •Step 1: mapping algorithm to DG –Based on the space-time indices in the recursivealgorithm –Shift-Invariance (Homogeneity) of DG–Localization of DG: broadcast vs. transmitted data•Step 2: mapping DG to SFG –Processor assignment: a projection method may beapplied (projection vector d )–Scheduling: a permissible linear schedule may be applied (schedule vector s )•Preserve the inter-dependence •Nodes on an equitemporalhyperplane should not beprojected to the same PE •Step 3: mapping an SFG onto an array processorVSP Lecture5 -Systolic Array (cwliu@.tw)5-15Example: FIR Filternkh(0)h(1)h(2)h(3)h(4)x(0)x(1)x(2)x(3)x(4)x(5)x(6)y(0)y(1)y(2)y(3)y(4)y(5)y(6)d s D D D D D DD D D D 2D 2D 2D 2D 2D x(0)x(1)x(2):y(0)2(1)y(2):Equitemporal hyperplanes VSP Lecture5 -Systolic Array (cwliu@.tw)5-16Space-Time Representation •The space representation or DG can be transformed to a space-time representation by interpreting one of the spatial dimensions as temporal dimension•2D DG:⎥⎥⎥⎦⎤⎢⎢⎢⎣⎡⎥⎥⎥⎦⎤⎢⎢⎢⎣⎡=⎟⎟⎟⎠⎞⎜⎜⎜⎝⎛=⎥⎥⎥⎦⎤⎢⎢⎢⎣⎡t j i t j i T t j i T T 00100'''s p It I j t i T T s p ===' ,' ,'Processor axis Scheduling time instance (2D-DG is mapped to a 1D systolic array)VSP Lecture5 -Systolic Array (cwliu@.tw)5-17Exampled sDDDD D D Dinput result VSP Lecture5 -Systolic Array (cwliu@.tw)5-18VSP Lecture5 -Systolic Array (cwliu@.tw)5-19Selection of Scheduling Vector •Linear schedulingSX =s T I X =(s 1s 2) (i x ,j x )TS Y =s T I Y =(s 1s 2) (i Y ,j Y )T•Affine scheduling (A transformation followed by a translation)S X =s T I X + x =(s 1s 2) (i x ,j x )T +xS Y =s T I Y + Y =(s 1s 2) (i Y ,j Y )T + Y•For a dependence relation X ÆY , where I X T =(i x ,j x )T and I y T =(i y ,j y )T . Then we have S Y ≥S X +T x , where S X and S Y are scheduling times for node X and Y, respectively, and T X is the computation time for node X.•Each edge of a DG leads to an inequality for selection of scheduling vectorsVSP Lecture5 -Systolic Array (cwliu@.tw)5-20Regular Iteration Algorithm (RIA)•Standard input RIA form–If the index of the inputs are the same for all equations•Standard output RIA form –If all the output indices are the same •For FIR filtering, we have O/I-relationship w(i+1,j) = w(i,j )x(i,j+1) = x(i,j )y(i+1,j-1) = y(i,j ) + w(i+1,j-1)x(i+1,j-1)•We can express it in standard output RIA form as w(i,j ) = w(i-1,j)x(i,j ) = x(i,j-1)y(i,j ) = y(i-1,j+1) + w(i,j)x(i,j)•It is obvious that the FIR filtering problem cannot be expressed instandard input RIA formVSP Lecture5 -Systolic Array (cwliu@.tw)5-21Selection of s T•Capture all the fundamentals edge in the reduced dependence graph (RDG), which is constructed by the regular iteration algorithm (RIA)•Construct the scheduling inequalities according S Y ≥S x +T x , if there is anedge X ÆY yVSP Lecture5 -Systolic Array (cwliu@.tw)5-22Exampleyys T (I y -I x ) + γy -γx ≥T xeX ÆYVSP Lecture5 -Systolic Array (cwliu@.tw)5-23VSP Lecture5 -Systolic Array (cwliu@.tw)5-24Matrix-Matrix Multiplication ⎟⎟⎠⎞⎜⎜⎝⎛⎟⎟⎠⎞⎜⎜⎝⎛=⎟⎟⎠⎞⎜⎜⎝⎛222112112221121122211211b b b b a a a a c c cc a(i,j+1,k) = a(i,j,k)b(i+1,j,k) = b(i,j,k)c(i,j,k+1) = c(i,j,k)+ a(i,j,k+1) b(i,j,k+1)Standard output RIA formExampleVSP Lecture5 -Systolic Array (cwliu@.tw)5-25 ExampleVSP Lecture5 -Systolic Array (cwliu@.tw)5-26。