HCF4030B
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MIN.
0.003
0.013 0.007
45° (typ.)
8.75
0.336
6.2
0.228
4.0
0.149
5.3
0.181
1.27
0.019
0.68
8° (max.)
inch TYP.
0.019
0.050 0.300
MAX. 0.068 0.007 0.064 0.018 0.010
0.344 0.244
OUTPUT
J, K, L, M L H H L
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VDD Supply Voltage
-0.5 to +22
V
VI
DC Input Voltage
-0.5 to VDD + 0.5
V
II
DC Input Current
5/9
HCF4030B WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
6/9
DIM.
a1 B b b1 D E e e3 F I L Z
HCF4030B
Plastic DIP-14 MECHANICAL DATA
MIN. 0.51 1.39
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
All voltage values are referred to VSS pin voltage.
HCF4030B
QUAD EXCLUSIVE OR GATE
s MEDIUM-SPEED OPERATION : tPD = 65ns (Typ.) at VDD = 10V
s LOW OUTPUT IMPEDANCE : 500Ω (Typ.) AT VDD - VSS = 10V
s QUIESCENT CURRENT SPECIFIED UP TO 20V
Data Inputs
3, 4, 10, 11 J, K, L, M Data Outputs
7
VSS
Negative Supply Voltage
14
VDD
Positive Supply Voltage
TRUTH TABLE
INPUTS
B, C, E, G
L L H H
A, D, F, H
L H L H
Symbol
Parameter
VDD (V)
Test Condition
tPLH tPHL Propagation Delay
5
Time
10
15
tTLH tTHL Output Transition
5
Time
10
15
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
4.95
9.95
9.95
V
0/15
<1 15 14.95
14.95
14.95
VOL Low Level Output 5/0
Voltage
10/0
<1 5
0.05
<1 10
0.05
0.05
0.05
0.05
0.05 V
15/0
பைடு நூலகம்<1 15
0.05
0.05
0.05
VIH High Level Input Voltage
PIN CONNECTION
September 2001
1/9
HCF4030B INPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAM
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1, 2, 5, 6, 8, 9, 12, 13
B, A, C, D, E, F, G, H
HHHHH L HH ..... ....... .
HL LL LLLH
-5 -127
L H H H H H H H 127
H L L L L L L L -128
The two’s complement adder-subtractor can add or subtract any two of the numbers in table 1.
0.157 0.208 0.050 0.026
PO13G 8/9
HCF4030B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics.
0/5 0.4 <1 5 0.44 1
0.36
0.36
Current
0/10 0.5 <1 10 1.1 2.6
0.9
0.9
mA
0/15 1.5 <1 15 3.0 6.8
2.4
2.4
II Input Leakage Current
0/18 Any Input 18
±10-5 ±0.1
±1
±1 µA
0.5/4.5 <1 5 3.5 1/9 <1 10 7
3.5
3.5
7
7
V
1.5/13.5 <1 15 11
11
11
VIL Low Level Input Voltage
4.5/0.5 <1 5 9/1 <1 10
1.5
1.5
1.5
3
3
3
V
13.5/1.5 <1 15
4
4
4
IOH Output Drive
Value (*)
Unit
Min. Typ. Max.
140 280 65 130 ns 50 100 100 200 50 100 ns 40 80
3/9
HCF4030B TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω)
4/9
8 BIT COMPARATOR
HCF4030B
8 BIT TWO’S COMPLEMENT ADDER SUBSTRACTOR
TABLE 1 : Two’s Complement Numbers and their Equivalent Decimal Values.
X8 X7 X6 X5 X4 X3 X2 X1 Decimal
X8 X7 X6 X5 X4 X3 X2 X1 Decimal
LLLLLLLL
0
LLLL LL LH
1
HHHHHHHH
-1
HHHHHHH L
-2
LLLL LLHL
2
L L L L L L HH
3
HHHHHH L H
-3
HHHHHHL L
-4
.......... ... L H H H H H H L 126
DIP
SOP
ORDER CODES
PACKAGE
TUBE
DIP SOP
HCF4030BEY HCF4030BM1
T&R HCF4030M013TR
monolithic silicon chip. Each exclusive-OR gate consists of four n-channel and four p-channel enhancement type transistors. All inputs and outputs are protected against electrostatics effects.
