IGZO 高迁移率氧化物薄膜晶体管

High mobility thin film transistors with indium oxide/gallium oxide bi-layer structures S.-L. Wang, J.-W. Yu, P.-C. Yeh, H.-W. Kuo, L.-H. Peng, A. A. Fedyanin, E. D. Mishina, and A. S. SigovCitation: Applied Physics Letters 100, 063506 (2012); doi: 10.1063/1.3683518View online: /10.1063/1.3683518View Table of Contents: /content/aip/journal/apl/100/6?ver=pdfcovPublished by the AIP PublishingArticles you may be interested inHigh mobility amorphous InGaZnO4 thin film transistors formed by CO2 laser spike annealingAppl. Phys. Lett. 106, 123506 (2015); 10.1063/1.4914373High stability mechanisms of quinary indium gallium zinc aluminum oxide multicomponent oxide films and thin film transistorsJ. Appl. Phys. 117, 045309 (2015); 10.1063/1.4906619Coplanar amorphous-indium-gallium-zinc-oxide thin film transistor with He plasma treated heavily doped layer Appl. Phys. Lett. 104, 022115 (2014); 10.1063/1.4862320Thin-film transistors with amorphous indium gallium oxide channel layersJ. Vac. Sci. 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Phys. 97, 064505 (2005); 10.1063/1.1862767High mobility thin film transistors with indium oxide/gallium oxide bi-layer structuresS.-L.Wang,1J.-W.Yu,1P.-C.Y eh,1H.-W.Kuo,1L.-H.Peng,1,a)A.A.Fedyanin,2E.D.Mishina,3and A.S.Sigov31Department of Electrical Engineering,Institute of Photonics and Optoelectronics,andCenter for Emerging Materials and Advanced Devices,National Taiwan University,Taipei106,Taiwan2Faculty of Physics,Lomonosov Moscow State University,Moscow119991,Russia3Moscow State Technical University of Radioengineering,Electronics,and Automation,Moscow119454,Russia(Received23November2011;accepted18January2012;published online9February2012)We investigate the transport properties of thin-film transistors using indium oxide(In2O3)/galliumoxide(Ga2O3)bi-layer stacks as the channel material.At low gate bias,we observe the transistorfield-effect mobility increases with thefilm resistivity to l FE¼51.3cm2/Vs and ON/OFF currentratio to108due to combinatorial layer thickness modulation.With the Ga2O3layer thickness ratioincrease to R¼14.35%,these observations are accompanied with one-order-of-magnitudereduction in the transistor subthreshold swing to0.38V/decade and suggest a trap-limitedconduction mechanism upon which the reduced scattering centers due to annihilation of subgapstates improve the device electric characteristics without post-growth annealing.V C2012AmericanInstitute of Physics.[doi:10.1063/1.3683518]Thinfilm transistors(TFTs)are an essential element for flat-panel displays and next-generation microelectronic devi-ces.1Hydrogenated amorphous silicon(a-Si:H)has been one of the widely used channel materials for TFTs.However,it suffers from issues such as low mobility(l<1cm2/Vs)and instability under illumination and electric bias stress.2 Alternative TFT channel design,comprising a superlattice structure made of hydrogenated silicon nitride(a-Si3N4:H)/ a-Si:H,has been proposed to increase the mobility by a fac-tor of5due to the quantization effect.2Recent study on amorphous indium-gallium-zinc-oxide(a-IGZO),3and their derivatives of a-IGO and a-IZO have drawn interest due to superior carrier mobility(l>10cm2/Vs)4and low tempera-ture processing.5Conventional wisdom suggests that the high carrier density in oxide semiconductors can be related to oxygen vacancies(V O)and other native defects.Model analysis indicates that carrier transport is controlled by mul-tiple trap-and-release events when the device is biased at low gate voltage with the Fermi level residing within the local-ized tail states.6The percolation conduction mechanism pre-vails when carriers are released to the non-localized states andfind the paths of least resistance.Wave function overlap between the s-orbitals of the adjacent In cations can make the carrier transportation insensitive to structure disorder, thus leading to highfield-effect mobility(l FE)in the oxide-based TFTs.7It was also noted that the formation energy of V O increases with Ga atoms,which can suppress the O-deficiency related defects and improve device stability.8,9 These observations outline a possibility to tailor the electric properties of oxide TFTs by adding Ga ions to enhance the material amorphization using the techniques such as sputter-ing10or solution-base process.11Here,we demonstrate another aspect of engineering the transport properties of oxide TFTs by mitigating the trap density of subgap states(D sg)in the In2O3/Ga2O3bi-layer system.We note that as the Ga2O3layer thickness ratio R, defined as tGa2O3/(tGa2O3þtIn2O3),increases from11%to 25%,the equivalentfilm resistivity(q eff)can span a wide range from104to107X cm with a rate of5.35%60.05%/ decade.From bottom-gate TFTs made of such In2O3/Ga2O3 bi-layer stack,we achieve a peakfield-effect mobility l FE¼51.3cm2/Vs,ON/OFF current ratio of108,and thresh-old voltage V T¼0.57V at a Ga2O3layer thickness ratio R¼14.35%(q eff¼9.2Â104X cm).These data are taken without post-growth annealing and concurred with an order of magnitude reduction in the TFT subthreshold swing to S¼0.38V/decade.Such behavior can be ascribed to a mech-anism of suppression of subgap trap density D sg in thin In2O3layers when interfaced to Ga2O3.8,9The preparation of In2O3/Ga2O3bi-layer stack materials used in this study was facilitated by the sputtering method at a temperature below60 C.The materials were typically grown at a sputtering power of70W and working pressure of4mTorr,withflow rate of argon(Ar)/oxygen(O2)fixed at 30/30sccm(standard cubic centimeter per minute).Under these conditions,a growth rate of0.14A˚/s and0.09A˚/s, respectively,can be found for depositing the In2O3and Ga2O3films on quartz substrates.A transmission line method (TLM),12with electrode patterns composed of200nm-thick molybdenum(Mo)stripes of4to16l m spacing,was applied to characterize q eff.Shown in the inset of Fig.1(a)are the resistance data taken on sample1designed to have7pairs of In2O3/Ga2O3 stack with3.5/0.57nm layer thickness in each pair.From a linear slopefitting of the resistance data to the Mo stripe spacing,one can extract q eff by considering a multiplication factor offilm thickness.This process allows us to examine the q eff distribution associated with various In2O3/Ga2O3a)Author to whom correspondence should be addressed.Electronic mail:peng@.tw.0003-6951/2012/100(6)/063506/4/$30.00V C2012American Institute of Physics100,063506-1APPLIED PHYSICS LETTERS100,063506(2012)layer thickness combination.Referred to Fig.1(a),logarith-mic increase in q eff at a rate of 5.35%60.05%/decade is observed on samples fixed with 3.5nm-thick In 2O 3layers but varied in the Ga 2O 3layer thickness.Similar increasing rate can also be found in Fig.1(b)according to the In 2O 3/Ga 2O 3layer thickness variation listed in Table I .With oxy-gen partial pressure fixed in our experiments,these analyses illustrate wide range of resistivity tunability (104to 107X cm)in the In 2O 3/Ga 2O 3multi-layer system due to layer thickness modulation.A plausible mechanism to the aforementioned phenom-ena is due to the mitigation of trap density of subgap states in the In 2O 3/Ga 2O 3system.8,9The latter was examined by applying a high-low frequency capacitance analysis 13to a metal insulator semiconductor capacitor (MIS-cap)device due to less parasitic circuit components than its TFT counter-part.14Two capacitor devices were prepared:MIS-cap A with a 30nm-thick In 2O 3single layer and MIS-capB with an additional 2nm-thick Ga 2O 3layer deposited to In 2O 3(Fig.2(a)).These MIS-cap devices were fabricated on Mo-covered quartz substrates using 40nm-and 200nm-thick Si 3N 4and Mo layers as the insulator and top/bottom electro-des.Here the low-frequency (lf,50Hz)and high-frequency (hf,100KHz)capacitance data were measured as a function of the bias voltage and normalized to that (C i ¼17.9pf)of Si 3N 4gate capacitance.A first glance of data shown in Fig.2(b)depicts a positive shift of the C-V curves of MIS-cap de-vice B to those of MIS-cap device A.It reveals a combined effect due to change in the flat-band voltage and work func-tion difference in the single-layer In 2O 3and bi-layer In 2O 3/Ga 2O 3structure.13Stretch-out of the high-frequency C-V component with respect to its low-frequency counterpart sig-nifies a subtlety that the interfacial traps/charges do not fol-low the high-frequency modulation signal such that the capacitance value slowly varies with the gate bias (V G ).One can further extract the interfacial trap density D it with Eq.(1),13where C i is the insulator (Si 3N 4)capacitance and C lf /C hf the low/high frequency,respectively.D it ¼ð1=q Þf½ð1=C lf ÞÀð1=C i Þ À1À½ð1=C hf ÞÀð1=C i Þ À1g :(1)Referred to the inset of Fig.2(b),our analysis indicates that an order of magnitude reduction in the peak value of D it ,varying from $2Â1013to $2Â1012eV À1cm À2at V G >0,can be achieved when a 2nm-thick Ga 2O 3layer is added to an In 2O 3MIS-cap device.These observations highlight a promising use of In 2O 3/Ga 2O 3bi-layer channel for TFT operation.As a proof,another set of TFTs was fabricated according to the layer thickness variation listed in Table I .A device cross-sectional view is shown in the inset of Fig.3(a).First,the quartz substrate was etched to a depth of $70nm followed by Mo-layer deposition which serves as the bottom-gate electrode.A 9nm-thick hafnium oxide (HfO 2)layer was then deposited on the Mo-covered quartz substrate using an atomic layer deposition method.The drain/source contacts were made of 200nm-thick Mo layers.The device surface was passivated with 100nm-thick SiO 2and a layout of 4l m gate length (L g )and 80l m gate width (L W )was used for electric characterization.Illustrated in Fig.3(a)are the representative output char-acteristics of TFT sample C having a Ga 2O 3layer thickness ratio R ¼14.35%,corresponding to nominal single layer thickness of In 2O 3¼3.71nm,Ga 2O 3¼0.63nm and q eff ¼9.2Â104X cm.We denote linear increase in the drain-to-source current (I DS )with respect to V DS ,followed by pinch-off and saturation of I DS with further increase of V DS .From the log-plot of transfer curve in Fig.3(b),one can denote an ON/OFF current ratio of 1Â108and a subthres-hold swing of S ¼0.38V/decade.One can further take advantage of the linear I DS -V GS characteristics to evaluate the transistor threshold voltage.15This was taken by linear interpolation of the I DS curve to intersect the V GS axis at I DS ¼0,which procedure shown in the inset of Fig.3(b)ren-ders V T ¼0.57V.One can further extract the transistor transconductance (g m )according to g m ¼@I DS /@V G .It can facilitate the derivation of field-effect mobility l FE for TFTl FE ¼ðL g Âg m Þ=ðL W ÂC OX ÂV DS Þ(2)This scenario leads to an increase of g m with V GS where maximum value of g m,max ¼277.2l S can be observedatFIG.1.(Color online)(a)The effective channel resistivity (q eff )for In 2O 3/Ga 2O 3devices fixed with 3.5nm-thick In 2O 3but varied in the Ga 2O 3layer thickness,inset:TLM data on device with 3.5/0.57nm In 2O 3/Ga 2O 3,and (b)dependence of q eff on the Ga 2O 3thickness ratio according to the In 2O 3/Ga 2O 3layer structures listed in Table I .TABLE I.Summary of the equivalent film resistivity and current ON/OFF ratio for TFT devices studied in Figs.1(b)and 4with various In 2O 3/Ga 2O 3thick-ness combination.TFT tIn 2O 3(nm)/tGa 2O 3(nm)Resistivity (X cm)I ON /I OFF ratio TFT tIn 2O 3(nm)/tGa 2O 3(nm)Resistivity (X cm)I ON /I OFF ratio A 4.06/0.54 2.46Â10410F 3.64/0.819.58Â105 1.3Â104B 3.92/0.63 4.88Â104 1.0Â105G 3.50/0.90 1.10Â106 1.0Â104C 3.71/0.639.20Â104 1.0Â108H 3.36/0.99 3.68Â106 1.0Â104D 3.50/0.63 1.43Â105 4.8Â107I3.22/1.089.20Â1061.1Â104E3.80/0.703.10Â1056.0Â105V GS ¼1.5V and V DS ¼0.1V.Continued with parameter extraction using dielectric constant e r ¼27.9for HfO 2and C ox ¼2.7l F/cm 2in Eq.(2),l FE of 51.3cm 2/Vs can be derived at L g /L W ¼4l m/80l m.Further compiled in Fig.4are the extracted data of l FE for devices designed to have various Ga 2O 3layer thickness ratio R and hence difference in the film resistivity (q eff ).The data were taken without post-growth annealing and measured at a low bias condition of V GS ¼1.5V and V DS ¼0.1V.Here,we denote an initial increase of l FE with q eff in the low-resistivity (104–105X cm)regime,reaching a peak value of 51.3cm 2/Vs at q eff ¼9.2Â104X cm,followed by rapid drop of l FE down to 5-10cm 2/Vs in the high-resistivity(106–107X cm)regime.Similar behavior in the l -q relation has been reported in the solution-processed In 2O 3TFTs annealed in air or in an O 2/O 3ambient,16or in the tin doped In 2O 3films deposited with various oxygen partial pressure.17Indeed the peak value of l FE ¼51.3cm 2/Vs observed in this work is comparable to that of In 2O 3TFT annealed at 500 C,16or in the doped In 2O 3film,17operated at a much large gate bias condition (V GS >15V).In comparison,our study on 50nm-thick IGZO TFT with 2.8Â104X cm film resistivity and thick 35nm-HfO 2/15nm-SiO 2bottom-gate dielectric exhibits low value mobility $8.9cm 2/Vs and high voltage operation characteristics of V DS ¼6and V GS ¼8V.18We further note that in the low resistivity regime (<105X cm),increase of l FE is accompanied with an order of mag-nitude reduction in the transistor subthreshold swing (S)from 3.4to 0.38V/decade and improved ON/OFF current ra-tio from 10to 1Â108(data listed in Table I and inset of Fig.4).Indeed,by correlating the trap density of subgap states (D SG )to the measured S value according to 15S ¼ln 10Áðk B T =e ÞÁð1þeD SG =C OX Þ;(3)one can discern D SG reduction from 9.6Â1014to 9.2Â1013/cm 2eV.Under the low gate bias condition,these observa-tions signify a trap-limited transport mechanism 6upon which the reduced scattering centers due to annihilation of subgap states in the HfO 2/In 2O 3/Ga 2O 3bi-layer channel increases the device mobility and improve the ON/OFF current ratio.17Compared with our recent work on thick-dielectric HfO 2/SiO 2/IZGO TFT,18it reveals the advantages of using thin high-k dielectric to reduce the operation voltage and thin Ga 2O 3layers to suppress D sg and enhance l FE.FIG.2.(Color online)(a)Schematic layout of the MIS-capacitor sample B with 2nm/30nm Ga 2O 3/In 2O 3.(b)High and low C-V data on MIS-capacitor samples A/B and normalized to the Si 3N 4gate capacitance (C i ¼17.9pf).Inset:extracted interfacial trap charge density (D it )as a function of gatebias.FIG.3.(Color online)(a)Output and (b)transfer characteristics for In 2O 3/Ga 2O 3TFT sample having an equivalent film resistivity q eff ¼9.2Â104X cm and Ga 2O 3layer thickness ratio R ¼14.3%.Inset:(a)schematic layout of the TFT structure,(b)the extraction of thresholdvoltage.FIG.4.(Color online)Dependence of field-effect mobility (l FE )in In 2O 3/Ga 2O 3TFTs having various Ga 2O 3layer thickness ratio R.Inset:the sub-threshold swing S and the extracted trap density of the subgap states D sg for devices at low gate bias (V GS ¼1.5V)and in the low resistivity regime (<105X cm).In summary,we demonstrated a device concept using the layer thickness modulation in an In2O3/Ga2O3bi-layer stack channel to achieve enhancement mode operation of TFT(V T¼0.57V)with highfield-effect mobility (l FE¼51.3cm2/Vs),low subthreshold swing(S¼0.38V/dec) and ON/OFF current ratio of108.At low gate bias and low resistivity regime,these observations are ascribed to a trap-limited transport mechanism upon which the reduced trap density of the subgap states dominates in the device electric properties.This research was supported by the National Science Council Grant98-2221-E-002-021-MY3,98-2923-E-002-001-MY3,100-2120-M-002-017-CC1,and NTU Excellent Research Project(10R80908).1C.Y.Kagan and P.W.E.Andry,Thin Film Transistors(Dekker,New York,2003).2M.Tsukude,S.Akamatsu,S.Miyazaki,and M.Hirose,Jpn.J.Appl.Phys. 26,L111(1987).3K.Nomura,H.Ohta,A.Takagi,T.Kamiya,M.Hirano,and H.Hosono, Nature432,488(2004).4M.Kimura,T.Kamiya,T.Nakanishi,K.Nomura,and H.Hosono,Appl. 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