KC75118资料
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KC75118C 1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
1INTRODUCTION
The KC75118C is an interline transfer CCD area image
sensor developed for NTSC 1/5 inch optical format PC
cameras, object detector and image pattern recognizer. High
sensitivity is achieved through the adoption of Ye, Cy, Mg and
G complementary color mosaic filter, on-chip micro lenses.
This chip features a field integration read out system and an
electronic shutter with variable charge storage time.
FEATURES
•Optical Size 1/5 inch Format
•Ye, Cy, Mg, G On-chip Complementary
Color Mosaic Filter
•Variable Speed Electronic Shutter
(1/60, 1/100 ~ 1/10, 000sec)
•Horizontal Register 3.3V ~ 5V Drive
•14pin Ceramic DIP Package
•No Adjust Substrate Bias
•Field Integration Read Out System
•No DC Bias on Reset Gate
STRUCTURE
•Number of Total Pixels:381(H) × 506(V)
•Number of Effective Pixels:362(H) × 492(V)
•Chip Size:3.75mm(H) × 3.30mm(V)
•Unit Pixel Size:8.10µm(H) × 4.45µm(V)
•Optical Blacks & Dummies:Refer to Figure Below
Vertical 1 Line (Even Field Only)14Pin Cer DIP
ORDERING INFORMATIONDevicePackageOperating
KC75118C14Pin Cer DIP-10 °C ~ +60 °C14236217
2
492
12V-CCD
OUTPUTDummyPixels
OpticalBlackPixels
EffectivePixelsEffective
Imaging
Area
H-CCD元器件交易网www.cecb2b.com1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERAKC75118C
2BLOCK DIAGRAM
PIN DESCRIPTIONFigure 1. Block Diagram
Table 1. Pin DescriptionPinSymbolDescriptionPinSymbolDescription
1ΦV4Vertical register transfer clock 48VDDOutput stage drain bias
2ΦV3Vertical register transfer clock 39GNDGround
3ΦV2Vertical register transfer clock 210ΦSUBSubstrate clock
4ΦV1Vertical register transfer clock 111VLProtection circuit bias
5NCNo connection12ΦRGReset gate clock
6GNDGround13ΦH1Horizontal CCD transfer clock 1
7VOUTSignal output14 ΦH2Horizontal CCD transfer clock 2
7VOUT654321
891011121314GNDNCΦV1ΦV2ΦV3ΦV4
VDDVLGNDΦH1ΦH2ΦRGΦSUBVertical Shift Register CCDVertical Shift Register CCDVertical Shift Register CCDVertical Shift Register CCD
Horizontal Shift Register CCD CyYe
Mg
Mg
MgMgMg
Ye
Ye
YeYeYeYe
YeG
G
GG
Cy
CyCyCyCy
GMgG
CyCy(Top View)元器件交易网www.cecb2b.comKC75118C 1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
3ABSOLUTE MAXIMUM RATINGS (NOTE)
NOTE:The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage
or temperature.Table 2. Absolute Maximum RatingsCharacteristicsSymbolsMin.Max.Unit
Substrate voltageSUB - GND-0.340V
Vertical clock input voltageΦV1, ΦV3, - GND-0.330V
ΦV2, ΦV4 - GND -0.317V
ΦV1, ΦV3, - VL-0.330V
ΦV2, ΦV4 - VL -0.317V
ΦV1, ΦV2, ΦV3, ΦV4 - SUB-4010V
Horizontal clock input voltageΦV1, ΦV2, - GND-0.316V
ΦH1, ΦH2 - VL-0.316V
Voltage difference between vertical and
horizontal clock input pinsΦV1, - ΦV3-3030V
ΦV2, - ΦV4-1616V
ΦH1, ΦH2-1616V
ΦH1, ΦH2 - ΦV4-1616V
Output clock input voltageΦRG - GND-0.316V
Protection circuit bias voltageVL - SUB-400.3V
Operating temperatureTOP-1060°C
Storage temperatureTSTG-3080°C元器件交易网www.cecb2b.com1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERAKC75118C
4DC CHARACTERISTICS
CLOCK VOLTAGE CONDITIONSTable 3. DC CharacteristicsItemSymbolMin.Typ.Max.UnitRemar
Output stage drain biasVDD14.5515.015.45V
Reset gate voltage adjustment rangeVRGL0V
Protection circuit bias voltageVLThe lowest vertical clock level
Output stage drain currentIDD5mA
Table 4. Clock Voltage Conditions
ItemSymbolMin.Typ.Max.UnitRemark
Read-out clock voltageVVT14.5515.015.45VHigh level
Vertical transfer clock voltageVVM1 ~ VVM4-0.050.00.05VVVH = (VVH1+VVH2)/2
VVL1 ~ VVL4-8.5-8.0-7.5VVVH = (VVH1+VVH2)/2
Horizontal transfer clock voltageVΦH3.05.05.25VHigh
VHL -0.050.00.05VLow
Charge reset clock voltageVΦRG4.755.05.25VHigh
VRGLH - VRGLL0.8VLow
Substrate clock voltageVΦSUB21.522.523.5VShutter元器件交易网www.cecb2b.comKC75118C 1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
5DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
Vertical Transfer Clock Waveform
0V100%
90%
10%
0%VVH1,VVH3
trtwhtf
VVH1VVH
VVHH
VVLLVVLVVL1VVLHVVHLVVHLVVHH¥ÕV1
VVH
VVHLVVHHVVHH
VVHLVVH4
VVLVVLH
VVLLVVL4¥ÕV4VVHHVVHHVVH
VVHLVVHLVVH2
VVLVVLLVVLHVVL2¥ÕV2VVL3VVHH
VVLVVHLVVHLVVH3VVHHVVH
VVLHVVLL¥ÕV3
VVH=(VVH1+VVH2)/2VVL=(VVL3+VVL4)/2V¥ÕV=VVHn-VVLn(n=1~4)VVHH=VVH+0.3VVVHL=VVH-0.3VVVLH=VVL+0.3VVVLL=VVL-0.3V元器件交易网www.cecb2b.com