初学STM32-2

STM32 LL库使用指南---By Fengzi熟悉STM32的都知道ST官方提供了非常方便好用的库函数供用户使用，多数人都使用过STM32标准外设库，STM32Cube库(即HAL库)，这个LL库是什么鬼，却从来没听说过。

好吧，我承认这个名字是我自己XJB取的。

目录一、初识LL 库 (1)二、怎么使用LL库 (3)三、新建STM32LL库工程模板 (5)四、第一个程序——点亮LED (8)五、添加其他程序功能 (10)………………………………………………………………………………………………………………………………………………….一、初识LL 库最近论坛发的STM32L476RG Nucleo开发板到手了，准备学习玩耍，当然第一步就是下载资料，于是我下载STM32L4Cube 1.1.0版本，打开逐个查看，好像和以前一样的，没什么特别嘛，于是准备开始开发。

等等，好像还真发现了有点不一样：熟悉HAL库的都知道，该库的文件几乎都是以stm32xxx_hal_xxx.h/.c命名的，为了和以前的标准库有个区分，上图中那些是什么鬼前辈说，遇到问题赶紧查手册，于是我果断打开STM32L4Cube库的说明手册(UM1884):原来这个东西叫做Low Layer APIs，作为英文渣渣表示实在不习惯洋里洋气的高大上名字，于是擅自把他叫做【STM32LL库】了(不服的你咬我啊）。

从这里看好像是说这个东东比HAL库更接近硬件，到底什么鬼，还不清楚。

但是以前好像没见过这个东西啊，就算是STM32L4Cube的1.0.0版本中都没有。

看看Cube发行历史：原来LL库是在1.1.0版本才加上的，大概意思就是：1.LL APIs是寄存器级的编程，嗯，也就是说我们常说的直接操作寄存器吧。

2.LL APIs适用于xxx等一大堆外设3.LL APIs函数全部定义为static inline函数，放在对应的头文件中，用户使用需要包含相关头文件4.参考这两个文档看看LL库文件在Cube库中的位置，有20多个文件，全部以stm32l4xx_ll_xxx.h命名：STM32Cube_FW_L4_V1.1.0\Drivers\STM32L4xx_HAL_Driver\IncSTM32L4是面向低功耗市场的，同时不失高性能，功耗和性能往往是两个矛盾的东西，ST在硬件设计上想了各种办法来实现兼顾低功耗高性能(例如各种低功耗模式，LP外设等)，而在软件层面，程序也讲求效率，LL库全是直接操作寄存器，直接操作寄存器往往效率较高，而且函数定义为内联函数，调用函数时不是堆栈调用，而是直接把函数的代码嵌入到调用的地方，利于提高代码相率，我想这也是ST在STM32L4系列中推出这个直接操作寄存器的LL库的原因之一吧。

前言一天入门STM32，仅一天的时间，是否有真的这么快。

不同的人对入门的理解不一样，这篇一天入门STM32的教程，我们先对入门达成一个共识，如果你有异议，一天入门不了，请不要较真，不要骂街，保持一个工程师该有的修养，默默潜心学习，因为你还有很大的上升空间。

我眼中的入门：（前提是你学过51单片机和C语言）1、知道参考官方的什么资料来学习，而不是陷入一大堆资料中无从下手。

2、知道如何参考官方的手册和官方的代码来独立写自己的程序，而不是一味的看到人家写的代码就觉得人家很牛逼。

3、消除对STM32的恐惧，消除对库开发的恐惧，学习是一个快乐而富有成就感的过程。

第1章一天入门STM32本章参考资料：《STM32中文参考手册》《CM3权威指南CnR2》学习本章时，配合《STM32中文参考手册》GPIO章节一起阅读，效果会更佳，特别是涉及到寄存器说明的部分。

1.151与STM32简介51是嵌入式学习中一款入门级的精典MCU，因其结构简单，易于教学，且可以通过串口编程而不需要额外的仿真器，所以在教学时被大量采用，至今很多大学在嵌入式教学中用的还是51。

51诞生于70年代，属于传统的8位单片机，如今，久经岁月的洗礼，既有其辉煌又有其不足。

现在的市场产品竞争激烈，对成本极其敏感，相应地对MCU的要求也更苛刻：功能更多，功耗更低，易用界面和多任务。

面对这些要求，51现有的资源就显得得抓襟见肘了。

所以无论是高校教学还是市场需求，都急需一款新的MCU来为这个领域注入新的活力。

基于这市场的需求，ARM公司推出了其全新的基于ARMv7架构的32位Cortex-M3微控制器内核。

紧随其后，ST（意法半导体）公司就推出了基于Cortex-M3内核的MCU—STM32。

STM32凭借其产品线的多样化、极高的性价比、简单易用的库开发方式，迅速在众多Cortex-M3MCU中脱颖而出，成为最闪亮的一颗新星。

STM32一上市就迅速占领了中低端MCU市场，受到了市场和工程师的无比青睐，颇有星火燎原之势。

2.3 STM32系列芯片
• 2004年ARM公司推出了Cortex-M3 MCU 内核。紧随其后，ST（意 法半导体）公司就推出了基于Cortex-M3内核的MCU，就是STM32。 STM32凭借其产品线的多样化、极高的性价比、简单易用的开发 方式，迅速在众多Cortex-M3 MCU中脱颖而出。
图 2.1 Cortex-M3 的内核架构简化框图
2.2.2 ARM Cortex-M3应用与编程
• Cortex-M3处理器是一个32位的处理器。内部的数据路径是32位的， 寄存器是32位的，寄存器接口也是32位的；Cortex-M3的指令和数 据各使用一条总线，所以Cortex-M3处理器对多个操作可以并行执 行，加快了应用程序的执行速度；Cortex-M3处理器使用Thumb-2 指令集，它允许32位指令和16位指令同时使用，代码密度与处理 性能大幅RM微处理器包括：ARM7系列、ARM9系列、ARM9E系列、 ARM10E系列、ARM11系列、SecurCore系列、Inter的XScale、ARM Cortex系列等。
• 1. ARM7系列
• 适用于对价位和功耗要求较高的消费类应用，应用领域：工业控 制、Intenet设备、网络和调制解调器、移动电话等。
• Cortex-M3内核的架构如图2.1图所示，下面主要关注架构图中标 了序号的模块：寄存器组、NVIC、中断和异常、储存器映射、总 线接口、调试支持。
• Cortex-M3中央内核基于哈佛架构，指令和数据各使用一条总线， 所以Cortex-M3处理器对多个操作可以并行执行，加快了应用程序 的执行速度。内核流水线分3个阶段：取指、译码和执行。
• 7．StrongARM和XScale系列 • Inter StrongARM SA - 1100处理器是32位RISC微处理器； • 采用ARM体系结构高度集成，融合Inter的设计和处理技术及ARM体系结构的

STM32F20xxx_21xxx单⽚机硬件开发⼊门笔记AN3320Application noteGetting started with STM32F20xxx/21xxx MCUhardware developmentIntroductionThis application note is intended for system designers who require a hardwareimplementation overview of the development board features such as the power supply, theclock management, the reset control, the boot mode settings and the debug management. It shows how to use the high-density performance line STM32F20xxx/21xxx product familiesand describes the minimum hardware resources required to develop anSTM32F20xxx/21xxx application.Detailed reference design schematics are also contained in this document with descriptionsof the main components, interfaces and modes.August 2011Doc ID 18267 Rev 21/29/doc/20ec15b314791711cd7917a6.htmlContents AN3320Contents1Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1.1Independent A/D converter supply and reference voltage . . . . . . . . . . . . 71.1.2Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1.3Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.2Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.3Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.3.1Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 91.3.2Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 101.3.3System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.1HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.1.1External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.2External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 132.2LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.1External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.2External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 142.3Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.1Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.2Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.3Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.2SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3.1SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3.2Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.3.3Internal pull-up and pull-down resistors on JT AG pins . . . . . . . . . . . . . . 194.3.4SWJ debug port connection with standard JTAG connector . . . . . . . . . 20 2/29 Doc ID 18267 Rev 2AN3320Contents5Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.1Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.2Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.3Ground and power supply (V SS, V DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.4Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.5Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.6Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.1Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.2Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.3Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.4SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.5Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.2Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Doc ID 18267 Rev 23/29List of tables AN3320 List of tablesTable 1.Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2.Debug port pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3.SWJ I/O pin availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4.Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 5.Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6.Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4/29 Doc ID 18267 Rev 2AN3320List of figures List of figuresFigure 1.Power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2.Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3.Power-on reset/power-down reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4.PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5.Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6.HSE external clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7.HSE crystal/ceramic resonators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 8.LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9.LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Boot mode selection implementation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11.Host-to-board connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12.JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13.Typical layout for V DD/V SS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14.STM32F207IG(H6) microcontroller reference schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 25Doc ID 18267 Rev 25/29Power supplies AN33206/29 Doc ID 18267 Rev 21 Power supplies1.1 IntroductionThe device requires a 1.8V to 3.6V operating voltage supply (V DD ), excepted the WLCSPpackage witch requires 1.65V to 3.6V. An embedded regulator is used to supply the internal 1.2V digital power.The real-time clock (RTC) and backup registers can be powered from the V BAT voltage when the main V DD supply is powered off.1.V DDA and V SSA must be connected to V DD and V SS , respectively.2.The voltage on V REF ranges from 1.65V to V DDA for WLCSP64+2 packages.AN3320Power suppliesDoc ID 18267 Rev 27/291.1.1 Independent A/D converter supply and reference voltageTo improve conversion accuracy, the ADC has an independent power supply that can be filtered separately, and shielded from noise on the PCB.●the ADC voltage supply input is available on a separate V DDA pin ●an isolated supply ground connection is provided on the V SSA pinWhen available (depending on package), V REF– must be tied to V SSA .On 100-pin package and above and on WLCSP64+2To ensure a better accuracy on low-voltage inputs, the user can connect a separate external reference voltage ADC input on V REF+. The voltage on V REF+ may range from 1.8V to V DDA . On WLCSP64+2, the V REF- pin is not available, it is internally connected to the ADC ground (V SSA ).On 64-pin packagesThe V REF+ and V REF- pins are not available, they are internally connected to the ADC voltage supply (V DDA ) and ground (V SSA ).1.1.2 Battery backupTo retain the content of the Backup registers when V DD is turned off, the V BAT pin can beconnected to an optional standby voltage supplied by a battery or another source.The V BAT pin also powers the RTC unit, allowing the RTC to operate even when the main digital supply (V DD ) is turned off. The switch to the V BAT supply is controlled by the power down reset (PDR) circuitry embedded in the Reset block.If no external battery is used in the application, it is highly recommended to connect V BAT externally to V DD .1.1.3 Voltage regulatorThe voltage regulator is always enabled after reset. It works in three different modesdepending on the application modes.●in Run mode, the regulator supplies full power to the 1.2V domain (core, memories and digital peripherals)●in Stop mode, the regulator supplies low power to the 1.2V domain, preserving the contents of the registers and SRAM●in Standby mode, the regulator is powered down. The contents of the registers and SRAM are lost except for those concerned with the Standby circuitry and the Backup domain.Note:Depending on the selected package, there are specific pins that should be connected either to V SS or V DD to activate or deactivate the voltage regulator. Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details .Power supplies AN33208/29 Doc ID 18267 Rev 21.2 Power supply schemesThe circuit is powered by a stabilized power supply, V DD .●Caution:–The V DD voltage range is 1.8V to 3.6V (and 1.65V to 3.6V for WLCSP64+2 package)●The V DD pins must be connected to V DD with external decoupling capacitors: one single T antalum or Ceramic capacitor (min. 4.7µF typ.10µF) for the package + one 100nF Ceramic capacitor for each V DD pin.●The V BAT pin can be connected to the external battery (1.65V < V BA T < 3.6V). If no external battery is used, it is recommended to connect this pin to V DD with a 100nF external ceramic decoupling capacitor.●The V DDA pin must be connected to two external decoupling capacitors (100nF Ceramic + 1µF Tantalum or Ceramic).●The V REF+ pin can be connected to the V DDA external power supply. If a separate, external reference voltage is applied on V REF+, a 100nF and a 1µF capacitors must be connected on this pin. In all cases, V REF+ must be kept between 1.65V and V DDA .●Additional precautions can be taken to filter analog noise:–V DDA can be connected to V DD through a ferrite bead.–The V REF+ pin can be connected to V DDA through a resistor (typ. 47Ω).●For the voltage regulator configuration, there are specific pins (REGOFF and IRROFF depending on the package) that should be connected either to VSS or VDD to activate or deactivate the voltage regulator specific. Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details .●When the voltage regulator is enabled, V CAP1 and V CAP2 pins must be connected to 2*2.2µF Ceramic capacitor.AN3320Power suppliesDoc ID 18267 Rev 29/291.Optional. If a separate, external reference voltage is connected on V REF+, the two capacitors (100 nF and1µF) must be connected.2.V REF + is either connected to V REF or to V DDA .3.N is the number of V DD and V SS inputs.4.Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet to connect REGOFF and IRROFFpins.1.3Reset & power supply supervisor1.3.1Power on reset (POR) / power down reset (PDR)The device has an integrated POR/PDR circuitry that allows proper operation starting from 1.8V .The device remains in the Reset mode as long as V DD is below a specified threshold, V POR/PDR , without the need for an external reset circuit. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics in STM32F20xxx/21xxx datasheets.On WLCSP66 package if IRROFF pin is set to V DD (in that case REGOFF pin must not be activated, refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details ), the PDR is not functional. Then the V DD can lower below 1.8V , but the external circuitry must ensure that reset pin is activated when V DD /V DDA becomes below 1.65V .Power suppliesAN332010/29 Doc ID 18267 Rev 21.t RSTTEMPO is approximately2.6ms. V POR/PDR rising edge is 1.74V (typ.) and V POR/PDR falling edge is1.70V (typ.). Refer to STM32F20xxx/21xxx datasheets for actual value.1.3.2 Programmable voltage detector (PVD)Y ou can use the PVD to monitor the V DD power supply by comparing it to a thresholdselected by the PLS[2:0] bits in the Power control register (PWR_CR).The PVD is enabled by setting the PVDE bit.A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicatewhether V DD is higher or lower than the PVD threshold. This event is internally connected to EXTI Line16 and can generatean interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when V DD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge configuration. As an example the service routine can perform emergency shutdown tasks.AN3320Power suppliesDoc ID 18267 Rev 211/291.3.3 System resetA system reset sets all registers to their reset values except for the reset flags in the clockcontroller CSR register and the registers in the Backup domain (see Figure 1).A system reset is generated when one of the following events occurs:1. A low level on the NRST pin (external reset)2. window watchdog end-of-count condition (WWDG reset)3. Independent watchdog end-of-count condition (IWDG reset)4. A software reset (SW reset)5.Low-power management resetThe reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR.The STM32F20xxx/21xxx does not require an external reset circuit to power-up correctly. Only a pull-down capacitor is recommended to improve EMS performance by protecting the device against parasitic resets. See Figure 5.Charging and discharging a pull-down capacitor through an internal resistor increases the device power consumption. The capacitor recommended value (100nF) can be reduced to 10nF to limit this power consumption;Clocks AN332012/29 Doc ID 18267 Rev 22 ClocksThree different clock sources can be used to drive the system clock (SYSCLK):●HSI oscillator clock (high-speed internal clock signal)●HSE oscillator clock (high-speed external clock signal)●PLL clockThe devices have two secondary clock sources:●32kHz low-speed internal RC (LSI RC) that drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby modes.●32.768kHz low-speed external crystal (LSE crystal) that optionally drives the real-time clock (RTCCLK)Each clock source can be switched on or off independently when it is not used, to optimize the power consumption.Refer to the STM32F20xxx/21xxx reference manual RM0033 for the description of the clock tree.2.1 HSE OSC clockThe high-speed external clock signal (HSE) can be generated from two possible clock sources:●HSE external crystal/ceramic resonator (see Figure 7)●HSE user external clock (see Figure 6)1.The value of R EXT depends on the crystal characteristics. Typical value is in the range of 5 to 6 R S(resonator series resistance).2.Load capacitance C L has the following formula: C L = C L1 x C L2 / (C L1 + C L2) + C stray where: C stray is the pincapacitance and board or trace PCB-related capacitance. Typically, it is between 2pF and 7pF. Please refer to Section 5: Recommendations on page 21 to minimize its value.Figure 6.HSE external clockFigure 7.HSE crystal/ceramicAN3320ClocksDoc ID 18267 Rev 213/292.1.1 External source (HSE bypass)In this mode, an external clock source must be provided. It can have a frequency from 1 to 16MHz (refer toSTM32F20xxx/21xxx datasheets for actual max value).The external clock signal (square, sine or triangle) with a duty cycle of about 50%, has to drive the OSC_IN pin while the OSC_OUT pin must be left in the high impedance state (see Figure 7 and Figure 6).2.1.2 External crystal/ceramic resonator (HSE crystal)The external oscillator frequency ranges from 4 to 26MHz.The external oscillator has the advantage of producing a very accurate rate on the mainclock. The associated hardware configuration is shown in Figure 7. Using a 25MHz oscillator frequency is a good choice to get accurate Ethernet, USB OTG high-speed peripheral, and I 2S.The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator.For C L1 and C L2 it is recommended to use high-quality ceramic capacitors in the 5pF-to-25pF range (typ.), designed for high-frequency applications and selected to meet the requirements of the crystal or resonator. C L1 and C L2, are usually the same value. Thecrystal manufacturer typically specifies a load capacitance that is the series combination of C L1 and C L2. The PCB andMCU pin capacitances must be included when sizing C L1 and C L2 (10 pF can be used as a rough estimate of the combined pin and board capacitance).Refer to the electrical characteristics sections in the datasheet of your product for more details.Clocks AN332014/29 Doc ID 18267 Rev 22.2 LSE OSC clockThe low-speed external clock signal (LSE) can be generated from two possible clocksources:●LSE external crystal/ceramic resonator (see Figure 9)●LSE user external clock (see Figure 8)1.“LSE crystal/ceramic resonators” figure:To avoid exceeding the maximum value of C L1 and C L2 (15pF) it is strongly recommended to use a resonator with a load capacitance C L ≤7pF. Never use a resonator with a load capacitance of 12.5pF.2.“LSE external clock” and “LSEcrystal/ceramic resonators” figures:OSC32_IN and OSC32_OUT pins can be used also as GPIO, but it is recommended not to use them as both RTC and GPIO pins in the same application.3.“LSE crystal/ceramic resonators” figure:The value of R EXT depends on the crystal characteristics. A 0Ω resistor would work but would not be optimal. To fine tube R S value, refer to AN2867 - Oscillator design guide for ST microcontrollers.2.2.1 External source (LSE bypass)In this mode, an external clock source must be provided. It can have a frequency of up to 1MHz. The external clock signal (square, sine or triangle) with a duty cycle of about 50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high impedance (see Figure 8).2.2.2 External crystal/ceramic resonator (LSE crystal)The LSE crystal is a 32.768kHz low-speed external crystal or ceramic resonator. It has theadvantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (RTC) forclock/calendar or other timing functions.The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator.Figure 8.LSE external clockFigure 9.LSE crystal/ceramicAN3320ClocksDoc ID 18267 Rev 215/292.3 Clock security system (CSS)The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.●If a failure is detected on the HSE oscillator clock, the oscillator is automaticallydisabled. A clock failure event is sent to the break input of the TIM1 advanced control timer and an interrupt is generated to inform the software about the failure (clocksecurity system interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex?-M3 NMI (non-maskable interrupt) exception vector.●If the HSE oscillator is used directly or indirectly as the system clock (indirectly means that it is used as the PLL input clock, and the PLL clock is used as the system clock), a detected failure causes a switch of the system clock to the HSI oscillator and thedisabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.For details, see the STM32F20xxx/21xxx (RM0033) reference manuals available from the STMicroelectronics website /doc/20ec15b314791711cd7917a6.html .Boot configuration AN332016/29 Doc ID 18267 Rev 23 Boot configuration3.1 Boot mode selectionIn the STM32F20xxx/21xxx, three different boot modes can be selected by means of theBOOT[1:0] pins as shown in Table 1.The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot mode.The BOOT pins are also resampled when exiting the Standby mode. Consequently, they must be kept in the required Boot mode configuration in the Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, and starts code execution from the boot memory starting from 0x0000 0004.3.2 Boot pin connectionFigure 10 shows the external connection required to select the boot memory of the STM32F20xxx/21xxx.1.Resistor values are given only as a typical example.Table 1.Boot modesBOOT mode selection pinsBoot mode AliasingBOOT1BOOT0x 0Main Flash memory Main Flash memory is selected as boot space01System memory System memory is selected as boot space11Embedded SRAMEmbedded SRAM is selected as boot spaceAN3320Boot configuration3.3 Embedded boot loader modeThe Embedded boot loader mode is used to reprogram the Flash memory using one of theavailable serial USART1(PA9/PA10), USART3(PB10/11 & PC10/11), CAN2(PB5/13) or USBOTG FS(PA11/12) in Device mode (DFU: device firmware upgrade).The USART peripheral operates with the internal 16MHz oscillator (HSI). The CAN andUSB OTG FS, however, can only function if an external clock (HSE) multiple of 1 MHz(between 4 and 26 MHz)is present.This embedded boot loader is located in the System memory and is programmed by STduring production.For additional information, refer to AN2606.Doc ID 18267 Rev 217/29Debug management AN332018/29 Doc ID 18267 Rev 24 Debug management4.1 IntroductionThe Host/Target interface is the hardware equipment that connects the host to theapplication board. This interface is made of three components: a hardware debug tool, a JTAG or SW connector and a cable connecting the host to the debug tool.Figure 11 shows the connection of the host to the evaluation board STM3220G-EVAL.Figure 11.Host-to-board connection 4.2 SWJ debug port (serial wire and JTAG)The STM32F20xxx/21xxx core integrates the serial wire / JT AG debug port (SWJ-DP). It is an ARM? standard CoreSight? debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-pin) interface.●The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-AP port●The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP portIn the SWJ-DP , the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP .4.3 Pinout and debug port pinsThe STM32F20xxx/21xxx MCU is offered in various packages with different numbers of available pins. As a result, some functionality related to the pin availability may differ from one package to another.4.3.1 SWJ debug port pinsFive pins are used as outputs for the SWJ-DP as alternate functions of general-purpose I/Os (GPIOs). These pins, shown in Table 2, are available on all packages.%VALUATION BOARD(OST 0#0OWER SUPPLY*4!' 37 CONNECTOR$EBUG TOOLAI BAN3320Debug managementDoc ID 18267 Rev 219/294.3.2 Flexible SWJ-DP pin assignmentAfter reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host).However, some of the JTAG pins shown in Table 3 can be configured to an alternate function through the GPIOx_AFRx registers.Table 3 shows the different possibilities to release some pins.For more details, see the STM32F20xxx/21xxx (RM0033) reference manual, available from the STMicroelectronics website /doc/20ec15b314791711cd7917a6.html .4.3.3 Internal pull-up and pull-down resistors on JTAG pinsThe JTAG input pins must not be floating since they are directly connected to flip-flops to control the debug mode features. Special care must be taken with the SWCLK/TCK pin that is directly connected to the clock of some of these flip-flops. Table 2.Debug port pin assignmentSWJ-DP pin nameJTAG debug portSW debug portPinassignment TypeDescription Type Debug assignment JTMS/SWDIO I JTAG test mode selection I/O Serial wire data input/output PA13JTCK/SWCLK I JTAG test clock I Serial wire clock P A14JTDII JTAG test data input --P A15JTDO/TRACESWO O JTAG test data output -TRACESWO if async traceis enabled PB3JNTRSTIJTAG test nReset。