K9F2G08R0A
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FLASH MEMORYK9F2G08U0AK9F2G08R0A K9F2G08UXA* Samsung Electronics reserves the right to change products or specification without notice.INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.FLASH MEMORYK9F2G08U0AK9F2G08R0A Document Title256M x 8 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.00.10.20.30.41.01.11.21.3RemarkAdvance AdvancePreliminaryPreliminaryPreliminary FinalHistory1. Initial issue1. 1.8V part is added.2. tRHW, tCSD parameter is defined.3. 4G DDP LGA part is deleted.4. Technical note is added.(p.18)1. FBGA package size is changed 2. 1.8V TSOP is deleted1. 1.8V Ioh/Iol condition is changed2. Min. tADL @3.3V is changed form 70ns to 100ns 1. 1.8V device supports Copy-Back Program1. 1.8V AC timing is changed2. tRPB/tRCB/tREAB is added for 1.8V device1. tCSD is changed.(10ns -> 0ns)1. tCS 31ns -> 25ns, tREH 15ns -> 10ns (@ 1.8V)Draft DateNov. 09. 2005Mar. 17th. 06May 25th 2006June 1st 2006June 29th 2006Aug 23th 2006Jan. 15th 2007Mar. 15th 2007June 4th 2007FLASH MEMORYK9F2G08U0AK9F2G08R0A GENERAL DESCRIPTIONFEATURES• Voltage Supply - 1.65V ~ 1.95V - 2.70V ~ 3.60V • Organization- Memory Cell Array : (256M + 8M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation- Page Size : (2K + 64)Byte - Random Read : 25µs(Max.) - Serial Access : 25ns(Min.) (*K9F2G08R0A: tRC = 42ns(Min))256M x 8 Bit NAND Flash Memory• Fast Write Cycle Time- Page Program time : 200µs(Typ.) - Block Erase Time : 1.5ms(Typ.)• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology-Endurance : 100K Program/Erase Cycles (with 1bit/512Byte ECC)- Data Retention : 10 Years • Command Driven Operation• Intelligent Copy-Back with internal 1bit/528Byte EDC • Unique ID for Copyright Protection • Package :- K9F2G08R0A-JCB0/JIB0 : Pb-FREE PACKAGE 63 - Ball FBGA I (10 x 13 / 0.8 mm pitch)- K9F2G08U0A-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9F2G08U0A-ICB0/IIB052 - Pin ULGA (12 x 17 / 1.00 mm pitch)Offered in 256Mx8bit, the K9F2G08X0A is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns(42ns with 1.8V device) cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as com-mand input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F2G08X0A ′s extended reli-ability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2G08X0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.PRODUCT LISTPart Number Vcc Range OrganizationPKG Type K9F2G08R0A-J 1.65 ~ 1.95V X8FBGA K9F2G08U0A-P 2.70 ~ 3.60VTSOP1K9F2G08U0A-I52ULGAK9F2G08R0AFLASH MEMORY K9F2G08U0AFLASH MEMORYK9F2G08U0AK9F2G08R0A K9F2G08R0A-JCB0/JIB0PIN CONFIGURATION (FBGA)R/B /WE /CE Vss ALE /WP /RE CLE NC NC NC NC Vcc NC NC I/O0I/O1NC NCVccI/O5I/O7VssI/O6I/O4I/O3I/O2VssNC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC N.CN.C N.C N.C N.C N.CN.CN.CN.C N.C N.C N.CN.C N.C N.C 34561 2A B C D G E F HTop ViewFLASH MEMORYK9F2G08U0AK9F2G08R0A 10.00±0.10#A1Side ViewTop View 1.00(M a x )0.45±0.05Bottom View13.00±0.1063-∅0.45±0.050.25(M i n .)0.10MAX0.20 M A B∅13.00±0.104321A BC D G 0.80 x 7= 5.6013.00±0.100.80 x 5= 4.000.80BA2.802.0010.00±0.10(Datum B)(Datum A)0.800.80 x 11= 8.800.80 x 9= 7.20 65EF H#A1 INDEX MARK(OPTIONAL)PACKAGE DEMENSIONS(FBGA)FLASH MEMORYK9F2G08U0AK9F2G08R0A 1.001.001.001.002.007 6 5 4 3 2 11.001.001.0012.00±0.10#A117.00±0.1017.00±0.10BA12.00±0.10(Datum B)(Datum A)12.0010.002.502.502.000.501.30A B C DEF GHJ K L M N12-∅1.00±0.0541-∅0.70±0.05Side View0.65(M a x .)0.10 C17.00±0.10Top ViewBottom ViewABC D EF G H J KL M N7654321PIN CONFIGURATION (ULGA)K9F2G08U0A-ICB0/IIB052-ULGA (measured in millimeters)NCNCNCNCNCNCNCNCNC NC NCNC NCNCNC NCVccVcc VssVssVss /RE NC/CENC CLENC ALE NC /WE NC /WPNC R/B NCVssIO0 NCIO1NCIO2IO3NCNC IO4 NC IO5NCIO6 NCIO7NC∅ABC M 0.1∅ABC M 0.1PACKAGE DIMENSIONSFLASH MEMORYK9F2G08U0AK9F2G08R0A PIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.Pin Name Pin FunctionI/O 0 ~ I/O 7DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CECHIP ENABLEThe CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation.REREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low.R/BREADY/BUSY OUTPUTThe R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.K9F2G08R0AFLASH MEMORY K9F2G08U0AFLASH MEMORYK9F2G08U0AK9F2G08R0A Product IntroductionThe K9F2G08X0A is a 2,112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2,112x8 columns. Spare 64x8columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-sists of 2,048 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F2G08X0A.The K9F2G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 264M byte physical space requires 29 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F2G08X0A.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.Table 1. Command SetsNOTE : 1. Random Data Input/Output can be executed in a page. 2. Read EDC Status is only available on Copy Back operation.3. Any command between 11h and 81h is prohibited except 70h and FFh.4. K9F2G08R0A does not support Two-Plane operation.Caution : Any undefined command inputs are prohibited except for above command set of Table 1.Function1st Cycle 2nd CycleAcceptable Command during BusyRead 00h30h Read for Copy Back 00h 35h Read ID 90h -Reset FFh -OPage Program80h 10h Two-Plane Page Program (3)80h---11h 81h---10h Copy-Back Program85h 10h Two-Plane Copy-Back Program (3)85h---11h 81h---10h Block Erase60h D0h Two-Plane Block Erase 60h---60h D0h Random Data Input (1)85h -Random Data Output (1)05h E0hRead Status 70h O Read EDC Status (2)7BhOFLASH MEMORYK9F2G08U0AK9F2G08R0A DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.ParameterSymbolTest Conditions 1.8V3.3V UnitMinTypMaxMinTypMaxOperating CurrentPage Read withSerial Access I CC 1tRC=25ns(K9F2G08R0A: 42ns)CE=V IL, I OUT =0mA-1020-1530mAProgramI CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC - -1--1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -1050-1050µAInput Leakage Current I LI V IN =0 to Vcc(max)--±10--±10Output Leakage Current I LO V OUT =0 to Vcc(max)--±10--±10Input High VoltageV IH (1)-0.8xVcc -Vcc+0.30.8xVcc-Vcc+0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVcc-0.3-0.2xVccOutput High Voltage Level V OH K9F2G08R0A: I OH=-100µAK9F2G08U0A: I OH =-400µA Vcc-0.1-- 2.4--Output Low Voltage Level V OLK9F2G08R0A: I OL=100µA K9F2G08U0A: I OL =2.1mA--0.1--0.4Output Low Current(R/B)I OL (R/B)V OL =0.4V34810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9F2G08X0A-XCB0 :T A =0 to 70°C, K9F2G08X0A-XIB0:T A =-40 to 85°C)Parameter Symbol 1.8V3.3V Unit Min Typ.Max Min Typ.Max Supply Voltage V CC 1.65 1.8 1.95 2.7 3.3 3.6V Supply VoltageV SSVABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol RatingUnit1.8V 3.3V Voltage on any pin relative to VSSV CC-0.6 to +2.45-0.6 to +4.6VV IN -0.6 to +2.45-0.6 to +4.6V I/O-0.6 to Vcc + 0.3 (< 2.45V)-0.6 to Vcc + 0.3 (< 4.6V)Temperature Under BiasK9F2G08X0A-XCB0T BIAS -10 to +125°C K9F2G08X0A-XIB0-40 to +125Storage Temperature K9F2G08X0A-XCB0T STG-65 to +150°CK9F2G08X0A-XIB0Short Circuit CurrentI OS5mAFLASH MEMORYK9F2G08U0AK9F2G08R0A CAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested.ItemSymbol Test ConditionMin Max Unit Input/Output Capacitance C I/O V IL =0V -10pF Input CapacitanceC INV IN =0V-10pFVALID BLOCKNOTE :1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.Parameter Symbol Min Typ.Max Unit K9F2G08X0AN VB2,008-2,048BlocksAC TEST CONDITION(K9F2G08X0A-XCB0 :T A =0 to 70°C, K9F2G08X0A-XIB0:T A =-40 to 85°C,K9F2G08R0A: Vcc=1.65~1.95V, K9F2G08UA: Vcc=2.7V~3.6V unless otherwise noted)ParameterK9F2G08R0A K9F2G08U0A Input Pulse Levels 0V to Vcc 0V to Vcc Input Rise and Fall Times 5ns 5ns Input and Output Timing Levels Vcc/2Vcc/2Output Load1 TTL GATE and CL=30pF1 TTL GATE and CL=50pFMODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(5clock)H L L H H Write Mode Command Input L H L H H Address Input(5clock)L L L HH Data Input L L L H X Data Output X X X X H X During Read(Busy)X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-byFLASH MEMORYK9F2G08U0AK9F2G08R0A AC Timing Characteristics for Command / Address / Data InputNOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycleParameterSymbol MinMaxUnit 1.8V 3.3V 1.8V 3.3V CLE Setup Time t CLS (1)2112--ns CLE Hold Time t CLH 55--ns CE Setup Time t CS (1)2520--ns CE Hold Time t CH 55--ns WE Pulse Width t WP 2112--ns ALE Setup Time t ALS (1)2112--ns ALE Hold Time t ALH 55--ns Data Setup Time t DS (1)2012--ns Data Hold Time t DH 55--ns Write Cycle Time t WC 4225--ns WE High Hold Timet WH 1510--ns Address to Data Loading Timet ADL (2)100100--nsProgram / Erase CharacteristicsNOTE : 1. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at3.3V Vcc and 25°C temperature .ParameterSymbol Min Typ Max Unit Program Time t PROG -200700µs Dummy Busy Time for Two-Plane Page Program t DBSY -0.51µs Number of Partial Program Cycles Nop --4cycles Block Erase Timet BERS- 1.52msFLASH MEMORYK9F2G08U0AK9F2G08R0A AC Characteristics for OperationNOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs. 2. This parameter (t RPB /t RCB /t REAB ) must be used only for 1.8V device.ParameterSymbol MinMaxUnit 1.8V 3.3V 1.8V 3.3V Data Transfer from Cell to Register t R --2525µs ALE to RE Delay t AR 1010--ns CLE to RE Delay t CLR 1010--ns Ready to RE Low t RR 2020--ns RE Pulse Width t RP 2112--ns WE High to Busy t WB --100100ns Read Cycle Time t RC 4225--ns RE Access Time t REA --3020ns CE Access Time t CEA --3525ns RE High to Output Hi-Z t RHZ --100100ns CE High to Output Hi-Zt CHZ --3030ns CE High to ALE or CLE Don’t Care t CSD 00--ns RE High to Output Hold t RHOH 1515--ns RE Low to Output Hold t RLOH 55--ns CE High to Output Hold t COH 1515--ns RE High Hold Time t REH 1010--ns Output Hi-Z to RE Low t IR 00--ns RE High to WE Low t RHW 100100--ns WE High to RE Lowt WHR 6060--ns Device Resetting Time(Read/Program/Erase)t RST --5/10/500(1)5/10/500(1)µs RE Pulse Width during Busy State t RPB (2)35---ns Read Cycle Time during Busy State t RCB (2)50---ns RE Access Time during Busy Statet REAB (2)--40-nsFLASH MEMORYK9F2G08U0AK9F2G08R0A NAND Flash Technical NotesIdentifying Initial Invalid Block(s)Initial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit /512Byte ECC.All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.*Check "FFh" at the column address 2048 Figure 3. Flow chart to create initial invalid block tableStartSet Block Address = 0Check "FFh"Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInitialof the 1st and 2nd page in the blockInvalid Block(s) TableFLASH MEMORYK9F2G08U0AK9F2G08R0A NAND Flash Technical Notes (Continued)Program Flow ChartStartI/O 6 = 1 ?I/O 0 = 0 ?No*Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterProgram Completedor R/B = 1 ?Program ErrorYesNoYes: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.*Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure ModeDetection and Countermeasure sequenceWrite Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement ReadSingle Bit FailureVerify ECC -> ECC CorrectionECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionK9F2G08R0AFLASH MEMORY K9F2G08U0AFLASH MEMORYK9F2G08U0AK9F2G08R0A NAND Flash Technical Notes (Continued)Copy-Back Operation with EDC & Sector Definition for EDCGenerally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors.K9F2G08X0A supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area."A" area 512 Byte(1’st sector)"H" area (4’th sector)Main Field (2,048 Byte)16 Byte"G" area (3’rd sector)16 Byte "F" area (2’nd sector)16 Byte "E" area (1’st sector)16 Byte "B" area 512 Byte(2’nd sector)"C" area 512 Byte(3’rd sector)"D" area 512 Byte(4’th sector)Spare Field (64 Byte)Table 2. Definition of the 528-Byte SectorSector Main Field (Column 0~2,047)Spare Field (Column 2,048~2,111)Area NameColumn AddressArea NameColumn Address 1’st 528-Byte Sector "A"0 ~ 511"E"2,048 ~ 2,0632’nd 528-Byte Sector "B"512 ~ 1,023"F"2,064 ~ 2,0793’rd 528-Byte Sector "C"1,024 ~ 1,535"G"2,080 ~ 2,0954’th 528-Byte Sector"D"1,536 ~ 2,047"H"2,096 ~ 2,111Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0.From the LSB page to MSB page DATA IN: Data (1)Data (64)(1)(2)(3)(32)(64)Data register Page 0Page 1Page 2Page 31Page 63Ex.) Random page program (Prohibition)DATA IN: Data (1)Data (64)(2)(32)(3)(1)(64)Data registerPage 0Page 1Page 2Page 31Page 63Addressing for program operation::::K9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AK9F2G08R0AFLASH MEMORY K9F2G08U0AFLASH MEMORYK9F2G08U0AK9F2G08R0A Read ID OperationCECLEWEALERE90hRead ID CommandMaker Code Device Code00h ECht REAAddress 1cycleI/Oxt ARDevice Device Code (2nd Cycle)3rd Cycle 4th Cycle 5th Cycle K9F2G08R0A AAh 00h 15h 44h K9F2G08U0ADAh10h95h44hDevice 4th cyc.Code3rd cyc.5th cyc.FLASH MEMORY K9F2G08U0AK9F2G08R0A4th ID DataDescription I/O7 I/O6I/O5 I/O4 I/O3I/O2I/O1 I/O0Page Size(w/o redundant area ) 1KB2KB4KB8KB0 00 11 01 1Block Size(w/o redundant area ) 64KB128KB256KB512KB0 00 11 01 1Redundant Area Size ( byte/512byte) 8161Organization x8x161Serial Access Minimum 50ns/30ns25nsReservedReserved1111ID Definition Table90 ID : Access command = 90HDescription1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Maker CodeDevice CodeInternal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size3rd ID DataDescription I/O7 I/O6I/O5 I/O4I/O3 I/O2I/O1 I/O0Internal Chip Number 12480 00 11 01 1Cell Type 2 Level Cell4 Level Cell8 Level Cell16 Level Cell0 00 11 01 1Number ofSimultaneouslyProgrammed Pages 12480 00 11 01 1Interleave Program Between multiple chips Not SupportSupport1Cache Program Not SupportSupport1FLASH MEMORY K9F2G08U0AK9F2G08R0A5th ID DataDescription I/O7I/O6 I/O5 I/O4I/O3 I/O2 I/O1I/O0Plane Number 12480 00 11 01 1Plane Size(w/o redundant Area) 64Mb128Mb256Mb512Mb1Gb2Gb4Gb8Gb0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Reserved 0 0 0。
