外文资料原件或复印件及译文
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外文资料原件或复印件及译文1、原文部分：Cyclone IntroductionThe CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logicelements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.FeaturesThe Cyclone device family offers the following features:■ 2,910 to 20,060 LEs, see Table 1–1■ Up to 294,912 RAM bits (36,864 bytes)■ Supports configuration through low-cost serial configuration device■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard■ High-speed (640 Mbps) LVDS I/O support■ Low-speed (311 Mbps) LVDS I/O support■ 311-Mbps RSDS I/O support■Up to eight global clock lines with six clock resources available per logic array block (LAB) row■Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAMDescriptionCyclone devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks. The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone devices range between 2,910 to 20,060 LEs. M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 250 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM. Each Cyclone device I/O pin is fed by an I/O element(IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66- and 33-MHz, 64- and 32-bit PCI standard and the LVDS I/O standard at up to 640 Mbps. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals.Dual-purpose DQS, DQ, and DM pins along with delay chains (used to phase-align DDR signals) provide interface support with external memory devices such as DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps). Cyclone devices provide a global clock network and up to two PLLs. The global clock network consists of eight global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support.2、译文部分：飓风系列芯片介绍：飓风系列可编程芯片核心电压 1.5V，采用0.13um制程，全铜工艺, 集成20，060个逻辑单元，并且内置288 K RAM空间。
集成PLLS使数据传递更快，高速DDR接口可满足DDR SDRAM 和RAM (FCRAM) 内存传输需求，所以说飓风芯片在数据应用方面是相当经济实用的。
飓风芯片支持众多的I/O 标准,支持66或33MHZ , 64或32 位基于PCI 标准的高速(640 Mbps) LVDS I/O , 另外它还支持的ASSP 和ASIC 设备。
并且Altera 公司会经常提供新型的低成本并行配置芯片来进行支持。
特点：飓风家族芯片具有以下特点:1、从2,910到20,060 个逻辑单元2、最大可支持294,912bit内存容量3、对低成本的配置芯片提供持续的支持4、支持LVTTL 、LVCMOS 、SSTL-2, 和SSTL-3 I/O 标准5、支持66或33MHZ , 64或32 位PCI 标准6、高速(640 Mbps) LVDS I/O 支持7、低速(311 Mbps) LVDS I/O 支持8、 311-Mbps RSDS I/O 支持9、每个逻辑单元供给8条全局时钟线路，六个时钟资源10、支持外置存储器件包括DDR SDRAM (133 兆赫)，FCRAM, 和单通道(SDR) SDRAM说明：飓风系列芯片包含一个二维列和基于珊块的体系来实现自定义逻辑，珊块和列的变化速度互联在处理块和记忆块之间提供连接。
逻辑列阵包括处理块,每个处理快包含10个小块。
每个小块是为用户提供逻辑功能的基础。
在芯片中，处理块贯穿于珊块和列。
飓风系列芯片处理块集成度从2910到20060。
M4K RAM块是具有4K比特内存的双端口记忆块，这些块提供简单的双端口或者36位宽度最高250MHZ的单端口记忆体，它们贯穿于芯片中的某些逻辑块。
飓风系列芯片提供从60到288千比特的嵌入式RAM。
每个飓风芯片的I/O端口由IOE定位在处理单元附近周围。
I/O端口支持多种终端和不同的I/O标准，比如66，33MHZ,64,32位的PCI标准和最高到640Mbps的LVDS I/O标准，每个IOE包含双向I/O缓冲、三个用来注册输入输出和说出使能端信号的记忆体，DQS、DQ、DM 端口连在一起（采用DDR信号）对像DDR SDRAM和运行在133MH(266MBPS)的ZFCRAM这类存储设备提供外部支持。
