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SN54HC193, SN74HC193
4ĆBIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122D − DECEMBER 1982 − REVISED OCTOBER 2003
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265DWide Operating Voltage Range of 2 V to 6 V
DOutputs Can Drive Up To 10 LSTTL Loads
DLow Power Consumption, 80-µA Max ICCDTypical tpd = 20 ns
D±4-mA Output Drive at 5 V
DLow Input Current of 1 µA MaxDLook-Ahead Circuitry Enhances Cascaded
Counters
DFully Synchronous in Count Modes
DParallel Asynchronous Load for Modulo-N
Count Lengths
DAsynchronous Clear
1
2
3
4
5
6
7
816
15
14
13
12
11
10
9B
QB
QA
DOWN
UP
QC
QD
GNDVCC
A
CLR
BO
CO
LOAD
C
DSN54HC193...J OR W PACKAGE
SN74HC193...D, N, NS, OR PW PACKAGE
(TOP VIEW)
3212019
9101112134
5
6
7
818
17
16
15
14CLR
BO
NC
CO
LOADQA
DOWN
NC
UP
QCQBNC
DCVA
D
GNDNCSN54HC193...FK PACKAGE
(TOP VIEW)
NC − No internal connectionBCC
Q
description/ordering information
The ’HC193 devices are 4-bit synchronous, reversible, up/down binary counters.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change
coincidentally with each other when so instructed by the steering logic. This mode of operation eliminates the
output counting spikes normally associated with asynchronous (ripple-clock) counters.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBERTOP-SIDE
MARKING
PDIP − NTube of 25SN74HC193NSN74HC193N
Tube of 40SN74HC193D
Reel of 2500SN74HC193DRSOIC − D
Reel of 250SN74HC193DTHC193
−40°C to 85°CSOP − NSReel of 2000SN74HC193NSRHC193
Tube of 90SN74HC193PW
Reel of 2000SN74HC193PWRTSSOP − PW
Reel of 250SN74HC193PWTHC193
CDIP − JTube of 25SNJ54HC193JSNJ54HC193J
°°CFP − WTube of 150SNJ54HC193WSNJ54HC193W−55C to 125C
LCCC − FKTube of 55SNJ54HC193FKSNJ54HC193FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.On products compliant to MILĆPRFĆ38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.SN54HC193, SN74HC193
4ĆBIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122D − DECEMBER 1982 − REVISED OCTOBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265description/ordering information (continued)
The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP
or DOWN). The direction of counting is determined by which count input is pulsed while the other count input
is high.
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on
the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the
data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers
simply by modifying the count length with the preset inputs.
A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The
clear function is independent of the count and LOAD inputs.
These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output
produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO)
output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counters then can
be cascaded easily by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter.SN54HC193, SN74HC193
4ĆBIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122D − DECEMBER 1982 − REVISED OCTOBER 2003
3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265logic diagram (positive logic)
Pin numbers shown are for the D, J, N, NS, PW, and W packages.S
C11D
R7911451412
13
QDBO
LOADCO
CLR
DS
C11D
R610
QCCS
C11D
R21
QBBS
C11D
R315
QAAUP
DOWN
S
R
