MC9S08LG32_icpdf

  • 格式:pdf
  • 大小:2.49 MB
  • 文档页数:51

Freescale Semiconductor Data Sheet: Technical DataDocument Number: MC9S08LG32Rev. 7, 8/2009Freescale reserves the right to change the detail specifications as may be required to permitimprovements in the design of its products.MC9S08LG3280-LQFPCase 917A14 mm × 14 mm64-LQFP Case 840F10 mm × 10 mm48-LQFP Case 9327 mm × 7mm Features •8-bit HCS08 Central Processor Unit (CPU)–Up to 40 MHz CPU at 5.5 V to 2.7 V across temperaturerange of –40 °C to 85 °C and –40 °C to 105 °C–HCS08 instruction set with added BGND instruction–Support for up to 32 interrupt/reset sources•On-Chip Memory–32 KB or 18 KB dual array flash; read/program/eraseover full operating voltage and temperature–1984 byte random access memory (RAM)–Security circuitry to prevent unauthorized access toRAM and flash contents•Power-Saving Modes–Two low-power stop modes (stop2 and stop3)–Reduced-power wait mode–Peripheral clock gating register can disable clocks tounused modules, thereby reducing currents–Low power on-chip crystal oscillator (XOSC) that canbe used in low-power modes to provide accurate clocksource to real time counter and LCD controller–100 μs typical wakeup time from stop3 mode•Clock Source Options–Oscillator (XOSC) — Loop-control Pierce oscillator;crystal or ceramic resonator range of 31.25 kHz to38.4kHz or 1 MHz to 16 MHz–Internal Clock Source (ICS) — Internal clock sourcemodule containing a frequency-locked-loop (FLL)controlled by internal or external reference; precisiontrimming of internal reference allows 0.2% resolutionand 2% deviation over temperature and voltage; supportsbus frequencies from 1 MHz to 20 MHz.•System Protection–COP reset with option to run from dedicated 1 kHzinternal clock or bus clock–Low-voltage warning with interrupt–Low-voltage detection with reset–Illegal opcode detection with reset–Illegal address detection with reset–Flash and RAM protection•Development Support–Single-wire background debug interface–Breakpoint capability to allow single breakpoint settingduring in-circuit debugging (plus two more breakpoints in on-chip debug module)–On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes; eight deep FIFO for storing change-of-flow addresses and event-only data; debug module supports both tag and force breakpoints •Peripherals –LCD — Up to 4 × 41 or 8 × 37 LCD driver with internal charge pump.–ADC — Up to 16-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; temperature sensor; internal bandgap reference channel; runs in stop3 and can wake up the system; fully functional from 5.5 V to 2.7 V –SCI — Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge –SPI — Full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting –IIC — With up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing –TPMx — One 6 channel and one 2 channel; selectable input capture, output compare, or buffered edge or center-aligned PWM on each channel –MTIM — 8-bit counter with match register; four clock sources with prescaler dividers; can be used for periodic wakeup –RTC — 8-bit modulus counter with binary or decimal based prescaler; three clock sources including one external source; can be used for time base, calendar, or task scheduling functions –KBI — One keyboard control module capable of supporting 8 × 8 keyboard matrix –IRQ — External pin for wakeup from low-power modes •Input/Output –39, 53, or 69 GPIOs –8 KBI and 1 IRQ interrupt with selectable polarity –Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins.•Package Options–48-pin LQFP, 64-pin LQFP, and 80-pin LQFP MC9S08LG32 SeriesCovers: MC9S08LG32 and MC9S08LG16Table of Contents1Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .102.1Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102.2Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . .102.3Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .102.4Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .112.5ESD Protection and Latch-Up Immunity. . . . . . . . . . . .122.6DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.7Supply Current Characteristics. . . . . . . . . . . . . . . . . . .172.8External Oscillator (XOSC) Characteristics . . . . . . . . .222.9Internal Clock Source (ICS) Characteristics. . . . . . . . .242.10ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .252.11AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .292.11.1Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . .292.11.2TPM Module Timing . . . . . . . . . . . . . . . . . . . . .302.11.3SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .312.12LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .342.13Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .342.14EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .352.14.1Radiated Emissions. . . . . . . . . . . . . . . . . . . . . .352.14.2Conducted Transient Susceptibility . . . . . . . . . .35 3Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383.1Device Numbering System. . . . . . . . . . . . . . . . . . . . . .39 4Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394.1Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .394.1.180-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .404.1.264-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .434.1.348-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 List of FiguresFigure1.MC9S08LG32 Series Block Diagram . . . . . . . . . . . . . . 3 Figure2.80-Pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure3.64-Pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure4.48-Pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure5.T ypical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure6.T ypical Low-side D rive (sink) characteristics – Low D rive (PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure7.T ypical High-side D rive (source) characteristics – High Drive (PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure8.T ypical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure9.T ypical Run I DD for FBE Mode at 1 MHz. . . . . . . . . . . 19 Figure10.T ypical Run I DD for FBE Mode at 20 MHz. . . . . . . . . 20 Figure11.T ypical Run I DD for FEE Mode at 1 MHz. . . . . . . . . . 20 Figure12.T ypical Run I DD for FEE Mode at 20 MHz. . . . . . . . . 21 Figure13.T ypical Stop2 I DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure14.T ypical Stop3 I DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure15.T ypical Crystal or Resonator Circuit: High Range and Low Range/High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure16.T ypical Crystal or Resonator Circuit: Low Range/Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure17.Internal Oscillator Deviation from Trimmed Frequency 25 Figure18.ADC Input Impedance Equivalency Diagram. . . . . . . 26 Figure19.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure20.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure21.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure22.Timer Input Capture Pulse. . . . . . . . . . . . . . . . . . . . . 30 Figure23.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 32 Figure24.SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . 32 Figure25.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 33 Figure26.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 33 Figure27.4MHz, Positive Polarity Pins 1 – 41 . . . . . . . . . . . . . 36 Figure28.4MHz, Positive Polarity Pins 42 – 80 . . . . . . . . . . . . 36 Figure29.4MHz, Negative Polarity Pins 1 – 41. . . . . . . . . . . . . 37 Figure30.4MHz, Negative Polarity Pins 42 – 80. . . . . . . . . . . . 37 Figure31.Device Number Example for Auto Parts. . . . . . . . . . . 39 Figure32.Device Number Example for IMM Parts. . . . . . . . . . . 39 Figure33.80-pin LQFP Package D rawing (Case 917A, D oc #98ASS23237W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure34.64-pin LQFP Package D rawing (Case 840F, D oc #98ASS23234W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure35.48-pin LQFP Package rawing (Case 932, oc #98ASH00962A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 List of TablesT able1.MC9S08LG32 Series Features by MCU and Package . 4 T able2.Pin Availability by Package Pin-Count. . . . . . . . . . . . . . 8 T able3.Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 10 T able4.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 11 T able5.Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 11 T able6.ESD and Latch-Up Test Conditions. . . . . . . . . . . . . . . 12 T able7.ESD and Latch-Up Protection Characteristics. . . . . . . 13 T able8.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 T able9. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 17 T able10.Oscillator Electrical Specifications (Temperature Range =–40 °C to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . 22 T able11.ICS Frequency Specifications (Temperature Range =–40°C to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . 24 T able12.12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 25 T able13.12-bit AD C Characteristics (V REFH = V DDAD, V REFL= V SSAD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 T able14.Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 T able15.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 T able16.SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 T able17.LCD Electricals, 3 V Glass . . . . . . . . . . . . . . . . . . . . . 34 T able18.Flash Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 34 T able19.Radiated Emissions, Electric Field . . . . . . . . . . . . . . . 35 T able20.Conducted Susceptibility, EFT/B. . . . . . . . . . . . . . . . . 35 T able21.Susceptibility Performance Classification . . . . . . . . . . 38 T able22.Device Numbering System . . . . . . . . . . . . . . . . . . . . . 38 T able23.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 39 T able24.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Figure 1. MC9S08LG32 Series Block Diagram8-BIT KEYBOARD INTERRUPT (KBI )IIC MODULE (IIC )SERIAL PERIPHERAL INTERFACE (SPI )USER FLASH B USER RAM ON-CHIP ICE (ICE ) and DEBUG MODULE (DBG )(LG32 = 16K BYTES)HCS08 CORE CPUBKGD INTBKP2-CHANNEL TIMER/PWM(TPM1)HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERA TION POWER MANAGEMENTIRQLVDLOW-POWER OSCILLA TORINTERNAL CLOCK Source (ICS )SERIAL COMMUNICA TIONS6-CHANNEL TIMER/PWM(TPM2)V LL3(LCD)V LL1V LL2V CAP1V CAP2LCD[44:0]V SS V DD VOLTAGE REGULATORUSER FLASH A (LG16 = 2K BYTES)LCD28/ADC5/TPMCLK /PTA7LCD27/ADC4/TPM2CH1/KBI7/PTA6LCD25/ADC2/RX2/KBI5/PTA4INTERFACE (SCI1)TxD1RxD1SSSPSCK SCLSDA MOSIMISO V SSA /V REFLV DDA /V REFH XT ALEXTALIRQKBI[7:0]P O R T ARESET LIQUID CRYST AL DISPLAY DRIVERANALOG-TO-DIGITAL CONVERTER (ADC )12-BITAD[15:0]TPM2CH[5:0]TPMCLK TPMCLKLCD24/ADC1/TX2/KBI4/PTA3LCD23/ADC0/SDA/PTA2LCD22/SCL/PTA1LCD21/PTA0(LG32 = 16K BYTES)(LG16 = 16K BYTES)LCD26/ADC3/TPM2CH0/KBI6/PTA5BKGD/MSTPM1CH[1:0]COPReal Time Counter(RTC )TMRCLKSERIAL COMMUNICA TIONSINTERFACE (SCI2)TxD2RxD2P O R T CEXTAL/PTF7XT AL/PTF6TPM2CH4/KBI1/MISO /PTF4P O R T FTPM2CH5/KBI0/SS/PTF3ADC14/IRQ/TPM1CH1/SPSCK/PTF2ADC13/TPM1CH0/RX1/PTF1ADC12/TPM2CH2/KBI3/TX1/PTF0TPM2CH3/KBI2/MOSI/PTF5SPSCK/SDA/TPM2CH1/PTI4P O R T IMOSI/TPM2CH2/PTI3MISO/TPM2CH3/PTI2TX2/TMRCLK/PTI1RX2/PTI0SS/SCL/TPM2CH0/PTI5P O R T D P O R T ELCD[40:37]/PTB[7:4]LCD[32:29]/PTB[3:0]LCD[7:0]/PTD[7:0]P O R T B LCD[15:8]/PTE[7:0]LCD[44:41]/PTG[7:4]LCD[36:33]/PTG[3:0]P O R T GADC11/TPM1CH0/KBI3/TX1/PTH5ADC10/TPM1CH1/KBI2/RX1/PTH4ADC[9:6]/KBI[7:4]/PTH[3:0]TPM2CH4/KBI1/PTH7ADC15/KBI0/TPM2CH5/PTH6P O R T H V SS2V LL3_2Available only on 80-pin packageAvailable only on 64-pin and 80-pin package */Default function out of reset /*BKGD/MS /PTC5RESET /PTC6Modulo Timer (MTIM )1984 BYTESLCD[20:16]/PTC[4:0]Pin Assignments1Pin AssignmentsThis section shows the pin assignments for the MC9S08LG32 series devices. The priority of functions on a pin is in ascending order from left to right and bottom to top. Another view of pinouts and function priority is given in Table 2.Table 1. MC9S08LG32 Series Features by MCU and PackageFeatureMC9S08LG32MC9S08LG16Flash size (bytes)32,76818,432RAM size (bytes)1984Pin quantity 8064486448ADC 16 ch 12 ch 9 ch 12 ch 9 ch LCD 8 x 374 x 418 x 294 x 338 x 214 x 258 x 294 x 338 x 214 x 25ICE + DBG yes ICS yes IIC yes IRQ yes KBI 8 pin GPIOs 6953395339RTC yes MTIM yes SCI1yes SCI2yes SPIyes TPM1 channels 2TPM2 channels 6XOSCyesPin AssignmentsFigure 2. 80-Pin LQFPNOTEV REFH /V REFL are internally connected to V DDA /V SSA .1234567891011121314151617181920212223242526272829303132333435363738394080-Pin LQFPP T E 0/L C D 8P T E 1/L C D 9P T E 2/L C D 10P T E 3/L C D 11P T E 4/L C D 12P T E 5/L C D 13P T G 0/L C D 33P T G 1/L C D 34P T G 4/L C D 41P T G 5/L C D 42P T G 6/L C D 43P T G 7/L C D 44V L L 3_2V S S 2P T E 6/L C D 14P T E 7/L C D 15P T C 0/L C D 16P T C 1/L C D 17P T C 2/L C D 18P T C 3/L C D 19PTD7/LCD7PTD6/LCD6PTD5/LCD5PTD4/LCD4PTD3/LCD3PTD2/LCD2PTB3/LCD32PTB2/LCD31PTB7/LCD40PTB6/LCD39PTB5/LCD38PTB4/LCD37PTB1/LCD30PTB0/LCD29PTD1/LCD1PTD0/LCD0V CAP1V CAP2V LL1V LL2V L L 3P T F 5/M O S I /K B I 2/T P M 2C H 3P T F 4/M I S O /K B I 1/T P M 2C H 4P T I 5/T P M 2C H 0/S C L /S S P T I 4/T P M 2C H 1/S D A /S P S C K P T I 3/T P M 2C H 2/M O S I P T I 2/T P M 2C H 3/M I S O P T I 1/T M R C L K /T X 2P T I 0/R X 2P T H 7/K B I 1/T P M 2C H 4V S SV D DP T F 7/E X T A L P T F 6/X T A L V D D A /V R E F HV S S A /V R E F LP T H 6/T P M 2C H 5/K B I 0/A D C 15P T F 2/S P S C K /T P M 1C H 1/I R Q /A D C 14P T F 1/R X 1/T P M 1C H 0/A D C 13P T F 0/T X 1/K B I 3/T P M 2C H 2/A D C 126059585756555453525150494847464544434241PTC4/LCD20PT A0/LCD21PTG2/LCD35PTG3/LCD36PT A1/SCL/LCD22PT A2/SDA/ADC0/LCD23PT A3/KBI4/TX2/ADC1/LCD24PT A4/KBI5/RX2/ADC2/LCD25PT A5/KBI6/TPM2CH0/ADC3/LCD26PT A6/KBI7/TPM2CH1/ADC4/LCD27PT A7/TPMCLK/ADC5/LCD28PTC5/BKGD/MS PTH0/KBI4/ADC6PTH1/KBI5/ADC7PTH2KBI6/ADC8PTH3/KBI7/ADC9PTH4/RX1/KBI2/TPM1CH1/ADC10PTH5/TX1/KBI3/TPM1CH0/ADC118079787776757473727170696867666564636261Pin AssignmentsFigure 3. 64-Pin LQFPNOTEV REFH /V REFL are internally connected to V DDA /V SSA .123456789101112131415161718192021222324252627282930313264-Pin LQFPP T E 0/L C D 8P T E 1/L C D 9P T E 2/L C D 10P T E 3/L C D 11P T E 4/L C D 12P T E 5/L C D 13P T G 0/L C D 33P T G 1/L C D 34V L L 3_2V S S 2P T E 6/L C D 14P T E 7/L C D 15P T C 0/L C D 16P T C 1/L C D 17P T C 2/L C D 18P T C 3/L C D 19PTD7/LCD7PTD6/LCD6PTD5/LCD5PTD4/LCD4PTD3/LCD3PTD2/LCD2PTB3/LCD32PTB2/LCD31PTB1/LCD30PTB0/LCD29PTD1/LCD1PTD0/LCD0V CAP1V CAP2V LL1V LL2V L L 3P T F 5/M O S I /K B I 2/T P M 2C H 3P T F 4/M I S O /K B I 1/T P M 2C H 4P T I 5/T P M 2C H 0/S C L /S S P T I 4/T P M 2C H 1/S D A /S P S C K P T H 7/K B I 1/T P M 2C H 4V S SV D DP T F 7/E X T A L P T F 6/X T A L V D D A /V R E F HV S S A /V R E F LP T H 6/T P M 2C H 5/K B I 0/A D C 15P T F 2/S P S C K /T P M 1C H 1/I R Q /A D C 14P T F 1/R X 1/T P M 1C H 0/A D C 13P T F 0/T X 1/K B I 3/T P M 2C H 2/A D C 124847464544434241403938373635343364636261605958575655545352515049PTC4/LCD20PT A0/LCD21PTG2/LCD35PTG3/LCD36PT A1/SCL/LCD22PT A2/SDA/ADC0/LCD23PT A3/KBI4/TX2/ADC1/LCD24PT A4/KBI5/RX2/ADC2/LCD25PT A5/KBI6/TPM2CH0/ADC3/LCD26PT A6/KBI7/TPM2CH1/ADC4/LCD27PT A7/TPMCLK/ADC5/LCD28PTC5/BKGD/MS PTC6/RESETPTH4/RX1/KBI2/TPM1CH1/ADC10PTH5/TX1/KBI3/TPM1CH0/ADC11PTF3/SS/KBI0/TPM2CH5Pin AssignmentsFigure 4. 48-Pin LQFPNOTEV REFH /V REFL are internally connected to V DDA /V SSA .PTD0/LCD012345678PTD3/LCD3V D D A /V R E F HP T F 6/X T A LV D DV S S P T F 4/M I S O /K B I 1/T P M 2C H 4P T F 5/M O S I /K B I 2/T P M 2C H 3PT A7/TPMCLK/ADC5/LCD28PTC6/RESETP T C 2/L C D 18P T E 7/L C D 15P T C 0/L C D 16P T C 1/L C D 173130292827261415171819373839132425364891011V CAP112V LL2V S S A /V R E F L20P T F 2/S P S C K S /T P M 1C H 1/I R Q /A D C 1421P T F 1/R X 1/T P M 1C H 0/A D C 132223PTC5/BKGD/MS P T E 6/L C D 1440P T E 5/L C D 1341P T E 4/L C D 1242P T E 3/L C D 1143PTD2/LCD2V CAP2V LL132333435P T E 1/L C D 9474645P T E 2/L C D 1044PTD5/LCD5PTD4/LCD4V L L 3PTF3/SS/KBI0/TPM2CH5P T C 3/L C D 1948-Pin LQFPPTD1/LCD1PTD7/LCD7PTD6/LCD6PT A1/SCL/LCD22PT A2/SDA/ADC0/LCD23PT A3/KBI4/TX2/ADC1/LCD24PT A4/KBI5/RX2/ADC2/LCD25PT A6/KBI7/TPM2CH1/ADC4/LCD27PT A5/KBI6/TPM2CH0/ADC3/LCD26PTC4/LCD20PTA0/LCD21P T E 0/L C D 8P T F 0/T X 1/K B I 3/T P M 2C H 2/A D C 1216P T F 7/E X T A LPin AssignmentsTable2. Pin Availability by Package Pin-CountPackages<-- Lowest Priority --> Highest 806448Port Pin Alt 1Alt 2Alt 3Alt 4 111PTD7LCD7———222PTD6LCD6———333PTD5LCD5———444PTD4LCD4———555PTD3LCD3———666PTD2LCD2———77—PTB3LCD32———88—PTB2LCD31———9——PTB7LCD40———10——PTB6LCD39———11——PTB5LCD38———12——PTB4LCD37———139—PTB1LCD30———1410—PTB0LCD29———15117PTD1LCD1———16128PTD0LCD0———17139V CAP1————181410V CAP2————191511V LL1————201612V LL2————211713V LL3————221814PTF5MOSI KBI2TPM2CH3—231915PTF4MISO KBI1TPM2CH4—2420—PTI5TPM2CH0SCL SS—2521—PTI4TPM2CH1SDA SPSCK—26——PTI3TPM2CH2MOSI——27——PTI2TPM2CH3MISO——28——PTI1TMRCLK TX2——29——PTI0RX2———3022—PTH7KBI1TPM2CH4——312316V SS————322417V DD————332518PTF7EXT AL———342619PTF6XT AL———352720V DDA V REFH———362821V SSA V REFL———3729—PTH6TPM2CH5KBI0ADC15—383022PTF2SPSCK TPM1CH1IRQ ADC14Pin Assignments Table2. Pin Availability by Package Pin-Count (continued)Packages<-- Lowest Priority --> Highest806448Port Pin Alt 1Alt 2Alt 3Alt 4 393123PTF1RX1TPM1CH0ADC13—403224PTF0TX1KBI3TPM2CH2ADC12 413325PTF3SS KBI0TPM2CH5—4234—PTH5TX1KBI3TPM1CH0ADC11 4335—PTH4RX1KBI2TPM1CH1ADC10 44——PTH3KBI7ADC9——45——PTH2KBI6ADC8——46——PTH1KBI5ADC7——47——PTH0KBI4ADC6——483626PTC6RESET———493727PTC5BKGD/MS———503828PT A7TPMCLK ADC5LCD28—513929PT A6KBI7TPM2CH1ADC4LCD27 524030PT A5KBI6TPM2CH0ADC3LCD26 534131PT A4KBI5RX2ADC2LCD25 544232PT A3KBI4TX2ADC1LCD24 554333PT A2SDA ADC0LCD23—564434PT A1SCL LCD22——5745—PTG3LCD36———5846—PTG2LCD35———594735PT A0LCD21———604836PTC4LCD20———614937PTC3LCD19———625038PTC2LCD18———635139PTC1LCD17———645240PTC0LCD16———655341PTE7LCD15———665442PTE6LCD14———6755—V SS2————6856—V LL3_2————69——PTG7LCD44———70——PTG6LCD43———71——PTG5LCD42———72——PTG4LCD41———7357—PTG1LCD34———7458—PTG0LCD33———755943PTE5LCD13———766044PTE4LCD12———Electrical Characteristics2Electrical Characteristics2.1IntroductionThis section contains electrical and timing specifications for the MC9S08LG32 series of microcontrollers available at the time of publication.2.2Parameter ClassificationThe electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a betterunderstanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:NOTEThe classification is shown in the column labeled “C” in the parameter tables where appropriate.2.3Absolute Maximum RatingsAbsolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section.This device contains circuitry that protects against damage due to high static voltage or electrical fields. However, it is advised that normal precautions should be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V SS or V DD ) or the programmable pull-up resistor associated with the pin is enabled.776145PTE3LCD11———786246PTE2LCD10———796347PTE1LCD9———806448PTE0LCD8———Table 3. Parameter ClassificationsP Those parameters are guaranteed during production testing on each individual device.CThose parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category.DThose parameters are derived mainly from simulations.Table 2. Pin Availability by Package Pin-Count (continued)Packages<-- Lowest Priority --> Highest806448Port Pin Alt 1Alt 2Alt 3Alt 4Electrical Characteristics2.4Thermal CharacteristicsThis section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take P I/O into account in power calculations, determine the difference between actual pin voltage and V SS or V DD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and V SS or V DD will be very small.The average chip-junction temperature (T J ) in °C can be obtained from:T J = T A + (P D × θJA )Eqn.1Table 4. Absolute Maximum RatingsRatingSymbol Value Unit Supply voltageV DD –0.3 to +5.8V Maximum current into V DD I DD 120mA Digital input voltageV In –0.3 to V DD +0.3V Instantaneous maximum currentSingle pin limit (applies to all port pins)1,2,31Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V DD ) and negative (V SS ) clamp voltages and use the largest of the two resistance values.2All functional non-supply pins are internally clamped to V SS and V DD .3Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (V In > V DD ) is greater than I DD , the injection current may flow out of V DD and could result in an external power supply going out of regulation. Ensure that the external V DD load will shunt current greater than maximum injection current, this will be of greater risk when the MCU is not consuming power. For instance, If no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).I D ±25±2mA Storage temperature rangeT stg–55 to 150°CTable 5. Thermal CharacteristicsRatingSymbol Value Unit Operating temperature range (packaged)T A T L to T H –40 to +105°C Maximum junction temperature T J125°CThermal resistance Single-layer board 80-pin LQFP 64-pin LQFP 48-pin LQFP θJA617180°C/WThermal resistance Four-layer board80-pin LQFP 64-pin LQFP 48-pin LQFPθJA485256°C/WElectrical Characteristicswhere:T A = Ambient temperature, °CθJA = Package thermal resistance, junction-to-ambient, °C/WP D = P int + P I/OP int = I DD× V DD, Watts — chip internal powerP I/O = Power dissipation on input and output pins — user determinedFor most applications, P I/O<< P int and can be neglected. An approximate relationship between P D and T J (if P I/O is neglected) is:P D = K ÷ (T J + 273 °C)Eqn.2 Solving Equation1 and Equation2 for K gives:K = P D× (T A + 273 °C) + θJA× (P D)2Eqn.3 where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P D (at equilibrium) for a known T A. Using this value of K, the values of P D and T J can be obtained by solving Equation1 and Equation2 iteratively for any value of T A.2.5ESD Protection and Latch-Up ImmunityAlthough damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for automotive grade integrated circuits. During the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM).A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification.Table6. ESD and Latch-Up Test ConditionsModel Description Symbol Value UnitHuman BodyModel Series resistance R11500ΩStorage capacitance C100pF Number of pulses per pin—3—Latch-up Minimum input voltage limit—–2.5V Maximum input voltage limit—7.5VElectrical Characteristics2.6DC CharacteristicsThis section includes information about power supply requirements and I/O pin characteristics.Table 7. ESD and Latch-Up Protection CharacteristicsNo.Rating 11Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted.Symbol Min Max Unit 1Human body model (HBM)V HBM 2500—V 2Charge device model (CDM)V CDM 750—V 3Latch-up current at T A = 85 °CI LAT±100—mATable 8. DC CharacteristicsNum C Characteristic Symbol Min Typ 1Max Unit 1—Operating Voltage— 2.7— 5.5V 2P Output high voltage — Low Drive (PTxDSn = 0)5 V , I Load = –2 mA 3 V , I Load = –0.6 mAV OHV DD – 0.8V DD – 0.8————VOutput high voltage — High Drive (PTxDSn = 1) V5 V , I Load = –10 mA 3 V , I Load = –3 mAV DD – 0.8V DD – 0.8————3P Output low voltage — Low Drive (PTxDSn = 0)5 V , I Load = 2 mA 3 V , I Load = 0.6 mAV OL———0.80.8VOutput low voltage — High Drive (PTxDSn = 1)5 V , I Load = 10 mA 3 V , I Load = 3 mA——0.80.84P Output high current — Max total I OH for all ports5 V 3 V I OHT——10060mA5C Output high current — Max total I OL for all ports 5 V 3 VI OLT——10060mA6P Bandgap voltage reference V BG — 1.225—V 7P Input high voltage; all digital inputs V IH 0.65 x V DD——V 8P Input low voltage; all digital inputs V IL ——0.35 x V DDV 9P Input hysteresis; all digital inputs V hys 0.06 x V DD——mV 10P Input leakage current; input only pins 2V In = V DD or V SS|I In |—0.11μA 11P High impedence (off-state) leakage currentV In = V DD or V SS|I OZ |—0.11μA 12P Internal pullup resistors 3R PU 204565k Ω13P Internal pulldown resistors 4R PD204565k Ω。