substrate design trainning

PCB的名词解释Printed Circuit Board (PCB)，即印刷电路板，是电子设备中的一种重要组成部分。

它采用了印刷技术，将电子元件和导线布局在一个绝缘基板上，提供了电子元件间的连接和支撑。

作为电子产品中的“大脑”，PCB在现代科技发展中起到了不可或缺的作用。

本文将对PCB中的一些关键名词进行解释和讨论。

1. 基板 (Substrate)基板是PCB的主要构成部分，它通常由绝缘材料制成，如玻璃纤维增强环氧树脂（FR-4）。

基板起到支撑电子元件和导线的作用，并且具有良好的电气绝缘性能，以防止元件之间的短路。

2. 导线 (Conductor)导线是PCB上用来传导电流的金属线路，一般采用铜箔制成。

导线的设计和布局直接影响电子设备的性能和稳定性。

通常使用导线间的间距、宽度和线路层数等参数来决定导线的电流承载能力和信号传输性能。

3. 元件 (Component)PCB上的元件是电子设备中的各种电子部件，如集成电路、电容器、电阻器等。

元件通过焊接或插座连接到PCB上，与导线相互连接，形成电路。

元件的选择和布局是PCB设计工程师的关键任务，它不仅影响电路的性能，还直接影响到产品的生产成本和空间利用率。

4. 焊接 (Soldering)焊接是将元件连接到PCB上的重要工艺过程。

通过熔化的焊锡，元件的引脚与PCB上的涂有焊膏的焊盘相连接。

焊接技术包括手工焊接和表面贴装技术（SMT）。

它们有助于保持元件在设备中的稳定性和可靠性。

5. 系统集成 (System Integration)系统集成是指将多个PCB组装在一起，通过元件之间的连接和互联，构成复杂的电子系统。

系统集成是现代电子设备制造的重要环节，它不仅要求PCB间的准确布局和可靠连接，还需要满足信号传输的要求和整体性能的优化。

6. PCB设计 (PCB Design)PCB设计是制定PCB布局、连线和元件安装的过程。

在PCB设计中，设计工程师需要根据电路原理图、电气要求和尺寸限制，合理布局元件和导线。

pcb生产流程培训英文版Here is the English essay on the topic of "PCB production process training" with a word count of over 1000 words:The production of printed circuit boards (PCBs) is a crucial process in the electronics industry, as these components serve as the backbone for a wide range of electronic devices, from smartphones to industrial equipment. Ensuring the proper training and understanding of the PCB production process is essential for maintaining high standards of quality and efficiency. In this essay, we will delve into the various stages of the PCB production process, providing a comprehensive overview for trainees and professionals alike.The first step in the PCB production process is the design phase. This involves the creation of a digital schematic or layout, which outlines the placement and interconnections of the various components that will be mounted on the board. The design phase requires a thorough understanding of electrical engineering principles, as well as the specific requirements and constraints of the intended application. Designers must consider factors such as component size, heat dissipation, and signal routing to ensure the PCB will function asintended.Once the design is complete, the next step is the fabrication of the PCB itself. This process begins with the creation of the base material, which is typically a thin, rigid substrate made of fiberglass or other insulating materials. The substrate is then coated with a thin layer of copper, which will serve as the conductive pathways for the electronic components. The copper layer is then etched away, leaving behind the desired circuit patterns.After the basic PCB structure has been created, the next step is the drilling process. This involves the use of specialized machinery to create the necessary holes and vias that will allow the components to be mounted and interconnected. The drilling process must be carried out with a high degree of precision, as the placement and size of these holes can have a significant impact on the overall performance and reliability of the PCB.Following the drilling process, the PCB undergoes a series of cleaning and preparation steps to ensure that the surface is ready for the next stage of production. This may include the application of a solder mask, which is a protective coating that helps to prevent short circuits and corrosion, as well as the application of a surface finish, such as gold or tin, to improve the solderability of the board.Once the PCB has been prepared, the next step is the component placement and soldering process. This involves the use of specialized equipment, such as pick-and-place machines, to accurately position the various electronic components on the board. The components are then secured in place using a process called soldering, which involves the melting of a metal alloy to create a strong, conductive bond between the component and the PCB.After the component placement and soldering process, the PCB undergoes a series of quality control checks to ensure that it meets the required standards for performance and reliability. This may include visual inspections, electrical testing, and even more advanced techniques such as automated optical inspection (AOI) and X-ray analysis.Finally, the completed PCB is packaged and prepared for shipment to the end customer. This may involve the addition of protective coatings, the installation of connectors or other hardware, and the labeling and documentation of the PCB.Throughout the entire PCB production process, it is essential that workers and trainees receive comprehensive training on the various techniques and equipment involved. This training should cover not only the practical aspects of the production process, but also the underlying principles and best practices that guide the industry. Byensuring that all personnel involved in the PCB production process are well-trained and knowledgeable, companies can ensure that their products meet the highest standards of quality and reliability.In conclusion, the PCB production process is a complex and multifaceted endeavor that requires a deep understanding of electrical engineering, materials science, and manufacturing techniques. By providing comprehensive training to all personnel involved in the process, companies can ensure that their PCBs are produced to the highest possible standards, helping to drive innovation and advancement in the electronics industry.。

cob陶瓷基板焊接时间English.Ceramic-on-Board (COB) Substrate Soldering Duration.Factors Affecting COB Substrate Soldering Duration.The duration of COB substrate soldering is influenced by several key factors:Substrate Material: The thermal conductivity and heat capacity of the substrate material significantly impact the soldering time. Ceramics with higher thermal conductivity, such as alumina (Al2O3), allow for faster heat transfer and shorter soldering times compared to materials with lower thermal conductivity, such as zirconia (ZrO2).Substrate Thickness: Thicker substrates require longer soldering times to ensure proper heating and solder flow throughout the substrate.Soldering Method: Different soldering methods, such as reflow soldering, wave soldering, and laser soldering, have varying heating profiles and soldering times. Reflow soldering typically involves longer soldering times than other methods to ensure uniform heating and solder reflow across the substrate.Solder Paste Composition: The composition of the solder paste, including the type of solder alloy and flux content, can affect the soldering time. Solder alloys with lower melting temperatures, such as SAC305 (Sn-3Ag-0.5Cu), require shorter soldering times compared to alloys with higher melting temperatures.Component Size and Density: The size and density of components mounted on the COB substrate influence the soldering time. Larger components with higher power dissipation require longer soldering times to ensure adequate heat transfer and solder wetting.Substrate Design: The layout of components and traceson the COB substrate can affect the soldering time. Substrates with complex designs and dense component placement may require longer soldering times to ensure proper heating and solder flow.Soldering Equipment: The performance and capabilities of the soldering equipment, such as the solder paste printer, reflow oven, or laser soldering system, can impact the soldering time.Typical Soldering Duration Ranges.The typical soldering duration ranges for COB substrates vary depending on the specific factors mentioned above. However, as a general guide, the following ranges can be considered:Reflow Soldering: 60-120 seconds.Wave Soldering: 5-15 seconds.Laser Soldering: 1-5 seconds.It is important to note that these ranges are approximate and may vary depending on the specific application and requirements.Optimization of COB Substrate Soldering Duration.Optimizing the soldering duration for COB substrates involves understanding the factors that influence the soldering time and making adjustments to achieve the desired results. This includes:Selecting the appropriate substrate material and thickness for the specific application.Using the appropriate soldering method based on the component size and density.Choosing a solder paste composition that provides the required melting temperature and fluxing action.Optimizing the component layout and substrate designfor efficient heat transfer and solder flow.Calibrating the soldering equipment to ensure proper heating profiles and temperature control.By optimizing the soldering duration, manufacturers can achieve high-quality and reliable COB substrates with strong solder joints and minimal thermal stress.中文回答：陶瓷基板焊接时间。

丝网印刷工艺流程详解英文回答：Silk screen printing, also known as screen printing, is a popular printing technique that involves using a mesh screen to transfer ink onto a substrate. It is widely usedin various industries, including textiles, electronics, advertising, and packaging. In this process, a stencil is created on the screen, which allows ink to pass throughonly in the desired areas.The silk screen printing process typically involves the following steps:1. Design Preparation: The first step is to prepare the design that will be printed. This can be done digitally using graphic design software or by hand-drawing the design. The design should be converted into a high-resolution image and separated into different colors if necessary.2. Screen Preparation: A mesh screen is prepared by stretching a fine fabric, such as silk or polyester, over a frame. The screen is then coated with a light-sensitive emulsion or film, which is then dried and exposed to ultraviolet light. The areas that are exposed to light harden, while the unexposed areas remain soft and can be washed away.3. Stencil Creation: After the screen is prepared, a stencil is created by blocking out the areas where ink should not pass through. This can be done using various methods, such as using a stencil film, applying a blocking agent, or using a photo emulsion technique.4. Ink Preparation: The ink used in screen printing is typically a thick, paste-like substance that is mixed with various additives to achieve the desired color, texture, and opacity. The ink is then loaded onto a squeegee, which is used to push the ink through the screen and onto the substrate.5. Printing: The screen is placed on top of thesubstrate, and ink is applied to the screen. The squeegeeis then used to evenly distribute the ink across the screen, forcing it through the open areas of the stencil and onto the substrate. This process is repeated for each color in the design, with each color requiring a separate screen and stencil.6. Drying and Curing: After the printing is complete, the substrate is typically dried or cured to ensure thatthe ink adheres properly. This can be done using heat, air drying, or UV curing, depending on the type of ink and substrate being used.7. Finishing: Once the ink is dry, the printedsubstrate may undergo additional finishing processes, such as trimming, folding, or heat pressing, depending on the desired final product.中文回答：丝网印刷，也被称为丝印，是一种常用的印刷技术，它使用网孔屏幕将油墨转移到基材上。

模具专业的英语词汇大全一、模具基础词汇1. Mold 模具2. Die 冲模3. Core 核心模4. Cavity 型腔5. Mold Base 模架6. Mold Steel 模具钢7. Runner 流道8. Gate 进浇口9. Ejector Pin 顶针10. Ejector Plate 顶板二、模具设计相关词汇1. Draft Angle 脱模斜度2. Parting Line 分模线3. Radius 圆角4. Undercut 难以脱模的凹槽5. Slide 滑块6. Lifters 顶杆7. Cooling Channel 冷却水道8. Injection Point 注射点9. Shrinkage 收缩率10. Molding Cycle 成型周期三、模具加工与维护词汇1. Machining 加工2. Milling 铣削3. Grinding 磨削4. EDM (Electrical Discharge Machining) 电火花加工5. Wire Cutting 线切割6. Polishing 抛光7. Assembly 装配8. Maintenance 维护9. Repair 修理10. Replacement 更换四、模具材料与热处理词汇1. Tool Steel 工具钢2. Stainless Steel 不锈钢3. Aluminum 铝4. Plastic 塑料5. Rubber 橡胶6. Heat Treatment 热处理7. Hardness 硬度8. Tempering 回火9. Quenching 淬火10. Annealing 退火五、模具行业相关词汇1. Mold Maker 模具师傅2. Mold Designer 模具设计师3. Mold Manufacturer 模具制造商4. Injection Molding 注塑成型5. Blow Molding 吹塑成型6. Compression Molding 压缩成型7. Transfer Molding 传递成型8. Prototype Model 原型模具9. Mass Production 批量生产10. Quality Inspection 质量检验六、模具测试与质量控制词汇1. First Article Inspection 首件检查2. Sample 样品3. Defect 缺陷4. Dimensional Accuracy 尺寸精度5. Tolerance 公差6. Surface Finish 表面光洁度7. Stress Analysis 应力分析8. Flow Analysis 流动分析9. Mold Flow Simulation 模具流动模拟10. Quality Control 质量控制七、模具行业常用设备词汇1. Injection Molding Machine 注塑机2. Extruder 挤出机3. Blow Molding Machine 吹塑机4. CNC Machine 数控机床5. Lathe 车床6. Milling Machine 铣床7. Grinder 磨床8. EDM Machine 电火花机床9. Laser Cutter 激光切割机10. Robot 自动化八、模具生产流程词汇1. Design Drawing 设计图纸2. Mold Construction 模具构建3. Machining Process 加工工艺4. Tooling Setup 模具安装5. Trial Run 试模6. Adjustment 调整7. Production Run 生产运行8. Mold Maintenance 模具保养9. Mold Modification 模具修改10. Mold Recycling 模具回收九、模具行业认证与标准词汇1. ISO Certification ISO认证2. Quality Management System 质量管理体系3. Standard 标准化4. DIN 德国工业标准5. ASTM 美国材料与试验协会6. JIS 日本工业标准7. Certification Body 认证机构8. Audit 审核检查9. Compliance 符合性10. Continuous Improvement 持续改进十、模具行业发展趋势词汇1. Automation 自动化2. Intelligent Manufacturing 智能制造3. 3D Printing 三维打印4. Rapid Prototyping 快速原型5. Industry 4.0 工业4.06. Internet of Things (IoT) 物联网7. Big Data 大数据8. Cloud Computing 云计算9. Sustainable Development 可持续发展10. CrossIndustry Integration 跨行业整合通过这些词汇，我们可以看到模具行业不仅涉及具体的技术和操作，还包括了管理、质量控制、认证以及未来的发展趋势。

ADS PCB 板图仿真学习笔记方法一：1.打开Cadence：Allegro PCB Designer 16.5，载入需要的PCB文件。

1.1File----->Change Editor，在弹出窗口选择Allegro PCB DesignXL(Legacy),选中Analog/RF,点击确定。

1.2Setup----->Cross-section 设置叠层厚度，介电常数等信息。

1.31.3.1RF-PCB----->IFF Interface----->Export，在弹出窗口选择Export Selection，然后点击PCB上需要导出仿真的线段等，点击OK.(也可以选择Export All等其它选项，根据需要选择)。

1.3.2在弹出窗口：RF IFF Export，选择文件存放的路径，然后点击layer map。

1.3.3在出现的窗口选择转换到ADS对应的层（我习惯4层板依次放在PC1~PC4），点击OK。

1.3.4回到RF IFF Export窗口，点击OK，生成文件。

在产生的报告中，Types of viasexported 后给出了过孔输出对应的层。

2打开ADS 20092.1新建一个PCB(可在Option----->Preferences 弹出窗口中选择layout units 设定layout 单位，也可以在layout 界面单机右键，选择Preferences。

另单击右键选择Grid Spaction 可设置栅格大小；选择Measure可用来测量长度)2.2File----->Export 在弹出的Export窗口中，File Type选择IFF;Destination file选择刚才生成的layout.IFF文件（备注：文件夹命名不能有空格等非法字符）。

2.3Momentum----->Substrate----->open 选择刚才生成的xxxx.slm文件，载入叠层设置。

衣服的胶印工艺流程英文回答：Screen Printing Process.Screen printing is a printing technique that uses a woven mesh to transfer ink onto a substrate, such as fabric. The process involves several steps:1. Artwork Preparation: The design is created digitally and then converted into a film positive.2. Screen Preparation: A screen is coated with a light-sensitive emulsion and exposed to the film positive. The exposed areas of the emulsion harden, while the unexposed areas wash away, creating a stencil.3. Ink Application: Ink is applied to the screen and forced through the open areas of the stencil onto the substrate.4. Drying: The printed substrate is heated to cure the ink.Sublimation Printing Process.Sublimation printing is a printing technique that uses heat to transfer dye onto a substrate, such as fabric. The process involves several steps:1. Artwork Preparation: The design is created digitally and then printed onto a special transfer paper.2. Transfer Paper Binding: The transfer paper is bound to the substrate, typically using a heat press.3. Heating: The bound substrate is heated to a high temperature, causing the dye to vaporize and penetrate the fibers of the substrate.4. Cooling: The heated substrate is allowed to cool, fixing the dye in place.Digital Printing Process.Digital printing is a printing technique that uses a computer-controlled printer to apply ink directly onto a substrate, such as fabric. The process involves several steps:1. Artwork Preparation: The design is created digitally and then sent to the printer.2. Printing: The printer applies ink to the substrate in a precise pattern, creating the desired design.3. Drying: The printed substrate is dried to fix the ink in place.Chinese回答：胶印工艺流程。

fcbga基板制作工艺流程英文回答：FCBGA Substrate Fabrication Process Flow.The fabrication process of FCBGA substrates involves multiple steps to create a reliable and functional substrate for electronic components. The general process flow includes:1. Substrate Preparation: The starting point is a raw substrate made of a material such as ceramic or organic resin. The substrate is cleaned and pre-treated to ensure proper adhesion of subsequent layers.2. Metallization: A thin layer of metal, typically copper or nickel, is deposited on the substrate's surface using methods like electroplating or electroless plating. This layer provides electrical conductivity and serves as a base for further processing.3. Build-Up Layer: A dielectric build-up layer is applied to insulate the metal traces and create the necessary spacing between layers. The build-up layer can be made of materials such as epoxy or photoresist.4. Patterning: The build-up layer is patterned using photolithography to define the electrical traces and solder pads. This step involves exposing the build-up layer to ultraviolet light through a photomask, followed by etching to remove the unwanted areas.5. Via Formation: Vias are created to connect different layers of the substrate. They can be formed by drilling or laser ablation, and then plated with metal to ensure electrical continuity.6. Surface Treatment: To enhance solderability and protect the substrate from oxidation, a surface treatmentis applied. This treatment can involve applying a solder mask, a protective coating, or a combination of both.7. Testing and Inspection: The completed substrate undergoes various tests and inspections to ensure its electrical and mechanical properties meet the design specifications. This includes continuity tests, capacitance measurements, and visual inspections.中文回答：FCBGA基板制作工艺流程。

Chapter7Advanced Substrates:A Materials and Processing PerspectiveBernd AppeltAbstract This chapter reviews materials and processing for fabricating organic substrates including laminate substrates for plastic BGA(PBGA),build-up substrates for flip chip BGA(FCBGA),tape substrate for tape BGA (TBGA),coreless substrate,and some specialty substrates such as substrates for RF modules,high performance substrates with low dielectric constant,and substrate with embedded components(active dies or passives).Future trend of organic substrate development is also covered in this chapter.Keywords Organic substratesÁCopper clad laminate(CCL)ÁAjinomoto Build-up Film(ABF)ÁCoreless,BGA,Blind via(BV)ÁHigh density interconnect(HDI)ÁLow dielectric constant7.1IntroductionSubstrates have become the most expensive element of electronic packages while at the same time limiting package performance.Ceramic,multi layer substrates have always been extremely expensive but did allow for a great deal of design freedom e.g.integration of passives.The only drawbacks were a high dielectric constant and a very low coefficient of thermal expansion(CTE) as compared to printed circuit boards(PCB)but closely matched to the silicon die.Conversely,organic substrates have a CTE which is matched to PCBs but is significantly larger than that of the silicon die.Organic substrates were originally introduced to significantly reduce the cost of packaging by taking advantage of low cost PCB manufacturing technology, materials and scale.While ceramics scaled only from a single unit to few units, organic substrates used the scale of PCBs(e.g.410mmÂ510mm)accommo-dating100to over1,000units.This approach is similar to wafer size scaling, moving from100to300mm.B.Appelt(*)ASE(U.S.)Inc.,3590Peterson Way,Santa Clara,CA95054e-mail:bernd.appelt@243 D.Lu,C.P.Wong(eds.),Materials for Advanced Packaging,DOI10.1007/978-0-387-78219-5_7,ÓSpringer ScienceþBusiness Media,LLC2009244 B.Appelt Today a few major categories of substrates exist:Ceramic substrates*virtually all are multi layer ceramic(MLC)*cavity ceramics e.g.for optical sensors*RF ceramics with integrated passivesOrganic substrates–which can be subdivided further*Laminate substrates–plastic ball grid array(PBGA)*PBGA with1,2,4&6layers of circuitry*high density substrates(HDI)¼build-up substrates for wire bonding *Tape substrates–typically based on polyimide film(TBGA)*Build-up substrates–typically used for Flip Chip die(FCBGA)*Specialty substrates*Embedded Passives Substrates(EPS)&Embedded Die Substrates(EDS) *Buried Passives Substrates(BPS)*Cavity substrates–here the die is located in a recessThese few types of substrates are assembled into a multitude of different types of electronic packages(see Fig.7.1,ASE Group,Inc.).It seems that almost any idea that can be expressed in a power point chart can be converted into a realmotivation.component given enough conviction and commercial Array Fig.7.1Packages based on substrates,lead frames and wafer level packaging11Reprint Courtesy of Advanced Semiconductor Engineering Inc.7Advanced Substrates245 7.1.1A Brief History:From PCBs to SubstratesThe early organic substrates were indeed simple,miniature PCBs and were significantly cheaper than ceramics.They were introduced as OMPAC by Motorola[4].Soon it became necessary to use more dedicated materials and processes to manufacture substrates to meet the rapidly increasing quality and technical requirements:smaller features(lines and spaces) and lighter weight at lower anic substrates were displacing cera-mic substrates for nearly all chip applications with the exception of high reliability,high I/O or high performance applications e.g.CPU/MPUs, ASICs,RF-applications.Today however ceramic substrates are declining in usage even for those applications.The invention of build-up PCBs by Tsukada(originally called Surface Laminar Carrier,SLC,[12])enabled high density packaging of components on PCBs.SLC essentially employs a PCB core on top of which fine line redistribution layers are being built up(hence the name Build Up,BU,technol-ogy).This approach is similar to using redistribution layers on high end multi-layer ceramic carriers(MLCC).This SLC technology was quickly applied to flip chip ASIC die especially when the wire bond die was pad limited or when superior electrical performance due to the short interconnect was required.The real driver for this technology became the CPU for personal computers with its ever increasing hunger for I/O,performance(lower dielectric constant(D k)) and cost reduction.The technology trend of finer lines/spaces had been going on at a steady, evolutionary pace until the consumer and communication market(e.g.MPEG players and cell phones)came into play.The explosive growth of this market was fueled by squeezing more innovations and applications into smaller spaces. These innovations demanded a large number of new components forcing accelerated improvements and inventions in assembly and in substrates. Today,relatively conventional PBGA substrates of a total thickness of 560m m coexist with WFBGA(very thin and fine ball grid array)substrates of 120m m thickness.When the organic substrates market started to boom,many PCB manu-facturers tried to enter the supply chain.They were attracted by the seemingly high price and margin for these many substrates on a single manufacturing panel.Initially substrates were considered simpler versions of the much more complex PCBs which typically contained a much higher layer count with similar line and space width.But there were many challenges in making substrates(see Table7.1).Few succeeded,especially in the US and Europe,for a number of reasons: assembly had moved to Asia and communication among Asian substrate sup-pliers and assemblers was more efficient.Dedicated substrate manufacturing operations were optimized for these special needs and thus were able to meet the quality requirements at the required low cost.7.2Ceramic SubstratesCeramic substrates are relegated to special applications of either high reliability requirements e.g.multi-chip modules in large servers and military applications or RF applications where passive elements like baluns and R,L,C elements need to be incorporated directly.Ceramics also can provide hermetic packages where required.Three dimensional features are also relatively easy to mold into ceramic material.But the total volume of ceramics is rather small in comparison to organic substrates and will therefore be left for others to review.7.3Organic SubstratesToday two types of die assembly techniques are used.The older and mature technique is wire bonding (WB)where the die is back bonded and wires connect from the top (face)of the die to the substrate.The newer technique is flip chip (FC)bonding,where the chip is bonded face down on the substrate and the interconnection is accomplished with a small solder ball or bump.A recent variation of FC bonding is gold stud bonding.WB substrates are arranged and processed in strip form and are singulated only after assembly.Significant cost optimization can be obtained by tuning strip size (e.g.187mm Â40mm)and lay-out within the active area of the panel (e.g.390mm Â490mm)as well as the substrate lay-out within the strip itself (6=units of 27mm Â27mm).Such strip formats are typical for PBGA substrates.Today,assemblers are working on increasing the strip size while reducing the rails on the strips to increase panel utilization and thereby reduce cost of materials and processing.Table 7.1Comparison of manufacturing challenges of substrates and PCBsCharacteristics Substrates onmanufacturing panel PCBs on manufacturing panel #of units per panel100–2,0001–10Circuit densityUniform across panel as per each substrate Many depopulated areas on a PCB per component placement Circuit defect densityimpactHigh High only in substrate location Gold fingers for wirebond chip attachTypically 100–1,000per substrate None Gold ball pads forsolder ball attachUniform density on ball side per substrate Only in substrate location Defect impact on goldsurfaceHigh Moderate Number of circuitlayers2–42–10for ‘low’end 10–20þfor ‘high’end Inspection content High Moderate246 B.Appelt7Advanced Substrates247 The next step in optimizing cost of WB substrates was the development of chip scale packaging(CSP).The original definition was that the size of a chip was of the substrate and was applied mostly to smaller die with I/O below300.In addition to shrinking the substrate,the substrates were brick walled into a matrix (MAPBGA)of three or four blocks.The block size was determined in part by overmold capabilities.The most recent trend here is also to increase and optimize strip size to maximize the number of units per panel.A few more percent of units can be added by reducing the number of mold blocks on the strip with the goal to work with a single mold block also referred to as chocolate bar.FC substrates were shipped in unit format so all panel optimization was primarily left to the substrate supplier.Unit format was chosen for substrate yield reasons as well as assembly process requirements.The latter were based on the ceramic technology which it was displacing.Today,all high end FC sub-strates,FCBGA,for CPU,graphics,chipset,ASICs,etc.applications are shipped in this format.Very few FCBGA substrates are shipped in strip form to take advantage of reduced handling in assembly as is done for PBGA.FCBGA substrates typically have high I/O and fine trace&space which are best served by blind via(BV)technology.This has lead to the use of build-up technology with a special build-up dielectric.The de facto standard is Ajino-moto Build-up Film(ABF),an unreinforced resin from Ajinomoto Fine Techno Co.,Japan,which is optimized for laser drilling and fine trace/space processing.Further,FC substrates have a solderable surface finish with no or low gold content to ensure the reliability of the FC solder joint.In the last few years,small FC die with I/O below300are also assembled on PBGA substrates.The lower I/O density can be accommodated on laminate technology.These FC substrates(FCCSP)are using the same strip format as MAPBGA with a FC compatible surface finish.FCCSP substrates are pre-sently the fastest growing sector in the substrate business.FCCSP technology is still evolving at a rapid pace trying to develop the most cost effective substrate and assembly technology.One of the early introductions of FC on laminate was a SRAM application by IBM on a four-layer(4L)substrate(Laine,2000). Today most applications use high density interconnect(HDI)substrates(see below)i.e.blind via technology although PTH technology is generally more cost effective.HDI type designs are used because of I/O density.HDI is also used in WB substrates but only for very high end/density designs.As indicated above, WBCSP and FCCSP differ mostly in the surface finish.Therefore,this unique requirement of FCCSP will be addressed in the surface finish section.7.3.12L PBGA SubstratesAs mentioned before,PBGA substrates come in a few simple configurations: two layers(2L),four layers(4L)and six layers(6L)of circuitry which are248 B.Appelt interconnected by plated through holes(PTH).Recently blind holes or vias are also used as interconnects to form HDI substrates with2L,1+2+1,2+2+2 and1+4+1layers.The basic building block is a core or copper clad laminate(CCL)which consists of glass fabric,coated with an electrically insulating organic resin sandwiched between two copper foils.Several plies of impregnated fabric, called prepreg(PP),may be used to achieve the desired thickness of the core. The fabric itself may be woven from glass fibers of varying thickness and thread count to provide more options to control the CCL thickness.After the migra-tion to RoHS and‘green’resin systems i.e.resins that contain less than900ppm of Chlorine,Bromine,Antimony and no Phosphorous,there are two major resin systems in use:Mitsubishi Gas&Chemicals‘BT–NX’series and Hitachi Chemicals‘E679-FGB’series.Cu foils come in varying degrees of thickness also designated by weight(ounces of Cu per sq foot).Most common are12m m¼1/3oz and18m m¼1/2oz although37m m¼1oz and75m m¼2oz are available for thermal or power designs.The properties of the most commonly used core materials are listed in Table7.2.The typical,simplified process flow for a2L substrate is shown in Fig.7.2. Every process step listed here actually consists of many sub-processes.For example,the patterning step can be divided into pretreatment,photo resist application,expose,develop,etch,strip and inspection steps which in them-selves are composed of further sub-divisions with many different chemicals and Table7.2Properties of the most common dielectric CCL materialsCompany Hitachi MGCType of CCL MCL-E679FGB HL832NXTg(o C)DMA190220Td(o C)TGA(5%)–310CTE(ppm/o C)x/y a113–1514CTE(ppm/o C)z a123–3330Thermal stress T288(min)–25Thermal conductivity(W/mK)0.71–0.830.44D k1GHz 4.6 4.7Loss tangent1GHz0.0170.013Volume Resistance(MOhm cm) 1.00E+8 5.00E+8Surface Resistance(MOhm) 1.00E+7 5.00E+8Peel Strength(KN/m)1/3oz0.650.75Flex Strength(MPa)450–550450Flex Modulus(GPa)3728Tensile Strength(MPa)200–300280Young’s Modulus(GPa)20–2629Poisson’s Ratio0.20–0.21–Water Absorption(%)0.050.47Flammability UL94-V094-V0Environmental RoHS&green RoHS&greenrinses.All wet chemical process steps are water based to minimize the use of organic solvents and to minimize the impact on the environment.Common CCL thickness used to be 200m m or greater.Now 150m m and 100m m have become popular in order to reduce the thickness of the finished substrate and thereby the final package thickness.Such thickness reductions require ever more careful handling of the cores during processing as well as either upgrading or new process equipment.These thin CCLs are easily torn or bent and creased manually or in the horizontal process equipment.The fragility increases especially in the pattern process when all the spaces have been etched to form the Cu traces and the reinforcement from the Cu foils no longer supports the prepreg (PP).A good reminder of the magnitude of the thickness challenge is the com-parison to a typical human hair which is 100m m thick.The thinnest core material available now is 60m m and 50m m thick of which 60m m is already used in considerable volume to yield a finished substrate of a total thickness of 120m m.The next target is to achieve a finished substrate thickness of 100m m.Table 7.3shows some representative substrate thickness and cross-sections.In order to reduce the thickness further,solder resist thickness has to be reduced and controlled more tightly.Typical solder resist thickness specification averages range between 15and 30m m.The de facto industry standard solder masks are from Taiyo Ink Mfg.Co.,Ltd.,Japan,and are liquid,photo imageable inks which are applied either by screen printing or roller coating.Immediately after applying the ink,the surface will level to be relatively flat.During drying,the ink will begin to develop a conformal topography over the traces and spaces i.e.the total amount of solvent to evaporate in the space between lines is much greater than over traces.Hence,hills and valleys are formed replicating the trace/space pattern.During curing of the solder mask,the topography is typically exacerbated due to cure shrinkage.Both reactive moieties in the solder mask,MaterialsReleaseNiAu Plating Fig.7.2Simplified process flow for 2L substrateTable 7.3Typical substrate thickness for 2L substratesTotal 100130160210260360560Solder mask 15203030303030Cu 15152025252525Core 406060100150250450Cu 15152025252525Solder mask 15203030303030All dimensions in m m.Tolerance on total is þ/À40m m.7Advanced Substrates249250 B.Appelt acrylate for photo reactivity and epoxy for thermal reactivity and chemical resistivity,typically exhibit large amounts of shrinkage during polymerization and cure.The topography can be minimized by several means:a)Careful control of the drying profile prior to exposure.As the solvent evapo-rates,the viscosity increases and retards leveling flow.This viscosity increase can be counter acted by increasing the temperature but of course evaporation rates increase as well.High temperatures can also lead to a skinning effect where the surface evaporation is faster than the bulk diffusion rate of the solvent.The most effective temperature profiles may therefore be step profiles.b)Adding solvents of varying boiling points can help to manage the viscosityprofile very effectively but do require extensive experimentation to deter-mine the best solvent mix and concentration.This is a common practice in impregnation of glass fabric to make prepreg.c)Lamination of PET cover film(polyethylenetherephthalate)under tempera-ture and pressure can provide some degree of leveling.The biggest benefit of the PET film however is an increase in image resolution.The acrylate photo reaction is usually retarded by oxygen which is present even in vacuum exposure systems and leads to a loss of resolution.The PET film minimizes rediffusion of oxygen into the solder mask during exposure and thereby yields much sharper images at higher resolution.d)Dry film solder mask:the most effective and simplest way to minimizetopography and thickness is to use a dry film solder mask.Essentially,it is a solder mask coated and supplied in the same fashion as dry film photo resist.The solder mask is coated onto a PET carrier film which protects the solder mask from contamination,handling and oxygen during exposure,and a PE (polyethylene)separator sheet to allow rolling up of the solder mask.Dry film solder mask does require vacuum lamination(vacuum,pressure,and elevated temperature)to fully encapsulate the traces without entrapping air.It does have another big manufacturing advantage.The cleanliness requirements of coating the material are handled by the material supplier instead of the substrate manufacturer.Dry film solder masks have been available for many years,the first of which where supplied for PCBs by DuPont under the trade name of Vacrel.The materials cost is significantly higher than liquid solder masks and has therefore delayed the implementation.For substrates the Dry Film solder mask standard is again from Taiyo Ink:AUS410.Typical solder masks and properties are listed in Table7.4.7.3.24L PBGA SubstratesThe simplest4L substrate which starts with a CCL which has been patterned is laminated on both sides with PP and Cu foil to yield four layers of Cu.This raw substrate is then essentially processed like a2L substrate(Fig.7.3).A more complex 4L substrate can have buried PTHs (BPTH)to increase wireability.The process flow essentially follows that of a 2L substrate up to solder mask.Then the patterned core with PTHs is laminated and processed like a standard 4L substrate (Fig.7.4).The registration requirements do increase with each level of complexity.Typically the internal lands for PTH connections are increased in size to ensure the PTHs are fully encircled by the land and avoid any hole break out.One way to ensure this improved regis-tration is to use x-ray drills:using x-ray cameras,the internal registration fiducials are located and the new tooling holes for subsequent PTH drilling are placed accordingly.Table 7.4Properties of typical Taiyo Ink PSR 4000solder mask materialsProperty AUS308AUS310AUS320AUS 410Test method Young’s modulus (GPa)2.43.0 3.4 3.2Tensile Elongation (%)3.0 3.5 3.54.9Tensile Tensile strength (MPa)50707075Tensile T g (o C)100103114110TMA CTE (ppm/o C)60/13060/14060/13050/160TMA Water absorption (%)1.3 1.1 1.1 1.0208C/24hPoisson’s ratio0.290.280.290.32Dk3.9 3.6 3.9 3.6Df 0.0290.0240.0300.022Fig.7.3Process flow for 4L PBGAsubstratesFig.7.4Process flow for 4L substrate with buried via hole7Advanced Substrates 2517.3.36L PBGA Substrates6L substrates are in moderate use only,the main reason being cost.Essentially the cost increases by approximately 50%for every layer pair added onto a 2L substrate when all other parameters remain the same.Again the simplest 6L substrate has only PTHs for interconnects and can be built either sequentially (as shown in Fig.7.5)or in parallel (as shown in Fig.7.6):Sequential processing starts with a patterned 2L core on to which prepreg and Cu is laminated to form the 4L core,followed by mination with prepreg and Cu is repeated to form the 6L core.This structure is processed like a standard CCL.A variation is to use a 2L core with PTHs,laminate prepreg and Cu.This blank 4L core may now be drilled,plated and patterned before it is laminated into a 6L core blank.Alternatively,the 4L blank may be patterned and relaminated into a 6L core blank.The 6L core blanks are then processed like standard CCLs.Parallel processing yields several options:with or without BPTHs.By lami-nating two patterned cores together with prepreg and Cu foil on the outside,a 6L substrate core blank is formed which can now be processed like a standard CCL.The same process can be used for cores with PTHs in one or both cores to yield a 6L substrate with BPTHs which allows for complex wiring without adding much manufacturingcomplexity.Fig.7.6Parallel process flow for 6Lsubstrate Fig.7.5Process flow for 6L sequential substrates252 B.AppeltThe advantages of parallel processing are cycle time reduction because the internal four layers can be built simultaneously,one lamination cycle instead of two(capacity),and yield optimization because cores can be inspected and marked.Parallel processing does require however a pinning scheme to ensure good registration during lamination so that the overlying lands for each PTH are not subject to hole break out.It is obvious by now that BPTHs can be placed anywhere in the cross-section of4L and6L substrates depending on design requirements and cost optimization.7.3.4High Density Interconnect Substrates–HDIWith the advent of laser drilling,it became possible to drill blind vias(BV)of controlled depth.BVs can also be drilled mechanically but depth control is much more difficult.Two types of laser drills dominate in substrate or PCB manufacturing:CO2and UV lasers.CO2lasers can drill through glass and organic matter but are stopped by Cu and have a limit of hole size currently at65m m or greater.Because they cannot drill through Cu,the intended hole pattern is first formed by conventional lithography i.e.the holes are etched in Cu using typical photo resists and develop-etch-strip(DES)technology.Subsequently,the CO2laser ablates the prepreg through this conformal Cu mask down to the capture pad.The hole shape is controlled by energy,pulse width and number of pulses.UV lasers can ablate Cu as well as prepreg.Ablation rates are different for both and it is therefore possible to stop at the capture pad.Hole formation speed is increased when there is no top Cu to burn through.Hole sizes for UV are typically50m m or less to achieve the best efficiency in throughput.Overall the CO2lasers still have better throughput and are therefore predominant.A good overview of laser drilling has been written by John Lau,2001.After laser drilling,the BV need to be cleaned(desmeared)and plated.These processes actually present quite a few challenges:the fluid dynamics is rather restrictive limiting the solution flow causing problems with surface wettability, diffusion limitations,and bubble entrapment.The typical aspect ratio(depth to diameter ratio)for high volume manufacturing is still0.7.Plating chemistry suppliers have made great advances in plating chemistries to improve on the aspect ratio and more so on enabling Cu hole fill i.e.plating the BV shut with Cu.The challenge as in PTH plating is to facilitate good throwing power into the holes.The goal is to preferentially plate the holes instead of the surface. 7.3.4.12L Via in Pad Substrates(2L HDI)The process flow for2L ViP(via in pad)substrates is the same as for standard 2L substrates with the exception of the drilling process(as shown in Fig.7.7).Asexplained above,a conformal mask if formed on one side (chip side)and the BVs are drilled by CO 2laser.Typical core thickness is still 100m m and therefore BV diameters are approximately 130m m at the top.The biggest challenge today is BV reliability.Vias have to be able to survive 1,000or more thermal cycles from –65to 1508C without cracking.To that end a resistance shift test has been devised.Several hundred BVs in a daisy chain are thermal cycled and resistance tested periodi-cally.Depending on the design,the resistance shift must be below a few percent to be acceptable.It has been shown that this indicator is extremely sensitive to crack formation.In turn,the crack formation is very sensitive to the cleanliness of the via hole bottom,electroless Cu quality and via shape at the bottom.The reason for employing this design is that the BGA pad is used as the capture pad for the BV.In PTH designs,a PTH land is required next to the BGA pad.This looks like a dog bone and requires more space.The trade off for the ViP design advantage is that in laser drilling every panel is drilled one by one,thus limiting throughput.Dog bone designs on the other hand,have very high throughput because two or more cores are stacked during mechanical drilling.It is also possible to use PTHs without dog bones,but the PTH must be filled with epoxy and cap plated.The filling process does require a post-fill grinding process to remove extraneous epoxy.This is a rather stressful process requiring careful control of grinding pressure to avoid stretching and tearing of the core.7.3.4.21+2+1Substrates (4L HDI)These four layer substrates are the first in a series of sequentially built high density substrates.In the simplest form,a 2L patterned core with PTHs is laminated with prepreg and Cu foil into a 4L blank ser via formation and substrate completion follows the same process flow as for 2L ViP.Care must be taken that a good registration strategy is employed because now the laser BV must be placed inside the capture pads.The laser must therefore have access to the fiducials which were used to form the capture pads.Ideally the same fiducials are then used again to expose the pattern after plating.The 1+2+1substrate may also incorporate PTHs connecting top and bottom layers.In that case,PTHs are drilled after laser drilling the BVs.Modified plating parameters are required to plate BVs and PTHs at the sametime.Fig.7.7Process flow for 2L ViP substrateThe BPTHs described so far had a doughnut shaped land i.e.the center was not covered with Cu because the PTH was filled with resin from prepreg during lamination of the next layer.To increase wiring density,the PTH may be capped with Cu.This requires some additional process steps.After drilling and plating the core,the PTHs must be filled or plugged and plated again. The process then continues with lamination of prepreg and Cu foil,etc.The BVs may be located on top of the PTH cap,hence the name via on PTH(VoP).Traditionally,PTH plugging has been done by screening an epoxy resin into the PTHs followed by curing and grinding off any residue of resin protruding above the Cu surface.Grinding is typically done with ceramic rollers.Care must be taken to control the pressure or the cores will be stretched in uncontrolled ways which in turn leads to high registration tolerances.Excessive grinding can also reduce the Cu thickness non-uniformly.The hole plugging epoxy is typi-cally filled with ceramic or silica particles to reduce the thermal expansion.The concern is that high thermal expansion during later processing can put a lot of stress on the Cu cap and lead to stress cracking.Resins with very high glass transition temperature(T g)and very high filler content are now available to minimize the CTE.Another enhancement is available.The grinding may be followed by Cu thinning i.e.uniform etching of the Cu surface to reduce the Cu thickness.This exposes small nubs of epoxy hole plug material again which is ground off again. This cycle can be repeated until the desired Cu thinness is achieved which will allow finer traces and spaces on the core after cap plating.The thinnest1+2+1substrates now in high volume production are260m m thick with220m m thick substrates emerging.7.3.4.31+4+1Substrates(6L HDI)The most common core is a4L core with PTHs.PTHs are capped usually and the BVs are VoP type.Consequently the process flow is essentially the same as for the corresponding1+2+1substrate except that a4L core is employed. 1+4+1has found limited application so far,mostly for designs with demand-ing power distribution and shielding requirements.7.3.4.42+2+2Substrates(6L HDI)In this case,a1+2+1core undergoes the BV process starting with lamination a second time to build up the second build-up layer pair.The most common design for2+2+2is to stagger the BVs.Recently it has become possible to plug the vias with Cu during plating.With the proper registration,this allows via stacking,and therefore,further densifi-cation of designs.The ultimate design is to stack the BVs on top of capped PTHs.For these designs usually there are no layer one to six connections with PTHs.。

一、目的1.使厂内常用名词统一、了解名词用法及意义。

2.用于新人训练的参考教材，可加速其对产品、流程的认识。

二、内容以下内容分为两大类：（1）SOP常用名词中英对照；（2）名词缩写与解释。

2-1.SOP常用名词中英对照2-1-1.产品种类（依字母顺序排列）2-1-2.产品流程（依流程顺序排列）2-1-3.使用设备与工具(依字母顺序排列)2-1-4.零组件（依字母顺序排列）2-1-5.常用名词（依字母顺序排列）2-2.名词缩写与解释（依字母顺序排列）（附录一）所有名词中英对照与解释--依字母排列顺序1. SOP常用名词中英对照ATE t est：Automatic Test Equipment，自动测试B/I：Burn In，烧机Barcode：条形码Bottom side of PCB：基板背面Bracket：铁片Capacitor：电容Capillary：导线管Carton：外箱Ceramic Substrate：陶瓷基板Coil：电磁圈Cold Solder：冷焊Component Damage：损件Conductive Sponge：导电泡棉Conductor Paste：导电油墨Connector：连接器Constant Temperature Soldering Iron：恒温烙铁Conveyor：输送带Crystal：XTAL，震荡器DC/DC Charger：充电器Dielectric Paste：介质绝缘油墨Diode：二极管Empty Solder：空焊Epoxy：数脂接着剂EPROM：Erasable and ProgrammableRead Only Memory，可重复读写只读存储器（多次烧写）ESD Wrist strap：静电环Fixture：治具Float：浮件FQA：Final Quality Assurance最终质量检验Furnace：烧结炉Fuse：保险丝Gauge：电压显示器Golden Finger：金手指Header：连接头Heat Sink：散热片High Speed Machine：高速机Hi-pot Test：高压测试Hybrid：混合ICIC (Integrated Circuit)：集成电路ICT：In Circuit Tester，静态电路自动测试Inductor：电感Inspection：总检Insulator：绝缘片Inverter：背光板Jack：插口LAN：网络卡Laser Scribe：雷射切割机Microscope：显微镜Modem：调制解调器Mylar：绝缘片Oven：烤箱Overglass Paste：玻璃绝缘油墨Oxidation：氧化P/N：Part Number，产品编号Pack：包装Partition：隔板Paste Roller：油墨滚动机Polarity：极性Printer：厚膜印刷机/锡膏印刷机Probe Card：测试探针板Probe：测试探针Programming Check：读码Programming：烧码PROM：Programmable Read OnlyMemory，可程序化只读存储器（单次烧写）R/W：Rework重工Reflow：回焊炉Repair：T/S；Trouble Shooting，修护Resistor Array：排阻Resistor Paste：电阻油墨Resistor：电阻Scanner：扫描仪Screen Cleaner：网版清洗机Shift：偏移Short：短路Silicone：热熔胶SIMM Socket：扩充内存插槽SMT：Surface Mount Technology，表面黏着技术Snap：裂片Socket：IC插槽Solder Ball：锡球Solder Icicle：锡尖Solder Paste：锡膏Solder Residue：锡渣Substrate：基板Switch：开关器T/U：Touch up，后焊Temperature Profile：温度曲线记录器Tension Gauge：张力计Thermal：散热胶Thick Measurement：测厚机Top side of PCB：基板正面Transformer：变压器Transistor：晶体管Tray：静电盘Universal Machine：泛用机Viscosity Meter：黏度计Visual Inspection：目检2.名词缩写与解释AQL：Acceptable Quality Level，允收质量水平，允收之检验批所含之最大不良率BOM：Bill Of Material，零件用量表Cassette：盛放机板的治具Cold Solder：冷焊，待焊物与锡之间，受轻微外力造成裂缝CQCN：Customer Quality Complain Notice，客户抱怨通知书CRP：Capacity Requirement Plan，产能需求计划D/W：Die mount / Wire bonding，着晶/着线站ECN/ECR：Engineering Change Request/ Notice工程变更通知书/工程变更需求Empty Solder：空（漏）焊，零件（含接脚）未完全吃锡ENG P roduction：量产（工程试产）ESD：Electric Static Discharge，静电放电破坏Golden Sample：标准品Hold Notice：停止出货通知书Identification：鉴别，不同制品于生产或出货期间的标示，使其不被混淆Lead Frame：与机板PAD以锡接和导架Lo ader/ Unlo ader：上/下料Marking：标示印刷MO：Manufacture Order，工单MRB：Material Review Board，制造异常报告书，属于制造过程中的任何质量异常；物料评议委员会，用来申请裁决MRP：Material Requirement Plan，物料需求计划MSC：Method Standard Change，制程方法变更OJT：On Job Training，在职训练P/R：Pilot Run，少量试产Pawl：搬运机板的工具PCB：Printed Circuit Board，印刷线路版Pin Pinch：接脚与接脚间的间距PM：Preventive And Maintenance，保养维护计划R/W：Rework重工，只需加工使功能或特性恢复者Repair：修护，需更换零件使功能或特性恢复者SDCN：Sample Design Change Notice，客户设计变更通知书，在产品设计、生产过程中客户或产品经理工程变更之需求SIP：Single In-Line Package，由机板的单边方向引出处接线的接脚方式SIP：Standard Inspection Procedure，标准检验流程Snap：裂片，将大片基板分离成小片之过程Solder Ball：锡球，球状的锡附着于基片或零件表面，但未构成焊接状态，且可以外力刮除Solder Icicle：锡尖，锡因过热或不纯，而在待焊物上形成突起Solder Residue：锡渣，非球状的锡附着于基片或零件表面，但未构成焊接状态，且可以外力刮除SOP：Standard Operation Procedure，标准作业程序SPC：Statistics Process Control，统计制程管制Tray：置放产品的导电或抗静电盘具Week code：周别码，用以识别产品的制造（或出货）日期WIP：Work In Process，在制品一般数据：品保手册、作业程序、作业规范、操作手册及职责规范代用料：除了BOM之外拟新增的材料或供货商技术数据：产品制程/检验/技术、实验、改善报告、仪器设备使用/维护手册、原料之数据手册巡检：品管人员不定期或定期稽核生产活动金球（第一点）：金线在芯片上之端点金球（第二点）：金线在基板上之端点金线：连接芯片与基板线路之导线客户规范：客户所提供之图面，作业规范、线路图等香蕉水：一种擦拭因印刷不良或油墨沾污清洁使用之有机溶剂修护品：产品外观或电性不良而需更换零件或修护者原始文件：定义产品需重工之文件，例如ECN、MRB、会议结论等接触角：锡与PAD熔接所造成之角度焊锡性：标面沾锡是否良好产品规范：直接用于生产线引以为据之作业规范，包括样品规范（Sa mple Run）、试产规范（Pilot Run）、制造规范（Manufacture Specification）、测试规范（Test Specification）、工程图面、零件/材料承认书、变更申请/通知书及制造异常报告书MRB异常：产品的质量或作业状况偏离正常水平或有劣化趋势者过热焊点：焊点受热过多过久，导致锡表面起皱无光泽裸线：导线未有保护绝缘，露出导体胶头：以硅胶作成各种形式专用于标示印刷锌版：Stencil标示的印膜锡未溶：锡点受热不足，导致锡未形成有光泽且均匀之合金（附录一）所有名词中英对照与解释--依中文笔划顺序1.SOP常用名词中英对照IC插槽：Socket二极管：Diode介质绝缘油墨：Dielectric Paste充电器：DC/DC Charger包装：Pack可重复读写只读存储器：EPROM；Erasable and Programmable ReadOnly Memory，（多次烧写）可程序化只读存储器：PROM；Programmable Read OnlyMemory，（单次烧写）外箱：Carton目检：Visual Inspection自动测试：ATE t est；Automatic Test Equipment 冷焊：Cold Solder油墨滚动机：Paste Roller治具：Fixture泛用机：Universal Machine空焊：Empty Solder表面黏着技术：SMT Surface MountTechnology，金手指：Golden Finger保险丝：Fuse厚膜印刷机/锡膏印刷机：Printer后焊：T/U；Touch up恒温烙铁：Constant Temperature Soldering Iron玻璃绝缘油墨：Overglass Paste背光板：Inverter重工：R/W；Rework修护：Repair；T/S（Trouble Shooting）氧化：Oxidation浮件：Float 烤箱：Oven回焊炉：Reflow高速机：High Speed Machine高压测试：Hi-pot Test偏移：Shift基板：Substrate基板正面：Top side of PCB基板背面：Bottom side of PCB张力计：Tension Gauge扫描仪：Scanner排阻：Resistor Array条形码：Barcode混合IC ：Hybrid产品编号：P/N；Part Number连接器：Connector连接头：Header陶瓷基板：Ceramic Substrate最终质量检验：FQA；Final QualityAssurance插口：Jack散热片：Heat Sink散热胶：Thermal测厚机：Thick Measurement测试探针：Probe测试探针板：Probe Card短路：Short绝缘片：Insulator绝缘片：Mylar裂片：Snap开关器：Switch损件：Component Damage极性：Polarity温度曲线记录器：Temperature Profile隔板：Partition雷射切割机：Laser Scribe电阻：Resistor电阻油墨：Resistor Paste电容：Capacitor晶体管：Transistor电感：Inductor电磁圈：Coil电压显示器：Gauge网版清洗机：Screen Cleaner网络卡：LAN数脂接着剂：Epoxy调制解调器：Modem热熔胶：Silicone震荡器：Crystal；XTAL，导电油墨：Conductor Paste导电泡棉：Conductive Sponge导线管：Capillary烧结炉：Furnace烧码：Programming烧机：B/I；Burn In集成电路：IC；Integrated Circuit输送带：Conveyor锡尖：Solder Icicle锡球：Solder Ball锡渣：Solder Residue锡膏：Solder Paste静电盘：Tray静电环：ESD Wrist strap静态电路自动测试：ICT；In Circuit Tester 总检：Inspection黏度计：Viscosity Meter扩充内存插槽：SIMM Socket铁片：Bracket读码：Programming Check 变压器：Transformer 显微镜：Microscope2.名词缩写与解释一般数据：品保手册、作业程序、作业规范、操作手册及职责规范上/下料：Lo ader/ Unlo ad er工单：MO，Manufacture Order工程变更通知书/工程变更需求：ECN/ECR；Engineering Change Request/ Notice 允收质量水平：AQL；Acceptable Quality Level，允收之检验批所含之最大不良率少量试产：P/R；Pilot Run代用料：除了BOM之外拟新增的材料或供货商印刷标示：Marking印刷线路版：PCB；Printed Circuit Board在制品：WIP，Work In Process在职训练：OJT；On Job Training冷焊：Cold Solder，待焊物与锡之间，受轻微外力造成裂缝技术数据：产品制程/检验/技术、实验、改善报告、仪器设备使用/维护手册、原料之数据手册巡检：品管人员不定期或定期稽核生产活动物料需求计划：MRP；Material Require ment Plan空（漏）焊：Empty Solder，零件（含接脚）未完全吃锡金球（第一点）：金线在芯片上之端点金球（第二点）：金线在基板上之端点金线：连接芯片与基板线路之导线保养维护计划：PM；Preventive And Maintenance客户抱怨通知书：CQCN；Customer Quality Complain Notice客户规范：客户所提供之图面，作业规范、线路图等客户设计变更通知书：SDCN；Sample Design Change Notice，在产品设计、生产过程中客户或产品经理工程变更之需求重工：R/W；Rework，只需加工使功能或特性恢复者香蕉水：一种擦拭因印刷不良或油墨沾污清洁使用之有机溶剂修护：Repair，需更换零件使功能或特性恢复者修护品：产品外观或电性不良而需更换零件或修护者原始文件：定义产品需重工之文件，例如ECN、MRB、会议结论等停止出货通知书：Hold Notice接触角：锡与PAD熔接所造成之角度焊锡性：标面沾锡是否良好产品规范：直接用于生产线引以为据之作业规范，包括样品规范（Sa mple Run）、试产规范（Pilot Run）、制造规范（Manufacture Specification）、测试规范（Test Specification）、工程图面、零件/材料承认书、变更申请/通知书及制造异常报告书MRB产能需求计划：CRP；Capacity Requirement Plan异常：产品的质量或作业状况偏离正常水平或有劣化趋势者盛放机板的治具：Cassette统计制程管制：SPC；Statistics Process Control着晶/着线站：D/W；Die mount / Wire bonding裂片：Snap，将大片基板分离成小片之过程周别码：Week code，用以识别产品的制造（或出货）日期量产（工程试产）：ENG P roduction过热焊点：焊点受热过多过久，导致锡表面起皱无光泽零件用量表：BOM；Bill Of Material裸线：导线未有保护绝缘，露出导体制造异常报告书/物料评议委员会：MRB；Material Review Board属于制造过程中的任何质量异常；物料评议委员会，用来申请裁决制程方法变更：MSC；Method Standard Change标准作业程序：SOP；Standard Operation Procedure标准品：Golden Sample标准检验流程：SIP；Standard Inspection Procedure胶头：以硅胶作成各种形式专用于标示印刷锌版：Stencil标示的印膜锡未溶：锡点受热不足，导致锡未形成有光泽且均匀之合金锡尖：Solder Icicle，锡因过热或不纯，而在待焊物上形成突起锡球：Solder Ball，球状的锡附着于基片或零件表面，但未构成焊接状态，且可以外力刮除锡渣：Solder Residue，非球状的锡附着于基片或零件表面，但未构成焊接状态，且可以外力刮除静电放电破坏：ESD；Electric Static Discharge鉴别：Identification，不同制品于生产或出货期间的标示，使其不被混淆。