BDIRAV CCA VCCBProduct FolderSample &BuyTechnical Documents Tools &SoftwareSupport &CommunitySN74LVC1T45SCES515K –DECEMBER 2003–REVISED DECEMBER 2014SN74LVC1T45Single-Bit Dual-Supply Bus Transceiver With Configurable VoltageTranslation and 3-State Outputs1Features3DescriptionThis single-bit noninverting bus transceiver uses two •Available in the Texas Instruments NanoFree™separate configurable power-supply rails.The A port Packageis designed to track V CCA .V CCA accepts any supply •Fully Configurable Dual-Rail Design Allows Each voltage from 1.65V to 5.5V.The B port is designed Port to Operate Over the Full 1.65-V to 5.5-V to track V CCB .V CCB accepts any supply voltage from Power-Supply Range1.65V to 5.5V.This allows for universal low-voltage bidirectional translation between any of the 1.8-V,•V CC Isolation Feature –If Either V CC Input Is at2.5-V,3.3-V,and 5-V voltage nodes.GND,Both Ports Are in the High-Impedance State •DIR Input Circuit Referenced to V CCA The SN74LVC1T45is designed for asynchronous communication between two data buses.The logic •Low Power Consumption,4-μA Max I CC levels of the direction-control (DIR)input activate •±24-mA Output Drive at 3.3Veither the B-port outputs or the A-port outputs.The •I off Supports Partial-Power-Down Mode Operation device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B •Max Data Ratesbus to the A bus when the A-port outputs are –420Mbps (3.3-V to 5-V Translation)activated.The input circuitry on both A and B ports –210Mbps (Translate to 3.3V)always is active and must have a logic HIGH or LOW level applied to prevent excess I CC and I CCZ .–140Mbps (Translate to 2.5V)–75Mbps (Translate to 1.8V)Device Information (1)•Latch-Up Performance Exceeds 100mA Per PART NUMBERPACKAGE BODY SIZE (NOM)JESD 78,Class II2.90mm ×1.60mm•ESD Protection Exceeds JESD 22SOT (6) 2.00mm ×1.25mm SN74LVC1T45–2000-V Human-Body Model (A114-A) 1.60mm ×1.20mm –200-V Machine Model (A115-A)DSBGA (6)1.39mm ×0.90mm–1000-V Charged-Device Model (C101)(1)For all available packages,see the orderable addendum atthe end of the datasheet.2Applications•Personal Electronic •Industrial •Enterprise •TelecomFunctional Block DiagramSN74LVC1T45SCES515K–DECEMBER2003–REVISED Table of Contents1Features..................................................................18Parameter Measurement Information. (11)2Applications...........................................................19Detailed Description.. (12)9.1Overview (12)3Description (1)9.2Functional Block Diagram (12)4Revision History (2)9.3Feature Description (12)5Description(Continued) (3)9.4Device Functional Modes (12)6Pin Configuration and Functions (3)10Applications and Implementation (13)7Specifications (4)10.1Application Information (13)7.1Absolute Maximum Ratings (4)10.2Typical Application (13)7.2ESD Ratings (4)11Power Supply Recommendations (16)7.3Recommended Operating Conditions (4)12Layout (16)7.4Thermal Information (5)12.1Layout Guidelines (16)7.5Electrical Characteristics (6)12.2Layout Example (16)7.6Switching Characteristics(V CCA=1.8V±0.15V) (7)13Device and Documentation Support (17)7.7Switching Characteristics(V CCA=2.5V±0.2V) (7)13.1Trademarks (17)7.8Switching Characteristics(V CCA=3.3V±0.3V) (8)13.2Electrostatic Discharge Caution (17)7.9Switching Characteristics(V CCA=5V±0.5V) (8)13.3Glossary (17)7.10Operating Characteristics (8)7.11Typical Characteristics............................................914Mechanical,Packaging,and OrderableInformation (17)4Revision HistoryNOTE:Page numbers for previous revisions may differ from page numbers in the current version.Changes from Revision J(December2013)to Revision K Page •Added Pin Configuration and Functions section,ESD Ratings table,Feature Description section,Device Functional Modes,Application and Implementation section,Power Supply Recommendations section,Layout section,Device and Documentation Support section,and Mechanical,Packaging,and Orderable Information section (1)Changes from Revision I(December2011)to Revision J Page •Updated document to new TI data sheet format-no specification changes (1)•Removed ordering information (1)•Added ESD warning (1)2Submit Documentation Feedback Copyright©2003–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LVC1T45DBV PACKAGE(TOP VIEW)DCK PACKAGE(TOP VIEW)DRL PACKAGE(TOP VIEW)YZP PACKAGE(BOTTOM VIEW)SN74LVC1T45 SCES515K–DECEMBER2003–REVISED DECEMBER2014 5Description(Continued)The SN74LVC1T45is designed so that the DIR input is powered by V CCA.This device is fully specified for partial-power-down applications using I off.The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.The V CC isolation feature ensures that if either V CC input is at GND,then both ports are in the high-impedance state.NanoFree package technology is a major breakthrough in IC packaging concepts,using the die as the package. 6Pin Configuration and FunctionsPin FunctionsPINI/O DESCRIPTIONNAME NO.V CCA1p SYSTEM-1supply voltage(1.65V to5.5V)GND2G Device GNDA3I/O Output level depends on V CC1voltage.B4I/O Input threshold value depends on V CC2voltage.DIR5I GND(low level)determines B-port to A-port direction.V CCB6P SYSTEM-2supply voltage(1.65V to5.5V)Copyright©2003–2014,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Links:SN74LVC1T45SN74LVC1T45SCES515K–DECEMBER2003–REVISED 7Specifications7.1Absolute Maximum Ratings(1)over operating free-air temperature range(unless otherwise noted)MIN MAX UNITV CCASupply voltage–0.5 6.5VV CCBV I Input voltage(2)–0.5 6.5VV O Voltage range applied to any output in the high-impedance or power-off state(2)–0.5 6.5VA port–0.5V CCA+0.5Voltage range applied to any output in the high or lowV O V state(2)(3)B port–0.5V+0.5CCBI IK Input clamp current V I<0–50mAI OK Output clamp current V O<0–50mAI O Continuous output current±50mAContinuous current through V CC or GND±100mAT stg Storage temperature,T stg–65150°C (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3)The value of V CC is provided in the recommended operating conditions table.7.2ESD RatingsVALUE UNITHuman-body model(HBM),per ANSI/ESDA/JEDEC JS-001(1)±2000Charged-device model(CDM),per JEDEC specification JESD22-±1000V(ESD)Electrostatic discharge VC101(2)Machine Model±200(1)JEDEC document JEP155states that500-V HBM allows safe manufacturing with a standard ESD control process.(2)JEDEC document JEP157states that250-V CDM allows safe manufacturing with a standard ESD control process.7.3Recommended Operating ConditionsSee(1)(2)(3)V CCI V CCO MIN MAX UNITV CCA 1.65 5.5 Supply voltage VV CCB 1.65 5.51.65o1.95V V CCI×0.652.3to2.7V 1.7High-levelV IH Data inputs(4)V input voltage3to3.6V24.5to5.5V V CCI×0.71.65o1.95V V CCI×0.352.3to2.7V0.7Low-levelV IL Data inputs(4)V input voltage3to3.6V0.84.5to5.5V V CCI×0.3(1)V CCI is the V CC associated with the input port.(2)V CCO is the V CC associated with the output port.(3)All unused data inputs of the device must be held at V CCI or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs,literature number SCBA004.(4)For V CCI values not specified in the data sheet,V IH min=V CCI×0.7V,V IL max=V CCI×0.3V.4Submit Documentation Feedback Copyright©2003–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LVC1T45SN74LVC1T45 SCES515K–DECEMBER2003–REVISED DECEMBER2014Recommended Operating Conditions(continued)See(1)(2)(3)V CCI V CCO MIN MAX UNIT1.65to1.95V V CCA×0.652.3to2.7V 1.7High-level DIRV IH V input voltage(referenced to V CCA)(5)3to3.6V24.5to5.5V V CCA×0.71.65to1.95V V CCA×0.352.3to2.7V0.7Low-level DIRV IL V input voltage(referenced to V CCA)(5)3to3.6V0.84.5to5.5V V CCA×0.3V I Input voltage0 5.5VV O Output voltage0V CCO V1.65to1.95V–42.3to2.7V–8I OH High-level output current mA3to3.6V–244.5to5.5V–321.65to1.95V42.3to2.7V8I OL Low-level output current mA3to3.6V244.5to5.5V321.65to1.95V202.3to2.7V20Data inputsInput transitionΔt/Δv3to3.6V10ns/V rise or fall rate4.5to5.5V5Control inputs 1.65to5.5V5T A Operating free-air temperature–4085°C (5)For V CCI values not specified in the data sheet,V IH min=V CCA×0.7V,V IL max=V CCA×0.3V.7.4Thermal InformationSN74LVC1T45THERMAL METRIC(1)DBV DCK DRL YZP UNIT6PINSRθJA Junction-to-ambient thermal resistance200.1286.8223.7131.0RθJC(top)Junction-to-case(top)thermal resistance144.593.988.7 1.3RθJB Junction-to-board thermal resistance45.795.558.422.6°C/WψJT Junction-to-top characterization parameter36.2 1.9 5.9 5.2ψJB Junction-to-board characterization parameter25.394.758.122.6RθJC(bot)Junction-to-case(bottom)thermal resistance N/A N/A N/A N/A(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.Copyright©2003–2014,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Links:SN74LVC1T45SN74LVC1T45SCES515K–DECEMBER2003–REVISED 7.5Electrical Characteristics(1)(2)over recommended operating free-air temperature range(unless otherwise noted)T A=25°C–40to85°C PARAMETER TEST CONDITIONS V CCA V CCB UNITMIN TYP MAX MIN MAXV CCOI OH=–100μA 1.65to4.5V 1.65to4.5V–0.1I OH=–4mA 1.65V 1.65V 1.2V OH V I=V IH VI OH=–8mA 2.3V 2.3V 1.9I OH=–24mA3V3V 2.4I OH=–32mA 4.5V 4.5V 3.8I OL=100μA 1.65to4.5V 1.65to4.5V0.1I OL=4mA 1.65V 1.65V0.45V OL I OL=8mA V I=V IL 2.3V 2.3V0.3VI OL=24mA3V3V0.55I OL=32mA 4.5V 4.5V0.55I I DIR V I=V CCA or GND 1.65to5.5V 1.65to5.5V±1±2μAA port0V0to5.5V±1±2I off V I or V O=0to5.5VμAB port0to5.5V0V±1±2A or BI OZ V O=V CCO or GND 1.65to5.5V 1.65to5.5V±1±2μAport1.65to5.5V 1.65to5.5V3I CCA V I=V CCI or GND,I O=0 5.5V0V2μA0V 5.5V-21.65to5.5V 1.65to5.5V3I CCB V I=V CCI or GND,I O=0 5.5V0V-2μA0V 5.5V2I CCA+I CCBV I=V CCI or GND,I O=0 1.65to5.5V 1.65to5.5V4μA (see Table1)A port at V CCA–0.6V,A port50DIR at V CCA,B port=openΔI CCA3to5.5V3to5.5VμA DIR at V CCA–0.6V,DIR B port=open,50A port at V CCA or GNDB port at V CCB–0.6V,ΔI CCB B port DIR at GND,3to5.5V3to5.5V50μAA port=openC i DIR V I=V CCA or GND 3.3V 3.3V 2.5pFA or BC io V O=V CCA/B or GND 3.3V 3.3V6pFport(1)V CCO is the V CC associated with the output port.(2)V CCI is the V CC associated with the input port.6Submit Documentation Feedback Copyright©2003–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LVC1T45SN74LVC1T45 SCES515K–DECEMBER2003–REVISED DECEMBER20147.6Switching Characteristics(V CCA=1.8V±0.15V)over recommended operating free-air temperature range,V CCA=1.8V±0.15V(see Figure9)V CCB=1.8V V CCB=2.5V V CCB=3.3V V CCB=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAXt PLH317.7 2.210.3 1.78.3 1.47.2A B nst PHL 2.814.3 2.28.5 1.87.1 1.77t PLH317.7 2.316 2.115.5 1.915.1B A nst PHL 2.814.3 2.112.9212.6 1.812.2t PHZ 5.219.4 4.818.5 4.718.4 5.117.1DIR A ns t PLZ 2.310.5 2.110.5 2.410.7 3.110.9t PHZ7.421.9 4.911.5 4.610.3 2.88.2DIR B ns t PLZ 4.216 3.79.2 3.38.4 2.4 6.4t PZH(1)33.725.223.921.5DIR A ns t PZL(1)36.224.422.920.4t PZH(1)28.220.81918.1DIR B ns t PZL(1)33.72725.524.1(1)The enable time is a calculated value,derived using the formula shown in the Enable Times section.7.7Switching Characteristics(V CCA=2.5V±0.2V)over recommended operating free-air temperature range,V CCA=2.5V±0.2V(see Figure9)V CCB=1.8V V CCB=2.5V V CCB=3.3V V CCB=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAX t PLH 2.316 1.58.5 1.3 6.4 1.1 5.1A B nst PHL 2.112.9 1.47.5 1.3 5.40.9 4.6t PLH 2.210.3 1.58.5 1.4817.5B A nst PHL 2.28.5 1.47.5 1.370.9 6.2t PHZ38.1 3.18.1 2.88.1 3.28.1DIR A ns t PLZ 1.3 5.9 1.3 5.9 1.3 5.91 5.8t PHZ 6.523.7 4.111.4 3.910.2 2.47.1DIR B ns t PLZ 3.918.9 3.29.6 2.88.4 1.8 5.3t PZH(1)29.218.116.412.8DIR A ns t PZL(1)32.218.917.213.3t PZH(1)21.914.412.310.9DIR B ns t PZL(1)2115.613.512.7(1)The enable time is a calculated value,derived using the formula shown in the Enable Times section.Copyright©2003–2014,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Links:SN74LVC1T45SN74LVC1T45SCES515K–DECEMBER2003–REVISED 7.8Switching Characteristics(V CCA=3.3V±0.3V)over recommended operating free-air temperature range,V CCA=3.3V±0.3V(see Figure9)V CCB=1.8V V CCB=2.5V V CCB=3.3V V CCB=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAXt PLH 2.115.5 1.480.7 5.80.7 4.4A B nst PHL212.6 1.370.850.74t PLH 1.78.3 1.3 6.40.7 5.80.6 5.4B A nst PHL 1.87.1 1.3 5.40.850.7 4.5t PHZ 2.97.337.3 2.87.3 3.47.3DIR A ns t PLZ 1.8 5.6 1.6 5.6 2.2 5.7 2.2 5.7t PHZ 5.420.5 3.910.1 2.98.8 2.4 6.8DIR B ns t PLZ 3.314.5 2.97.8 2.47.1 1.7 4.9t PZH(1)22.814.212.910.3DIR A ns t PZL(1)27.615.513.811.3t PZH(1)21.113.611.510.1DIR B ns t PZL(1)19.914.312.311.3(1)The enable time is a calculated value,derived using the formula shown in the Enable Times section.7.9Switching Characteristics(V CCA=5V±0.5V)over recommended operating free-air temperature range,V CCA=5V±0.5V(see Figure9)V CCB=1.8V V CCB=2.5V V CCB=3.3V V CCB=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAX t PLH 1.915.117.50.6 5.40.5 3.9A B nst PHL 1.812.20.9 6.20.7 4.50.5 3.5t PLH 1.47.21 5.10.7 4.40.5 3.9B A nst PHL 1.770.9 4.60.740.5 3.5t PHZ 2.1 5.4 2.2 5.4 2.2 5.5 2.2 5.4DIR A ns t PLZ0.9 3.81 3.81 3.70.9 3.7t PHZ 4.820.2 2.59.818.5 2.5 6.5DIR B ns t PLZ 4.214.8 2.57.4 2.57 1.6 4.5t PZH(1)2212.511.48.4DIR A ns t PZL(1)27.214.412.510t PZH(1)18.911.39.17.6DIR B ns t PZL(1)17.611.6108.6(1)The enable time is a calculated value,derived using the formula shown in the Enable Times section.7.10Operating CharacteristicsT A=25°CV CCA=V CCA=V CCA=V CCA=TEST VCCB =1.8V V CCB=2.5V V CCB=3.3V V CCB=5VPARAMETER UNITCONDITIONSTYP TYP TYP TYP A-port input,B-port output C L=0pF,3444C pdA(1)f=10MHz,pFB-port input,A-port output18192021t r=t f=1nsA-port input,B-port output C L=0pF,18192021C pdB(1)f=10MHz,pFB-port input,A-port output3444t r=t f=1ns(1)Power dissipation capacitance per transceiver8Submit Documentation Feedback Copyright©2003–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LVC1T45SN74LVC1T45 SCES515K–DECEMBER2003–REVISED DECEMBER20147.11Typical CharacteristicsCopyright©2003–2014,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Links:SN74LVC1T45SN74LVC1T45SCES515K–DECEMBER2003–REVISED Typical Characteristics(continued)10Submit Documentation Feedback Copyright©2003–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LVC1T45V OH V OLLOAD CIRCUIT × V CCOOpenOutput Control (low-level enabling)Output Waveform 1S1 at 2 × V CCO (see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 VV CCI0 VV CCAV CCOVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESVOLTAGE WAVEFORMS PULSE DURATIONVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESInputt pd t PLZ /t PZL t PHZ /t PZHOpen 2 × V CCO GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, Z O = 50 Ω, dv/dt ≥ 1 V/ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .H.V CCI is the V CC associated with the input port.I.V CCO is the V CC associated with the output port.J.All parameters and waveforms are not applicable to all devices.1.8 V ± 0.15 V2.5 V ± 0.2 V3.3 V ± 0.3 V 5 V ± 0.5 V2 k Ω2 k Ω2 k Ω2 k ΩV CCO R L 0.15 V 0.15 V 0.3 V 0.3 VV TP C L 15 pF 15 pF 15 pF 15 pFSN74LVC1T45SCES515K –DECEMBER 2003–REVISED DECEMBER 20148Parameter Measurement InformationFigure 9.Load Circuit and Voltage WaveformsCopyright ©2003–2014,Texas Instruments Incorporated Submit Documentation Feedback11Product Folder Links:SN74LVC1T45BDIRAV CCA V CCBSN74LVC1T45SCES515K –DECEMBER 2003–REVISED DECEMBER 20149Detailed Description9.1OverviewThe SN74LVC1T45is single-bit,dual-supply,non-inverting voltage level translation.Pin A and that direction control pin (DIR)are supported by V CCA and pin B is supported by V CCB .The A port is able to accept I/O voltages ranging from 1.65V to 5.5V,while the B port can accept I/O voltages from 1.65V to 5.5V.The high on the DIR allows data transmissions from A to B and a low on the DIR allows data transmissions from B to A.9.2Functional Block DiagramFigure 10.Logic Diagram (Positive Logic)9.3Feature Description9.3.1Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-VPower-Supply Range Both V CCA and V CCB can be supplied at any voltage between 1.65V and 5.5V,making the device suitable for translating between any of the voltage nodes (1.8-V,2.5-V,3.3-V and 5-V).9.3.2Support High Speed TranslationSN74LVC1T45can support high data rate applications.The translated signal data rate can be up to 420Mbps when the signal is translated from 3.3V to 5V.9.3.3I off Supports Partial Power-Down Mode OperationI off will prevent backflow current by disabling I/O output circuits when device is in partial-power-down mode.9.4Device Functional ModesTable 1.Function Table (1)INPUT OPERATION DIR L B data to A bus HA data toB bus(1)Input circuits of the data I/Os always are active.12Submit Documentation FeedbackCopyright ©2003–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LVC1T45SYSTEM-1SYSTEM-2SN74LVC1T45 SCES515K–DECEMBER2003–REVISED DECEMBER2014 10Applications and ImplementationNOTEInformation in the following applications sections is not part of the TI componentspecification,and TI does not warrant its accuracy or completeness.TI’s customers areresponsible for determining suitability of components for their purposes.Customers shouldvalidate and test their design implementation to confirm system functionality.10.1Application InformationThe SN74LVC1T45device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another.The max data rate can be up to420Mbps when device translates signals from3.3V to5V.10.2Typical Application10.2.1Unidirectional Logic Level-Shifting ApplicationFigure11shows an example of the SN74LVC1T45being used in a unidirectional logic level-shifting application.Figure11.Unidirectional Logic Level-Shifting Application10.2.1.1Design RequirementsFor this design example,use the parameters listed in Table2.Table2.Design ParametersDESIGN PARAMETER EXAMPLE VALUEInput voltage range 1.65V to5.5VOutput voltage range 1.65V to5.5V10.2.1.2Detailed Design ProcedureTo begin the design process,determine the following:•Input voltage range-Use the supply voltage of the device that is driving the SN74LVC1T45device to determine the input voltage range.For a valid logic high the value must exceed the V IH of the input port.For a valid logic low the value must be less than the V IL of the input port.•Output voltage range-Use the supply voltage of the device that the SN74LVC1T45device is driving to determine the output voltage range.Copyright©2003–2014,Texas Instruments Incorporated Submit Documentation Feedback13Product Folder Links:SN74LVC1T45SYSTEM-1SYSTEM-2SN74LVC1T45SCES515K –DECEMBER 2003–REVISED DECEMBER 201410.2.1.3Application CurveFigure 12.Translation Up (1.8V to 5V)at 2.5MHz10.2.2Bidirectional Logic Level-Shifting ApplicationFigure 13shows the SN74LVC1T45being used in a bidirectional logic level-shifting application.Since the SN74LVC1T45does not have an output-enable (OE)pin,the system designer should take precautions to avoid bus contention between SYSTEM-1and SYSTEM-2when changing directions.Figure 13.Bidirectional Logic Level-Shifting Application10.2.2.1Design Requirements Please refer to Design Requirements .10.2.2.2Detailed Design ProcedureTable 3shows data transmission from SYSTEM-1to SYSTEM-2and then from SYSTEM-2to SYSTEM-1.Table 3.SYSTEM-1and SYSTEM-2Data TransmissionSTATE DIR CTRLI/O-1I/O-2DESCRIPTION1H Out In SYSTEM-1data to SYSTEM-2SYSTEM-2is getting ready to send data to SYSTEM-1.I/O-1and I/O-2are disabled.The bus-2H Hi-Z Hi-Z line state depends on pullup or pulldown.(1)DIR bit is flipped.I/O-1and I/O-2still are disabled.The bus-line state depends on pullup or 3L Hi-Z Hi-Z pulldown.(1)4LOutInSYSTEM-2data to SYSTEM-1(1)SYSTEM-1and SYSTEM-2must use the same conditions,i.e.,both pullup or both pulldown.14Submit Documentation FeedbackCopyright ©2003–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LVC1T45SN74LVC1T45 SCES515K–DECEMBER2003–REVISED DECEMBER201410.2.2.2.1Enable TimesCalculate the enable times for the SN74LVC1T45using the following formulas:•t PZH(DIR to A)=t PLZ(DIR to B)+t PLH(B to A)•t PZL(DIR to A)=t PHZ(DIR to B)+t PHL(B to A)•t PZH(DIR to B)=t PLZ(DIR to A)+t PLH(A to B)•t PZL(DIR to B)=t PHZ(DIR to A)+t PHL(A to B)In a bidirectional application,these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected.For example,if the SN74LVC1T45initially is transmitting from A to B,then the DIR bit is switched;the B port of the device must be disabled before presenting it with an input.After the B port has been disabled,an input signal applied to it appears on the corresponding A port after the specified propagation delay.10.2.2.3Application CurveFigure14.Translation Down(5V to1.8V)at2.5MHzCopyright©2003–2014,Texas Instruments Incorporated Submit Documentation Feedback15Product Folder Links:SN74LVC1T45SN74LVC1T45SCES515K–DECEMBER2003–REVISED 11Power Supply RecommendationsThe SN74LVC1T45device uses two separate configurable power-supply rails,V CCA and V CCB.V CCA accepts any supply voltage from1.65V to5.5V and V CCB accepts any supply voltage from1.65V to5.5V.The A port and B port are designed to track V CCA and V CCB,respectively allowing for low-voltage bidirectional translation between any of the1.8-V,2.5-V,3.3-V and5-V voltage nodes.12Layout12.1Layout GuidelinesTo ensure reliability of the device,the following common printed-circuit board layout guidelines are recommended:•Bypass capacitors should be used on power supplies.•Short trace lengths should be used to avoid excessive loading.•Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depends on the system requirements12.2Layout Exampleyout Example16Submit Documentation Feedback Copyright©2003–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LVC1T45SN74LVC1T45 SCES515K–DECEMBER2003–REVISED DECEMBER201413Device and Documentation Support13.1TrademarksNanoFree is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.13.2Electrostatic Discharge CautionThese devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.13.3GlossarySLYZ022—TI Glossary.This glossary lists and explains terms,acronyms,and definitions.14Mechanical,Packaging,and Orderable InformationThe following pages include mechanical,packaging,and orderable information.This information is the most current data available for the designated devices.This data is subject to change without notice and revision of this document.For browser-based versions of this data sheet,refer to the left-hand navigation.Copyright©2003–2014,Texas Instruments Incorporated Submit Documentation Feedback17Product Folder Links:SN74LVC1T45PACKAGING INFORMATION(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.Addendum-Page 1PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF SN74LVC1T45 :•Automotive: SN74LVC1T45-Q1•Enhanced Product: SN74LVC1T45-EPNOTE: Qualified Version Definitions:•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defectsAddendum-Page 2。
