具有恒定跨导的Rail-to-Rail CMOS运算放大器设计指导陈斯(徐州师范大学物理系电子科学教研室)注：文章中有很多关于MOS方面的基础知识，可能对于你们来说比较陌生，可以去找一些关于这方面的书籍看看。
下学期我会给你们做专门的讲解的。
你们先作个大概的了解，并确定具体的方向。
1引言近年来，随着集成电路工艺尺寸的不断减小，低电压的发展趋势越来越快。
下图为半导体工艺与电源电压的关系。
从图中可以看出，电压随着工艺最小尺寸的减小而不断降低。
电压减小的原因是因为尺寸的减小导致了器件的击穿电压的减小。
此外数字电路的功耗正比于电源电压的平方，因此，为了减小功耗必须降低电源的电压。
但是从模拟电路设计者来看，电源电压的减小会导致模拟信号动态范围的减小。
如果MOS管的域值电压随着电源的降低而等比减小的话，动态范围就不会受到严重的影响。
但由于数字逻辑的原因，域值电压不能大幅地减小，所以低电压会对电路的设计带来一定的影响。
2 一般原理在模拟电路和数模混合电路中，对于低电压的追求逐渐成为集成电路的一种时尚。
然而低电压导致了运算放大器输入共模范围的降低，传统的PMOS或NMOS差分对输入已不能满足大的输入共模范围的要求。
为解决这一瓶颈，rail-to-rail运算放大器随之而产生。
通常的Rail-to-Rail运放采用两级结构，运放的输出级可以采用简单的class-A或class-AB来实现，难点在于输入级的设计。
输入级一般采用PMOS和NMOS并联的互补差分结构，但其跨导在整个共模输入范围内变化两倍。
这种跨导的变化不仅影响环路的增益, 也会影响运放的频率补偿。
同时，由于输入信号是rail-to-rail ，具有很高的信噪比，因此要求整个rail-to-rail 运放的输入级保持恒定的跨导(g m )。
一般来说，运算放大器的输入级都采用差分放大器的输入模式。
在CMOS 工艺中，差分放大器可以通过PMOS 或NMOS 的差分对来实现。
Rail to Rail 轨对轨运放传统的模拟集成器件，如运放、A/D、D/A等，其模拟引脚的电压范围一般都达不到电源，以运放为例，电源为+/-15V的运放，为确保性能（首先是不损坏，其次是不反相，最后是足够的共模抑制比），输入范围一般不要超过+/-10V，常温下也不要超过+/-12V；输出范围，负载10kohm时一般只有+/-11V，小负载电阻(600ohm)时只能保证+/-10V。
这对器件的应用带来很多不便。
rail-to-rail的器件，一般都是低压器件（+/-5V 或single +5V），输入输出电压都能达到电源（输入甚至可以超过）。
其原理上的秘诀便在于电流模＋NPN/PNP互补输入结构。
rail-to-rail器件的某些设计思想，对我们自己设计电路也可以提供一些有益的思路。
现在rail-to-rail的单电源模拟器件已形成系列（如MAXIM,AD,TI等），在许多对性能（精度）要求不高的场合，我们可以考虑全部采用单+5V甚至+2.7V的模拟器件来构成我们的系统，这样模拟电路和数字电路便可以公用一个电源（不过要注意电源去耦）。
而且这类器件大量采用SOT封装，有利于设计出体积功耗都很小的产品。
rail-to-rail，即“轨至轨”，有时也称为“满摆幅”，是指输出(或输入)电压范围与电源电压相等或近似相等。
从输入方面来讲，其共模输入电压范围可以从负电源电压到正电源电压；从输出方面来讲，其输出电压范围可以从负电源电源到正电源电压。
也可以说，这是一个与供电电压密切相关的特性，对器件的输入或输出无失真动态范围有很大的影响，当ΔV 很小时(10mV--100mV)，无失真动态范围最小电压为VSS+ΔV，最大值为VCC-ΔV，具有这样动态范围的运放就叫Rail to Rail运放。
理想状态下，器件的正常工作输入与输出电压范围可同时达到运放正负电源端的电压范围。
实际上，器件很难达到真正的“轨至轨”。
比较常见的“轨至轨”表现方式有，输入rail-to-rail；输入达到或超过Vee；输出比较接近rail-to-rail；在同一器件上的输入/输出实现（或接近）rail-to-rail。
Brief PapersA Rail-to-Rail Constant-(1)while the pMOS pair is in conduction for low input common-mode voltages,we can obtain a constant transconductance;for low-input common-mode voltages only the pMOS pair0018–9200/97$10.00©1997IEEEis active,where for high ones only the nMOS pair is in conduction.For“middle”values,both pairs are“ON,”but each with reduced contribution(exactly the half in the“crossing-point”condition).Theconstant-m,is the thermal voltageandA,the supply voltage for theused technology is about1.33V).In Fig.2(a),a feedback circuit which gives an equal valueof transconductance for low and high input signals is shown.Two dummy circuits have been placed operating,respectively,at high(M)and low(M)input levels.Afeedback MOST(M)controls the current in the pMOS inputstage and makes it equal to the nMOS stage one,the transistorsworking in weak inversion.To take into account the influenceof the slope factor,transistorM has been designed with aslightly higher valueof m).In Fig.2(b),two other feedback loops ensuring a constantsupply voltage by means of sensing the“crossing-point”condition,performed by equal transistorsM andM–M–M–M–M)and a regulating MOST(MM with areference current(flowing onM).The right loop is a voltageregulating system which,by means of an external supplyvoltage(,which can be a battery),controls the internalsupplyvoltage and keeps it constant.In this manner,thewhole circuit is robust to possible discharges of the externalsupply.The feedback circuitry can work with valuesofcomprised in the range1.3–2.2V.For low-input common-mode voltages,only the pMOS inputpair is active and the currentflowing on M and M is givenby the drain current ofM().are both“OFF”and no currentflowsin,.This(a)(b)(c)Fig.1.(a)Rail-to-rail input stage;(b)transconductance versus input com-mon-mode voltage(nonconstant g m input stage);and(c)transconductanceversus input common-mode voltage(constant g m input stage).total current is kept equalto by means of the feedbackcircuit described in Fig.2(a).Since the input transistors arein weak inversion,the input transconductance is the same forlow-and high-input common-mode voltages.For“middle”values of common-mode input voltages,areduced value of currentflows in both the input pairs.Thiscurrent,in the“crossing point”condition,is exactly half ofthe value compared to low and high common inputs.But thetotal currentflowing in the input transistors and,consequently,the input transconductance are always the same.The inputvoltage which realizes the“crossing point”condition is strictlylinked to the valueof.In fact,it is about half of it.Thefeedback circuit of Fig.2(b)prohibits the variationsofand,consequently,fixes the“crossing point”condition.(a)(b)(c)Fig.2.(a)Feedback circuit ensuring equal transconductance for low and high input signals,(b)feedback circuit ensuring the crossing point condition and a constant internal supply voltage,and(c)the main schematic of the op-amp.(In the schematics all the MOS have W=1000 m,L=1:2 m except if W is specified).(a)(b)(c)Fig.3.(a)Microphotograph of the chip,(b)simulated and experimental GBW versus common-mode input voltage,and (c)internal versus external supply voltages.In Fig.2(c),the main schematic of the op-amp is shown.It is formed by the input stage (previously described),a summingstage (MM MAX =6%)Gain Bandwidth (GBW) 1.3MHz (PM =64 )Low frequency gain84dBPower Consumption (total quiescent current in the input stages =10 A;in the output stage =90 A)0.46mW (215 W in the main stage,230 W in the biasing and feedback loops,only 15 W in the regulator)Slew Rate1V/ s Total Harmonic Distortion (1KHz,V pp =60%V AL )1%Equivalent input voltage noise 25nV/pHz (1=f noise negligible)Input offset voltage typical =0.8mV;3 value =60:2mV Settling time0.38 s (1%);0.58 s (0.1%)Overload Recovery 100nsCMRR 56dB @10Hz;52dB @100KHz PSRR +48dB @10Hz;26dB @100KHz PSRR 051dB @10Hz;32dB @100KHz Chip area1.2mm 2III.O P -A MP E XPERIMENTAL R ESULTSThe chip [see photo–Fig.3(a)]has been designed in0.7-m and the threshold voltages about 0.7V.The test of the chip has been done with a testset for automatic characterization of opamps (TACO)[22].Fig.3(b)shows the simulated and experimental gain bandwidth (GBW)versus input voltage.The difference is due to mismatch.Fig.3(c)shows the internal and external supply voltages.From this figure,we can notice that the circuit is still operating for a minimum external voltage of 1.3V.In Table I,the experimental results are collected (in the operating condition of 1.5-V supply voltage and 15-pF of load capacitance).These values can be considered valid in the supply range 1.3–1.8V.IV.C ONCLUSIONA new way to realize aconstant-[5],“Design of low-voltage bipolar opamps,”in Proc.AACD,Scheveningen,1992,pp.39–59.[6]R.G.H.Eschauzier,L.P.T.Kerklaan,and J.H.Huijsing,“A100-MHz100-dB operational amplifier with multipath nested Miller compensation structure,”IEEE J.Solid-State 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