eda数字钟实验设计
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when "101"=>mseg<=mf;outbit<="100000";
when others=>null;
end case;
end process;
p6:process(st)
begin
case mseg is
when "0001"=> outseg1<="0110000";
when "0010"=> outseg1<="1101101";
when "1010"=> outseg2<="1110111";
when "1011"=> outseg2<="0011ห้องสมุดไป่ตู้11";
when "1100"=> outseg2<="1001110";
when "1101"=> outseg2<="0111101";
when "1110"=> outseg2<="1001111";
end if;
end if;
end if;
end process;
p4:process (fpa)
begin
if (fpa'event and fpa='1') then
st<=st+1;
end if;
end process;
p5:process (st) begin
case st is
when "000"=>mseg<=ma;outbit<="000001";
p7:process(st) begin
case mseg is
when "0001"=> outseg2<="0110000";
when "0010"=> outseg2<="1101101";
when "0011"=> outseg2<="1111001";
when "0100"=> outseg2<="0110011";
《EDA技术与应用》实验报告
姓名
孔亚男
学号
3118020007
专业年级
11级电子信息工程
同组同学姓名
刘留
同组同学学号（与左边姓名对应）
3118020002
实验题目
数字钟的设计
实验目的
熟悉EDA技术开发流程并应用，设计数字钟
实验原理
数字钟电路设计要求所设计电路就有以下功能：用6位数码管显示时、分、秒（按00:00:00～23:59:59显示），能高电平清零和高电平使能计数。
when "1111"=> outseg2<="1000111";
when others=> outseg2<="1111110";
end case;
end process;
end a_counter;
注：每个同学都需要写实验报告。若发现同一小组同学的实验报告完全相同，该小组同学全部给60分。
本人在实验中所起的作用
输入vhdl语句，和同学一起检查完成设计。
附录
（原理图或VHDL代码）
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity szz is
port(inclk,enable,reset:in std_logic;
when "0011"=> outseg1<="1111001";
when "0100"=> outseg1<="0110011";
when "0101"=> outseg1<="1011011";
when "0110"=> outseg1<="1011111";
when "0111"=> outseg1<="1110000";
me<="0000";mf<="0000";
else
ifme=9 then
mf<=mf+1;
me<="0000";
else
me<=me+1;
end if;
end if;
else
md<=md+1;
end if;
else
mc<=mc+1;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
实验内容
参考天煌教仪，《KHF-4型实验指导书》实验七完成设计数字钟，硬件检验实现。
实验步骤
输入szz.vhdl文件，编译，创建工程，在硬件上检验。
实验结果及分析
硬件验证结果
实验过程中所遇到的问题及相应的解决方法
硬件检验时第二个数码管不能正确显示，检查比较后才发现是译码出了问题，改正后显示正确,但频率不是1Hz，时间显示太快，经过同学研究后改正lm为11057，才得到1Hz。
outseg1,outseg2:out std_logic_vector(6 downto 0);
outbit:out std_logic_vector(5 downto 0));
end szz;
architecture a_counter of szz is
signal ma,mb,mc,md,me,mf,mseg:std_logic_vector(3 downto 0);
when "1101"=> outseg1<="0111101";
when "1110"=> outseg1<="1001111";
when "1111"=> outseg1<="1000111";
when others=> outseg1<="1111110";
end case;
end process;
if lm=11057 then
lm<="00000000000000";fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
p2:process(fpa)
begin
if (fpa'event and fpa='1') then
ifhm=499 then
signal lm,hm:std_logic_vector(13 downto 0);
signal fpa,fpb:std_logic;
signal st:std_logic_vector(2 downto 0);
begin
p1:process(inclk)
begin
if (inclk'event and inclk='1') then
hm<="00000000000000";fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
p3:process(fpb) begin
ifreset='1' then
ma<="0000";mb<="0000";mc<="0000";md<="0000";me<="0000";mf<="0000";
elsif (fpb'event and fpb='1') then
if enable='1' then
ifma=9 then
ma<="0000";
ifmb=5 then
mb<="0000";
ifmc=9 then
mc<="0000";
ifmd=5 then
md<="0000";
if(me=3 and mf=2) then
when "1000"=> outseg1<="1111111";
when "1001"=> outseg1<="1111011";
when "1010"=> outseg1<="1110111";
when "1011"=> outseg1<="0011111";
when "1100"=> outseg1<="1001110";
when others=>null;
end case;
end process;
p6:process(st)
begin
case mseg is
when "0001"=> outseg1<="0110000";
when "0010"=> outseg1<="1101101";
when "1010"=> outseg2<="1110111";
when "1011"=> outseg2<="0011ห้องสมุดไป่ตู้11";
when "1100"=> outseg2<="1001110";
when "1101"=> outseg2<="0111101";
when "1110"=> outseg2<="1001111";
end if;
end if;
end if;
end process;
p4:process (fpa)
begin
if (fpa'event and fpa='1') then
st<=st+1;
end if;
end process;
p5:process (st) begin
case st is
when "000"=>mseg<=ma;outbit<="000001";
p7:process(st) begin
case mseg is
when "0001"=> outseg2<="0110000";
when "0010"=> outseg2<="1101101";
when "0011"=> outseg2<="1111001";
when "0100"=> outseg2<="0110011";
《EDA技术与应用》实验报告
姓名
孔亚男
学号
3118020007
专业年级
11级电子信息工程
同组同学姓名
刘留
同组同学学号（与左边姓名对应）
3118020002
实验题目
数字钟的设计
实验目的
熟悉EDA技术开发流程并应用，设计数字钟
实验原理
数字钟电路设计要求所设计电路就有以下功能：用6位数码管显示时、分、秒（按00:00:00～23:59:59显示），能高电平清零和高电平使能计数。
when "1111"=> outseg2<="1000111";
when others=> outseg2<="1111110";
end case;
end process;
end a_counter;
注：每个同学都需要写实验报告。若发现同一小组同学的实验报告完全相同，该小组同学全部给60分。
本人在实验中所起的作用
输入vhdl语句，和同学一起检查完成设计。
附录
（原理图或VHDL代码）
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity szz is
port(inclk,enable,reset:in std_logic;
when "0011"=> outseg1<="1111001";
when "0100"=> outseg1<="0110011";
when "0101"=> outseg1<="1011011";
when "0110"=> outseg1<="1011111";
when "0111"=> outseg1<="1110000";
me<="0000";mf<="0000";
else
ifme=9 then
mf<=mf+1;
me<="0000";
else
me<=me+1;
end if;
end if;
else
md<=md+1;
end if;
else
mc<=mc+1;
end if;
else
mb<=mb+1;
end if;
else
ma<=ma+1;
实验内容
参考天煌教仪，《KHF-4型实验指导书》实验七完成设计数字钟，硬件检验实现。
实验步骤
输入szz.vhdl文件，编译，创建工程，在硬件上检验。
实验结果及分析
硬件验证结果
实验过程中所遇到的问题及相应的解决方法
硬件检验时第二个数码管不能正确显示，检查比较后才发现是译码出了问题，改正后显示正确,但频率不是1Hz，时间显示太快，经过同学研究后改正lm为11057，才得到1Hz。
outseg1,outseg2:out std_logic_vector(6 downto 0);
outbit:out std_logic_vector(5 downto 0));
end szz;
architecture a_counter of szz is
signal ma,mb,mc,md,me,mf,mseg:std_logic_vector(3 downto 0);
when "1101"=> outseg1<="0111101";
when "1110"=> outseg1<="1001111";
when "1111"=> outseg1<="1000111";
when others=> outseg1<="1111110";
end case;
end process;
if lm=11057 then
lm<="00000000000000";fpa<=not fpa;
else
lm<=lm+1;
end if;
end if;
end process;
p2:process(fpa)
begin
if (fpa'event and fpa='1') then
ifhm=499 then
signal lm,hm:std_logic_vector(13 downto 0);
signal fpa,fpb:std_logic;
signal st:std_logic_vector(2 downto 0);
begin
p1:process(inclk)
begin
if (inclk'event and inclk='1') then
hm<="00000000000000";fpb<=not fpb;
else
hm<=hm+1;
end if;
end if;
end process;
p3:process(fpb) begin
ifreset='1' then
ma<="0000";mb<="0000";mc<="0000";md<="0000";me<="0000";mf<="0000";
elsif (fpb'event and fpb='1') then
if enable='1' then
ifma=9 then
ma<="0000";
ifmb=5 then
mb<="0000";
ifmc=9 then
mc<="0000";
ifmd=5 then
md<="0000";
if(me=3 and mf=2) then
when "1000"=> outseg1<="1111111";
when "1001"=> outseg1<="1111011";
when "1010"=> outseg1<="1110111";
when "1011"=> outseg1<="0011111";
when "1100"=> outseg1<="1001110";
