ON 安森美晶闸管

晶闸管的结构原理及应用1. 晶闸管的概述晶闸管（Thyristor）是一种主要用于电能控制的半导体器件，广泛应用于电力电子技术领域。

晶闸管具有高压、大电流、能耗低、可靠性好等特点，被广泛应用于家电、工业控制、交通运输等领域。

2. 晶闸管的结构原理晶闸管的结构采用P-N-P-N四层结构，主要由控制极（G：Gate）、阳极（A：Anode）、阴极（K：Cathode）三个电极组成。

其结构和工作原理如下：•P层：阳极侧为P型半导体，控制极侧为薄的N型半导体层；•N层：阳极侧为N型半导体，控制极侧为一薄层的P型半导体层；•控制极：通过控制极加上一个触发脉冲，使得晶闸管的导通；•阳极：负责控制晶闸管的输出电流；•阴极：负责晶闸管的接地。

3. 晶闸管的工作原理晶闸管的工作原理可分为四个状态：关断（Off）、导通（On）、保持（Hold）、关断恢复（Off Recovery）。

1.关断状态：晶闸管在没有施加控制信号时处于关断状态，此时无法通过阳极和控制极之间的电流。

晶闸管的控制极与阳极之间存在电压可能会使其进入导通状态；2.导通状态：当控制极与阳极之间施加一个足够大的正向电压时，晶闸管进入导通状态。

此时，晶闸管的阳极和控制极之间的电流将开始流动；3.保持状态：在晶闸管进入导通状态后，控制极与阳极之间的电压可以降至较低水平，晶闸管仍然保持导通状态。

然而，如果该电压降至一定程度以下，则晶闸管将自动进入关断状态；4.关断恢复状态：当控制极与阳极之间的电压降至负值时，晶闸管将从导通状态恢复到关断状态。

4. 晶闸管的应用由于晶闸管具有可控性强、效率高、可靠性好等优点，被广泛应用于以下领域：•电力调节：晶闸管可用于交流电压调节，实现对电力的控制。

例如，晶闸管可以用于家庭用电中的调光灯、风扇等电器，以及电力工业中的电动机调速器、变频器等设备；•电流控制：晶闸管可用于控制电流的大小和方向。

例如，晶闸管可以用于电焊机，控制焊接电流，使焊接效果更加稳定和高效；•能量回收：晶闸管可以将电能回收并用于其他用途。

SymbolV DS V GSI DM T J , T STGSymbolTyp Max 5662.581110R θJL4048Absolute Maximum Ratings T A =25°C unless otherwise noted Parameter MaximumUnits Drain-Source Voltage 20V Gate-Source Voltage ±8V AT A =70°C 4.2Pulsed Drain Current B20Continuous DrainCurrent AT A =25°C I D 5T A =70°C1.28W Power DissipationT A =25°C P D 2Steady-State °C/W Junction and Storage Temperature Range -55 to 150°CThermal Characteristics Maximum Junction-to-Lead CSteady-State°C/WParameterUnits Maximum Junction-to-Ambient A t ≤ 10s R θJA °C/W Maximum Junction-to-Ambient A AO9926Dual N-Channel Enhancement Mode Field Effect TransistorFeb 2003FeaturesV DS (V) = 20V I D = 5AR DS(ON) < 50m Ω (V GS = 4.5V)R DS(ON) < 65m Ω (V GS = 2.5V)R DS(ON) < 90m Ω (V GS = 1.8V)General DescriptionThe AO9926 uses advanced trench technology to provide excellent R DS(ON) and low gate charge. They offer operation over a wide gate drive range from 1.8V to 8V. The two devices may be used individually, in parallel or to form a bidirectional blocking switch.G1S1G2S2D1D1D2D212348765G1D1S1G2D2S2SOIC-8Alpha & Omega Semiconductor, Ltd.查询AO9926供应商捷多邦，专业PCB打样工厂，24小时加急出货SymbolMin TypMaxUnits BV DSS 20V 1T J =55°C5I GSS 100nA V GS(th)0.40.61V I D(ON)15A 4050T J =125°C56705465m Ω7290m Ωg FS 11S V SD 0.761V I S2A C iss 436pF C oss 66pF C rss 44pF R g3ΩQ g 5.54nC Q gs 1.26nC Q gd 0.52nC t D(on)5ns t r 7ns t D(off)29ns t f 6.2ns t rr 13.7ns Q rr3.8nCI F =5A, dI/dt=100A/µsI F =5A, dI/dt=100A/µsElectrical Characteristics (T J =25°C unless otherwise noted)ParameterConditions STATIC PARAMETERS Drain-Source Breakdown Voltage I D =250µA, V GS =0V I DSS Zero Gate Voltage Drain Current V DS =16V, V GS =0VµA Gate-Body leakage current V DS =0V, V GS =±8V Gate Threshold Voltage V DS =V GS I D =250µA On state drain currentV GS =10V, V DS =5V R DS(ON)Static Drain-Source On-ResistanceV GS =4.5V, I D =5Am ΩV GS =1.8V, I D =2AV GS =2.5V, I D =4A V GS =0V, V DS =0V, f=1MHzForward TransconductanceV DS =5V, I D =5ADiode Forward Voltage I S =1A,V GS =0V Maximum Body-Diode Continuous CurrentDYNAMIC PARAMETERS Input Capacitance V GS =0V, V DS =10V, f=1MHz Output Capacitance Reverse Transfer Capacitance Turn-On Rise Time Turn-Off DelayTime Gate resistanceBody Diode Reverse Recovery TimeBody Diode Reverse Recovery Charge Turn-Off Fall TimeSWITCHING PARAMETERS Total Gate Charge V GS =4.5V, V DS =10V, I D =5AGate Source Charge Gate Drain Charge Turn-On DelayTime V GS =5V, V DS =10V, R L =2Ω, R GEN =6ΩA: The value of R θJA is measured with the device mounted on 1in 2FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The value in any a given application depends on the user's specific board design. The current rating is based on the t ≤ 10s thermal resistance rating.B: Repetitive rating, pulse width limited by junction temperature.C. The R θJA is the sum of the thermal impedence from junction to lead R θJL and lead to ambient.D. The static characteristics in Figures 1 to 6 are obtained using 80 µs pulses, duty cycle 0.5% max.E. These tests are performed with the device mounted on 1 in 2FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The SOA curve provides a single pulse rating.Alpha & Omega Semiconductor, Ltd.。

安森美半导体推出新的晶闸管浪涌保护器件系列安森美半导体针对电信应用推出新的NPxxx 系列晶闸管浪涌保护器件(TSPD)，扩充了公司的电路保护解决方案阵容。

NPxxx 系列的44 款器件为中心局(CO)、接入端和用户前端设备中电信电路提供过压保护。

这系列器件的应用包括调制解调器(MODEM)、住宅网关、数字用户线路接入复用器(DSLAM)和集成语音数据(IVD)卡。

这些器件同时提供受业界青睐的DO-214AA 表面贴装封装(SMB)和强韧的DO-15 轴向引线封装，可靠且经济。

用作次级保护电路的一部分时，这些器件将电能转移出受保护电路来提供过压保护。

NPxxx 器件获UL497A 认证，在电子应用中采用这些器件就能够符合GR-1089-CORE、ITUK.20/K.21/K.45、IEC 61000-4-5、IEC 60950、YD/T 993、YD/T 950 和YD/T 1082 等不同规范的要求。

安森美半导体亚太区标准产品部市场营销副总裁麦满权说：“安森美半导体致力于为客户面对的日益复杂的电路保护问题提供解决方案。

除了NPxxx系列器件，我们还将推出其它的电路保护解决方案，为当今电信系统设计人员解决他们各种的电路保护挑战。

”器件的功能特性这44 款新的NPxxx 器件是大浪涌电流TSPD，保护电压范围从64 到350 伏(V)之间，提供额定浪涌电流为50、80 和100 安培(A)等不同版本。

这些器件限制电压，并将浪涌电流转移至地。

它们属于双向保护器件，因此能够在一个封装中提供两个器件的功能，节省出电路板弥足珍贵的空间。

基本上，这些器件在过压发生时进行“消弧”——将可能带来潜在损伤的电能转移出敏感电路或器件。

一旦瞬态过压状况过去，这些器件就会恢复到它们正常的“关闭”或。

安森美半导体推出8款新器件用于消费和工业应用2008 年11 月13 日&ndash; 全球领先的高性能、高能效硅解决方案供应商安森美半导体(ON Semiconductor，美国纳斯达克上市代号：ONNN)推出8 款新的MOSFET 器件，专门为中等电压开关应用而设计。

这些MOSFET 非常适用于直流马达驱动、LED 驱动器、电源、转换器、脉宽调制(PWM)控制和桥电路中，这些应用讲究二极管速度和换向安全工作区域(SOA)，安森美半导体的新MOSFET 器件提供额外的安全裕量，免应用受未预料的电压瞬态影响。

这些新的60 伏(V)器件均是单N 沟道MOSFET，提供较低的导通阻抗(RDS(on))，将功率耗散降到最低。

这些器件更提供低门电荷和低门电荷比，降低传导和开关损耗。

所有这些性能特性，使电源子系统能效更高。

安森美半导体MOSFET 产品部副总裁兼总经理Paul Leonard 说：这些新的中等电压器件，壮大了安森美半导体优异的、配合市场需要的功率MOSFET阵容。

我们计划持续推出针对市场应用的MOSFET 解决方案，满足我们消费和工业应用的扩大客户需求，强化安森美半导体高能效电源开关解决方案供应商的业界领先地位。

器件这些器件提供宽的规范点范围，让设计人员能够灵活地选择采用DPAK、D2PAK 和TO-220 封装的最优导通阻抗(RDS(on))和门电荷组合。

器件型号封装VDS (V)ID (A)Rdson (m&Omega;) @ 10 VQg (typ) (nc)EAS (mJ) NTB5411ND2PAK60758.592336NTP5411NTO-22060758.592336NTB5412ND2PAK60601462211NTP5412NTO- 22060601462211NTB5426ND2PAK6012051701000NTP5426NTO- 2206012051701000NTD5413NDPAK60452133101NTD5414NDPAK602037.521.2。

半导体分立器件企业名录全文共四篇示例，供读者参考第一篇示例：半导体分立器件是现代电子行业中不可或缺的一部分，其在电子设备中扮演着重要的角色。

随着半导体产业的快速发展，许多企业致力于研发和生产各种半导体分立器件，为各种电子产品提供了技术支持。

以下是一份关于半导体分立器件企业名录，介绍一些在这一领域中具有重要地位的企业。

1. 英飞凌半导体（Infineon Technologies）英飞凌半导体是一家总部位于德国的跨国半导体公司，专注于生产各种先进的半导体产品，包括功率半导体器件、传感器、微控制器和安全解决方案等。

该公司的产品广泛应用于汽车、工业、通讯和消费电子等领域，为客户提供优质的半导体解决方案。

2. 台积电（Taiwan Semiconductor Manufacturing Company，TSMC）台积电是全球领先的芯片制造公司之一，总部位于台湾。

该公司专注于生产先进的半导体分立器件，包括逻辑芯片、存储芯片、功率半导体和模拟器件等。

台积电致力于技术创新和持续发展，为全球客户提供高品质的半导体产品。

3. 意法半导体（STMicroelectronics）意法半导体是一家总部位于瑞士的半导体制造公司，其产品覆盖了智能手机、汽车、工业控制和消费电子等多个领域。

该公司专注于功率半导体、传感器和微控制器等产品的研发和生产，为客户提供全方位的半导体解决方案。

4. 硅力半导体（Silicon Labs）硅力半导体是一家总部位于美国的高科技公司，专注于生产和销售各类精密时钟、晶体振荡器和RF产品等。

该公司产品广泛应用于通讯、工业、汽车和消费电子等领域，为客户提供高性能的半导体器件解决方案。

5. 安森美半导体（ON Semiconductor）安森美半导体是一家跨国半导体生产公司，总部位于美国。

该公司专注于生产功率半导体器件、模拟器件和传感器等产品，广泛应用于汽车、工业控制、通讯和消费电子等领域，为客户提供创新、可靠的半导体产品。

AND8174/DNIS6111 Better ORing Diode Operation NotesPrepared by: Ryan Liu ON SemiconductorGeneral DescriptionThe NIS6111 is a simple and reliable device consisting of an integrated control IC with a low R DS(on) power MOSFET,using hybrid technology. It is designed to replace Schottky diodes in ORing applications to obtain higher system power efficiency. It can be connected to allow load sharing with automatic switchover of the load between two or more input power supplies. A single NIS6111 is able to run up to 20 A without any air flow. To meet high current requirement ( i.e. 60 A), the NIS6111 is designed to drive more than four paralleled additional NTD110N02 MOSFETs. The unique package design of NIS6111 offers higher thermal efficiency to minimize cooling requirements.This application note presents more details of the 30 A and 60 A demonstration boards. Both of them can be easily connected to power sources and loads for any test purpose.ApplicationsParalleled N + 1 Redundant Power Supplies Telecommunications Power SystemsHigh−Reliability , Distributed Power NetworksNIS6111 Simplified Block DiagramReg_in (Pin 5): Input pin for internal voltage regulator.Bias (Pin 2): Output of internal voltage regulator. It is 5.0 V under normal operating conditions. It provides power for internal components only. No external connections are necessary at this pin.Gate (Pin 3): Gate driver output for internal and external N−Channel MOSFET. The gate turn on time is typically 22 nS.Source (Pin 1): Power input, connected to the system power source output. This is the anode of the rectifier.Drain (Pin 4): Power output, connected to the system load. This pin is the cathode of the rectifier and will be common to the cathodes of the other rectifiers, when used in a high side configuration.UVLO Function: The UVLO is set for a trip point of 3.85 V rising and 3.65 V falling of the bias supply. Before the bias voltage reaches 3.85 V , the UVLO disables the gate driver. As soon as the bias voltage reaches 3.85 V or more,the UVLO enables the gate driver.Figure 1.Reg_inBias Gate Drain APPLICATION NOTEV_capTTFigure 2.NIS6111 Basic Operating Circuit and SequenceThe BERS will function as a normal silicon rectifier ifthere is no bias power applied to the Reg_in. In order toachieve the full benefit of the BERS internal MOSFET, theReg_in must be more than 6.0 volts above the source (anode)pin 1. This level will disable the UVLO and supply voltageto the input regulator.Figure 3. Basic Operation CircuitOutputLoadTiming Sequence: In the ORing applications, the Reg_inshould be energized before the forward current is applied tothe BERS. This recommended procedure allows the gatedrive control circuit to respond quickly to any currentpolarity changes.It is permissible to allow the voltage on Reg_in and theinput power supply (PS), V in to rise simultaneously. TheReg_in may trail the V in voltage, but these methods wouldallow body diode conduction during the interval whereReg_in is lower than V in plus the 6.0 threshold. This modeof operation will not damage the device as long as the powerdissipation does not cause the maximum junctiontemperature for the NIS6111 to be exceeded.Under no circumstance should the Reg_in voltage gomore negative than the pin 1 source (anode). It isrecommended that a signal diode (1N4148) be installed inseries with the Reg_in pin 5.The number of external MOSFETs recommended inTable 1 is based upon no airflow or heat sink other than thenormal printed circuits board (PCB) installation. The testdata is taken from the 60 A demonstration board. If aspecific system application already provides cooling airflow or metal heatsinking, then the actual number of addedMOSFETs may be decreased from the recommendation.Table 1. Recommended Selection of ExternalMOSFETs Based on Load CurrentsUnder No Air Flow and No Heat Sink ConditionRecommended SelectionMax Load CurrentRating (A)Single NIS611120NIS6111 and One NTD110N0230NIS6111 and Two NTD110N0240NIS6111 and Three NTD110N0250NIS6111 and Four NTD110N0260TEST CIRCUITFigure 4. Test CircuitPS1PS2R snub2C snub2Basic Test CircuitThe test circuit in Figure 4 is set to test peak reverse current and recovery time for multiple power source operation.With Vin_2 > Vin_1, the load current will flow through IC2 and its paralleled MOSFETs. After switching on S1(Shut Vin_2), IC1 and its paralleled MOSFETs will take over the power transfer path, and current will go through them instead of IC2 and its paralleled MOSFETs.Meanwhile, since V o > Vin_2 (after shutting Vin_2) a small amount of reverse current will be forced to go through IC1and its MOSFETs, which will terminate the conduction of this switch.Note that in ORing applications it is probable to have an instance where the PS voltages Vin_1, Vin_2 iterated up to Vin_n, are higher than the Reg_in power source. The signal blocking diodes must be used in series with each of the Reg_in pins to protect them from reverse voltages.The high switching speed of the BERS diode makes the distributed circuit board inductance and capacitancebecome non−trivial. The demonstration board has loops provided to monitor the currents with a suitable probe.Specific applications will have wire or PCB distribution bus inductances. The demonstration boards and specific systems have a combination of low ESR ceramic filter and some aluminum electrolytic (E−cap) type capacitors. The E−caps give some energy storage, but their ESRs provide the needed RLC circuit damping resistance. The type (KME, LXF,LXV) and Farad value can be selected for the optimum damping factor.The NIS6111 and any attendant NTD110N02’s require some amount of reverse current to achieve turn−off. This will generate some ½ Li 2 energy in the stray inductance which must be dissipated. For the 60 A demonstration board with four MOSFETs, the (turn−off) current will be about 5 A. This generates about 12.5 m Joule per m H of stray inductance. The snubber resistors Rsnub1, Rsnub2 and capacitors Csnub1 and Csnub2 must be applied across the BERS anode to cathode to absorb the energy and prevent undamped oscillations.Bias Power Circuit Notes: The ORing circuits are applied to protect power busses from an event (short circuit) that is not well controlled. As a result, the circuit must be resistant to unpredictable response of the external components. Most power supplies execute a controlled power−down after the overcurrent is detected. It is possible that a failing PS would not respond predictably and may cause voltage spikes as the short circuit bounces open and closed.The BERS is a 24 V part, and can tolerate over voltage from a 12 to 18 V bus. The NIS6201 V CC is rated at 18 Vdc and has an internal Zener. The boost converter NCP1403 V DD is rated at 6.0 V, and should have a 5.6 V Zener protection diode in parallel. Both of these voltage boosters should have a current limiting resistor in series with the respective power bus voltage and their V CC or V DD for protection from PS over−shoot.Using the NIS6111 in ORing circuitsThe NIS6111 is ideally suited to the ORing application as compared to the Schottky diodes, but there are subtle performance differences. Application note AND8189/D describes the reverse current required to switch off the NIS6111. The reverse current will be provided by the applications failing PS, as required by the power bus ORing design.The BERS Difference: The obvious advantage of the BERS over Schottky diodes is the low−loss, highly conductive switch path that it provides. The incredibly low R DS(on) of 4 m W creates an interesting situation. The benefit of low thermal loss is obvious. The side effect of the highly conductive channel is that relatively large currents can flow in either direction with an extremely small driving voltage. There is no barrier voltage or other effect that would give a zero−current condition the ability to switch the state of the device. The ON Semiconductor NIS6111 has a very sensitive comparator carefully placed near the FET. Yet it still requires about one amp of reverse current to generate sufficient offset voltage that can reset the device to its off state.The Schottky, or any other diode device which has a junction, also has a barrier voltage that must be overcome before current will flow. As the forward current in a Schottky diode falls and approaches zero, the diode forward voltage collapses to zero and effectively shuts off the conduction channel.Why Use ORing Diodes At All? ORing diodes are costly and they waste power. It is true that multiple power supplies will work if the outputs are just wired together in parallel. Two 5−volt AC/DC power supplies taken off the shelf and wired together in parallel will give five volts output when they are both powered up, but they may not share the load very well. The one with the highest set−point will provide almost all the current. But if one of them is powered off, the other will supply the entire load current. It will also bias up the output filter capacitor of the first (off) power supply. The ORing diodes are used for one single purpose; to protect the system power bus. If one of the power supplies has a failure in the output rectifier or filter capacitors that causes it to short−circuit, then the ORing diode protects the system bus from being shorted.The ORing diode will also prevent the system bus from dumping a charge current into a powered−down supply that is installed while the system is still on. This function is more the business of a hot−swap controller, but it also works with ORing diodes. The ORing system works best if the design has forced current sharing to get the greatest PS utilization. ORing does not protect the individual power supplies from catastrophic failures.Be aware of Schottky−specific design constraints: Schottky has been used for ORing for some time. The design and test specifications used in ORing applications may have included the non−ORing, junction diode properties for validation. Schottky ORing diode characteristic of zero−current switch−off may be an expected parameter even though this feature is not important for the function of PS ORing.Test procedures may use individual power supply de−activation by method of power−down or forced OVP, then the voltage of that PS is verified to be zero. This test method does not validate an ORing function, but it is easier and quicker to perform.The proper test method for ORing diode requires that the test unit power supply must be shorted or have an output current over load (OCP) applied.The proper test method for hot−swap must have the system powered up and functional with the test PS previously removed from the system. It must be “cold” or have no voltage on its output terminals. The input power to the test unit PS must be off at the start of the test and must remain off for the full length of the test. The test must begin with the insertion or connection of the cold power supply in the system. If the cold PS output stays near zero volts, the ORing diode passes the test. If the cold PS output is forced to some voltage higher than 0.5 volts, the diode fails the test.OVP Detection Notes: In some cases, the overvoltage protection (OVP) may be forced during test to validate that the OVP of an individual PS is functional at the end item test level. This test may also validate that the forced OVP results in a shut−down and detection for that particular supply. In most operating current ranges, the BERS will probably have a slightly higher positive ratio of dynamic impedance than the Schottky diode. Therefore the test PS will reach its OVP threshold then shut down before the bus exceeds the upper voltage limit. However, the power supply which shuts down will not sink enough reverse current to switch off the BERS ORing diode.The OVP disabled PS will stop driving current so the system bus does not OVP, but it also is not supplying power even though the outputs may be floating in the range of normal bus voltage. For good design practice, the system designer must use the OVP detection and not depend solely upon the power supply output voltage as a means of detecting power supply failures.Another OVP design problem that may be found in ORing systems with forced current sharing is that as one of the power supplies starts to over−voltage, it drives up the power bus voltage. The current sharing method would cause all power supplies in the system to raise their voltages together. Each of the power supplies has an OVP threshold that will not be identical to the others. Two or more power supplies could reach their separate OVP limits and shut down in sequence. Only one of the power supplies had the control loop fault yet it can cause the chain reaction of multiple PS shut downs.AND8174/D30 A DEMONSTRATION BOARDFigure 5. 30 A Demonstration Board SchematicFigure 6.NOTE:The selection of input and output capacitors vary, based on the PCB layout andthe maximum load in the applications.Figure 7. Top PCB Layout Figure 8. Bottom PCB LayoutTable 2 and Figure 9 present the current sharing data at different load conditions.Table 2. Current Sharing Test ResultsCurrent Sharing Rating (A)Load CurrentNIS6111NTD110N022.0 1.10.95.0 2.7 2.310 5.4 4.6158.07.02010.59.5251312301614Figure 9. Current Sharing vs. Load Current181********642005101520253035C U R R E N T R A T I N G (A )LOAD CURRENT (A)Table 3. Thermal Test ResultsUnder No Air Flow and No Heat Sink ConditionThermal DataLoad Current(A)NIS6111Max Temp (5C)NTD112N02Max Temp (5C)308378Reverse Current and Recovery Time Test ResultsFigure 10 shows the waveforms at a typical load condition (10 A). The reverse current is 1.5 A, the recovery time is 140 nS.In Figure 10, the slope (di/dt) of the waveform (Ch3) is a function of the parasitic inductance and capacitance of the system. With increasing the current path length and the component spaces on the PCB, decreasing the slope (di/dt).Ch1: Gate Voltage of NIS6111 (10 V/DIV)Ch2: Output Voltage (10 V/DIV)Ch3: Current Through NIS6111 (5.0 A/DIV)Figure 10.AND8174/DAND8174/D60 A DEMONSTRATION BOARD (continued)Figure 12.Figure 13. Top PCB Layout Figure 14. Bottom PCB Layout1160 A DEMONSTRATION BOARD (continued)Table 4 and Figure 15 present the current sharing data at different load conditions.Table 4. Current Sharing Test ResultsCurrent Sharing Ratings (A)Io (A)NIS6111M101M102M1035.0 1.3 1.1 1.1 1.210 2.6 2.4 2.2 2.415 4.0 3.63.4 3.620 5.44.8 4.85.0256.8 5.8 6.0 6.0308.47.47.07.4359.68.48.28.640119.79.59.84512.410.810.6115013.51211.51255151312.513Figure 15. Current Sharing vs. Load Currents1614121086420010203040506070C U R R E N T R A T I N G (A )LOAD CURRENT (A)Table 5. Thermal Test ResultsUnder No Air Flow and No Heat Sink ConditionDevices Max Load Current Rating (A)Max ThermalRating TypicalSingle NIS61112065NIS6111 and One NTD110N023078NIS6111 and Two NTD110N024081NIS6111 and Three NTD110N025082NIS6111 and Four NTD110N026086Reverse Current and Recovery Time Test ResultsFigure 16 presents the waveforms at a typical load condition (10 A). The reverse current is 3.4 A, the recovery time is 440 nS.ConclusionThe application note describes the NIS6111 device operation and the details of 30 A and 60 A demonstration boards.Figure 16.Ch1: Gate Voltage of NIS6111 (10 V/DIV)Ch2: Output Voltage (10 V/DIV)Ch3: Output Current (5.0 A/DIV)ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。

实现大功率DCDC电源转换，快来了解安森美全桥的LLC方案不断增加的开关电源功率密度，已经受到了无源器件尺寸的限制。

采用高频运行，可以大大降低无源器件（如变压器和滤波器）的尺寸，但过高的开关损耗势必成为高频运行的一大障碍。

LLC电路是由2个电感和1个电容构成的谐振电路，故称之为LLC，由于能实现软开关，有效地减小开关损耗和容许高频运行，所以在高频功率变换领域得到广泛的重视和研究。

LLC拓扑结构根据MOS管的配列可以分为半桥或全桥类型，半桥LLC一般用于小功率场合，具有开关管数量少等特点，全桥LLC开关管相对于半桥LLC多，适用于大功率场合。

想全面了解安森美(onsemi)全桥的LLC方案，这场线上研讨会不容错过。

产品秀安森美的NCP13992是一种用于半桥LLC的高性能电流模式控制器，该控制器内置600V门极驱动器，简化布局，减少了外部部件数量。

内置的欠电压输入功能简化了该控制器在所有应用中的实施。

在需要 PFC 前级的应用中，NCP13992 具有一个专门的输出来驱动 PFC 控制器。

此功能结合专门的跳周期(quiet skip)模式技术进一步提高了整个应用的轻负载能效。

基于LLC架构的NCP13992电路拓扑示例NCP13992 提供了一套保护功能，可实现在任何应用中的安全运行。

其中包括：过载保护、放置硬开关周期的过电流保护、欠电压检测、开路光耦合器检测、自动停滞时间调节、过电压(OVP) 和高温(OTP) 保护。

此外，NCP13992可配合PFC级工作，获得更高的效率以及轻载空载功耗，同时PFC可根据负载程度控制。

在轻载或故障时可使用动态自供电技术保证芯片运行和降低功耗。

可用于笔记本适配器、液晶电视、大功率适配器、电脑电源、工业及医疗应用和照明应用等。

安森美半导体推出新的浪涌保护器件安森美半导体宣布推出新的低电容晶闸管浪涌保护器件(T SPD )系列,专为保护下一代高速电信设备而设计。

新器件杰出地平衡小尺寸和高浪涌能力,同时维持低电容和低泄漏,是先进电信产品的极佳组合。

N P 0080、N P 0120和N P0160低电容、低泄漏T SPD 器件采用节省空间的TS O P 25封装,保护数字用户线路(D S L )芯片组和线路驱动器。

虽然在正常电路工作期间它们本质上并不参与工作,但在发生浪涌和静电放电(ES D )事件时它们发挥极佳的电路保护性能。

它们在工作电压范围内拥有小于3皮法(pF )的固有低差分电容,能够排除高速数据线路上的信号失真。

在发生8x 20微秒(uS )浪涌事件时,具有大于50安(A )的电流承受能力。

它们通常在接入和客户端设备(CP E )的D S L 隔离变压器和D S L 线路驱动器之间用作第三级保护。

安森美半导体新的TSPD 系列还包括以高性价比S M B 封装的超低电容N P 2M C 系列。

具有低于30pF 的超低电容,用于额定电流100A 的器件,为设计人员在不同高速应用中提供替代气体放电管(GD T )的选择。

由于具有超低的关态电容,N P 2M C 器件为V D S2+和T 1�E1电路等高速设备提供微乎其微的信号失真。

低额定关态电容转化为极低的差分电容,为所应用的电压或频率提供极佳的线性度。

它们通常在D S L 隔离变压器的线路端用作次级保护器。

这些T SPD 器件对于开发互联网协定数字用户线路接入复用器(I P -D S LAM )、家庭网关和调制解调器、语音IP (V o I P )及其它设备等可靠的接入和客户端设备而言必不可少,帮助设计人员符合标准,并将对信号质量的影响减至最小。

希　雷创立达科技推出新一代微触发单向可控硅2008年8月11日,国内领先功率半导体器件、芯片和模块供应商无锡创立达科技有限公司宣布成功推出新一代微触发单向可控硅T SE 2P 4M 和TSE 405。

晶闸管工作原理晶闸管（Thyristor）是一种半导体器件，具有电流控制功能。

它由四个层次的PNPN结构组成，其中有三个电极：阳极（A）、阴极（K）和控制极（G）。

晶闸管的工作原理是基于PNPN结构的特性以及控制极的作用。

当晶闸管的阳极与阴极之间施加一个正向电压时，PNPN结构中的两个PN结会被正向偏置，形成一个低阻抗通路，电流可以流过晶闸管。

这种状态下，晶闸管处于导通状态，称为正向导通。

然而，要使晶闸管进入导通状态，还需要在控制极施加一个正脉冲信号。

当控制极施加一个正脉冲信号时，晶闸管会进入一个临界状态，称为触发状态。

在这个状态下，晶闸管的PNPN结中的P区电子会被注入到N区，从而形成一个导电通道，使得晶闸管能够导通。

一旦晶闸管进入导通状态，它将保持导通，直到电流通过晶闸管降为零或者施加一个负脉冲信号到控制极。

当电流降为零时，晶闸管会进入封锁状态，无法再导通。

如果施加一个负脉冲信号到控制极，晶闸管会被迅速关断，回到封锁状态。

晶闸管的工作原理可以用以下几个步骤来总结：1. 施加正向电压：在阳极和阴极之间施加一个正向电压，使得PNPN结的两个PN结正向偏置。

2. 施加正脉冲信号：在控制极施加一个正脉冲信号，使得晶闸管进入触发状态，形成导电通道。

3. 进入导通状态：晶闸管进入导通状态，电流可以流过晶闸管。

4. 保持导通或关断：晶闸管将保持导通状态，直到电流降为零或者施加一个负脉冲信号到控制极。

晶闸管广泛应用于电力电子领域，如变流器、交流调速器、交流电压调节器等。

它具有可控性强、耐压能力高、功率损耗低等优点，被广泛应用于电力系统中的高压、大功率的控制和调节场合。

总结起来，晶闸管的工作原理是基于PNPN结构和控制极的作用，通过施加正向电压和正脉冲信号，使晶闸管进入导通状态，从而实现电流的控制和调节。

它是一种重要的电力电子器件，对于电力系统的稳定运行和高效能耗具有重要意义。