芯片TLC549介绍(中文的)

摘要在日常生活和各种电学实验中电压、电流和电阻三个量经常需要被测量，其中以电压的测量最多，这就要用到电压表。

与传统的指针电压表相比，数字电压表具有很多优点。

电压表的数字化，是将连续的模拟量(如直流电压)转换成不连续的离散的数字形式并加以显示。

这有别于传统的以指针与刻度盘进行读数的方法，避免了读数的视差和视觉疲劳，而且显示的范围宽，分辨率高。

由于CMOS 技术的发展．集成电路的功耗变得很小．即发热量很小，这样就可以在同一块芯片上集成更多的元件，形成大规模或超大规模集成电路，因此数字电压表的集成度高、功耗小、抗干扰能力强。

直流数字电压表本身可以扩展成交流电压表、交直电流表、峰值表、功率表等，还可以附加智能化。

本设计采用TLC549芯片将模拟量转化为数字量，通过单片机AT89C52与LCD1602显示出来。

关键词：数字电压表TLC549 AT89C52 LCD1602AbstractIn daily life and various electrical experiments, voltage, current, resistance, the three volumes often needs to be measured, most of which measure voltage, which use the voltage meter. And compared to the traditional pointer voltmeter, digital voltage meter has many advantages. Digital voltage meter, is the continuous analog (such as DC voltage) into discrete discontinuous and display them in digital form. This is different from the traditional to the pointer and dial for readings and preventing the reading of the disparity and visual fatigue, and display wide range of high resolution. IC power consumption becomes very small. That heat is very small, so that you can chip in with an additional component, the formation of large-scale or large scale integrated circuits, the digital voltage meter high integration, low power consumption, anti-jamming capability. DC digital voltage meter itself can be extended into the AC voltmeter, AC-DC current meter, peak meter, power meter, etc., you can also add intelligent. This design uses TLC549 chip analog to digital conversion by SCM AT89C52 and LCD1602 displayKey words :Digital V oltmeter TLC549 AT89C52 LCD1602目录前言 (5)第一章绪论 (6)第一节单片机的定义 (6)第二节单片机的发展历程 (6)第三节单片机的应用领域 (7)第四节单片机学习应用的六大重要部分 (8)第二章总体设计 (12)第一节设计实现功能 (12)第二节总体框图 (12)第三章单元电路设计 (13)第一节模数转换电路 (13)第二节单片机AT89C52 (17)第三节液晶LCD1602显示 (24)第四章程序流程图 (26)第五章总体电路图 (27)结束语 (28)参考文献 (29)附录 (30)致谢 (35)前言数字电压表用于测量电压的数字仪表。

任务书1、查阅资料，熟悉硬件和软件；（所使用硬件芯片型号，所使用软件编辑环境）2、掌握TLC549芯片和TLC5615芯片的特性，引脚功能。

3、确定详细软件设计方案，画程序流程图4、根据TLC549的时序图，使用汇编语言/C语言编写单片机STC89C52与TLC549的软件通信程序代码。

实现模/数转换功能。

5、根据TLC5615的时序图，使用汇编语言/C语言编写单片机STC89C52与TLC5615的软件通信程序代码。

实现数/模转换功能。

6、整合模数、数模转换代码，实现信号发生器在MAX1247输入端输入正弦波（频率不限），示波器在TLC5615输出端测量到同样的正弦波,记录输出波形。

7 .撰写课程设计报告。

目录1、绪论 (XX)2、方案论证（规划、选定） (XX)3、方案说明（设计）XX (XX)4、硬件方案设计 (XX)5、软件方案设计 (XX)6、调试 (XX)6、技术小结（结束语） (XX)8、参考文献 (XX)9、附录（源程序代码、电路图等） (XX)1.绪论本实验主要是基于单片机微型控制器的控制，实现将模拟信号转换成数字信号的一个简单实验。

通过这个实验，可以为广大研究人员提供一个比较系统的模数数模转换基础资料，以便于将模拟信号转换为数字信号或将数字信号转换成模拟信号。

2.方案论证2.1.试验原理本实验主要是通过单片机stc89c52芯片控制模数转换芯片tlc549将所给模拟信号转换成数字信号，然后将数字信号读进数模转换芯片tlc5615，从输出端口将转换后的信号输出来。

可用图1简洁明了地表现出来：2.2模/数转换器（1）模/数转换器的作用TLC549是一种高性能的８位A/D转换器，它以８位开关电容逐次逼近的方法实现A/D转换，本实验通过用该芯片采集模拟量，然后将采集到的模拟量转换为数字量后送至单片机。

（2）芯片特性；TLC549芯片, 可与通用微处理器、控制器通过I/ O CLOCK、CS、DATA OU T 三条口线进行串行接口。

⽬前常⽤的AD芯⽚（TI公司）⽬前AD/DA的常⽤芯⽚介绍：TI公司AD/DA器件：1)TLC548/549TLC548和TLC549是以8位开关电容逐次逼近A/D转换器为基础⽽构造的CMOSA/D转换器。

它们设计成能通过3态数据输出与微处理器或外围设备串⾏接⼝。

TLC548和TLC549仅⽤输⼊/输出时钟和芯⽚选择输⼊作数据控制。

TLC548的最⾼I/OCLOCK 输⼊频率为2.048MHz,⽽TLC549的I/OCLOCK输⼊频率最⾼可达1.1MHz。

TLC548和TLC549的使⽤与较复杂的TLC540和TLC541⾮常相似；不过，TLC548和TLC549提供了⽚内系统时钟，它通常⼯作在4MHz且不需要外部元件。

⽚内系统时钟使内部器件的操作独⽴于串⾏输⼊/输出端的时序并允许TLC548和TLC549象许多软件和硬件所要求的那样⼯作。

I/OCLOCK和内部系统时钟⼀起可以实现⾼速数据传送，对于TLC548为每秒45,500次转换，对于TLC549为每秒40,000次的转换速度。

TLC548和TLC549的其他特点包括通⽤控制逻辑，可⾃动⼯作或在微处理器控制下⼯作的⽚内采样-保持电路，具有差分⾼阻抗基准电压输⼊端，易于实现⽐率转换(ratiometricconversion).定标(scaling)以及与逻辑和电源噪声隔离的电路。

整个开关电容逐次逼近转换器电路的设计允许在⼩于17µs的时间内以最⼤总误差为±0.5最低有效位(LSB)的精度实现转换。

2)TLV5616TLV5616是⼀个12位电压输出数模转换器(DAC),带有灵活的4线串⾏接⼝，可以⽆缝连接TMS320.SPI.QSPI和Microwire串⾏⼝。

数字电源和模拟电源分别供电，电压范围2.7～5.5V。

输出缓冲是2倍增益rail-to-rail输出放⼤器，输出放⼤器是AB类以提⾼稳定性和减少建⽴时间。

rail-to-rail输出和关电⽅式⾮常适宜单电源。

串行AD转换器TLC549的应用设计
一、TLC549的简介
TLC549是一种高精度的8位左对齐的模拟-数字转换器，它由Texas Instruments公司公司开发。

使用了低功耗CMOS和 Flash-Plus（快速结构）技术，它具有较高的性能，抗干扰性和功耗低的特点。

它的电源电压
为3 V - 5 V，并具有外部时钟，转换速度可达6个MHz，带宽为200 KHz，转换精度高达8位。

根据TLC549的特性，它可以实现高精度，高带宽，高速率，低功耗，低失真和低噪声等功能，因此，它在很多领域中得到了广泛的应用。

（1）量测系统
应用TLC549可以设计一种低功耗的量测系统，因为TLC549可以将模
拟量（如温度、湿度、压力等）转换成数字量，并将数字量输出至数字接口，从而实现模拟信号检测以及声音检测的功能。

TLC549采用单片机的
接口结构，它的带宽高达200KHz，转换精度高达8位，可以满足多种精度，带宽的需求。

（2）无线传感器系统
TLC549可以用于设计无线传感器系统，它可以将模拟信号转换成数
字信号，然后将数字信号传输至接收端，进而实现无线传感器的功能。

TLC549能够将模拟信号转换为8位高精度的数字信号，并将数据以比特
的形式传输出去，降低了传输成本，实现了真正的无线传感器系统。

8位串行模数转换器TLC548、TLC549的应用1. 概述TLC548，TLC549是美国德州仪器公司生产的8位串行A/D转换器芯片，可与通用微处理器、控制器通过CLK、CS、DATA OUT三条口线进行串行接口。

具有4MHz片内系统时钟和软、硬件控制电路，转换时间最长17μs，TLC548允许的最高转换速率为45 500次/s，TLC549为40 000次/s。

总失调误差最大为±0.5LSB，典型功耗值为6mW。

采用差分参考电压高阻输入，抗干扰，可按比例量程校准转换范围，V REF-接地，V REF+－V REF-≥1V，可用于较小信号的采样。

2. 芯片简介2.1 TLC548、TLC549的内部框图和管脚名称TLC548、TLC549的内部框图和引脚名称如图1所示。

2.2 极限参数TLC548/549的极限参数如下：●电源电压：6.5V；●输入电压范围：0.3V～V CC＋0.3V；●输出电压范围：0.3V～V CC＋0.3V；●峰值输入电流(任一输入端)：±10mA；●总峰值输入电流(所有输入端)：±30mA；●工作温度：TLC548C、TLC549C：0℃～70℃TLC548I、TLC549I：－40℃～85℃TLC548M、TLC549M：－55℃～125℃3. 工作原理TLC548、TLC549均有片内系统时钟，该时钟与I/O CLOCK是独立工作的，无须特殊的速度或相位匹配。

其工作时序如图2所示。

当CS为高时，数据输出(DATA OUT)端处于高阻状态，此时I/O CLOCK 不起作用。

这种CS控制作用允许在同时使用多片TLC548、TLC549时，共用I/O CLOCK，以减少多路(片)A/D并用时的I/O控制端口。

一组通常的控制时序为：(1)将CS置低。

内部电路在测得CS下降沿后，再等待两个内部时钟上升沿和一个下降沿后，然后确认这一变化，最后自动将前一次转换结果的最高位(D7)位输出到DATA OUT端上。

TLC548，TLC549 8位串行A/D转换器芯片介绍TLC548，TLC549是美国德州仪器公司生产的8位串行A/D转换器芯片，可与通用微处理器、控制器通过I/O CLOCK、CS、DATA OUT三条口线进行串行接口。

具有4MHz片内系统时钟和软、硬件控制电路，转换时间最长17μs，TLC548允许的最高转换速率为45 500次/s，TLC549为40 000次/s。

总失调误差最大为±0.5LSB，典型功耗值为6mW。

采用差分参考电压高阻输入，抗干扰，可按比例量程校准转换范围，VREF-接地，VREF+－VREF-≥1V，可用于较小信号的采样。

2. 芯片简介2.1 TLC548、TLC549的内部框图和管脚名称TLC548、TLC549的内部框图和引脚名称如图1所示。

2.2 极限参数TLC548/549的极限参数如下：●电源电压：6.5V；●输入电压范围：0.3V～VCC＋0.3V；●输出电压范围：0.3V～VCC＋0.3V；●峰值输入电流(任一输入端)：±10mA；●总峰值输入电流(所有输入端)：±30mA；●工作温度：TLC548C、TLC549C：0℃～70℃TLC548I、TLC549I：－40℃～85℃TLC548M、TLC549M：－55℃～125℃3. 工作原理TLC548、TLC549均有片内系统时钟，该时钟与I/O CLOCK是独立工作的，无须特殊的速度或相位匹配。

其工作时序如图2所示。

当CS为高时，数据输出(DATA OUT)端处于高阻状态，此时I/O CLOCK不起作用。

这种CS控制作用允许在同时使用多片TLC548、TLC549时，共用I/O CLOCK，以减少多路(片)A/D并用时的I/O 控制端口。

一组通常的控制时序为：(1)将CS置低。

内部电路在测得CS下降沿后，再等待两个内部时钟上升沿和一个下降沿后，然后确认这一变化，最后自动将前一次转换结果的最高位(D7)位输出到DATA OUT端上。

TLC549 8bit 模数转换和串行控制●微处理器外设和独立操作●8bit分辨率A/D转换●差分参考输入电压●转化时间最大…17us●每秒访问总次数和转换周期：TCL549 (40000)●片上软件控制器，采样和保持●最大误差…±0.5LSB●4M内部系统时钟●电源电压范围…3-6V●低功耗…最大15mW●理想的高性价比，高性能的应用，包括电池供电的便携式仪表。

●引脚和控制信号与TLC540和TLC545 8位A / D转换器以及TLC1540 10位A / D转换器兼容描述TLC548和TLC549是围绕8位开关电容逐次逼近型ADC构建的CMOS模数转换器(ADC)集成电路。

这个器件设计用于通过3态数据输出和模拟输入与微处理器或外设进行串行接口。

TLC548和TLC549使用I/O CLOCK以及片选(CS)输入进行数据控制。

TLC548的最大I/O CLOCK输入频率为2.048 MHz，TLC549的I/O CLOCK输入频率为1.1 MHz。

TLC548和TLC549的操作与更复杂的TLC540和TLC541设备的操作非常相似；然而，TLC548和TLC549提供片上系统时钟，通常工作在4 MHz，无需外部元件。

片内系统时钟允许内部器件操作独立于串行输入/输出数据定时进行，并允许按照所需的软件和硬件要求操作TLC548和TLC549。

I/O CLOCK 与内部系统时钟允许TLC548的高速数据传输和每秒45500次转换的转换速率，以及TLC549的每秒40000次转换。

另外TLC548和TLC549的特征包括多功能控制逻辑，可在微处理器控制下工作的片上采样保持电路，以及具有差分高阻参考电压输入的高速转换器用来简化比例转换，缩放，独立的逻辑电路抑制噪声。

完全开关电容逐次逼近型转换器电路的设计允许在小于17μs 的时间内实现±0.5最低有效位（LSB ）的最大总误差转换。

TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19961POST OFFICE BOX 655303 •DALLAS, TEXAS 75265D Microprocessor Peripheral or Standalone OperationD 8-Bit Resolution A/D ConverterD Differential Reference Input Voltages D Conversion Time ...17 µs MaxDTotal Access and Conversion Cycles Per Second– TLC548...up to 45500– TLC549...up to 40000D On-Chip Software-Controllable Sample-and-Hold FunctionD Total Unadjusted Error ...±0.5 LSB Max D 4-MHz Typical Internal System Clock D Wide Supply Range ...3V to 6VD Low Power Consumption ...15mW Max D Ideal for Cost-Effective, High-Performance Applications including Battery-Operated Portable InstrumentationDPinout and Control Signals Compatible With the TLC540 and TLC545 8-Bit A/D Converters and with the TLC1540 10-Bit A/D ConverterDCMOS TechnologydescriptionThe TLC548 and TLC549 are CMOS analog-to-digital converter (ADC) integrated circuits built around an 8-bit switched-capacitor successive-approximation ADC. These devices are designed for serial interface with a microprocessor or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 use only the input/output clock (I/O CLOCK) input along with the chip select (CS) input for data control. The maximum I/O CLOCK input frequency of the TLC548 is 2.048 MHz, and the I/O CLOCK input frequency of the TLC549 is specified up to 1.1 MHz.AVAILABLE OPTIONSPACKAGET A SMALL OUTLINE(D)PLASTIC DIP(P)0°C to 70°C TLC548CD TLC549CD TLC548CP TLC549CP –40°C to 85°CTLC548ID TLC549IDTLC548IP TLC549IPCopyright © 1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.12348765REF+ANALOG INREF–GNDV CCI/O CLOCK DATA OUT CSD OR P PACKAGE(TOP VIEW)TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19962POST OFFICE BOX 655303 •DALLAS, TEXAS 75265description (continued)Operation of the TLC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541devices; however, the TLC548 and TLC549 provide an on-chip system clock that operates typically at 4 MHz and requires no external components. The on-chip system clock allows internal device operation to proceed independently of serial input/output data timing and permits manipulation of the TLC548 and TLC549 as desired for a wide range of software and hardware requirements. The I/O CLOCK together with the internal system clock allow high-speed data transfer and conversion rates of 45500 conversions per second for the TLC548, and 40000 conversions per second for the TLC549.Additional TLC548 and TLC549 features include versatile control logic, an on-chip sample-and-hold circuit that can operate automatically or under microprocessor control, and a high-speed converter with differential high-impedance reference voltage inputs that ease ratiometric conversion, scaling, and circuit isolation from logic and supply noises. Design of the totally switched-capacitor successive-approximation converter circuit allows conversion with a maximum total error of ±0.5 least significant bit (LSB) in less than 17 µs.The TLC548C and TLC549C are characterized for operation from 0°C to 70°C. The TLC548I and TLC549I are characterized for operation from –40°C to 85°C.functional block diagramREF –6488DATAOUT8-Bit Analog-to Digital Converter (Switched-Capacitors)8-to-1 Data Selector and DriverOutput Data RegiserInternal System ClockSample and Hold75231ANALOG INREF +CSI/O CLOCKControl Logic and Output Countertypical equivalent inputsINPUT CIRCUIT IMPEDANCE DURING SAMPLING MODEINPUT CIRCUIT IMPEDANCE DURING HOLD MODE1 k Ω TYPC i = 60 pF TYP (equivalent input capacitance)5 M Ω TYPANALOG INANALOG INTLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19963POST OFFICE BOX 655303 •DALLAS, TEXAS 75265operating sequencet ent ent su(CS)B7B0B1B2B3B4B5B6B7Conversion Data BMSB MSB LSBHi-Z StateMSBLSB (see Note B)MSB Previous Conversion Data AA7A7A6A5A4A3A2A1A0Hi-Z StateDon’t11(see Note A)t conv t su(CS)Access Cycle B88765432765432CLOCK I/O CSOUTDATA CareSample Cycle BAccess Cycle CSample Cycle Ct wH(CS)NOTES: A.The conversion cycle, which requires 36 internal system clock periods (17 µs maximum), is initiated with the eighth I/O clock pulsetrailing edge after CS goes low for the channel whose address exists in memory at the time.B.The most significant bit (A7) is automatically placed on the DATA OUT bus after CS is brought low. The remaining seven bits (A6–A0)are clocked out on the first seven I/O clock falling edges. B7–B0 follows in the same manner.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V CC (see Note 1) 6.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range at any input –0.3 V to V CC + 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range –0.3 V to V CC + 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak input current range (any input) ±10 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak total input current range (all inputs) ±30 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, T A (see Note 2): TLC548C, TLC549C 0°C to 70°C. . . . . . . . . . . . . TLC548I, TLC549I –40°C to 85°C. . . . . . . . . . . . Storage temperature range, T stg –65°C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOTES: 1.All voltage values are with respect to the network ground terminal with the REF– and GND terminals connected together, unlessotherwise noted.2.The D package is not recommended below –40°C.TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19964POST OFFICE BOX 655303 •DALLAS, TEXAS 75265recommended operating conditionsTLC548TLC549MINNOMMAXMIN NOMMAXUNIT Supply voltage, V CC356356V Positive reference voltage, V ref+ (see Note 3) 2.5V CC V CC +0.12.5V CC V CC +0.1V Negative reference voltage, V ref – (see Note 3)–0.10 2.5–0.10 2.5V Differential reference voltage, V ref+, V ref – (see Note 3)1V CC V CC +0.21V CC V CC +0.2V Analog input voltage (see Note 3)0V CC0V CCV High-level control input voltage, V IH (for V CC = 4.75 V to 5.5 V)22V Low-level control input voltage, V IL (for V CC = 4.75 V to 5.5 V)0.80.8V Input/output clock frequency, f clock(I/O) (for V CC = 4.75 V to 5.5 V)0 2.0480 1.1MHz Input/output clock high, t wH(I/O) (for V CC = 4.75 V to 5.5 V)200404ns Input/output clock low, t wL(I/O) (for V CC = 4.75 V to 5.5 V)200404ns Input/output clock transition time, t t(I/O)(for V CC = 4.75 V to 5.5 V) (see Note 4 and Operating Sequence)100100ns Duration of CS input high state during conversion, t wH(CS)(for V CC = 4.75 V to 5.5 V) (see Operating Sequence)1717µs Setup time, CS low before first I/O CLOCK, t su(CS) (for V CC = 4.75 V to 5.5 V) (see Note 5) 1.4 1.4µs TLC548C, TLC549C 070070CTLC548I, TLC549I–4085–4085°NOTES: 3.Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that appliedto REF– convert to all zeros (00000000). For proper operation, the positive reference voltage V ref+, must be at least 1 V greater than the negative reference voltage, V ref–. In addition, unadjusted errors may increase as the differential reference voltage, V ref+ – V ref–,falls below 4.75 V.4.This is the time required for the I/O CLOCK input signal to fall from V IH min to V IL max or to rise from V IL max to V IH min. In the vicinityof normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition applications in which the sensor and the ADC are placed several feet away from the controlling microprocessor.5.To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and one falling edge of internalsystem clock after CS ↓ before responding to control input signals. This CS setup time is given by the t en and t su(CS) specifications.TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19965POST OFFICE BOX 655303 •DALLAS, TEXAS 75265electrical characteristics over recommended operating free-air temperature range,V CC = V ref+ = 4.75 V to 5.5 V, f clock(I/O) = 2.048 MHz for TLC548 or 1.1 MHz for TLC549 (unless otherwise noted)PARAMETERTEST CONDITIONS MIN TYP †MAXUNIT V OH High-level output voltage V CC = 4.75 V,I OH = –360 µA 2.4V V OL Low-level output voltageV CC = 4.75 V,I OL = 3.2 mA 0.4V I OZ High impedance off state output current V O = V CC ,CS at V CC 10High-impedance off-state output current V O = 0,CS at V CC–10µA I IH High-level input current, control inputs V I = V CC 0.005 2.5µA I IL Low-level input current, control inputsV I = 0–0.005–2.5µA I I()Analog channel on-state input current during sample Analog input at V CC 0.41I(on)g g cycleAnalog input at 0 V –0.4–1µA I CCOperating supply current CS at 0 V 1.8 2.5mA I CC + I ref Supply and reference current V ref+ = V CC1.93mA Input capacitance Analog inputs 755C iInput capacitanceControl inputs515pFoperating characteristics over recommended operating free-air temperature range, V CC = V ref+ = 4.75 V to 5.5 V, f clock(I/O) = 2.048 MHz for TLC548 or 1.1 MHz for TLC549 (unless otherwise noted)TEST CONDITIONS TLC548TLC549PARAMETERTEST CONDITIONS MINTYP †MAX MIN TYP †MAX UNIT E L Linearity error See Note 6±0.5±0.5LSB E ZS Zero-scale error See Note 7±0.5±0.5LSB E FS Full-scale error See Note 7±0.5±0.5LSB Total unadjusted error See Note 8±0.5±0.5LSB t convConversion timeSee Operating Sequence 8171217µs Total access and conversion timeSee Operating Sequence 12221925µs t a Channel acquisition time (sample cycle)See Operating Sequence44I/O clock cycles t v Time output data remains valid after I/O CLOCK ↓1010nst d Delay time to data output valid I/O CLOCK ↓200400ns t en Output enable time 1.4 1.4µs t dis Output disable time 150150ns t r(bus)Data bus rise timeSee Figure 1300300nst f(bus)Data bus fall time 300300ns †All typicals are at V CC = 5 V, T A = 25°C.NOTES: 6.Linearity error is the deviation from the best straight line through the A/D transfer characteristics.7.Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the differencebetween 11111111 and the converted output for full-scale input voltage.8.Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19966POST OFFICE BOX 655303 •DALLAS, TEXAS 75265PARAMETER MEASUREMENT INFORMATIONSee Note B0.4 V2.4 V t f(bus)Outputt r(bus)0.8 V2.4 V 0.8 Vt dDATA OUTVOLTAGE WAVEFORMS FOR RISE AND FALL TIMESVOLTAGE WAVEFORMS FOR DELAY TIMEV CC3 k Ω3 k ΩV CCSee Note B 50%50%0 V0 Vt PLZI/O CLOCKVOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMESOutput Waveform 1(see Note C)t PHZV OH 90%10%t PZL0 VV CC 50%CSLOAD CIRCUIT FOR t PZL AND t PLZLOAD CIRCUIT FOR t PZH AND t PHZLOAD CIRCUIT FORt d , t r , AND t fSee Note BOutput Under Test Test Point3 k Ω1.4 VOutput Waveform 2(see Note C)C L(see Note A)Output Under Test Test Point C L(see Note A)Output Under Test Test PointC L(see Note A)t PZH50%NOTES: A.C L = 50 pF for TLC548 and 100 pF for TLC549; C L includes jig capacitance.B.t en = t PZH or t PZL , t dis = t PHZ or t PLZ .C.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.Figure 1. Load Circuits and Voltage WaveformsTLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19967POST OFFICE BOX 655303 •DALLAS, TEXAS 75265APPLICATIONS INFORMATIONsimplified analog input analysisUsing the equivalent circuit in Figure 2, the time required to charge the analog input capacitance from 0 to V S within 1/2 LSB can be derived as follows:The capacitance charging voltage is given byV C = V S 1–e–t c /R t C i ( )(1)whereR t = R s + r iThe final voltage to 1/2 LSB is given by(2)V C (1/2 LSB) = V S – (V S /512)Equating equation 1 to equation 2 and solving for time t c givesV S –(V S /512) = V S 1–e(3)–t c /R t C i( )andt c (1/2 LSB) = R t × C i × ln(512)(4)Therefore, with the values given the time for the analog input signal to settle ist c (1/2 LSB) = (R s + 1 k Ω) × 60 pF × ln(512)(5)This time must be less than the converter sample time shown in the timing diagrams.R sr i V SV C 1 k Ω MAXDriving Source †TLC548/9V IV I = Input Voltage at ANALOG IN V S = External Driving Source Voltage R s = Source Resistance r i = Input Resistance C i = Input Capacitance†Driving source requirements:•Noise and distortion for the source must be equivalent to the resolution of the converter.•R s must be real at the input frequency.C i55 pF MAX Figure 2. Equivalent Input Circuit Including the Driving SourceTLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19968POST OFFICE BOX 655303 •DALLAS, TEXAS 75265PRINCIPLES OF OPERATIONThe TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internal system clock, sample-and-hold function, 8-bit A/D converter, data register, and control logic circuitry. For flexibility and access speed, there are two control inputs: I/O CLOCK and chip select (CS). These control inputs and a TTL-compatible 3-state output facilitate serial communications with a microprocessor or minicomputer. A conversion can be completed in 17 µs or less, while complete input-conversion-output cycles can be repeated in 22 µs for the TLC548 and in 25 µs for the TLC549.The internal system clock and I/O CLOCK are used independently and do not require any special speed or phase relationships between them. This independence simplifies the hardware and software control tasks for the device.Due to this independence and the internal generation of the system clock, the control hardware and software need only be concerned with reading the previous conversion result and starting the conversion by using the I/O clock. In this manner, the internal system clock drives the “conversion crunching” circuitry so that the control hardware and software need not be concerned with this task.When CS is high, DATA OUT is in a high-impedance condition and I/O CLOCK is disabled. This CS control function allows I/O CLOCK to share the same control logic point with its counterpart terminal when additional TLC548 and TLC549 devices are used. This also serves to minimize the required control logic terminals when using multiple TLC548 and TLC549 devices.The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain the conversion result. A normal control sequence is:1.CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edgesand then a falling edge of the internal system clock after a CS ↓ before the transition is recognized. However,upon a CS rising edge, DATA OUT goes to a high-impedance state within the specified t dis even though the rest of the integrated circuitry does not recognize the transition until the specified t su(CS) has elapsed. This technique protects the device against noise when used in a noisy environment. The most significant bit (MSB)of the previous conversion result initially appears on DATA OUT when CS goes low.2.The falling edges of the first four I/O CLOCK cycles shift out the second, third, fourth, and fifth most significantbits of the previous conversion result. The on-chip sample-and-hold function begins sampling the analog input after the fourth high-to-low transition of I/O CLOCK. The sampling operation basically involves the charging of internal capacitors to the level of the analog input voltage.3.Three more I/O CLOCK cycles are then applied to the I/O CLOCK terminal and the sixth, seventh, and eighthconversion bits are shifted out on the falling edges of these clock cycles.4.The final (the eighth) clock cycle is applied to I/O CLOCK. The on-chip sample-and-hold function begins thehold operation upon the high-to-low transition of this clock cycle. The hold function continues for the next four internal system clock cycles, after which the holding function terminates and the conversion is performed during the next 32 system clock cycles, giving a total of 36 cycles. After the eighth I/O CLOCK cycle, CS must go high or the I/O clock must remain low for at least 36 internal system clock cycles to allow for the completion of the hold and conversion functions. CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise glitches on the I/O CLOCK line. If glitches occur on I/O CLOCK, the I/O sequence between the microprocessor/controller and the device loses synchronization. When CS is taken high, it must remain high until the end of conversion. Otherwise, a valid high-to-low transition of CS causes a reset condition, which aborts the conversion in progress.A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through 4 before the 36 internal system clock cycles occur. Such action yields the conversion result of the previous conversion and not the ongoing conversion.TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 19969POST OFFICE BOX 655303 •DALLAS, TEXAS 75265PRINCIPLES OF OPERATIONFor certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.This device accommodates these applications. Although the on-chip sample-and-hold function begins sampling upon the high-to-low transition of the fourth I/O CLOCK cycle, the hold function does not begin until the high-to-low transition of the eighth I/O CLOCK cycle, which should occur at the moment when the analog signal must be converted. The TLC548 and TLC549 continue sampling the analog input until the high-to-low transition of the eighth I/O CLOCK pulse. The control circuitry or software then immediately lowers I/O CLOCK and starts the holding function to hold the analog signal at the desired point in time and starts the conversion.PACKAGING INFORMATIONOrderableDeviceStatus (1)Package Type Package DrawingPins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)TLC548CD ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548CDG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548CDR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548CDRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548CP ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC548CPE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC548ID ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548IDG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548IDR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548IDRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC548IP ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC548IPE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC549CD ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549CDG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549CDR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549CDRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549CP ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC549CPE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC549ID ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549IDG4ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549IDR ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549IDRG4ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM TLC549IP ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC549IPE4ACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type TLC549IPSACTIVESOPS880Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIMPACKAGE OPTION ADDENDUM6-Nov-2006Addendum-Page 1分销商库存信息:TITLC549IP TLC549CP TLC549CD TLC548CP TLC549ID TLC548IP TLC548ID TLC548CD TLC549CDR TLC549CDRG4TLC549IDR TLC549IDRG4 TLC548CDR TLC548CDRG4TLC549IPSR TLC549IPSRG4TLC548IDR TLC548IDRG4 TLC549CPE4TLC549IPE4TLC549CDG4 TLC548CPE4TLC549IDG4TLC548IPE4 TLC549IPS TLC549IPSG4TLC548CDG4 TLC548IDG4。

串行AD实验预习报告一．实验目的学习利用串行模数转换芯片TLC549进行电压搜集和数据处置。

二．实验原理TLC549是美国德州仪器（TI）公司生产的8位串行逐次比较型A/D转换芯片。

通用微处置器通过串行操纵线可实现对该芯片的操纵。

该芯片具有4MHz片内系统时钟和软、硬件操纵电路，转换时刻最长17μs，转换速度为40 000次/s。

总失调误差最大为±0.5LSB，典型功耗值为6mW。

管脚封装如图1所示：图1 TLC549管脚封装图管脚概念为：4、8脚为电源输入和接地；2脚AIN模拟采样电压的输入；5脚-CS为片选信号，当-CS为高时，数据输出DATA_OUT 端处于高阻状态；7脚I/OCLK为时钟信号的输入；6脚DOUT为转换后的串行数据输出；1、3脚为参考电压输入，其中1脚REF+，3脚REF-，一样为保证器件工作良好，REF+电压应高于REF-电压至少1V，为减少误差，建议相差4.75V 以上。

TLC549的工作时序如图2所示：图2 TLC549工作时序图如上图所示，第一将CS置低，内部电路在测得CS下降沿后，等待ten后自动将前一次转换结果的最高位(D7)位输出到DATA OUT端上。

前四个IO_CLOCK 周期的下降沿依次移出第2、3、4 和第5 个位(D6、D5、D4、D3)，片上采样维持电路在第4个IO_CLOCK 下降沿开始采样模拟输入。

接下来的3个IO_CLOCK 周期的下降沿移出第6、7、8(D2、D1、D0)个转换位。

最后，片上采样维持电路在第8个I/O CLOCK 周期的下降沿后，开始A/D转换。

第8个IO_CLOCK后，CS 必需为高，或IO_CLOCK维持低电平，这种状态需要维持tconv以等待维持和转换工作的完成。

三．实验设备及器件PC机，DP-51PROC单片机综合仿真实验仪。

四．实验内容1. 实验要求1.1 REF+连基准源的+5V（通过可调电阻调整），CLK、DAT和-CS别离连P10、P11和P12。