OB6561P Design Guide

L6563引脚定义1、INV：误差放大器反向输入端。

PFC预调节器的输出电压信息通过一个电阻分压流入此脚.此脚正常特性为高阻抗，但是如果运用了跟踪Boost功能，一个用TBO（6脚)编程的内部电流产生器将被激活。

它将从此脚吸入电流来改变输出电压，所以它跟踪了主电压。

2、COMP：误差放大器的输出端。

需要再此脚与INV（1脚）之间加入一个补偿网络来达到控制环路的稳定和确保高PF和低THD。

3、MULT：乘法器的主输入。

此脚通过一个电阻分压连接到整流后的主电压端，并且给电流环路提供一个正弦参考。

此脚上的电压也被用来得到主电压的有效值信息。

4、CS：输入到PWM比较器。

流入MOSFET的电流通过一个电阻感测，其感测后的结果电压加入到此脚与内部的参考进行比较来决定MOSFET的开关。

一个第二次的比较水平1。

7V来探测不正常的电流（比如：由于BOOST电感保护）,一旦发生这种情况，关断IC，将其损耗降低到几乎与启动时同样的水平，将PWM_LATCH （8脚）置为高电平。

此功能在L6563A中没有。

5、VFF：1/V2的乘法器的第二个输入端。

一个电容和并联电阻必须从此脚连接到GND。

他们完成内部的峰值保持电路，此峰值保持电路从主电压的有效值获得信息。

此脚的电压直流水平与MULT脚(3脚）的峰值电压相等,此电压补偿依赖于主电压的控制环路增益.不要将此脚直接连接到GND.6、TBO：跟踪BOOST功能。

此脚提供一个缓冲VFF电压。

通过一个电阻将此脚连接到GND来定义从INV（1脚）流入的电流.在这种情况下，输出电压相对主电压成比例的变化（跟踪BOOST）.如果不用此功能将此脚悬空。

7、PFC_OK：PFC预调节输出电压监测或使能功能端.此脚通过一个电阻分压来感测PFC预调节输出电压,也被用作保护目的。

如果此脚电压超过2。

5V,IC被关断，其损耗降低到接近启动时的水平并且此情况被锁住.PWM_LATCH脚被置为高电平。

L6561功率因数校正1■■特征非常精确的可调输出过电压保护微功率启动电流(50µATYP.)非常低的电源电流（4mA TYP.)内部启动定时器片上电流检测滤波器禁止功能1%精密(@ T j= 25°C)内部参考电压过渡模式操作图腾柱输出电流：±400mADIP-8/SO-8套餐图1.软件包DIP-8SO-8■订购代码表1.部件号L6561L6561DL6561D013TR包装DIP-8SO-8带卷■■■■■■■2描述L6561是改良版的L6560 stan-dard功率因数修正器.完全兼容with the standard version, it has a superior perfor-mant乘数使设备的工作能力，在宽输入电压范围的应用ing（从85V到265V)了一个良好的THD.此外当前开始向上在数已减少tensmA和禁用的功能已经实现，教育署对ZCD针，保证较低的电流消费模式下的立场.图2.框图COMP2INV12.5V-+在混合BCD技术变现，该芯片提供以下好处：–微功率启动电流– 1%高精度内部参考电压– (Tj = 25°C)–软输出过电压保护–无需外部低通滤波器需要对电流，租金感–非常低的静态电流最低，es功耗图腾柱输出级驱动能力一个电源MOS或源IGBT和汇电流租金的±400mA.设备运行中tran-sition模式，它是电子灯优化镇流管应用，AC-DC适配器和SMPS.MULT3440KCSMULTIPLIERVOLTAGE REGULATOR OVER-VOLTAGEDETECTION-+5pFV 8VINTERNALSUPPLY 7VR1+UVLORSDRIVERQ720VGDR2V2.1V1.6VZERO CURRENTDETECTORSTARTER6GNDJune 2004-+-DISABLE5ZCDREV的. 161/13L6562中文数据手册,L6562 Datasheet PDF,L6562芯片中文资料【L6561表2.绝对最大额定值符号I VccI GDINV, COMPMULTCSZCDP totT jT stg针871, 2, 345I q+ I Z; (I GD= 0)图腾柱输出电流(2µs) 峰值模拟输入和输出电流检测输入零电流检测器功率消耗@T amb= 50 °C结温工作范围贮藏温度(DIP-8)(SO-8)参数价值30±700-0.3到7-0.3到750（源）-10（汇）10.65-40到150-55到150单位mAmAVVmAmAWW°C°C图3.引脚连接（顶视图）INV COMP MULTCS 1234DIP88765V CCGDGNDZCD热数据表3.符号R th j-amb参数结到环境的热阻苏8150MINIDIP100单位°C/W表4.引脚说明N. 12345 6 78名称INVCOMPMULTCSZCDGNDGDV CC功能反相误差放大器的输入.一个电阻分压器的输出之间连接稳压这一点，提供电压反馈.误差放大器的输出.一个反馈补偿网络之间设置这个引脚和INV引脚.乘法器的输入阶段.一个电阻分压器连接到这个引脚的整流电源.一个电压信号，比例整流电源，出现在该引脚.输入到控制回路比较.该感应电流通过电阻和由此产生的电压施加到该管脚.零电流检测输入.如果是连接到GND,设备被禁用.当前返回驱动器和控制电路.门驱动器输出.一个推挽输出级可驱动峰值目前电源MOS400mA（源和接收器）.电源电压驱动器和控制电路.(1)参数由设计保证，而不是在生产测试.2/13L6561电气特性表5.(V CC = 14.5V; T amb = -25°C 到125°C ，除非另有规定）符号V CC V CC ON V CC OFF Hys I START-UI q I CCIqV ZV INV针88888888881齐纳电压电压反馈输入门槛线路调整I INV G V GB I COMPV COMP221电流输入偏置电压增益增益带宽源电流灌电流上钳位电压低钳位电压乘第V MULT ∆VCS-----------------∆VmultKV CS I CS t d (H-L)4444V ZCD53线性工作电压输出最大.斜坡V MULT 从= 0V 到0.5V V COMP =上钳位电压V MULT = 1V VCOMP= 4V V MULT = 2.5VV COMP =上钳位电压V OS = 00到31.650到3.51.9VV COMP = 4V, V INV = 2.4V V COMP = 4V, VINV= 2.6VI SOURCE = 0.5mA I Sink = 0.5mA-22.5开环60误差放大器部分T amb = 25°C 12V < VCC< 18VV CC = 12到18V2.4652.442-0.1801-44.55.82.25-82.5 2.5352.565-1V V mV µA dB MHzmA mA V V参数工作范围启动阈值关断阈值迟滞启动电流静态电流工作电源电流静态电流C L = 1nF @ 70KHz 在OVP 条件Vpin1= 2.7VV PIN5≤150mV,V CC > V CC off V PIN5≤150mV, V CC< VCC offI CC = 25mA2018前开启(VCC=11V)测试条件后开启最小.11118.72.220129.52.5502.641.41.45020Typ.最大.181310.32.89045.52.12.19022单位V V V V µA mA mA mA mA µA V电源电压一节当前节供应Gain 电流检测基准钳电流输入偏置到输出的延电流检测失调输入阈值电压上升边缘迟滞上钳位电压上钳位电压(1)(1)0.451.60.61.7-0.0520002.10.751.8-1450151/VV µA ns mVV 电流检测比较器零电流检测器0.34.54.70.55.15.20.75.96.1V V VV ZCD V ZCD55I ZCD = 20µA I ZCD = 3mA3/13L6561电气特性表5.（续）(V CC = 14.5V; T amb = -25°C 到125°C ，除非另有规定）符号V ZCD I ZCD I ZCD I ZCD V DIS I ZCD V GD针5555557参数低钳位电压灌电流偏置源出电流能力灌电流能力禁用门槛禁用后，重新启动电流漏失电压V ZCD < Vdis ; V CC> VCCOFFI GDsource = 200mA I GDsource = 20mA I GDsink = 200mA I GDsink = 20mAt r t f I GD off I OVP7772输出电压上升时间输出电压下降时间IGD 灌电流OVP 触发电流阈值静态OVP重新启动定时器t START启动定时器70150400µsC L = 1nF C L = 1nF V CC =3.5V VGD= 1V5352.1404010402.25测试条件I ZCD = -3mA 1V ≤V ZCD ≤4.5V-33150-100200-2001.20.7最小.0.3Typ.0.652-1010250-300211.50.3100100-452.4最大.1单位V µAmA mA mV µAV V V V ns ns mAµA V输出部分输出过压段3过电压保护OVP输出电压，预计将在电路的PFC 接近其标称值操作保存.这是由两个外部电阻R1和R2比例设置（见图.5),同时考虑到非反相误差放大器的输入偏置内部L6561在2.5V.在稳态条件下，通过R1和R2电流为：V 出–2.5 2.5V-I R1sc= ------------------------- =I R2= ------------R1R2并且，如果外部补偿网络是由只有一个电容Ccomp ,电流通过Ccomp输出电压等于zero.When 突然增大电流通过R1变为：V outsc +∆V 出–2.5I R1= ---------------------------------------------------- =I R1sc +∆I R1-R1由于电流通过R2不改变，∆I R1必须流过电容器Ccomp 并输入误差放大器.这个电流进行监测，当内L6561达到约37µA 了多输出电压钳被迫减少，从而减少电源得出的能量.如果电流超过40µA,保护的OVP 触发（动态OVP),和外部功率晶体管切换到关闭电流降至大约比10µA.但是，如果过压仍然存在，一个内部比较器（静态OVP)证实了OVP 条件外部电源开关保持关闭（见图.4）.最后，过压触发OVP 功能是：∆V 出= R 1· 40µA.为R 典型值1, R 2和C 显示在应用电路.可设置过压indepen -4/13L6561判断的平均输出电压.在设置过压阈值精度的7% ov-ervoltage值（例如∆V= 60V ± 4.2V).3.1 Disable功能零电流检测器(ZCD)引脚可用于设备以及禁用.通过接地ZCD电压年龄的设备被禁用减低1.4mA典型(@ 14.5V电源电压，电源电流消耗，年龄）.释放ZCD引脚的内部启动定时器将重新启动设备.图4.过电压V OUT nominalI SC 40µA 10µAé / A输出2.25V动态OVP静态OVP D97IN592A 图5.过电压保护电路Ccomp.+VoR11 R2-+2.5V-2.25V ∆I +E/A∆I2X PWM DRIVER40µAD97IN5915/13L6561图6.典型应用电路(80W, 110VAC)D1 BYT03-400C6TR7 (*)950KC3 680nF68K52174+Vo=240VPo=80WR3 (*)240KBRIDGE+ 4 x 1N4007FUSE 4A/250V-Vac(85V to 135V)NTCR1010KD3 1N4150D21N5248BR210010nFR1C11µF250VR9 (*)950K8R510L65613C222µF25VC710nF6MOSSTP7NA40C5100µF315VR6 (*)0.311WR810K1%D97IN549B-(*) R3 = 2 x 120KΩR6 = 0.619Ω/2R7 = 2 x 475KΩ, 1%R9 = 2 x 475KΩTRANSFORMERT: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A7) primary 90T of Litz wire 10 x 0.2mmsecondary 11T of #27 AWG (0.15mm)gap 1.8mm for a total primary inductance of 0.7mH图7.典型应用电路(120W, 220VAC)D1 BYT13-600 C6TR7 (*)998KC3 1µF68K52174+Vo=400V Po=120WR3 (*)440KBRIDGE+ 4 x 1N4007FUSE 2A/250V-Vac(175V to 265V)NTCR1010KD3 1N4150D21N5248BR210010nFR1C1560nF400VR9 (*)1.82M8R510L65613C222µF25VC710nF6MOSSTP5NA50C556µF450VR6 (*)0.411WR86.34K1%D97IN550B-(*) R3 = 2 x 220KΩR6 = 0.82Ω/2R7 = 2 x 499KΩ, 1%R9 = 2 x 909KΩTRANSFORMERT: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8) primary 90T of Litz wire 10 x 0.2mmsecondary 7T of #27 AWG (0.15mm)gap 1.25mm for a total primary inductance of 0.8mH图8.典型应用电路(80W,宽范围电源）D1 BYT13-600C6TR7 (*)998KC3 1µF68K52174+Vo=400VPo=80WR3 (*)240KBRIDGE+ 4 x 1N4007FUSE 4A/250V-Vac(85V to 265V)NTC R1010K D3 1N4150D21N5248BR210012nFR1C1 1µF 400V R9 (*)1.24M8R510L65613C222µF25VC710nF6MOSSTP8NA50C547µF450VR6 (*)0.411WR86.34K1%D97IN553B-(*) R3 = 2 x 120KΩR6 = 0.82Ω/2R7 = 2 x 499KΩ, 1%R9 = 2 x 620KΩTRANSFORMERT: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8) primary 90T of Litz wire 10 x 0.2mmsecondary 7T of #27 AWG (0.15mm)gap 1.25mm for a total primary inductance of 0.8mH6/13L6561图9.电气原理演示板(EVAL6561-80)D1STTH1L06R4 180 kR5180 kTD81N4150C5 12 nFR14100R1 750 kD21N5248BR668 kR50 12 kC3 470 nFR12750 kR11750 kVo=400VPo=80WNTC2.5BRIDGEFUSE 4A/250V +W04MC11 µF400VC231 µFR2750 k836C210nF52174R733C647 µF450VVac (85V to 265V)-L6561MOSSTP8NM50R310 kC2922 µF25VC4100 nFD3 1N4148C710 µF35 VR1691 kR15220R90.411WR100.411WR139.53 k-Boost Inductor Spec (ITACOIL E2543/E)E25x13x7 core, 3C85 ferrite1.5 mm gap for 0.7 mH primary inductancePrimary: 105 turns 20x0.1 mmSecondary: 11 turns 0.1mmTHD REDUCER (optional)图10. EVAL6561-80: PCB和组件布局（顶视图，实际尺寸57x108mm)表6. EVAL6561-80:评价结果.V in（VAC）85110135175220265针(W)87.285.284.283.583.182.9V o(Vdc)400.1400.1400.1400.1400.1400.1∆Vo(Vdc)141414141414Po (W)80.780.780.780.780.780.7η(%)92.894.795.896.697.197.3W / O型THD减速PF0.9990.9960.9890.9760.9400.890THD (%)3.75.06.28.310.713.7与THD减速PF0.9990.9960.9890.9760.9410.893THD (%)2.93.23.74.35.68.17/13L6561图11. OVP电流阈值随温度D94IN047A 图13.电源电流与电源电压I CC(mA)10D97IN548AIOVP(µA)4151 400.50.10.05390.010.005发光= 1nFf = 70KHz电讯局长= 25˚C 05101520V CC(V)38-50 -250255075100 125 T (˚C)图12.欠压阈值分离与温度的关系V CC-ON(V)131211V CC-OFF(V)109-2502550T (˚C)75100125D94IN044A图14.电压反馈输入阈值与温度的关系V REF(V)D94IN048A2.502.482.46-50050100T (˚C)8/13L6561图15.输出饱和电压和接收器当前VPIN7(V)VCC = 14.5V 2.0D94IN046图17.乘数特征系列V CS(pin4)(V)upper voltageclampD97IN555AV COMP(pin2)(V)3.5水槽 1.61.41.25.04.54.03.21.51.01.00.80.6 0.50.40.20100200300400 IGD (mA)03.02.82.60.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5V MULT(pin3) (V)图16.输出饱和电压与源电流VPIN7(V)VCC = 14.5VVCC -0.5D94IN053VCC -1.0VCC -1.5VCC -2.0消息来源0100200300400 IGD (mA)9/13L6561图18. DIP-8机械尺寸数据与包装mm暗淡.最小.Aa1Bbb1DEee3e4FIL Z3.187.952.547.627.626.65.083.811.520.1250.511.150.3560.2041.650.550.30410.929.750.3130.1000.3000.3000.2600.2000.1500.060TYP.3.320.0200.0450.0140.0080.0650.0220.0120.4300.384最大.最小.TYP.0.131最大.寸外形与机械数据DIP-810/13L6561图19. SO-8机械尺寸数据与包装mm暗淡.最小.AA1A2BCD(1)EeH h L k ddd 5.800.250.401.350.101.100.330.194.803.801.276.200.501.270.2280.0100.016TYP.最大.1.750.251.650.510.255.004.00最小.0.0530.0040.0430.0130.0070.1890.150.0500.2440.0200.050TYP.最大.0.0690.0100.0650.0200.0100.1970.157寸外形与机械数据0˚（分钟），8˚（最大）0.100.004Note: (1) Dimensions D does not include mold flash, protru-sions or gate burrs.Mold flash, potrusions or gate burrs shall not exceed0.15mm (.006inch) in total (both side).SO-80016023 C11/13L6561表7.修订历史记录日期一月2004 June 2004修订1516创刊号改良的样式符合期待与“企业技术刊物设计指南“.改变了功率放大器的输入连接到乘数（图2).更改说明12/13L6561提供的资料被认为是准确和可靠.然而，意法半导体的后果不承担任何责任这类信息也不对任何第三方的专利或可能导致其使用的其他权利的侵犯使用.未授通过暗示或以其他方式意法半导体的任何专利或专利的权利.本出版物中提到的规格如有变更，恕不另行通知.本刊物并取代以前提供的所有信息.意法半导体的产品不做为关键元件的授权使用寿命支持设备或系统未经明确的书面意法半导体的批准.ST的标志是意法半导体公司的注册商标.所有其他名称均为其各自所有者的财产© 2004意法半导体-版权所有意法半导体公司集团澳大利亚-比利时-巴西-加拿大-中国-捷克共和国-芬兰-法国-德国- Hong Kong -印度-以色列-意大利-日-马来西亚-马耳他-摩洛哥-新加坡-西班牙-瑞典-瑞士-英国-美国13/13。

1Rev 0DESCRIPTIONElectrical Evaluation for LTC6561Four-Channel Transimpedance Amplifierwith Output MultiplexingDemonstration circuit 2808A features the LTC ®6561 four-channel transimpedance amplifier (TIA) with output multiplexing. The DC2808A accepts voltage pulses and converts them to current for the TIA. The board can also be used to measure bandwidth and channel isolation with a network analyzer . The LTC6561, which features 74KΩ transimpedance gain and 30uA linear input current range, is ideal for LIDAR receivers using Avalanche Photodiodes (APD). The LTC6561 operates from 5V single supply and consumes only 220mW. Utilizing the LTC6561’s outputAll registered trademarks and trademarks are the property of their respective owners.BOARD PHOTOMUX, multiple LTC6561 devices can combine into a single output. The LTC6561’s fast overload recovery makes it well suited for LIDAR receivers. The LTC6561’s single-ended output can swing 2V P-P into a 100Ω load. The LTC6561 is packaged in a compact 4mm × 4mm 24-pin leadless QFN package with an exposed pad for thermal management and low inductance.Design files for this circuit board are available.Figure 1. Connection Diagram2Rev 0QUICK START PROCEDURE1) Connect a voltage pulse generator to the input to J1, J2, J3, and J4. These inputs are 50Ω terminated to ground, and then AC-coupled. A 2k series resistor converts the voltage to a current. Refer to the input circuit descrip-tion for details. As an input example, a 25dB attenuator can be used to scale down the pulse generators output that is set to 1V P-P . This will produce a peak current that is approximately 28uA. The combination of 100pFAC-coupled input and 1000pF AC-coupled output limits the DC2808A repetition rate to less than 100 KHz. 2) Connect J7 to an oscilloscope that is 50Ω terminated or other 50Ω systems. J7 is AC-coupled with a 1000pF capacitor.3) Connect a 5V low-noise power supply shown in Figure 1. V CCO is hardwired to V CC by default.OUTPUT CIRCUIT DESCRIPTIONINPUT CIRCUIT DESCRIPTIONFor convenience, the LTC6561 offers two outputs: OUTTERM pin has an internal series 50Ω source resistor , and OUT pin has a direct connection. The schematic is shown in Figure 3. Only one output can be used to moni-tor at a time. The DC2808A output stage is AC-coupled 50Ω source to allow for interfacing to 50Ω systems. J7 is populated by default; this configuration connects to OUT pin on the LTC6561. J8 and its passives can be populated to use the OUTTERM pin. The LTC6561 imple-ments a class B output stage, a 1K pull-down resistor on OUTTERM provide a DC path to ground. This helps the LT6561 output pull to ground when the LTC6561 output is AC-coupled.The input stage, shown in Figure 2, is AC-coupled and 50Ω terminated to allow for interfacing to voltage pulse generators. A series resistor is used to convert the voltagepulse to a current pulse. This allows the use of a pulse generator to inject a current into the TIA. The following equation should be used to calculate the injected current to the LTC6561:I LTC6561=V INPP /2k ΩEQ1The DC2808A allows insertion of excess capacitance C9, C12, C21, C24 respectively to simulate the effect of sensor (APD) capacitance on rise time and bandwidth.R1C270603Figure 2. Input Circuit for DC2808AFigure 3. Ouput Circuit for DC2808AOUTR10R21OUTTERM OPTR9C163Rev 0The LTC6561 multiplexing capability allows compact mul-tichannel designs without external multiplexers. To set the channel on the DC2808A, JP2 and JP3 are used. By placing the jumper in the 1 position, the channel select pinThe outputs of the LTC6561 can be wire OR’d together to combine multiple inputs. When the OMUX pin is high, the LTC6561s output goes to a high impedance state. When the OMUX pin is low, the LTC6561 is enabled. Only one LTC6561 can be enabled at a time. Source resistors are necessary to avoid reflections from the paths that are inactive. Be sure to keep the output lengths as short as possible to mitigate the effects of transmission line stubs. Figure 4 shows how multiple LTC6561 are connected. Both J7 (Out Pin) or J8 (OUTTERM Pin) can be used to implement output MUXing. By replacing C16 or C21 respectively with a 0Ω 0402 resistor , the output can be DC coupled to connect multiple DC2808A boards. A DC block can then be used to interface with 50Ω systems.will be tied to VCC. In the 0 position, the channel select pin will float and the internal pull-down resistors pulls the channel to ground. Refer to Table 1 for channel selection.USING THE LTC6561 CHANNEL SELECTSCONNECTING MULTIPLE LTC6561S FOR OUTPUT MUXINGFigure 4. Diagram of Wire OR’d Outputs of Multiple LTC6561'sTable 1. Channel SelectionCHSEL1 (JP3)CHSEL0 (JP2)ACTIVE CHANNEL0010121031144Rev 0LAYOUT CONSIDERATIONSThe DC2808A layout is optimized to maximize the LTC6561’s performance. The V REF . capacitor for IN1 and IN4 should be orthogonal to the input trace. This orienta-tion helps to reduce coupling from the input to V REF . The V REF . capacitors for IN2 and IN3 should be placed as close as possible. Local bypass for V CCO and V CC should be asclose as possible to the LTC6561. The ground pad in the center of the LTC6561 is important for dissipating the heat from the die and to minimize the ground inductance. Maximizing the number of vias and employing multiple ground plane layers will most effectively heat sink the LTC6561. Figure 5 shows the DC2808A layout.The input of the DC2808A is shown in Figure 6 and is attenuated by 25dB. A 25dB reduction of 300mV is 16.9mV. Using Equation 1, the peak current that the TIA sees is 8.4uA. Thus, the output of the DC2808A should be 310 mV since the scope is 50Ω terminated.INPUT AND OUTPUTFigure 5. Recomended Layout (Left) Top Layer (Right) Bottom LayerFigure 6. Scope Shoot of DC2808ATOP LAYERBOTTOM LAYER5Rev 0Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.EXTERNAL CONNECTIONSConnections:J1, J2, J3, J4: IN1, IN2, IN3, IN4 – The LTC6561’s IN1, IN2, IN3, and IN4 channels. The input stage is AC-coupled and then 50Ω terminated to allow for interfacing to volt-age pulse generators.J7: OUT - the analog output of the LTC6561.J8: OUTTERM - the analog output of the LTC6561 with the internal 50Ω series resistor .Turrets:E1: V CC – LTC6561 V CC analog input. The V CCO analog input is connected to this node when JP1 is in the V CC position.E2: V CCO – LTC6561 V CCO analog input when JP1 is in the external (EXT) position.E3, E4: GND – the DC2808A ground.Jumpers:JP1: V CCO_SEL – selects the input for the LTC6561 V CCO to V CC turret (V CC ) or external (EXT) through the V CCO turret. V CCO is hardwired to V CC by default.JP2: CHSEL0 – The LTC6561 LSB for channel selection. JP3: CHSEL1 – The LTC6561 MSB for channel selection.JP4: O_MUX – Enables (EN) or disables (DIS) the LTC6561 output. The output goes high impedance when the LTC6561 O_MUX is disabled. The power of the LTC6561 will not be reduced in either mode.6Rev 0ANALOG DEVICES, INC. 201904/19ESD CautionESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.Legal Terms and ConditionsBy using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. 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1/9AN1757APPLICATION NOTEApril 20041INTRODUCTIONConceived on the same core of the L6561 and pin-to-pin compatible with it (see fig. 1), the L6562 is the new ST's Transition Mode (TM) controller for high Power Factor Corrector stages: the replacement can be done with minimum or no modification of a stage designed with the L6561.As the building blocks of these two IC's are the same (fig. 1), one can design with the L6562 using the guidelines given for L6561, in particular in the ST Application Note 966 ("L6561, enhanced transition mode power factor corrector"). All the documentation produced for L6561 can be easily adapted to the L6562 ([1] [2] [3] [4]).The first paragraph of this Application Note is dedicated to explain the differences in terms of Electrical Charac-teristics between these two controllers: it will be clear that these modifications do not require component chang-ing when switching from L6561 to L6562.Besides providing good results in term of power factor, this new IC considerably reduces the Total Harmonic Distortion (THD) without need for external components: an innovative circuit improves the behavior of the sys-tem reducing the conduction dead-angle that occurs to the AC input current near the zero-crossings of the line voltage (paragraph 3) making easier the compliancy with regulation.The increased gate driver capability (typically 600mA sourcing and 800mA sinking) makes the L6562 suitable for a wide range of applications (with output power up to 300W).Based on that, L6562 can be fit the following applications: Lighting, IEC61000-3-2 compliant SMPS (TV, Desktop, PC, Monitors…), hi-end AC-DC adapter/charger, entry level server & web server.2L6562 VS. L6561: ELECTRICAL CHARACTERISTICS DIFFERENCESA series of tables will follow highlighting the differences between L6561 and L6562 in terms of Electrical Char-acteristics; at the end of each section, a short description explains the impact of these differences on the appli-cation and the consequent benefits.Figure 1. Block Diagramby Luca SalatiSWITCHING FROM THE L6561 TO THE L6562AN1757 APPLICATION NOTE2/9ELECTRICAL CHARACTERISTICSThe supply voltage upper limit is extended to 22V (min.) to provide more headroom for supply voltage changes.This also makes it easier to fit the supply voltage of the L6562 to that of the cascaded DC-DC converter control IC.The consumption of the chip has been reduced providing an advantage in terms of power dissipation on the start-up resistors, if used, and consumption of the self-supply circuit.The improved control process allows reducing the statistical spread of this parameter; this change does not im-pact on the application design but improves reliability of IC's quiescent pointThe improved control process allows reducing the statistical spread of this parameter; this change does not im-pact on the application design but improves reliability of IC's quiescent point.SymbolParameterTest conditionL6561L6562UnitMinTypMaxMinTypMaxSUPPLY VOLTAGE V CC Operating range After turn-on 10.31810.322V V ZZener voltagefor L6561: I CC =25mA for L6562: I CC =20mA182022222528VSUPPLY CURRENT SymbolParameterTest condition L6561L6562Unit I ST ART -UP Start-up currentbefore turn-on (V CC=11V)2050904070µA I Q Quiescent current After turn-on 2.64 2.5 3.75mA I CC Operating Supply Current@ 70KHz45.5 3.55mA I QQuiescent currentDuring OVP (either static or dynamic) or V ZCD ≤150mV2.12.2mAMULTIPLIER INPUT SymbolParameterTest conditionL6561L6562Unit K Gain V MULT =1V, V COMP =4V 0.45 0.60.750.50.60.71/VERROR AMPLIFIER Symbol Parameter Test condition L6561L6562Unit I COMP Source CurrentV COMP =4V, V INV =2.4V-2 -4 -8 -2-3.5-5mA V COMPUpper clamp voltage I SOURCE =0.5mA 5.8 5.3 5.76V Lower clamp voltage I SINK = 0.5 mA2.252.12.252.4VCURRENT SENSE COMPARATOR Symbol Parameter Test conditionL6561L6562Unit td (H-L)Delay to Output200450200350ns Current sense offset15mV V COMP =0V 30mV V COMP =2.5V5mV3/9AN1757 APPLICATION NOTEThe maximum propagation delay (Delay to output) of the current loop has been reduced: this provides advan-tages at both light load (lowering the minimum duty cycle) and heavy load (reducing the amount of peak inductor current exceeding the programmed value).Offset of the current sense comparator: in the L6561 it depends on the manufacturing process; in the L6562such parameter is kept under control because it defines the amount of correction introduced by the internal THD corrector circuit (see paragraph "3. THD optimizer circuit").Upper clamp voltage: the change does not have impact on the application design; it just reflects a change of internal structure that reduces temperature drift.The source and sink current capabilities for the L6562 are lower than the relevant in the L6561: this is the effect of the reduced spread of these two parameters. From the application design point of view this leads to a higher value for the minimum resistance connected between the auxiliary winding and the ZCD pin (R6 in the schematic of Figure 5). Generally this is not a key issue because the value for this resistor is kept much higher than the minimum calculated, to achieve optimum MOSFET turn-on.The restart threshold, not specified in the L6561 though present, is specified in the L6562.The restart current after disable has been reduced to limit IC consumption while disabled.The improved control process allows reducing the statistical spread of this parameter; this change does not im-pact on the application designThis parameter, not specified in the L6561 though present, is specified in the L6562ZERO CURRENT DETECTOR SymbolParameterTest conditionL6561L6562Unit V ZCDH Upper clamp voltage for L6561: I ZCD =-3mAfor L6562: I ZCD =-2.5mA 4.7 5.26.1 5.0 5.76.5V I ZCDsrc Source current capability-3-10-2.5-5.5mA I ZCDsnk Sink current capabil-ity3102.5mA V ZCDen Restart threshold 350mV I ZCDresRestart current after disable-100-200-3003075µASTARTER Symbol Parameter Test conditionL6561L6562Unit t ST ARTStart Timer period7015040075130300µsOUTPUT OVERVOLTAGE Symbol Parameter Test conditionL6561L6562Unit Hys.Dynamyc OVP Hys-teresys30µAAN1757 APPLICATION NOTE4/9ELECTRICAL CHARACTERISTICS (continued)Dropout voltage: this is a fixed offset due to the internal driver structure that has been changed.Current Rise and fall time: the driver modification has led to a lower driver dynamic resistance and the effect is the reduction of fall and rise time of the driver current.Output Clamp voltage: the high-level voltage of this pin is clamped at about 12V to avoid excessive gate volt-ages in case the pin is supplied with a high Vcc.(*): the aim of this feature is to avoid undesired MOSFET turn-on due to spurious spikes when the IC is under UVLO condition. In the L6561 this feature is characterized through the current that the GD pin is able to sink under the given test conditions.For the L6562 it is guaranteed that over the whole UVLO range, the GD pin is able to sink up to 10mA without exceeding 1.1V, a voltage definitely lower than the turn-on threshold of the MOS.3THD OPTIMIZER CIRCUITThe L6562 is equipped with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably reduced, as shown in fig. 2.Figure 2. L6562 vs. L6561: THDGATE DRIVER Symbol ParameterTest condition L6561L6562Unit V OH Dropout voltageI Gdsource = 20 mA0.712 2.6V I GDsource = 200 mA 1.22 2.53V V OL I GDsink = 200 mA1.50.9 1.9V tf Current fall time 401003070ns tr Current rise time 401004080ns V Oclamp Output clamp volt-ageI GDsource = 5mA; Vcc = 20V not present101215V (*)I GD Sink Current V CC =3.5V V GD = 1V 510mA (*)UVLO saturationVcc = 0 to Vccon, I sink =10mA1.1VAN1757 APPLICATION NOTE A major cause of this distortion is the inability of the system to transfer energy effectively when the instanta-neous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop.To overcome this issue, the circuit embedded in the L6562 forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter ca-pacitor after the bridge.Figure 3 shows the THD corrector circuit block diagram and the waveforms in the significant points; the multiplier has two inputs: the first one is a fraction of the rectified input voltage and the second one is the output of L6562 error amplifier. The multiplier output is the product of these two quantities and (ideally) is a rectified sinusoid whose peak amplitude decreases by increasing the input voltage.This waveform represents the threshold that the current sense voltage must cross to trigger the PWM compar-ator (see fig. 1).Essentially the THD improvement circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is re-duced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves to-ward the top of the sinusoid.The effect of the circuit is shown in the figure 4, where the key waveforms of a standard TM PFC controller are compared to those of the L6562.To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC pre-regulator - thus making the action of the optimizer circuit little effective.Figure 3. THD corrector: block diagram5/9AN1757 APPLICATION NOTE6/9Figure 4. Effect of THD optimizer circuitFigure 5. EVAL6562N-80W schematicImains Vdrain Imains Vdrain Input current Input currentMOSFET's drain voltageMOSFET's drain voltageRectified mains voltage Rectified mains voltageInput currentInput currentT1FUSEB1C1R1R5R6C5NTC R4D8D2D18521R14C3C23R5R51R2R11R12V O =400VP O =80W+7/9AN1757 APPLICATION NOTEPART LISTT1: Boost Inductor Spec (ITACOIL E2543/E)–E25x13x7 core, 3C85 ferrite–1.5mm gap for 0.7mH primary inductance –Primary: 105 turns (20 x 0.1mm)–Secondary: 11 turns (0.1mm)Figure 6. EVAL6562N-80W: efficiency (left, in %) and Power Factor (right) vs. input voltageR1750k Ω 1%R14100Ω, 5%C647µF, 450VR2750k Ω 1%R15shorted C7N.A.R310k Ω 1%R5012k ΩC23330nF R4, R5180k Ω 5%R51N. A.C2922µF, 25V R668k Ω 5%NTC 2.5D1STTH1L06R733ΩC10.47µF 400VD21N5248B R847k ΩC210nF D81N4148R9, R100.82Ω, 0.6W C30.68µF Q1 (TO220)STP8NM50R11, R12750k Ω, 1%C4100nF BRIDGE DF06M R139.53k Ω, 1%C512nFFUSE4A/250VAN1757 APPLICATION NOTEFigure 7. EVAL6562N-250 schematicPART LIST:R1, R2910kΩ 1%R179.53KΩ, 1%C9OPEN R313kΩ 1%R18SHORT D11N4148 R4, R5180kΩ 5%R19SHORT D2 (DO-201AD)STTH3L06 R6100Ω 5%C11µF, 400V D3ZENER 18V R747kΩ 5%C222µF, 25V D41N5406R8, R11, R14OPEN C3100nF D51N4148 R920kΩ C4, C510nF Q1 (TO220)STP20NM50 R1033Ω, 5%C6680nF BRIDGE STBR606 (ST) R12, R130.33Ω, 1W C7220nF FUSE4A/250V R15, R16750KΩ, 1%C8100µF 450V NTC 2.5 HEATSINKER: Aavid Thermalloy Max Clip S508T1: Boost Inductor Spec: EB0057-C (COILCRAFT)8/9Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronics.All other names are the property of their respective owners© 2004 STMicroelectronics - All rights reservedSTMicroelectronics GROUP OF COMPANIESAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States9/9AN1757 APPLICATION NOTEFigure 8. PF vs. Input VoltageFigure 9. THD vs. Input VoltageFigure 10. Efficiency ( %) vs. Input VoltageL6562-250W demo board evaluation:REFERENCESAN1007: "L6561 - BASED SWITCHER REPLACES MAG AMPS IN SILVER BOXES"AN1059: "DESIGN EQUATIONS OF HIGH - POWER - FACTOR FLYBACK CONVERTERS BASED ON THEL6561"AN1060: "FLYBACK CONVERTERS WITH THE L6561 PFC CONTROLLER"AN1089: "CONTROL LOOP MODELING OF L6561 - BASED TM PFC"。

©On-Bright Electronics Confidential DESCRIPTIONSOB6563 is an active transition-mode (TM) power factor correction (PFC) controller for AC-DC switching mode power supply applications.OB6563 features an internal start-up timer for stand-alone applications, a one quadrant multiplier with THD optimizer for near unity power factor, zero current detector (ZCD) to ensure TM operation, a current sensing comparator with built-in leading-edge blanking, and a totem pole output ideally suited for driving a power MOSFET.OB6563 offers great protection coverage including system over-voltage protection (OVP) to eliminate runaway output voltage due to load removal, VCC under voltage lockout (UVLO), cycle-by-cycle current limiting, multiplier output clamping that limit maximum peak switch current, and gate drive output clamping for external power MOSFET protection.With added system open loop protection feature, OB6563 shuts down system when the feedback loop is open.In OB6563, the dynamic OVP sensing current is set to 10uA, which will decrease system standby power greatly. When used with On-Bright PWM controller OB2298 or Quasi-Resonant controller OB2203 in a 150W AC/DC power design, it can deliver <0.4W standby power at universal AC range input.OB6563 is offered in SOP-8 and DIP-8 packages.FEATURES• Transition Mode (TM) Operation• One quadrant multiplier with THD optimizer • Low Dynamic OVP Sensing Current Setting • Low Start-up Current and Operating Current • Cycle-by-Cycle Current Limiting • Internal RC Filter• Trimmed 1.5% Internal Bandgap Reference • Under Voltage Lockout with Hysteresis• Very Precise Adjustable Output Overvoltage Protection• Internal Start-up Timer for Stand-alone Applications • Disable Function• Totem Pole Output with High State Clamping • System Open Loop Protection• Proprietary Audio Noise Free Operation • 9.5V to 28V wide range of VCC voltageAPPLICATIONS• Electronic Ballast • AC-DC SMPSTYPICAL APPLICATIONGD CSVCC 12348765ZCD MULT COMP INV ACGND OB6563C1C2C3R1C4C5R2R3R4R5Q1D1L1C6R6D2D3R7R8++On -B ri g ht Co nf i dnt i a l toC h a r mr i ch©On-Bright Electronics Confidential GENERAL INFORMATIONTerminal Assignment In SOP8 or DIP8 Package.Ordering Information Part Number Description OB6563AP 8 Pin DIP, Pb free in Tube OB6563CP 8 Pin SOP, Pb free in Tube OB6563CPA 8 Pin SOP, Pb free in T&RPackage Dissipation RatingPackageR θJA (　C/W) DIP8 90 SOP8 150Absolute Maximum Ratings Symbol Parameter Value VCC DC Supply voltage30 VI_ZCDZero CurrentDetector Max.Current50mA(source)-10mA(sink)CS INV COMP MULTAnalog inputs & outputs-0.3 to 7VTj Min/Max Operating Junction Temperature-40 to 150 oC TstgMin/Max StorageTemperature-55 to 150 oCLead Temperature (Soldering, 10secs ) 260 oCNote: Stresses beyond those listed under “absolute maximumratings” may cause permanent damage to the device. These are stress ratings only, functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.12348765INVCOMP MULTCS VCC GD GND ZCD On -B ri g ht Co nf i de nt i a l toC h a r mr i ch©On-Bright Electronics Confidential Marking InformationTERMINAL DESCRIPTIONSPin Num Pin Name I/O Description 1 INV I Inverting Input of Error Amplifier. Connected to Resistor Divider fromSystem Output. This pin is also used for system open loop protection.2 COMP O Output of Error Amplifier. A feedback compensation network is placedbetween COMP and the INV pin.3 MULT I Input of Multiplier. Connected to Line Voltage after Bridge Diodes via AResistor Divider to Provide Sinusoidal Reference Voltage to the Current Loop.4 CS I Current Sense Input Pin. Connected to MOSFET Current Sensing Node.5 ZCD I Zero Current Detection Input. When Activated, A New Switching CycleStarts. If it is connected to GND, the device is disabled.6 GND P Ground Pin7 GD O Gate driver output. Drive Power MOSFET.8 VCC P DC Supply Voltage.On -B ri g ht Co nf i de nt i al toC h a r mr i ch©On-Bright Electronics Confidential BLOCK DIAGRAMOn -B ri g ht Co nf i de nt i a l toC h a r mr i ch©On-Bright Electronics Confidential ELECTRICAL CHARACTERISTICS(T A = 25O C if not otherwise noted)Symbol Pin Parameter Test Conditions Min Typ Max Unit SUPPLY VOLTAGE SECTION Vcc 8 Operating Range After Turn On 11 28 V 8 Turn-on Threshold 11 12 13 VUVLO8 Turn-off Threshold 8.5 9.5 10.5 VHys 8 Hysteresis 2.5 V Vz 8 Zener Voltage Icc =5mA 30 33 36 VSUPPLY CURRENT SECTIONIcc-start 8 Start-up Current Vcc =11V 35 70 uA Iq 8 Quiescent Current, NoSwitchingVcc =14.5V 2.9 4 mAC L =1nf @ 70kHz 4 5.5 mAIcc 8 Operating Supply Current In OVP condition Vpin1=2.7V1.42.1 mAVpin5≤150mV Vcc=14.5V1.12.1 mAIq 8 Quiescent Current Vpin5≤150mV, Vcc<Vcc off35 70 uA ERROR AMPLIFIER SECTIONVinv 1 Voltage Feedback Input Threshold V cc =14.5V 2.45 2.5 2.55 V Vinv 1 Line Regulation 12V<Vcc<28V 2 5 mVIinv 1 Input Bias Current I DD = 10 mA -0.1 -1 uA Gv Voltage Gain Open Loop 60 80 dB Gb Gain Bandwidth 1.2 MHzSource Current Vcomp=3.6V, Vinv=2.4V -1 -3 -5 mAIcomp 2Sink Current Vcomp = 3.6V, Vinv = 2.6V 1 3 5 mA Upper Clamp Voltage Isource=0.5mA 4.9 VVcomp 2Lower Clamp Voltage Isink =0.2mA2.25 V MULTIPLIER SECTION Vmult 3 Linear Operating Range Vcomp=3.0V 0 to3.5VΔVcs/ ΔVmult Output Max. Slope Vmult=from 0 to 0.5v Vcomp=Upper ClampVoltage1.65 1.9 V/V K Gain Vmult =1V, Vcomp =3.5V 0.65 1/V CURRENT SENSE COMPARATOR Vcs 4 Current Sense Reference Clamp Vmult=2.5V Vcomp=Upper ClampVoltage1.55 1.7 1.85 VIcs 4 Input Bias Current Vcs=0 0.1 uA Td(H-L) 4 Delay to Output 200 450 ns On -B ri g ht Co nf i de nt i a l toC h a r mr i ch©On-Bright Electronics Confidential ELECTRICAL CHARACTERISTICS (Continued)(T A = 25O C if not otherwise noted)Symbol Pin Parameter Test Conditions Min Typ Max Unit ZERO CURRENT DETECTOR Input Threshold Voltage Rising Edge1.9VVzcd 5 Hysteresis 0.3 0.5 0.7 VVzcd 5 Upper Clamp Voltage Izcd=2.5mA 5.1 5.7 6.3 V Vzcd 5 Lower Clamp Voltage Izcd =-2.5mA 0.4 0.65 0.8 V Izcd 5 Input Bias Current 1V ≤Vzcd ≤4.5V 2 uA Izcd 5 Source Current Capability -3 -5 mA Izcd 5 Sink Current Capability 3 10 mA Vdis 5 Disable Threshold 150250 350mV Izcd 5 Restart Current After Disable Vzcd<VdisVcc>Vccoff-100 -200 -400 uAGATE DRIVE SECTIONVoL 7 Low Output Voltage Vcc=14.5V, Io=100mA 1.5 VVoH 7 High Output Voltage Vcc=14.5V, Io=100mA 8 VTr 7 Rising Time Cl =1000pF, 10~90% 80 150ns Tf 7 Falling Time Cl =1000pF, 10~90% 30 70 ns Voclamp 7 Output ClampVoltage Vcc =28V 16 18 V OUTPUT OVER VOLTAGE SECTION Iovp 2 Dynamic OVP Triggering Current 8 10 12 uAStatic OVP Threshold 2.1 2.25 2.4 V STARTUP TIMER Tstart Re-Start Timer Period 70 150 300 us SYSTEM OPEN LOOP PROTECTION COMPARATOR Vth_ol System Open Loop Protection Comparator Threshold250 mVOn -B ri g ht Co nf i de nt i a l toC h a r mr i ch©On-Bright Electronics Confidential TYPICAL PERFOMANCE CHARTOperating Current vs Supply Voltage 3.03.54.04.55.05.51015202530VCC(V)I c c (m A )Quiescent Current vs VCC1234051015202530VCC(V)I q (m A )Operating Current vs Temperature4.04.24.44.64.85.0-20104070100130Temperature(℃)I c c (m A )UVLO vs Temperature8910111213-20104070100130Temperature(℃)U V L O (V )Reference Voltage vs Temperature2.402.452.502.552.60-20104070100130Temperature(℃)V i n v (V )Multiplier Gain vs Temperature0.40.50.60.70.8-20104070100130Temperature(℃)K (1/V )On -B ri g ht Co nf i de nt i a l toC h a r mr i ch©On-Bright Electronics ConfidentialCurrent Sense Threshold Clamping vsTemperature1.41.51.61.71.8-20104070100130Temperature(℃)V C S (V )Startup Current vs Temperature20253035404550-20104070100130Temperature(℃)I s t a r t u p (u A )Gate Driver Clamping vs Temperature1415161718-20104070100130Temperature(℃)V g a t e _m a x (V )Restart Timer Period vs Temperature100120140160180-20104070100130Temperature(℃)T _w a t c h d o g (u s )Multiplier Characterization0.00.20.40.60.81.01.21.41.61.82.00.00.51.01.52.02.53.03.54.04.5Vmult(V)M u l t i p l i e r O u t p u t (V )COMP=2.8V COMP=3.0V COMP=3.2V COMP=3.5V COMP=4.0V COMP=4.5V COMP=5.0VDynamic OVP Triggering Current(uA)vsTemperature89101112-201040 70 100130Temperature(℃ )O-B ri g ht Co nf i de nt i a l toC h a r mr i ch©On-Bright Electronics ConfidentialOPERATIONAL DESCRIPTIONOB6563 is a highly integrated power factor correction (PFC) controller IC. The transition mode control greatly reduces the switch turn-on loss, improves the conversion efficiency and provides very good power factor correction.• Error AmplifierConnected to a resistor divider from output line, the inverting input of the Error Amplifier (E/A) is compared to an internal reference voltage(2.5V) to set the regulation on output voltage.The E/A output is internally connected to the multiplier input and externally connected for loop compensation. It is usually realized with a capacitor which connected between the inverting input and EA output. The system loop bandwidth is set below 20 Hz to suppress the AC ripple of the line voltage.• MultiplierThe one quadrant multiplier output limits the MOSFET peak current with respect of the system output voltage and the AC half wave rectified input voltage. Through controlling the CS comparator threshold as the AC line voltage traverses sinusoidally from zero to peak line voltage, the PFC preconverter’s load appears to be resistive to the AC line.In OB6563, the two inputs for the multiplier are designed to achieve good linearity over a wide dynamic range to represent an AC line free from distortion. Special efforts have been made to assure universal line applications with respect to a 90 to 264 VAC range.The multiplier output is internally clamped to 1.7V. So the MOSFET is protected against critical operation during start up.• Output Overvoltage ProtectionLimited by low loop bandwidth setting, detection of output OVP could become very slow in regular approach. OB6563 offers two level OVP protection including dynamic OVP for output fast transient protection and static OVP for output stead-state protection.In an output transient OVP event, current in proportion to ΔV flows into Error Amplifier output COMP through compensation network. When this current reaches 8uA, the output of multiplier is forced to decrease and on-time of MOSFET is reduced. When current continues to exceed 10uA, the power MOSFET is turned off until the current falls below ~2.5uA. In this way, the system output cannot reach to a very high value.When OVP event lasts long enough, the Error Amplifier Output, COMP, will saturate and stay low. Static OVP comparator is activated and power MOSFET Gate is off when COMP voltage is dropped below 2.25V. Normal operation is resumed when Error Amplifier goes back to its linear region after output voltage drops.Overvoltage protection block• Startup Current and Start up ControlThe typical startup current of OB6563 is 35uA when the VCC pin is lower than the UVLO threshold so that VCC could be charged up and start up the device. A high value, low wattage startup resistor can therefore be used to minimize the power loss during the normal operation.• Current Sensing Comparator and Leading EdgeBlankingCycle-by-cycle current limiting is provided in OB6563’s peak current mode control. The switch current is detected by a sense resistor into the sense pin. The multiplier output voltage is compared with this sense voltage through an internal comparator. An internal RC filter is connected at the CS pin which smoothes the switch-on current spike. The remaining switch-on spike is blanked out via an internal leading edge blanking (LEB) circuit. Another extra function of LEB is that it limits the system minimum on time, thus the THD of system at light load will be decreased.The RS flip-flop ensures that only one single switch-on and switch-off pulse appears at the gate drive output during a given cycle.• Zero Current DetectionOn -B ri g ht Co nf i de nt i a l toC h a r mr i ch©On-Bright Electronics Confidential OB6563 can perform zero current detection by using an auxiliary winding of the inductor. When the stored energy is fully released to the output, the voltage at ZCD decrease. A new switching cycle is initiated following the ZCD triggering. The turn on of power MOSFET is initiated at moment that the inductor’s current reaches zero.• Disable FunctionWhen the ZCD pin is pulled low, OB6563 is disabled and some internal functional blocks are turned off. The operation current is very small under this condition until the ZCD pin is released.• Gate Drive OutputThe output stage is designed to ensure zero cross-conduction current. This minimizes heat dissipation, increase efficiency, and enhance reliability. The output driver is also slew rate controlled to minimize EMI. Thebuilt-in 16V clamp at the gate output protects the MOSFET gate from high voltage stress.• Protection ControlsOB6563 ensures good reliability design through its good protection coverage. Output dynamic and static over-voltage protection (OVP), VCC under voltage lockout (UVLO), cycle-by-cycle current limiting and output gate clamp are standard features provided by OB6563.• System Open Loop ProtectionA new function of system open loop protection is provided in OB6563. The voltage at INV pin is sensed. If INV pin is below 0.25V typical, the switching will be stopped. In this way, the system output voltage cannot increase too high (only the rectified line voltage), and the pre-converter will be protected from damage.On -B ri g ht Co nf i de nt i a l toC h a r mr i ch©On-Bright Electronics ConfidentialPACKAGE MECHANICAL DATA8-Pin Plastic DIPDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 3.710 4.310 0.146 0.170 A1 0.500 0.020 A2 3.200 3.600 0.126 0.142B 0.350 0.650 0.014 0.026 B1 1.524 (BSC) 0.060 (BSC)C 0.200 0.360 0.008 0.014D 9.000 9.500 0.354 0.374E 6.200 6.600 0.244 0.260 E1 7.320 7.920 0.288 0.312 e 2.540 (BSC) 0.100 (BSC) L 3.000 3.600 0.118 0.142 E2 8.200 9.000 0.323 0.354On -B ri g ht Co nf i de nt i a l toC h a r mr i ch©On-Bright Electronics Confidential8-Pin Plastic SOPDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 1.350 1.750 0.053 0.069 A1 0.100 0.250 0.004 0.010 A2 1.300 1.550 0.051 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010D 4.700 5.150 0.185 0.203E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 0.244 e 1.270 (BSC) 0.050 (BSC)L 0.400 1.270 0.016 0.050 θ 0º 8º 0º 8ºOn -B ri g ht Co nf i de nt i a l toC h a r mr i ch©On-Bright Electronics Confidential IMPORTANT NOTICERIGHT TO MAKE CHANGESOn-Bright Electronics Corp. reserves the right to make corrections, modifications, enhancements, improvements and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.WARRANTY INFORMATIONOn-Bright Electronics Corp. warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with its standard warranty. Testing and other quality control techniques are used to the extent it deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.On-Bright Electronics Corp. assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using On-Bright’s components, data sheet and application notes. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.LIFE SUPPORTOn-Bright Electronics Corp.’s products are not designed to be used as components in devices intended to support or sustain human life. On-bright Electronics Corp. will not be held liable for any damages or claims resulting from the use of its products in medical applications.MILITARYOn-Bright Electronics Corp.’s products are not designed for use in military applications. On-Bright Electronics Corp. will not be held liable for any damages or claims resulting from the use of its products in military applications.On -B ri g ht Co nf i de nt i a l toC h a r mr i ch。

PHY6562D(DIP-8L&SOP-8L) PHY6562D图图1.1cos将电压ωcos(ω，其中电压与电流的相角之差为图1.41.4图1.3图1.3所示的全波整流电路中，输入交流电压滤波后得到如图黑粗线所示的波形。

图可以看出尽管v脉动的波形含有许多谐波成份，这些谐波成份亦为影响功率因数的原因。

此时cos(图2.1i v Vdc图图校正器使用一种类似与图的控制方案。

具有低频极点的误差放大器向参考乘法器提供一个误差信号，乘法器的另一个输入是经整流的交流输入线电压的比例信号。

乘法器的输出是误差放大器的近似直流信号与全波整流比例信号的乘积，它也是经增益系数变换后的全波整流正弦信号，且被用作输入电压的参考。

此信号的幅度经调整后可保持正确的平均功率，以使输出电压保持在稳定的水平。

PHY6562DPHY6562DPHY6562D2.42.4当功率开关导通时，构成如图所示的等效电路，转换器将形成两个独立的回路。

回路对升压电感则是由电容与级负载所组成，此时输出电容将原先所储存的能量供给负载以维持所示。

此时输入电压2.2.55LDT L T t v on )( 为功率开关为占空比。

由上式可知，在一个输入电压周期内，若功率开关的导通所示。

这样输入电流与输入电压为同相PHY6562DPHY6562D 比较器和过压保护模块器和过压保护模块器和过压保护模块I∆图2.6 乘法器功能模块乘法器功能模块四分之一象限乘法器是获得功率因数校正的关键。

乘法器的输入主要来自两个信号，一个来自输入交流经全波整流后的取样信号，一个来自误差放大器E/A的输出与参考电压器的输出控制限流比较器的门限电压，这样可以使电感的峰值电流跟随交流线电压，从而迫使输入的平均电流为正弦波。

换而言之，这将产生一个固定的驱动时间，以迫使而使预转换器负载对交流线路呈现电阻性。

下面的公式描述了乘法器的输入与输出的关系。

的输出所控制。

而在非正常状态下，譬如，预转换器以高压启动或输出电压跌落，在这些情况下，乘法器的输出亦即电流比较器的门限，将被内部箝位在功能模块零电流检测功能模块模式，内置的零电流检测器能够利用辅助绕组实现对电感上零电流的检测功能。

L6561 应用笔记中文版L6561 ，增强版的临界模式功率因数校正器TM（临界模式）技术广泛应用于低功率产品的功率因数校正，例如灯具镇流器，视频终端控制电路。

L6561是后期针对这个市场推出的产品，不但符合要求而且是一款低价的功率因数校正器。

基于一个非常好的电路架构，L6561展现出非常优越的性能，而且应用领域更为广泛。

介绍传统的单级离线式转换电路，都是由一个全桥整流和一个电容滤波构成。

通过交流主线电源获得一个未校准的直流电压，滤波电容必须足够大以便可以得到一个纹波电压比较小的直流电压，这就意味着在大多数时间内，电容上的电压高于输入AC电源线电压，这就意味着，全桥整流电路仅在输入线电压每半周期内（因为有整流桥的存在，整流后的每个周期相当于AC电源的半个周期），工作很短的时间。

使得从电网输入的电流变成很窄的脉冲波形，其幅度是同等直流电压下电流幅度的5-10倍。

许多缺点因此而产生：过高的峰值电流和RMS电流比，使得交流电网电压畸变，在三相线输电电网中，使中性线过电流，总之，会使电网的输电能力减弱。

关于这项指标，可以参考谐波允许量标准EN61000-3-2,或功率因数PF，有功功率（传送到输出端的功率）和输入视在功率（线电压真有效值和线电流真有效值的乘积）的比值，功率因数PF是最直观的。

传统的输入电容滤波电路功率因数很低（05-0.7），并且谐波含量很高。

图1. L6561内部模块图由于使用了开关技术，功率因数矫正器（PFC）位于整流桥和滤波电容之间，从电源获取一个准正弦波电流，与线电压同步，功率因数变得非常接近1（可以超过0.99），上述的缺点得以消除。

从理论上来讲，任何开关拓扑技术都可以用来获取一个高功率因数，但是，实际应用中，升压拓扑是一种最流行的方式，因为它有以下优势：1）主要是，因为升压电路所需的元件最少，因此这种方式最便宜。

还有：2）由于升压电感位于整流桥和开关之间，引起的电流di/dt比较低，可以使输入产生的噪音最小化，可以减少输入EMI滤波元件。

1200AP40 1200AP60、1203P60 200D6、203D6 DAP8A 可互代203D6/1203P6 DAP8A 2S0680 2S0880 3S0680 3S0880 5S0765 DP104、DP704 8S0765C DP704加24V的稳压二极管ACT4060 ZA3020LV/MP1410/MP9141 ACT4065 ZA3020/MP1580 ACT4070 ZA3030/MP1583/MP1591MP1593/MP1430 ACT6311 LT1937 ACT6906 LTC3406/AT1366/MP2104 AMC2576 LM2576 AMC2596 LM2596 AMC3100 LTC3406/AT1366/MP2104 AMC34063A AMC34063 AMC7660 AJC1564 AP8012 VIPer12A AP8022 VIPer22A DAP02 可用SG5841 /SG6841代换DAP02ALSZ SG6841 DAP02ALSZ SG6841 DAP7A、DP8A 203D6、1203P6 DH321、DL321 Q100、DM0265R DM0465R DM/CM0565R DM0465R/DM0565R 用cm0565r代换〔取掉4脚的稳压二极管〕DP104 5S0765 DP704 5S0765 DP706 5S0765 DP804 DP904 FAN7601 LAF0001 LD7552 可用SG6841代〔改4脚电阻〕LD7575PS 203D6改1脚100K电阻为24K OB2268CP OB2269CP OB2268CP SG6841改4脚100K电阻为20-47K OCP1451 TL1451/BA9741/SP9741/AP200 OCP2150 LTC3406/AT1366/MP2104 OCP2160 LTC3407 OCP2576 LM2576 OCP3601 MB3800 OCP5001 TL5001 OMC2596 LM2596/AP1501 PT1301 RJ9266 PT4101 AJC1648/MP3202 PT4102 LT1937/AJC1896/AP1522/RJ9271/MP1540 SG5841SZ SG6841DZ/SG6841D SM9621 RJ9621/AJC1642 SP1937 LT1937/AJC1896/AP1522/RJ9271/MP1540 STR-G5643D STR-G5653D、STR-G8653D TEA1507 TEA1533 TEA1530 TEA1532对应引脚功能接入THX202H TFC719 THX203H TFC718S TOP246Y TOP247Y VA7910 MAX1674/75 L6920 AJC1610 VIPer12AVIPer22A [audio01]ICE2A165(1A/650V.31W);ICE2A265(2A/650V.52W);ICE2B0565(0.5A/6 50V.23W):ICE2B165(1A/650V.31W);ICE2B265(2A/650V.52W);ICE2A180(1A/800V.29W);ICE2 A280(2A/800.50W).KA5H0365R, KA5M0365R, KA5L0365R, KA5M0365RN# u) t! u1 W1 B) R, PKA5L0365RN, KA5H0380R, KA5M0380R, KA5L0380R1、KA5Q1265RF/RT〔大小两种体积〕、KA5Q0765、FSCQ1265RT、KACQ1265RF、FSCQ0765RT、FSCQ1565Q这是一类的，这些型号的引脚功能全都一样，只是输出功率不一样。

GL85XDesignGuide（E）_201Genesys Logic, Inc.USB 2.0 High-Speed HUB Controller Design GuideRevision 2.01 Oct. 14, 2010USB 2.0 Hub Design GuideCopyrightCopyright ? 2010 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.Ownership and TitleGenesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder.DisclaimerAll Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice.Genesys Logic, Inc.12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel : (886-2) 8913-1888 Fax : (886-2) 6629-6168http :///doc/d150fc3ab90d6c85ec3ac648. html2010 Genesys Logic, Inc. - All rights reserved.Page 2USB 2.0 Hub Design GuideRevision HistoryRevision 1.00 1.10 1.11 1.12 1.50 1.60 1.70 1.80 Date 07/03/2003 10/29/2003 03/23/2004 02/22/2005 07/13/2005 11/13/2006 11/29/2006 08/31/2009 First formal release Change large contents in Ch1 ~ Ch6 Add notice item 7 in Ch6 Add GL850A Add GL852, remove GL850 Modify X’tal. Modify Figure3 Modify 2.1, 2.3, p.6-7 Add 2.4, 2.5, p.7-8 Modify Ch4, Ch5, p.11-12 Modify 2.1, p.6 Add 2.6, p.9 Modify Ch5, p.13 Add 5.6, p.13 Modify 5.6, p.13 Description1.902.00 2.0112/17/2009 01/26/2010 10/14/20102010 Genesys Logic, Inc. - All rights reserved.Page 3USB 2.0 Hub Design GuideTable of Contents1.PREFACE ............................................................................................................. ................ 5 2. GENERAL OF THE USB2.0 HIGH SPEED SIGNAL ALLOCATION........................ 6 2.1 Circuitry Routing and Component Placement of the 4-Layer PCB......................... 6 2.2 Routing and Placing of Components on 2-Layer PCB.. (7)2.3 Layout of D+, D- ............................................................................................................ 7 2.4The Completeness of GND............................................................................................ 8 2.5 Power Trace ...................................................................................................................8 2.6 Crystal Routing and Placement ................................................................................... 9 3. LAYOUT DIAGRAM........................................................................................................10 3.1 Single Side Placement (10)3.2 Placement on the Both Sides....................................................................................... 11 3.3 Differential Signal Source Traces (D+, D-) ............................................................... 114. GROUNDING AND POWER LAYOUT......................................................................... 125. SPECIALNOTES ..............................................................................................................132010 Genesys Logic, Inc. - All rights reserved.Page 4USB 2.0 Hub Design Guide1. PREFACEThe purpose of this document is to provide suggestions and descriptions for the design of PCB layout about USB 2.0 High-Speed Hub Controller of Genesys Logic Inc., so that the client can verify in the shortest time and start mass production.2010 Genesys Logic, Inc. - All rights reserved.Page 5USB 2.0 Hub Design Guide2. GENERAL OF THE USB2.0 HIGH SPEED SIGNAL ALLOCATION2.1 Circuitry Routing and Component Placement of the 4-Layer PCB1. Use 4-layer PCB: 1st Layer for component placement and signal layout, 2nd Layer: GND, 3rd Layer: Power, and 4th Layer: layout of signal lines. Layer Layer 1 Layer 2 Layer 3 Layer 4 Description Signal Layer 1 Ground Power Signal Layer 2 Routing of USB2.0 D+/D- data signal shall be on Signal layer 1 2. Firstly place X’tal and D+ & D- write; they must be of equal length, parallel and equal spacing.3. No wire is allowed underneath the X’tal. X’tal is to be as near the IC as possible. The maximum su ggested distance between X’tal trace and the IC is 1cm.4. Both sides of X’tal IN/OUT leads shall be enveloped by GND to avoid noise interference. (Fig. 3.2)5. Enlarge the Power Trace of upstream port and downstream port to at least 50 mil. If punch-through hole is required to connect the pack face, use multiple holes to avoid voltage drop. Take special attention on this, for voltage drop is verified at USB-IF Logo certification. Unsteady voltage causes signal to jitter severely and thus failure of compatibility test.6. All wires shall not have 90-degree turns. If such turns are inevitable, make an arc or double 45° to replace them, see Fig. 2.1. It will help to minimize the EMI problems.Figure 2.12010 Genesys Logic, Inc. - All rights reserved.Page 6USB 2.0 Hub Design Guide7. Forbid any Power Trace or Clock Line to pass underneatha Chip. 8. All Beads are to be placed as near to the USB connectoras possible. 9. All bypass and electrolytic capacitors are to be placed as near the IC as possible. 10. All coupling capacitors of D+/D- shall be placed as near the IC as possible. 11. Avoid punch-through holes at: D+, D-, X1 and X2. A punch-through hole may cause variation of signal line impedance, and distortion of signal in severe case. If it is inevitable to make such holes, the waveform will be inferior to that without the holes. The client shall make their own decision.2.2 Routing and Placing of Components on 2-Layer PCB1. Using 2-layer PCB: GL provides 2-layer Demo Boards presently, of which the layout principle is similar to 4-layer boards as described above.2. When using a 2-layer board, GND shall be paved on the back of D+/D- signal lines so as to lower trace impedance of the D+/D- signal line and stabilize the signal.2.3 Layout of D+, D1. Keep aw ay from the X’tal, keep in the same layer as possibly can, make minimum turns and take shorted length to the USB connector. 2. Wires for D+, D- shall be parallel and guarded by GND.3. Beware of stubs on HS signals. (Resister and capacitors shall be mounted directly on the wires.)4. Wiring diagram of D+, D- (90 Ohm impedance) is as Fig. 2.2: This is a reference diagram of 4-layer PCB with a 1.6 mm thick; trace for the 2-layer PCB shall have the same values. Mind the width of D+/D- Tracing and the spacing between them; get PCB thickness from the manufacturer so as to verify the PCB Impedance if it meets with 90 ±10% . If the PCB manufacturer provides TDR measurement, it helps control the PCB Impedance. The GND of the signal lines shall have spacing of at least 20mil with the signal lines. The width and spacing of the D+/D- tracing shall be the same and approximate the spacing (W approximate S). (Fig. 2.2)Figure 2.22010 Genesys Logic, Inc. - All rights reserved.Page 7USB 2.0 Hub Design Guide 2.4 The Completeness of GNDKeep GND plane with no interruptions when routing power traces.Power (Bottom) GND Plane (Bottom) DP/DM (Top)XFigure 2.32.5 Power TraceKeep the PCB power trace connected to the internal 5 to 3.3V regulator as short as possible in order to prevent the interference between other signal lines and power trace. It will help to minimize EMI problem.3.3Vout 5VinFigure 2.42010 Genesys Logic, Inc. - All rights reserved.Page 8USB 2.0 Hub Design Guide 2.6 Crystal Routing and Placement1. Keep the distance between X’tal and the IC less then 1cm to avoid triggering high frequency oscillation on PCB.2. If over 1cm is unavoidable in the design, place the capacitors and the resistor as close as possible to the IC. Recommend less than 1cm if possible. And the resistor need be between the IC and the capacitor. See Figure2.5.Figure 2.53. Do not route X1 and X2 underneath the IC. In this case, itmay cause noise on PCB and will trigger high frequency oscillation.Figure 2.62010 Genesys Logic, Inc. - All rights reserved.Page 9USB 2.0 Hub Design Guide3. LAYOUT DIAGRAM3.1 Single Side PlacementFigure 3.11. In single sided placement, layout the 0.1μF bypass capacitor nearest to the chip.2. Trace the D+, D- in priority, with the resister nearest to the chip (Fig.3.1). 3. Better EMI effect can be attained by a one-piece GND underneath the IC furnished with PTH holes to enlarge the GND area (as shown in Fig. 3.1).4. The X’tal (oscillator) traces shall be surrounded by GND to prevent interference to other signal wires (as shown in Fig. 3.1). The X’tal traces shall be symmetrical and parallel in order to get better oscillation wave form and better EMI protection (as shown in Fig. 3.2).Figure 3.22010 Genesys Logic, Inc. - All rights reserved.Page 10USB 2.0 Hub Design Guide 3.2 Placement on the Both Sides For placement on the both sides, place the 0.1μF bypass capacitor to the opposite side of the IC as shown in Fig. 3.3.Figure 3.33.3 Differential Signal Source Traces (D+, D-)USB signal traces shall be placed parallel as in Fig. 3.4, not asin Fig. 3.5.Figure 3.4Figure 3.52010 Genesys Logic, Inc. - All rights reserved.Page 11USB 2.0 Hub Design Guide4. GROUNDING AND POWER LAYOUTProper design of grounding cleans up signal by effectively draining the noises, it also saves testing time and lowers production cost, and, it does not affect the product’s function.1. Distribute Power and GND in grids.2. Make power plane smaller than ground area.3. Use multi-place GND (as in Fig.4.1), fill empty space with GND. Make ground area as large and as large and integrated as possible.Figure 4.14. Reserve Ferrite Beads for the Shielding GND of USB connectors.5. Beads shall be added before connecting the Power and GND to an IC.6. A shielding band, 1/2” on the peripheral of the upper and lower layers, shall be provided and connected to the Shielding GND.7. Digital GND and Analog GND can be placed together in one-piece so as to enlarge the GND, and thus helping dissipation of noises.8. Digital Power and Analog Power shall be handled separately with different blocks to supply power to IC chip and peripheral components; a bead shall be connected in-between to isolate the noise source.2010 Genesys Logic, Inc. - All rights reserved.Page 12USB 2.0 Hub Design Guide5. SPECIAL NOTES1. GL85X is relatively sensitive to Power Noise interference, and therefore an extra 1μF needs to be added on the PLL AVDD power source (Refer to the reference schematic). And remember to place it as near to the IC outlet as possible.2. For Analog Power to work in a clean environment, add a large bypass capacitor 0.1μF and electrolytic capacitor 10μF in parallel on Input and Output of the 5V->3.3V regulator to ensure the stability. 3. 50ppm precision class is recommended for the X’t al.4. When using internal regulator, suggest enlarging the GND area underneath the IC as big as possible to prevent thermal problem.5. The suggested resistance value of Rreff is 680 ohm ±1%. Caution: a wrong value for the Rreff resister will directly affect signal quality.6. T o prevent EMI problems, for GL850G/GL852G, suggest adding one BEAD on pin34/pin38/pin39 of LQFP48, pin16/pin18 of SSOP28, pin21/pin23 of QFN28. For GL854G, suggest adding one BEAD on pin47/pin53/pin54. Besides, reserve commmon choke on every D+/D- path can aslo help prevent EMI problems. Remember to place the BEAD or common choke as near to the IC outlet as possible.2010 Genesys Logic, Inc. - All rights reserved.Page 13。

All leaflets are available on: Air Preparation - 19651652653* High pressure assisted version.• High flow with a wide range of adjustable output pressure ranges• Optional low profile integrated gauge, round gauge, digital gauge or digitalpressure switch• Optional extended temperature range of -40°C to +80°C • Threaded ports allow for individual or modular mounting • Sintered polyethylene elements include 5 and 25 Microns• Innovative two position plastic drain with manual and semi-automatic functions.Additional drains include an automatic style (brass) and manual (stainless steel)• Polycarbonate and Aluminium bowls with or without glass gauge, to meet industry all application requirements• Key lockable and tamper resistant models • Air Purity Class according to ISO 8573-1: 2010PARTICULATE FILTER/REGULATOR01805G B -2017/R 02-A v a i l a b i l i t y , d e s i g n a n d s p e c i fi c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e . A l l r i g h t s r e s e r v e d.All leaflets are available on: 20 - Air Preparation651652653HOW TO ORDERParticulate Filter/Regulator(1) Conforms to ISO standards 1179-1.(2)M etal Bowl Types K or L only.(3)I f multiple options are required, please use the on-line CAD configurator on the website to generate the part number ().(4)C ompressed air must be dry enough so no ice formation is present on the product. All bowls should be emptied prior to ambient temperatures dropping below 0°C.G 651 A P B P 2 G A00 H NThread connection G = ISO 228/1-G (1)8 = NPTF Product series 651652653Revision letter AProduct type P = Filter/Regulator - Particulate Gauge type B = Digital pressure switch - PNP C = Digital pressure switch - NPN D = Digital gauge G = Low profile integrated gauge bar/PSI J = L ow profile integrated gauge bar/PSI with pressure range indicators Q = Round gauge bar/PSI 0 = No gauge port P = Port Plate Rc 1/8Options (3)A00 = Without option101 = Side Mounting Brackets 102 = Panel Nut (651 or 652) 103 = T amper resistant 104 = K ey lockable105 = High temperature (+80°C) 106 = Low temperature (-40°C) (4) 109 = FPM seals113 = Stainless steel fasteners 114 = P rovision for key lock 117 = A TEX zones 1-21 119 = P anel Bracket with Panel Nut (651 or652)121 = N on-relieving 123 = G auge type mounted for right-to-leftflow124 = CUTR Certification (EAC) 125 = CUTR Ex 202 = 105 + 109 2A9 = 105 + 106Pressure range D = 0,2..3 bar H = 0,5..10 barN = 0,5..16 bar (653 only)(2)ElementsB =5 μm (White) J= 25 μm (Yellow)Bowl type K = M etal bowl without sight gauge L= Metal bowl with sight gauge (glass)P =Polycarbonate bowl with bowl guardPort size1 = 1/8 (651 Series)2 = 1/4 (651 or 652 Series)3 = 3/8 (652 Series)4 =1/2 (652 Series)5= 3/4 (653 Series)6 = 1 (653 Series)Drain type 0 = Without A = Auto drain normally open N = Manual/Semi-automatic drain Q = Manual drain - Stainless steel01805G B -2017/R 02A v a i l a b i l i t y , d e s i g n a n d s p e c i fi c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e . A l l r i g h t s r e s e r v e d .Q P JGDB/CJB123119104103101QNAConfigurator - CAD FilesAll leaflets are available on: Air Preparation - 21651652653Dimensional Drawing - 651/652/653 Series Particulate Filter/RegulatorCross Section -651/652/653 SeriesParticulate Filter/Regulator"J" dimension.01805G B -2017/R 02A v a i l a b i l i t y , d e s i g n a n d s p e c i fi c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e . A l l r i g h t s r e s e r v e d .Configurator - CAD Files653 Series High Pressure(16 bar)All leaflets are available on: 22 - Air Preparation65165265301805G B -2017/R 02A v a i l a b i l i t y , d e s i g n a n d s p e c i fi c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e . A l l r i g h t s r e s e r v e d .Particulate Filter/Regulator Flow Charts。