基于MSP430F149单片机毕业论中英文对照资料外文翻译文献

Step of electric machine universal controller realizes which based on the MSP430F149 Single Chip Microcomputer.Abstract：With the infiltration in the social field of the computer in recent years, the application of the one-chip computer is moving towards deepening constantly, drive tradition is itmeasure crescent benefit to upgrade day to control at the same time. In measuring in real time andautomatically controlled one-chip computer application system, the one-chip computer often usesas a key part, only one-chip computer respect knowledge is not enough, should also follow thestructure of the concrete hardware , and direct against and use the software of target'scharacteristic to combine concretely, in order to do perfectly.This article mainly introduced realizes a step of machine universal controller based on the MSP430F149 monolithic integrated circuit. This controller may simultaneously control the multi-tablecloths machine according to the curve way movement, including adds and subtracts fast, the localization and the commutation function and so on. In the article discussed with emphasis step machine has risen to low the speed and the curve design proposal and its the realization method.1. a preface：based on the step of machine control system, except step machine generally also needs the special actuation power source, actuates the power source merely to complete the power actuation part, the user certainly cannot cause the entire control system according to prearrange, the expectation active status movement, must control to its actuation power source, the user needs to develop once more.In view of this, has designed a step of machine universal controller which realizes based on the MSP430F149 monolithic integrated circuit, may satisfy the majority controllingfield originally request. The controller main function is:(1) May control the multi- wraps step of machine actuation system; At present may simultaneously control 3 sets of systems.(2) work way is flexible, may according to the hypothesis curve movement, the curve most reach 8 sections; May according to the control signal movement which exterior examines; May according to the simulation adjustment test function movement;2. Systems designs2.1 systems structureThis controller has mainly realized thematic- tablecloths machine in the multistage curve operating control.2.2 microprocessors choiceThis design has selected MSP which Incorporation produces series monolithic integrated circuit MSP430F149.The goal is applies its rich connection resources and the formidable timer function, the MSP430F149 performance characteristic as follows:(1) 6 eight bit parallel connections; Definitely may realize this system all signals input, the output, does not need the hardware to expand, P1, the P2 eight bit parallel ports each mouth line all has the severance function, softly causes the keyboard, the hardware design to change is extremely simple.(2) 12 A/D switch ADC; Completes the simulation hypothesis function.(3) Formidable timer function; TIMER-A3, TIMER-B7 respectively be have3 and 7 captures/compares the register 16 timers, may satisfy the system speed the hypothesis and the curve fixed time request.(4)Liquid crystal actuation module;(5) In sets at 2KB RAM, 60KB FLASH;MSP430F149 provides the rich resources, the periphery hardware expands only must do thevery few work, not only designs changes extremely imply, and moreover this controller volume small, the reliability is high.2.3 steps of machine starting and add/decelerate the control planThe step of motive highest starting frequency (step frequency) generally is 0.1KHz arrives 3-4KHz, but the highest movement frequency may achieve N*102 KHz. Surpasses the highest starting frequency the frequency direct-on starting, will appear\" Falls out of step \" Phenomenon, even is unable to start.The more ideal starting curve should be according to the index rule starting. But the practical application to starts the section processing to be possible to use according to the fitting a straight Line method, namely \" Steps and ladders law \”. May according to two kind of situations processing, (1) known frequency press the frequency partition to start, the partition counts n=f/f q.(2) Unknown frequency, then to assigns according to the section. Uses \" Steps and ladders law \" Continuously raises the speed the speed which needs, then locking, according to pre-placed curve movement. Fitting the starting frequency, after each section of frequencies hand over the increase (to call steps and ladders frequency) △f=f/8, namely uses 8 sections of fitting. In the operating control process, (frequency) divides into the outset speed n minute achievement steps and ladders frequency, When 2.4 steps of machine commutation questions step of machine commutation, certainly must stop in the electrical machinery or fall commutates again to the frequency range in, in order to avoid has a bigger impact to damage the electrical machinery. The commutation signal certainly must last the CP pulse finish after the preceding direction as well as in front of the next direction first CP pulse sends out.2.4 steps of machine commutation questionsStep of machine commutation, certainly must stop in the electrical machinery or fall commutates again to the frequency range in, in order to avoid has a bigger impact to damage the electrical machinery. The commutation signal certainly must last the CP pulse finish after the preceding direction as well as in front of the next direction first CP pulse sent out in some highspeed under, the reverse cut essence has contained -> the commutation -> three processes2.5 speeds and the timer starting value transformationThis system speed control is the dependence fixed time produces; the hypothesis speed which the CP pulse completes with has the CP pulse timer starting value to have the certain relations. The MSP430F149 timer work way has many kinds of, this design timer work under continual way. In the continual pattern, the timer starts from its current value to count, after counts to 0FFFFH from \" 0\" Starts redo count. Under this way, compares the timer current value and comparison register CCRX, if equal has the severance, and May the time which has the next event add to in this interrupt service is on comparison register CCRX.Fixed time the starting value = must fixed time the value/count the cycle; Often assigns regarding the step of machine its speed value by the frequency form, such as movement under 20KHZ, therefore the previous type may transform is: Fixed time the starting value = counts the frequency/speed value. (Counts frequency for system clock frequency)3. ConcludingRemark this controller may realize step machine under the multistage hypothesis curve operating control, has the hardware simply, the reliable high characteristic, has used in on the electric wire production line platoon line control section it, has obtained the satisfying effect. This topic funds the project for the north industry big school scientific research foundation.译文译文基于MSP430F149单片机实现的步进电机通用控制器。

中文翻译材料英文题目FSK Modulation and Demodulation With the MSP430 Microcotroller中文题目基于MSP430的FSK调制解调学院：计算机科学与技术学院专业：通信工程学生姓名：指导教师：二O一三年六月IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PR OPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright 1998, Texas Instruments IncorporatedContents1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (1)2 Demodulation Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.1 Choosing the Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2 Front End Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3 FSK Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.4 Bit Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Modulation Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1 Choosing the Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2 Constructing the Look Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3 FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 2 2 3 4 4 4 44 Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5)4.1 A/D Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5)4.2 D/A Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5)5 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (6)6 Exercising the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (7)6.1 FSK Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (7)6.2 FSK Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (7)7 Example Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (8)7.1 Using the MSP430C325 as Main Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (8)7.2 Example Telephone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (8)8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (10)9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (11)FSK Modulation and Demodulation With the MSP430 MicrocontrolleriFSK Modulation and Demodulation With the MSP430MicrocontrollerABSTRACTThis application report describes a software program for performing V.23 FSK modemtransceiver functions using an MSP430 microcontroller. It makes use of novel filterarchitecture to perform DSP functions on a processor with only shift and add capabilities.1 IntroductionMany measurement applications (for example, electric and gas meters) requirea way to communicate electronically with a central office so that measured datacan be reported back to the central office and new tariffs can be set in the remotesite. Telephony provides a convenient means of data communication.Frequency shift keying (FSK) and dual tone multi frequency (DTMF) are twopopular methods of representing binary data over telephone circuits. Thisapplication report describes a V.23-compliant FSK transceiver software module.Integrating the measurement and communication functions onto the same chipyields cost as well as power-saving benefits. Using the MSP430, a high MIPs ultralow power microprocessor, allows power to be drawn from the telephone line insome cases.This report describes the mathematical formulas for FSK signal transmission anddetection. A list of the software modules is included with a reference schematicfor telephone interface and low cost A/D converter. The schematic is only areference, since the precise implementation can vary from country to country.1Demodulation Theory2 Demodulation TheoryA quadrature demodulator provides the FSK demodulation. In this type ofdemodulation, the signal and its delayed version are multiplied together and then low-pass filtered. If the delay, T, is set such that Wcarrier ⋅ T = /2, then thelow-pass filter result is proportional to the frequency deviation from the carrier and therefore represents the bit value sent.If wWcarrierwhere w = 2π ⋅ f : + " Wdelta and T+ Wcarrier +p 2 ³2.1 cos[wt].cos[w(t –T)]coswT coswTsin[" Wdelta] + ) cos(2wt –wT) ³ Low Pass Filter +" sin[Wdelta]_ Choosing the Sampling RateThe sampling is chosen to be Fcarrier4 for the purpose of obtaining thedelayed sample without computational overhead. For V.23, the F carrierfrequency is 1700 Hz and therefore the sampling rate becomes 6800 Hz. Using a 32768-Hz crystal yields 6793.3 Hz, which is 0.1% out. The sampling frequency is set by the 8-bit interval timer. Because this timer is limited to 256 counts, the interrupt rated is set to twice the sampling rate and the processing is divided into two halves with signal sampling performed every other interrupt.2.2 Front End ProcessingMost A/D converters, including the successive approximation A/D converter in the MSP430C325, need a dc bias; this yields an unsigned integer sample with an offset. Before this sample can be processed further, it needs to go through an unbias filter to take out the dc bias and turn the sample into a signed integer value. This unbias filtering also gives 30 dB or so of rejection for main frequencies.2.3 FSK DemodulationThe signed integer sample and its delayed version are multiplied together; in this application, an 8×8 signed multiplication loop is used.The product, made up of two frequency elements, is low-pass filtered to remove the double frequency element. The remainder is a signed integer valuerepresenting the original bit value transmitted.The low-pass filter uses the digital wave filtering technique. This technique gives stable characteristics with very good coefficient tolerance. All multiplication is done through shifts and adds with the number of shift/add operations minimized through rounding off the coefficients. Because the filter has good coefficienttolerance, this rounding off does not affect the filter performance. The Butterworth filter used here gives approximately 40-dB attenuation in the stop band with 1-dB pass and ripple.2SLAA037Demodulation Theory2.4Bit SynchronizationThe bit values coming out from demodulation need to be determined andsynchronized to produce the incoming data bit stream. This process is alsoknown as bit slicing and clock recovery. Because the sampling rate at 6800 is notan integer multiple of the data rate (baud rate) at 1200, an additional step isneeded to consolidate between the two rates. This is done through a count-downcounter with a sequence of preload value (5,6,5). Every 17 samples, the samplingrate and the data baud rate are resynchronized. Bit synchronization or clockrecovery is done by monitoring bit value transitions. Lead or lag information isthen obtained and the count-down counter is adjusted accordingly. Because ofthe difference between the sampling clock and the data clock, the data bit is neversampled at the middle of the baud period; instead a –5% to 13% variation isintroduced. However, this should not have any adverse effect on the accuracy ofthe system, as it has been verified experimentally.3FSK Modulation and Demodulation With the MSP430 MicrocontrollerModulation Theory3 Modulation TheoryFSK modulation involves alternating the value of a delta frequency from a carrierfrequency according to the value of the bit to be represented. For V.23, a bit valueof 0 = 400 Hz and a bit value of 1 = –400 Hz.FSK signal + Amplitudecos[t| 2p(Fcarrier" Fdelta)]The sinusoidal signal is generated through a lookup table which contains cosine values from 0 to 2π. A parameter called PHASER (16 bit) represents the current angle: 0=0 degree, 8000 hex = 180 degree 10000 hex = 360 degree. With each sample, this angle is advanced by another parameter DELTA (16 bit) which determines the frequency of the signal (larger DELTA value = higher frequency). Frequency modulation is realized by changing the DELTA value according to the bit value to be transmitted at each baud period, according to the following formula:DELTA + Fdesired Fsampling65536.The advantage of this method over a digital oscillator method is that this methodpreserves the phase relationship even when the frequency is shifted from sampleto sample.3.1Choosing the Sampling RateThe 8-bit interval timer sets the sampling rate to 19200 samples/s. This rate issubdividable into the data baud rate of 1200. Also, it is sufficiently high to makethe D/A process simpler.3.2Constructing the Look Up TableTo save ROM space, only the first quadrant (0 to 127 degrees) in Q7 format iscoded. This is done by dividing the first quadrant (90 degrees) into 128 steps ofapproximately 0.7 degrees each. The remaining three quadrants can be workedout from this first quadrant table using additional computation.3.3FSK ModulationThe parameter PHASER is advanced by the amount DELTA at every interrupt.The first 9 bits of the PHASER is used to look up the cosine value. For the cosinefunction, the third and fourth quadrant are the same as the second and firstquadrant, and so only the absolute value of the first 9 bits of PHASER is used.Next, all second quadrant values are derived from the first quadrant ROM table.The 8-bit result value is stored onto P0.OUT.Every 16 interrupts, the parameter DELTA is updated with the next frequency bylooking at the next bit to be transmitted.4SLAA037Data Conversion 4 Data ConversionThis section describes the required digital-to-analog (D/A) and analog-to-digital(A/D) data conversions.4.1A/D ConversionThe most straightforward way to digitize the incoming FSK signal is to use the12-bit mode of the internal 14-bit A/D converter of the MSP430C325. However,not all of the 12 bits are needed to achieve good dynamic range for the FSKdemodulation. Simulation results indicate that an 8-bit A/D stage gives gooddynamic range up to 25 dB using internal AGC software. With an additionalexternal AGC stage, the dynamic range can be further widened. As economicalmeans of building 8-bit single slope A/D exists, this extends the application of thismodule to the rest of the MSP430 family. The application software included hereuses a single slope A/D (universal timer with external comparator) for thedemodulator. This makes the software universally applicable for the whole family.4.2D/A ConversionA 6-bit external R–2R ladder is used to construct the D/A converter. Because thecarrier frequency of 19200 Hz is nine times the highest frequency of the FSK of2100 Hz, the post filtering stage should be relatively simple. In the applicationcircuit, a single capacitor forms a single pole low pass filter but more poles canbe realized using additional passive networks.5FSK Modulation and Demodulation With the MSP430 MicrocontrollerPower Consumption5 Power ConsumptionThe FSK concept is designed with low power in mind. The FSK demodulatortakes less than 2 MIPs. With a low power op-amp as a front-end, total powerconsumption of less that 1.5 mA should be achievable. Thus, it is possible thatthe power can be derived entirely from the telephone line. A schematic is includedfor a suggested telephone line interface. The precise configuration may vary fromcountry to country.SLAA0376Exercising the Software 6 Exercising the SoftwareThis section describes operation of the software.6.1FSK ReceiverThe FSK signal is derived from the telecom interface circuit. This signal shouldhave a dc bias of 1.2 V and a peak-to-peak level of 400 mV. The software decodesthis FSK signal and produces three outputs which lets the user monitor thedemodulated data.TP.3. This is the clock signal recovered from the input FSK.TP.5. This is the data recovered from the input FSK; data is latched out everyrising edge of TP.3.P0.2–P0.7. These six bits output the low pass filtered result. With an externalR–2R ladder this becomes very useful in monitoring the analogue FSKdemodulator output level. It is hard limited to 8 bits with the MSB 6 bits loadedto port P06.2FSK TransmitterThe transmitter software outputs an FSK signal according to the BIT MAP datadefined in TX_DATA_TABLE. The bitmap pattern starts with a preamble followedby a long MARK period. Then the actual data is transmitted. This table uses a zeroword as an end marker, and the software restarts the whole data sequence uponreaching a zero value in the bit map data.7FSK Modulation and Demodulation With the MSP430 MicrocontrollerExample Circuits7 Example CircuitsThis section shows and describes example circuits.7.1Using the MSP430C325 as Main ProcessorFigure 1 shows an example circuit using the MSP430C325 as the mainprocessor. The circuit is tested with 400 mV peak-to-peak FSK input. To obtainthe same results, Rx needs to be biased at 1.2 V with a 400 mV peak-to-peak FSKsignal superimposed.VSSR1 R2PO.2PO.3PO.4PO.5PO.6PO.7MSP430E325TP.5TP.1 TP.4 CIN TP.3RX_CLKLine InterfaceRXTXHook 14066AC13VCC1N414833 kΩVoltage RampPNPSample_HoldNPN 1 nF 6_ 5+B 2RX_DATA7Figure 1. Main Processor and A/D Converter7.2Example Telephone InterfaceFigure 2 shows an example telephone interface, and Table 1 lists FSK transceiverperformance data.8SLAA037Example Circuits 20 kΩ1 ∝Φ+ 1 kΩ1 kΩVREF(1.5 V)TLC22796_5+33 kΩ20 kΩ20 kΩ20 kΩ10 kΩ9_10+Telephone LineAB33 nF500 &6–8 V ZenersTuning ForMinimum Side Tone6–8 V ZenersTX7DC TelephoneIsolationTransformer8150 kΩ400 mV pk–pkRX 1 ∝Φ+–+131233 kΩ33 kΩ680Hook150 kΩ14This is a reference circuit only and may not be applicable under some circumstances.Figure 2. Telephone InterfaceTable 1. FSK Transceiver PerformanceRAM (BYTES)FSK Receiver FSK Transmitter1812ROM (BYTES)512400MIPS (APPROX.)21.4FSK Modulation and Demodulation With the MSP430 Microcontroller9Summary8 SummaryFSK transceivers are normally realized by either analog means or by the use ofDSPs with hardware MAC units. Using an MSP430 RISC processor without ahardware MAC to achieve the transceiver function is a very unusual approach.The ability to create filters using digital wave filtering techniques, together with theorthogonal instruction set and the 16 bit architecture of the MSP430, makes thecode very ROM and MIPs efficient. Moreover, the ultra low power capability of theMSP430 means that power can readily be derived from the phone line. This leadsto component-efficient designs. The author has conducted other tests toconclude that, with some enhancements, the FSK receiver can work with an 8-bitA/D converter with enough sensitivity. Therefore the FSK transceiver can beimplemented economically across the whole MSP430 family.SLAA03710References9 References1. Texas Instruments: MSP430 Family, Architecture User’s Guide and ModuleLibrary.2. Texas Instruments Digital Signal Processing Application with the TMS320Family Volume 2.3. Gaszi, L: Explicit Formulas for Lattice Wave Digital Filters; IEEE Trans. OnCircuits and Systems VOL. CAS-32, NO. 1, January 198511FSK Modulation and Demodulation With the MSP430 Microcontroller基于MSP430的FSK调制解调——应用报告声明德州仪器（TI）及其附属公司（TI）保留改进产品或停止任何服务的权力，并且不再另行通知，建议客户获核实最新版本或相关信息，在下订单前，该信息是当前最有效和完整的。

单片机英文文献Principle of MCUSingle-chip is an integrated on a single chip a complete computer system. Even though most of his features in a small chip, but it has a need to complete the majority of computer components: CPU, memory, internal and external bus system, most will have the Core. At the same time, such as integrated communication interfaces, timers, real-time clock and other peripheral equipment. And now the most powerful single-chip microcomputer system can even voice, image, networking, input and output complex system integration on a single chip.Also known as single-chip MCU (Microcontroller), because it was first used in the field of industrial control. Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large number of peripherals and CPU in a single chip, the computer system so that smaller, more easily integrated into the complex and demanding on the volume control devices. INTEL the Z80 is one of the first design in accordance with the idea of the processor, From then on, the MCU and the development of a dedicated processor parted ways.Early single-chip 8-bit or all of the four. One of the most successful is INTEL's 8031, because the performance of a simple and reliable access to a lot of good praise. Since then in 8031 to develop a single-chip microcomputer system MCS51 series. Based on single-chip microcomputer system of the system is still widely used until now. As the field of industrial control requirements increase in the beginning of a 16-bit single-chip, but not ideal because the price has not been very widely used. After the 90's with the big consumer electronics product development, single-chip technology is a huge improvement. INTEL i960 Series with subsequent ARM in particular, a broad range of applications, quickly replaced by 32-bit single-chip 16-bit single-chip high-end status, and enter the mainstream market. Traditional 8-bit single-chip performance has been the rapid increase in processing power compared to the 80's to raise a few hundred times. At present, the high-end 32-bit single-chip frequency over 300MHz, the performance of the mid-90's close on the heels of a special processor, while the ordinary price of the model dropped to one U.S. dollars, the most high-end models, only 10 U.S. dollars. Contemporary single-chip microcomputer system is no longer only the bare-metal environment in the development and use of a large number of dedicated embedded operating system is widely used in the full range of single-chip microcomputer. In PDAs and cell phones as the core processing of high-end single-chip or even a dedicated direct access to Windows and Linux operating systems.More than a dedicated single-chip processor suitable for embedded systems, so it was up to the application. In fact the number of single-chip is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will have a single-chip integration. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse in the Department are equipped with 1-2 single chip. And personal computers also have a large number of single-chip microcomputer in the workplace. Vehicles equipped with more than 40 Department of the general single-chip, complex industrial control systems and even single-chip may have hundreds of work at the same time! SCM is not only far exceeds the number of PC and other integrated computing, even more than the numberof human beings.Hardwave introductionThe 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a company's entire line of products since it can perform many functions and developers will only have to learn this one platform.The basic architecture consists of the following features:·an eight bit ALU·32 descrete I/O pins (4 groups of 8) which can be individually accessed·two 16 bit timer/counters·full duplex UART· 6 interrupt sources with 2 priority levels·128 bytes of on board RAM·separate 64K byte address spaces for DA TA and CODE memoryOne 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).单片机原理单片机是指一个集成在一块芯片上的完整计算机系统。

外文翻译：The monolithic In order to prevent without authorization the visit or the copy monolithic integrated circuit machine in the procedure, the majority of monolithic integrated circuits all has the encryption to lock the localization or the encryption byte, by protects the internal procedure. If in programming time encrypts locks the localization to enable (locking), is unable with the ordinary programming directly reading in the monolithic integrated circuit the procedure, this is the so-called copy protection or says the fixed function. In fact, such protective measures are very frail, is very easily explained. The monolithic integrated circuit aggressor with the aid of the special purpose equipment or the self-made equipment, using the monolithic integrated circuit chip design in loophole or the software flaw, through the many kinds of technical method, may withdraw the essential information from the chip, gains in the monolithic integrated circuit the procedure. Therefore, has the newest technology extremely as electronic products project engineer which the essential understanding current monolithic integrated circuit attacks, achieves knows oneself and the other side, knows fairly well, can effectively prevent oneself spends the product which the massive moneys and the time laboriously designs the matter occurrence which is counterfeited by a others night between.monolithic integrated circuits attacks technology：At present, attacks the monolithic integrated circuit mainly to have four kind of technologies, respectively is:This technical usual use processor correspondence connection and in the use agreement, the encryption algorithm or these algorithm security loophole carries on the attack. The software attack obtains the success a case in point is to early A T M E L A the T 89 C series monolithic integrated circuit attack. The aggressor has used in this series monolithic integrated circuit cleaning operation succession design loophole, uses from arranges the procedure to lock the localization after the cleaning encryption, stops the next step of cleaning internal program memory data the operation, thus makes to add the dense monolithic integrated circuit not to turn the encryption monolithic integrated circuit, then use programming read-out internal procedure.This technology usually monitors the processor by the high time resolution when the normal operation all power sources and the connection connection simulation characteristic, and through monitors its electromagnetic radiation characteristic to implement the attack. Because the monolithic integrated circuit is an active electronic device, when it carries out the different instruction, the corresponding mains input consumption also correspondingly changes. Like this analyzes and examines these changes through the use special electronic surveying instrument and mathematics statistical method, then gains in the monolithic integrated circuit the specific essential information.the mistake has the technology This technical use exceptionally working condition causes the processor to make a mistake, then provides the extra visit to carry on the attack. Uses the most widespread mistake to have the attack method including the voltage impact and the clock impact. The low voltage and the high voltage attack may usefor to forbid the protection circuit work or to fortected the information. The power source and the clock transient state jump may affect the single scroll instruction in certain processors the decoding and the ece the processor to carry out the misoperation. Perhaps the clock transient state jump can reposition the protection circuit but not to be able to destroy is proxecution.This technology is the direct exposed chip interior segment, then the observation, holds controls, disturbs the monolithic integrated circuit by to achieve the attack goal.In order to facilitate in order to, the people divide into above four kind of attacks technology two kinds, a kind is the invasion attack (physical attack), this kind of attack needs to destroy the seal, then with the aid of the semiconductor test facility, the microscope and the micro locator, several hours even several week time can complete on the special laboratory flower. All micro probes technology all belongs to the invasion attack. Moreover three methods belong to the non- invasion attack, the monolithic integrated circuit which attacks cannot by the physical damage. In certain situation non- invasion attacks is specially dangerous, this is because the non- invasion attack needs the equipment usually to be possible the self-restraint and the promotion, therefore is extremely inexpensive.The majority of non- invasions attack needs the aggressor to have the good processor knowledge and the software knowledge. Is opposite with it, the invasion probe attack then does not need too many initial knowledge,moreover usually may use the one whole set similar technology to cope with the width scope the product. Therefore, the attack often starts to the monolithic integrated circuit from the invasion reverse engineering, the accumulation experience is helpful to the development more inexpensive and the fast non- invasion attack technology.Last step will be seeks the protection melt silk the position and protects the melt silk to expose under the ultraviolet ray. With enlargement factor at least 100 time of microscopes, inputs the foot from the programming voltage the segment to track generally, seeks the protection melt silk.This technical use exceptionally working condition causes the processor to make a mistake, then provides the extra visit to carry on the attack. Uses the most widespread mistake to have the attack method including the voltage impact and the clock impact. The low voltage and the high voltage attack may use for to forbid the protection circuit work or to force the processor to carry out the misoperation. Perhaps the clock transient state jump can reposition the protection circuit but not to be able to destroy is protected the information. The power source and the clock transient state jump may affect the single scroll instruction in certain processors the decoding and the execution.(4) probe technologyThis technology is the direct exposed chip interior segment, then the observation, holds controls, disturbs the monolithic integrated circuit by to achieve the attack goal.In order to facilitate in order to, the people divide into above four kindof attacks technology two kinds, a kind is the invasion attack (physical attack), this kind of attack needs to destroy the seal, then with the aid of the semiconductor test facility, the microscope and the micro locator, several hours even several week time can complete on the special laboratory flower. All micro probes technology all belongs to the invasion attack. Moreover three methods belong to the non- invasion attack, the monolithic integrated circuit which attacks cannot by the physical damage. In certain situation non- invasion attacks is specially dangerous, this is because the non- invasion attack needs the equipment usually to be possible the self-restraint and the promotion, therefore is extremely inexpensive.The majority of non- invasions attack needs the aggressor to have the good processor knowledge and the software knowledge. Is opposite with it, the invasion probe attack then does not need too many initial knowledge,moreover usually may use the one whole set similar technology to cope with the width scope the product. Therefore, the attack often starts to the monolithic integrated circuit from the invasion reverse engineering, the accumulation experience is helpful to the development more inexpensive and the fast non- invasion attack technology.3 invasions attacks general process：The invasion attack first step uncovers the chip seal. Some two methods may achieve this goal: The first kind is dissolves the chip seal completely, the exposed metal segment. The second kind is only moves above the silicon nucleus plastic seal. The first method needs the chip to tests on the jig, with the aid of Taiwan to operate. The second method except needs to have the aggressor certain knowledge and Wants outside skill, but also needs individual wisdom and the patience, but operates relatively quite is convenient.Above the chip plastic may use the knife to open, around the chip epoxy resin may use the aqua fortis perish. The hot aqua fortis can dissolve the chip seal but not to be able to affect the chip and the segment. This process carries on generally under the extremely dry condition, because the water existence possibly can corrode already the aluminum wire connection which exposes.Then first uses the acetone in the supersonic pond to clean this chip by except the remaining nitric acid, then cleans with the clear water by and is dry except the salinity. Not the supersonic pond, jumps over generally this step. In this kind of situation, the chip surface can a little dirty, but not too affects the ultraviolet ray to the chip operation effect.Last step will be seeks the protection melt silk the position and protects the melt silk to expose under the ultraviolet ray. With enlargement factor at least 100 time of microscopes, inputs the foot from the programming voltage the segment to track generally, seeks the protection melt silk.If does not have the microscope, then uses the chip different partially exposes to the ultraviolet ray under and the observed result way carries on the simple search. When operation applies not the opaque slip of paper cover chipby to protect the program memory not by the ultraviolet ray cleaning. Will protect the melt silk to expose in the ultraviolet ray next 5 ~ 10 minutes can broken the protection position protective function, afterwards, will use the simple programming to be possible the direct readout program memory content.Regarding used the protective layer to protect E E P R O the M unit the monolithic integrated circuit to say that, the use ultraviolet ray repositioned the protection circuit is not feasible. Regarding this kind of type monolithic integrated circuit, uses the micro probe technology reading the memory content generally. Opens after the chip seal, puts in the chip under the microscope to be able very easy finding中文翻译单片机为了防止未经授权访问或拷贝单片机的机内程序，大部分单片机都带有加密锁定位或者加密字节，以保护片内程序。

本科毕业设计外文文献及译文文献、资料题目：MPS430 Mixed Signal Microcontroller 文献、资料来源：期刊（著作、网络等）文献、资料发表（出版）日期：2005.3.25学院：信息与电气工程学院专业：通信工程班级：通信姓名：学号：2006081060指导教师：翻译日期：2010.4.8外文文献：MSP430 MIXED SIGNAL MICROCONTROLLER _ Low Supply-Voltage Range, 1.8 V . . . 3.6 V_ Ultralow-Power Consumption:− Active Mode: 330μA at 1 MHz, 2.2 V− Standby Mode: 1.1μA− Off Mode (RAM Retention): 0.1μA_ Five Power-Saving Modes_ Wake-Up From Standby Mode in less than 6μs_ 16-Bit RISC Architecture, 125-ns Instruction Cycle Time_ Three-Channel Internal DMA_ 12-Bit A/D Converter With InternalReference, Sample-and-Hold and Autoscan Feature_ Dual 12-Bit D/A Converters With Synchronization_ 16-Bit Timer_A With Three Capture/Compare Registers_ 16-Bit Timer_B With Three or Seven Capture/Compare-With-Shadow Registers _ On-Chip Comparator_ Serial Communication Interface (USART0), Functions as Asynchronous UART or Synchronous SPI or I2CTM Interface_ Serial Communication Interface (USART1), Functions as Asynchronous UART or Synchronous SPI Interface_ Supply Voltage Supervisor/Monitor With Programmable Level Detection_ Brownout Detector_ Bootstrap Loader_ Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by SecurityFuse_ Family Members Include:− MSP430F155:16KB+256B Flash Memory512B RAM− MSP430F156:24KB+256B Flash Memory1KB RAM− MSP430F157:32KB+256B Flash Memory,1KB RAM− MSP430F167:32KB+256B Flash Memory,1KB RAM− MSP430F168:48KB+256B Flash Memory,2KB RAM− MSP430F169:60KB+256B Flash Memory,2KB RAM− MSP430F1610:32KB+256B Flash Memory5KB RAM− MSP430F1611:48KB+256B Flash Memory10KB RAM− MSP430F1612:55KB+256B Flash Memory5KB RAM_ Available in 64-Pin Quad Flat Pack (QFP) and 64-pin QFN (see Available Options) _ For Complete Module Descriptions, See the MSP430x1xx Family User’s Guide, Literature Number SLAU049descriptionThe Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6μs.The MSP430x15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bitA/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), I2C, DMA, and 48 I/O pins. In addition, the MSP430x161x series offersextended RAM addressing for memory-intensive applications and large C-stack requirements. Typical applications include sensor systems, industrial control applications, hand-held meters, etc.MSP430F169 MIXED SIGNAL MICROCONTROLLERshort-form descriptionCPUThe MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.instruction setThe instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.operating modesThe MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.The following six operating modes can be configured by software:_ Active mode AM;− All clocks are active_ Low-power mode 0 (LPM0);− CPU is disabledACLK and SMCLK remain active. MCLK is disabled_ Low-power mode 1 (LPM1);− CPU is disabledACLK and SMCLK remain active. MCLK is disabledDCO’s dc-generator is disabled if DCO not used in active mode_ Low-power mode 2 (LPM2);− CPU is disabledMCLK and SMCLK are disabledDCO’s dc-generator remains enabledACLK remains active_ Low-power mode 3 (LPM3);− CPU is disabledMCLK and SMCLK are disabledDCO’s dc-generator is disabledACLK remains active_ Low-power mode 4 (LPM4);− CPU is disabledACLK is disabledMCLK and SMCLK are disabledDCO’s dc-generator is disabledCrystal oscillator is stoppedinterrupt vector addressesThe interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence special function registersMost interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.interrupt enable 1 and 2WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected.Active if watchdog timer is configured as general-purpose timer.OFIE: Oscillator-fault-interrupt enableNMIIE: Nonmaskable-interrupt enableACCVIE: Flash memory access violation interrupt enableURXIE0: USART0: UART and SPI receive-interrupt enableUTXIE0: USART0: UART and SPI transmit-interrupt enableURXIE1 : USART1: UART and SPI receive-interrupt enableUTXIE1 : USART1: UART and SPI transmit-interrupt enableURXIE1 and UTXIE1 are not present in MSP430x15x devices.interrupt flag register 1 and 2WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation Reset on VCC power-on, or a reset condition at the RST/NMI pin in reset mode OFIFG: Flag set on oscillator faultNMIIFG: Set via RST/NMI pinURXIFG0: USART0: UART and SPI receive flagUTXIFG0: USART0: UART and SPI transmit flagURXIFG1 : USART1: UART and SPI receive flagUTXIFG1 : USART1: UART and SPI transmit flagmodule enable registers 1 and 2URXE0: USART0: UART mode receive enableUTXE0: USART0: UART mode transmit enableUSPIE0: USART0: SPI mode transmit and receive enableURXE1 : USART1: UART mode receive enableUTXE1 : USART1: UART mode transmit enableUSPIE1 : USART1: SPI mode transmit and receive enableURXE1, UTXE1, and USPIE1 are not present in MSP430x15x devices.flash memoryThe flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:_ Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size._ Segments 0 to n may be erased in one step, or each segment may be individually erased._ Segments A and B can be erased individually, or as a group with segments 0−n. Segments A and B are also called information memory._ New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use.peripheralsPeripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family Use r’s Guide, literature number SLAU049.DMA controllerThe DMA controller allows movement of data from one memory address to another without CPU intervention.For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.oscillator and system clockThe clock system in the MSP430x15x and MSP430x16x(x) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The basic clock module provides the following clock signals:_ Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. _ Main clock (MCLK), the system clock used by the CPU._ Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. brownout, supply voltage supervisorThe brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).digital I/OThere are six 8-bit I/O ports implemented—ports P1 through P6:_ All individual I/O bits are independently programmable._ Any combination of input, output, and interrupt conditions is possible._ Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2._ Read/write access to port-control registers is supported by all instructions.watchdog timerThe primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.hardware multiplier (MSP430x16x/161x Only)The multiplication operation is supported by a dedicated peripheral module. The module performs 16_16, 16_8, 8_16, and 8_8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.peripheralsPeripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049.DMA controllerThe DMA controller allows movement of data from one memory address to another without CPU intervention.For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.oscillator and system clockThe clock system in the MSP430x15x and MSP430x16x(x) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than6μs. The basic clock module provides the following clock signals:_ Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. _ Main clock (MCLK), the system clock used by the CPU._ Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. brownout, supply voltage supervisorThe brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision(the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).digital I/OThere are six 8-bit I/O ports implemented—ports P1 through P6:_ All individual I/O bits are independently programmable._ Any combination of input, output, and interrupt conditions is possible._ Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2._ Read/write access to port-control registers is supported by all instructions.watchdog timerThe primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.hardware multiplier (MSP430x16x/161x Only)The multiplication operation is supported by a dedicated peripheral module. The module performs 16_16, 16_8, 8_16, and 8_8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles arerequired.USART0The MSP430x15x and the MSP430x16x(x) have one hardware universalsynchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered transmit and receive channels.The I2C support is compliant with the Philips I2C specification version 2.1 and supports standardmode (up to 100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported, as well as master and slave modes. The USART0 also supports 16-bit-wide I2C data transfers and has two dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I2C mode.USART1 (MSP430x16x/161x Only)The MSP430x16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit (USART1) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. With the exception of I2C support, operation of USART1 is identical to USART0.timer_A3Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.timer_B3 (MSP430x15x Only)Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.timer_B7 (MSP430x16x/161x Only)Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.comparator_AThe primary function of the comparator_A module is to support precision slopeanalog−to−digital conversions, battery−voltage supervision, and monitoring of external analog signals.ADC12The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 wordconversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.DAC12The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.中文译文：MSP430混合信号微控制器●低供电电压范围：1.8V…3.6V●超低功耗：－活动模式：1MHz，2.2V 时为280μA－等待模式：1.6μA－关闭模式（RAM 保持）：0.1μA●五种省电模式●6μS 内从等待状态唤醒●16 位精简指令结构，125 纳秒指令时间周期●三个内部DMA 通道●具有内部参考电平、采样保持和自动扫描特性的12 位A/D 转换器●同步的双12 位D/A 转换器●带有三个捕捉/比较寄存器的16 位定时器A●带有三个或七个捕捉/比较影子寄存器的16 位定时器B●片内集成比较器●串行通讯接口（USART1），具有异步UART 或者同步SPI 接口的功能●串行通讯接口（USART0），具有异步UART 或者同步SPI 或者I2C 接口●具有可编程电平检测的供电电压管理器/监视器●欠电压检测器●串行在线编程，无需外部编程电压，可编程的安全熔丝代码保护●Bootstrap Loader●器件系列包括：－MSP430F155:16KB+256B flash 存储器512B RAM－MSP430F156:24KB+256B flash 存储器1KB RAM－MSP430F157:32KB+256B flash 存储器1KB RAM－MSP430F167:32KB+256B flash 存储器1KB RAM－MSP430F168:48KB+256B flash 存储器2KB RAM－MSP430F169:60KB+256B flash 存储器2KB RAM－MSP430F1610:32KB+256B flash 存储器5KB RAM－MSP430F161148KB+256B flash 存储器；10KB RAM●64 引脚Quad Flat Pack（QFP）封装●要获得完整的模块描述参见MSP430x1xx 系列用户手册，文献号SLAU049说明德州仪器公司的MSP430 系列超低功耗微控制器，由针对各种不同应用目标具有不同外围设备的芯片系列组成。

基于MSP430单片机的液位测量仪设计摘要：本文介绍了基于MSP430系列单片机的液位测量仪的组成、原理、硬件及软件设计，并介绍了多路复用测量和控制仪器对页面测量和控制。

该系统由压力传感器、信号处理电路、电磁阀、输出驱动电路、汉字液晶显示器、键盘、光报警电路和MSP430MCU 组成，实现了液位自动监测和自动报警功能。

关键词：液位测量；主从通信；MSP430SCM ；V/F 转换器中国图书分类：TP273 文献标示码：B1． 前言测量和控制仪表的液位表属于智能仪表，是20世纪70年代开发成功的。

这是一个智能的可综合测量和可控制相结合的产品，可在许多工业领域用于测量各种介质的液位。

例如：石化、冶金、电工、电力、制药、环保产业。

该仪器可以测量液位，并计算出它的重量，所以它可以用来测量、控制液体静态、动态地品种，还有全球报警功能。

2． 系统设计2．1 液位传感器的选择有各种各样的传感器可以用于液位测量，例如：压力传感器、超声波传感器、浮动式传感器等。

系统设计不仅需要实现测量液位的功能，还要探测出液体的重量。

在实验中，检测液体的重量P 是直接通过计算获得，这是ρ⨯⨯=S H P (H 为液体公分，S 是圆的面积， ρ是液体密度)。

因此，用1厘米的液体测量构造系统来进步测量液位重量的测量精度。

此外，我们认为，压力传感器接口电路比超声波传感器容易，所以我们决定采用压力传感器。

2．2 MSP430系列单片机低功耗16位的MSP430单片机，具有典型特征的SOC ，是大量的外围集成设备。

特别是微调波特率内部集成器件，它可以使任何单片机晶体振荡器工作在32768Hz 以上(但不超出晶体振荡器上限)，其通信频率的选择没有小数限制，也就是说，它可以使用答应频带率范围内的晶体振荡器工作在任何的频率值。

此外，MSP430单片机内部集成有温度传感器，因此它可以很方便的实现对压力传感器测量液位的温度补偿。

此外，MSP430系列单片机针对不同的模块有不同的应用和微控制器，还设计了电池供电，它可以工作很长时间。

微机发展简史IEEE的论文剑桥大学，2004/2/5莫里斯威尔克斯计算机实验室剑桥大学第一台存储程序的计算开始出现于1950前后，它就是1949年夏天在剑桥大学，我们创造的延迟存储自动电子计算机（EDSAC）。

最初实验用的计算机是由象我一样有着广博知识的人构造的。

我们在电子工程方面都有着丰富的经验，并且我们深信这些经验对我们大有裨益。

后来，被证明是正确的，尽管我们也要学习很多新东西。

最重要的是瞬态一定要小心应付，虽然它只会在电视机的荧幕上一起一个无害的闪光，但是在计算机上这将导致一系列的错误。

在电路的设计过程中，我们经常陷入两难的境地。

举例来说，我可以使用真空二级管做为门电路，就象在EDSAC中一样，或者在两个栅格之间用带控制信号的五级管，这被广泛用于其他系统设计，这类的选择一直在持续着直到逻辑门电路开始应用。

在计算机领域工作的人都应该记得TTL，ECL和CMOS，到目前为止，CMOS已经占据了主导地位。

在最初的几年，IEE（电子工程师协会）仍然由动力工程占据主导地位。

为了让IEE 认识到无线工程和快速发展的电子工程并行发展是它自己的一项权利，我们不得不面对一些障碍。

由于动力工程师们做事的方式与我们不同，我们也遇到了许多困难。

让人有些愤怒的是，所有的IEE出版的论文都被期望以冗长的早期研究的陈述开头，无非是些在早期阶段由于没有太多经验而遇到的困难之类的陈述。

60年代的巩固阶段60年代初，个人英雄时代结束了，计算机真正引起了重视。

世界上的计算机数量已经增加了许多，并且性能比以前更加可靠。

这些我认为归因与高级语言的起步和第一个操作系统的诞生。

分时系统开始起步，并且计算机图形学随之而来。

综上所述，晶体管开始代替正空管。

这个变化对当时的工程师们是个不可回避的挑战。

他们必须忘记他们熟悉的电路重新开始。

只能说他们鼓起勇气接受了挑战，尽管这个转变并不会一帆风顺。

小规模集成电路和小型机很快，在一个硅片上可以放不止一个晶体管，由此集成电路诞生了。

中英文对照外文翻译文献Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers .An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chipcomputers, such as 8031 , 8032, 80C ,etc.. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only needouter quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) Inthe slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharingThe circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouths, its output grade draws the resistance supremly. When using it as the mouth in common use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the resistance on taking to be outer with it while inputting togo out to fail. When being used as introduction, should write "1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate , can draw the pin to the high level fast ; When resistance value is very large, P1 mouth, in order to hinder the introduction state high. Output as P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw the resistance on needn't answer and thenning. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end. Relatively about 20,000 ohms because of the load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1. P3 mouth one multi-functional port, mouth getting many than P1 it have "and " 3 door and 4 buffer". Two part these, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and " door 3 function one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W =At 1 o'clock, output Q end signal; Act as Q =At 1 o'clock, can output W line signal . At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance . It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location (the location or the byte ) to visit to P3 mouth /at not lasting lining, there are inside hardware latch Qs =1.The operation principle of P3 mouth is similar to P1 mouth.Output grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially , make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal:Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having onemore , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.MCS -51系列单片机的功能和结构MCS - 51系列单片机具有一个单芯片电脑的结构和功能，它是英特尔公司生产的系列产品的名称。

英文原文DescriptionThe at89s52 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel at89s52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe at89s52 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the at89s52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description:VCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs theduring accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the at89s52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through adivide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access tointernal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Status of External Pins During Idle and Power Down Modesmode Program memory ALE ^psen Port0 Port1Port2Port3idle internal 1 1 data data data Data Idle External 1 1 float Data data Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 float data Data data Power Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash：The at89s52 is normally shipped with the on-chip Flash memory array in theRDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: T he entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except thatP3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.中文翻译描述at89s52是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大at89s52单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。

单片机外文翻译外文文献英文文献基于单片机的超声波测距系统的研究与设计附录附录A外文翻译the equivalent dc value. In the analysis of electronic circuits to be considered in a later course, both dc and ac sources of voltage will be applied to the same network. It will then be necessary to know or determine the dc (or average value) and ac components of the voltage or current in various parts of the system.EXAMPLE 13.13 Determine the average value of the waveforms of Fig. 13.37.FIG. 13.37Example 13.13.Solutions:a. By inspection, the area above the axis equals the area below over one cycle, resulting in an average value of zero volts.b. Using Eq.(13.26):as shown in Fig. 13.38.26In reality, the waveform of Fig. 13.37(b) is simply the square wave of Fig. 13.37(a) with a dc shift of 4 V; that is v2 =v1 + 4 VEXAMPLE 13.14 Find the average values of the following waveforms over one full cycle:a. Fig. 13.39.b. Fig. 13.40.27Solutions:We found the areas under the curves in the preceding example by using a simple geometric formula. If we should encounter a sine wave or any other unusual shape, however, we must find the area by some other means. We can obtain a good approximation of the area by attempting to reproduce the original wave shape using a number of small rectangles or other familiar shapes, the area of which we already know through simple geometric formulas. For example,the area of the positive (or negative) pulse of a sine wave is 2Am. Approximating this waveform by two triangles (Fig. 13.43), weobtain(using area1/2 base height for the area of a triangle) a rough idea of the actual area:A closer approximation might be a rectangle with two similar triangles(Fig. 13.44):28which is certainly close to the actual area. If an infinite number of forms were used, an exact answer of 2Am could be obtained. For irregular waveforms, this method can be especially useful if data such as the average value are desired. The procedure of calculus that gives the exact solution 2Am is known as integration. Integration is presented here only to make the method recognizable to the reader; it is not necessary to be proficient in its use to continue with this text. It is a useful mathematical tool, however,and should be learned. Finding the area under the positive pulse of a sine wave using integration, we havewhere ? is the sign of integration, 0 and p are the limits of integration, Am sin a is thefunction to be integrated, and da indicates that we are integrating with respect to a.Integrating, we obtainSince we know the area under the positive (or negative) pulse, we can easily determine the average value of the positive (or negative) region of a sine wave pulse by applying Eq. (13.26):For the waveform of Fig. 13.45,29EXAMPLE 13.15 Determine the average value of the sinusoidal waveform of Fig. 13.46.Solution: By inspection it is fairly obvious thatthe average value of a pure sinusoidal waveform over one full cycle is zero.EXAMPLE 13.16 Determine the average value of the waveform of Fig. 13.47.Solution: The peak-to-peak value of the sinusoidal function is16 mV +2 mV =18 mV. The peak amplitude of the sinusoidal waveform is, therefore, 18 mV/2 =9 mV. Counting down 9 mV from 2 mV(or 9 mV up from -16 mV) results in an average or dc level of -7 mV,as noted by the dashed line of Fig. 13.47.EXAMPLE 13.17 Determine the average value of the waveform of Fig. 13.48.Solution:30EXAMPLE 13.18 For the waveform of Fig. 13.49, determine whether the averagevalue is positive or negative, and determine its approximate value.Solution: From the appearance of the waveform, the average value is positive and in the vicinity of 2 mV. Occasionally, judgments of this type will have to be made. InstrumentationThe dc level or average value of any waveform can be found using a digital multimeter (DMM) or an oscilloscope. For purely dccircuits,simply set the DMM on dc, and readthe voltage or current levels.Oscilloscopes are limited to voltage levels using the sequence of steps listed below:1. First choose GND from the DC-GND-AC option list associated with each vertical channel. The GND option blocks any signal to which the oscilloscope probe may be connected from entering the oscilloscope and responds with just a horizontal line. Set the resulting line in the middle of the vertical axis on the horizontal axis, as shown in Fig. 13.50(a).2. Apply the oscilloscope probe to the voltage to be measured (ifnot already connected), and switch to the DC option. If a dc voltage is present, the horizontal line will shift up or down, as demonstrated in Fig. 13.50(b). Multiplying the shift by the vertical sensitivity will result in the dc voltage. An upward shift is a positive voltage (higher31potential at the red or positive lead of the oscilloscope), while a downward shift is a negative voltage (lower potential at the red or positive lead of the oscilloscope). In general,1. Using the GND option, reset the horizontal line to the middle of the screen.2. Switch to AC (all dc components of the signal to whichthe probe is connected will be blocked from entering the oscilloscope—only the alternating, or changing,components will be displayed).Note the location of some definitive point on the waveform, such as the bottom of the half-wave rectified waveform of Fig. 13.51(a); that is, note its position on the vertical scale. For the future, whenever youuse the AC option, keep in mind that the computer will distribute the waveform above and below the horizontal axis such that the average value is zero; that is, the area above the axis will equal the area below. 3. Then switch to DC (to permit both the dc and the ac components of the waveform to enter the oscilloscope), and note the shift in the chosen level of part 2, as shown in Fig. 13.51(b). Equation(13.29) can then be used to determine the dc or average value of the waveform. For the waveform of Fig. 13.51(b), the average value is aboutThe procedure outlined above can be applied to any alternating waveform such as the one in Fig. 13.49. In some cases the average valuemay require moving the starting position of the waveform under the AC option to a different region of the screen or choosing a higher voltage scale. DMMs can read the average or dc level of any waveform by simply choosing the appropriate scale.3213.7 EFFECTIVE (rms) VALUESThis section will begin to relate dc and ac quantities with respect to the power delivered to a load. It will help us determine the amplitude of a sinusoidal ac current required to deliver the same power as a particular dc current. The question frequently arises, How is it possible for a sinusoidal ac quantity to deliver a net power if, over a full cycle, the net current in any one direction is zero (average value 0)? It would almost appear that the power delivered during the positive portion of the sinusoidal waveform is withdrawn during the negative portion, and since the two are equal in magnitude, the net power delivered is zero. However, understand that irrespective of direction, currentof any magnitude through a resistor will deliver power to that resistor. In other words,during the positive or negative portions of a sinusoidal ac current, power is being delivered at eachinstant of time to the resistor. The power delivered at each instant will, of course, vary with the magnitude of the sinusoidal ac current, but there will be a net flow during either the positive or the negativepulses with a net flow over the full cycle. The net power flow will equal twice that delivered by either the positive or the negative regions of sinusoidal quantity. A fixed relationship between ac and dc voltages and currents can be derived from the experimental setup shown in Fig. 13.52. A resistor in a water bath is connected by switches to a dc and an ac supply. If switch 1 is closed, a dc current I, determined by the resistance R and battery voltage E, will be established through theresistor R. The temperature reached by the water is determined by the dc power dissipated in the form of heat by the resistor.If switch 2 is closed and switch 1 left open, the ac current through the resistor will have a peak value of Im. The temperature reached by the water is now determined by the ac power dissipated in the form of heat by the resistor. The ac input is varied until the temperature is the same as that reached with the dc input. When this is accomplished, the average electrical power delivered to the resistor R by the ac source is the same asthat delivered by the dc source. The power delivered by the ac supply at any instant of time is33The average power delivered by the ac source is just the first term, since the average value of a cosine wave is zero even though the wave may have twice the frequency of the original input current waveform. Equating the average power delivered by the ac generator to that delivered by the dc source,which, in words, states thatthe equivalent dc value of a sinusoidal current or voltage is 1/2 or 0.707 of itsmaximum value.The equivalent dc value is called the effective value of the sinusoidal quantity.In summary,As a simple numerical example, it would require an ac current with a peak value of 2 (10) 14.14 A to deliver the same power to the resistorin Fig. 13.52 as a dc current of 10 A. The effective value of any quantity plotted as a function of time can be found by using the following equation derived from the experiment just described:34which, in words, states that to find the effective value, the function i(t) must first besquared. After i(t) is squared, the area under the curve isfound by integration. It is then divided by T, the length of the cycle or the period of the waveform, to obtain the average or mean value of thesquared waveform. The final step is to take the square root of the meanvalue. This procedure gives us another designation forthe effectivevalue, the root-mean-square (rms) value. In fact, since therms term isthe most commonly used in the educational and industrial communities,it will used throughout this text. EXAMPLE 13.19 Find therms values of the sinusoidal waveform in each part of Fig. 13.53.Solution: For part (a), Irms 0.707(12 10 3 A) 8.484 mA.For part (b), againIrms 8.484 mA. Note that frequency did notchange the effective valuein (b) above compared to (a). For part (c),Vrms 0.707(169.73 V) 120 V, the same as available from a home outlet.EXAMPLE 13.20 The 120-V dc source of Fig. 13.54(a) delivers 3.6 W to the load. Determine the peak value of the applied voltage (Em) and the current (Im) if the acsource [Fig. 13.54(b)] is to deliver the same power to the load.35Solution:EXAMPLE 13.21 Find the effective or rms value of the waveform of Fig.13.55.Solution:36EXAMPLE 13.22 Calculate the rms value of the voltage of Fig. 13.57.Solution:EXAMPLE 13.23 Determine the average and rms values of the square wave of Fig. 13.59.37Solution: By inspection, the average value is zero.The waveforms appearing in these examples are the same as thoseused in the examples on the average value. It might prove interesting tocompare the rms and average values of these waveforms.The rms values of sinusoidal quantities such as voltage or currentwill be represented by E and I. These symbols are the same as thoseused for dc voltages and currents. To avoid confusion, the peak valueof a waveform will always have a subscript m associated with it: Imsin qt. Caution: When finding the rms value ofthe positive pulse of asine wave, note that the squared area is not simply (2Am)24A2m; itmust be found by a completely new integration. This will always bethe case for any waveform that is not rectangular.A uniquesituation arises if a waveform has both a dc and an ac componentthat may be due to a source such as the one in Fig. 13.61. Thecombination appears frequently in the analysis of electronic networkswhere both dc and ac levels are present in the same system.38The question arises, What is the rms value of the voltage vT? Onemight be tempted tosimply assume that it is the sum of the rms valuesof each component of the waveform; that is, VT rms 0.7071(1.5 V) 6 V 1.06 V 6 V 7.06 V. However, the rms value is actuallydetermined bywhich for the above example is39直流值相等。

毕业设计（论文）单片机英文中文翻译论文AT89S52FeaturesCompatible with MCS-51 Products8K Bytes of In-System Programmable ISP Flash Memory –Endurance 10000 WriteErase Cycles40V to 55V Operating RangeFully Static Operation 0 Hz to 33 MHzThree-level Program Memory Lock256 x 8-bit Internal RAM32 Programmable IO LinesThree 16-bit TimerCountersEight Interrupt SourcesFull Duplex UART Serial ChannelLow-power Idle and Power-down ModesInterrupt Recovery from Power-down ModeWatchdog Timer Dual Data PointerPower-off Flag Fast Programming TimeFlexible ISP Programming Byte and Page ModeGreen PbHalide-free Packaging OptionDescriptionThe AT89S52 is a low-power high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applicationsThe AT89S52 provides the following standard features 8K bytes of Flash 256 bytes of RAM 32 IO lines Watchdog timer two data pointers three 16-bit timercounters a six-vector two-level interrupt architecture a full duplex serial port on-chip oscillator and clock circuitry In addition the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes The Idle Mode stops the CPU while allowing the RAM timercounters serial port and interrupt system to continue functioning The Power-down mode saves the RAM con-tents but freezes the oscillator disabling all other chip functions until the next interrupt or hardware resetPin Description21 VCC Supply voltage22 GND Ground23 Port 0Port 0 is an 8-bit open drain bidirectional IO port As an output port each pin can sink eight TTL inputs When 1s are written to port 0 pins the pins can be used as high-impedance inputs Port 0 can also be configured to be the multiplexed low-order addressdata bus during accesses to external program and data memory In this mode P0 has internal pull-ups Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification External pull-ups are required during program verification24 Port 1Port 1 is an 8-bit bidirectional IO port with internal pull-ups The Port 1 output buffers can sinksource four TTL inputs When 1s are written to Port 1 pins they are pulled high by the inter-nal pull-ups and can be used as inputs As inputs Port 1 pins that are externally being pulled low will source current IIL because of the internal pull-ups In addition P10 and P11 can be configured to be the timercounter 2 external count input P10T2 and the timercounter 2 trigger input P11T2EX respectively as shown in the follow-ing tablePort 1 also receives the low-order address bytes during Flash programming and verificationPort Pin Alternate Functions P10 T2 external count input to TimerCounter 2 clock-out P11 T2EX TimerCounter 2 capturereloadtrigger and direction control P15 MOSI used for In-System Programming P16 MISO used for In-System Programming P17 SCK used for In-System Programming 25 Port 2Port 2 is an 8-bit bidirectional IO port with internal pull-ups The Port 2 output buffers can sinksource four TTL inputs When 1s are written to Port 2 pins they are pulled high by the inter-nal pull-ups and can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current IIL because of the internal pull-ups Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses MOVX DPTR In this application Port 2 uses strong internal pull-ups when emitting 1s During accesses to external data memory that use 8-bit addresses MOVX RI Port 2 emits the contents of the P2 Special Function Register Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification26 Port 3Port 3 is an 8-bit bidirectional IO port with internal pull-ups The Port 3 output buffers can sinksource four TTL inputs When 1s are written to Port 3 pins they are pulled high by the inter-nal pull-ups and can be used as inputs As inputs Port 3 pins that are externally being pulled low will source current IIL because of the pull-ups Port 3 receives some control signals for Flash programming and verification Port 3 also serves the functions of various special features of the AT89S52as shown in the fol-lowing tablePort Pin Alternate Functions P30 RXD serial input portP31 TXD serial output port P32 external interrupt 0P33 external interrupt 1 P34 T0 timer 0 external inputP35 T1 timer 1 external input P36 external data memory write strobe P37 external data memory read strobe 27 RSTReset input A high on this pin for two machine cycles while the oscillator is running resets the device This pin drives high for 98 oscillator periods after the Watchdog times out The DISRTO bit in SFR AUXR address 8EH can be used to disable this feature In the default state of bit DISRTO the RESET HIGH out feature is enabled28 ALEAddress Latch Enable ALE is an output pulse for latching the low byte of the address during accesses to external memory This pin is also the program pulse input during Flash programming In normal operation ALE is emitted at a constant rate of 16 the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped dur-ing each access to external data memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With the bit set ALE is active only during a MOVX or MOVC instruction Otherwise the pin is weakly pulled high Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode29 Program Store Enable is the read strobe to external programmemory When the AT89S52 is executing code from external program memory is activated twice each machine cycle except that two activations are skipped during each access to exter-nal data memory210 VPPExternal Access Enable must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note however that if lock bit 1 is programmed will be internally latched on reset should be strapped to VCC for internal program executions This pin also receives the 12-volt programming enable voltage VPP during Flash programming 211 XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit212 XTAL2Output from the inverting oscillator amplifierMemory OrganizationMCS-51 devices have a separate address space for Program and Data Memory Up to 64K bytes each of external Program and Data Memory can be addressed31 Program MemoryIf the pin is connected to GND all program fetches are directed to external memory On the AT89S52 if is connected to VCC program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory32 Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM The upper 128 bytes occupy a parallel address space to the Special Function Registers This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space When an instruction accesses an internal location above address 7FH the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space Instructions which use direct addressing access the SFR space For example the following direct addressing instruction accesses the SFR at location 0A0H which is P2MOV 0A0H dataInstructions that use indirect addressing access the upper 128 bytes of RAM For example the following indirect addressing instruction where R0 contains 0A0H accesses the data byte at address 0A0H rather than P2 whose address is 0A0HMOV R0 dataNote that stack operations are examples of indirect addressing so the upper 128 bytes of data RAM are available as stack spaceWatchdog Timer One-time Enabled with Reset-outThe WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets The WDT consists of a 14-bit counter and the Watchdog Timer Reset WDTRST SFR The WDT is defaulted to disable from exiting reset To enable the WDT a user must write 01EH and 0E1H insequence to the WDTRST register SFR location 0A6H When the WDT is enabled it will increment every machine cycle while the oscillator is running The WDT timeout period is dependent on the external clock frequency There is no way to disable the WDT except through reset either hardware reset or WDT overflow reset When WDT over-flows it will drive an output RESET HIGH pulse at the RST pin41 Using the WDTTo enable the WDT a user must write 01EH and 0E1H in sequence to the WDTRST register SFR location 0A6H When the WDT is enabled the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow The 14-bit counter overflows when it reaches 16383 3FFFH and this will reset the device When the WDT is enabled it will increment every machine cycle while the oscillator is running This means the user must reset the WDT at least every 16383 machine cycles To reset the WDT the user must write 01EH and 0E1H to WDTRST WDTRST is a write-only register The WDT counter cannot be read or written When WDT overflows it will generate an output RESET pulse at the RST pin The RESET pulse dura-tion is 98xTOSC where TOSC 1FOSC To make the best use of the WDT it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset42 WDT During Power-down and IdleIn Power-down mode the oscillator stops which means the WDT also stopsWhile in Power-down mode the user does not need to service the WDT There are two methods of exiting Power-down mode by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode When Power-down is exited with hardware reset servicing the WDT should occur as it normally does whenever the AT89S52 is reset Exiting Power-down with an interrupt is significantly different The interrupt is held low long enough for the oscillator to stabilize When the interrupt is brought high the interrupt is serviced To prevent the WDT from resetting the device while the interrupt pin is held low the WDT is not started until the interrupt is pulled high It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode To ensure that the WDT does not overflow within a few states of exiting Power-down it is best to reset the WDT just before entering Power-down mode Before going into the IDLE mode the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled The WDT keeps counting during IDLE WDIDLE bit 0 as the default state To prevent the WDT from resetting the AT89S52 while in IDLE mode the user should always set up a timer that will periodically exit IDLE service the WDT and reenter IDLE mode With WDIDLE bit enabled the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE5 UARTThe UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C526 Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C527 Timer 2Timer 2 is a 16-bit TimerCounter that can operate as either a timer or an event counter The type of operation is selected by bit C in the SFR T2CON Timer 2 has three operating modes capture auto-reload up or down counting and baud rate generator The modes are selected by bits in T2CON as shown in Table 6-1 Timer 2 consists of two 8-bit registers TH2 and TL2 In the Timer function the TL2 register is incremented every machine cycle Since a machine cycle consists of 12 oscillator periods the count rate is 112 of the oscil-lator frequencyTable 6-1 Timer 2 Operating ModesRCLK TCLK CP TR2 MODE 0 0 1 16-bit Auto-reload 01 1 16-bit Capture 1 X 1 Baud Rate Generator XX 0 Off In the Counter function the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in theregister during S3P1 of the cycle following the one in which the transition was detected Since two machine cycles 24 oscillator periods are required to recognize a 1-to-0 transition the imum count rate is 124 of the oscillator frequency To ensure that a given level is sampled at least once before it changes the level should be held for at least one full machine cycle71 Capture ModeIn the capture mode two options are selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON This bit can then be used to generate an interrupt If EXEN2 1 Timer 2 performs the same operation but a 1-to-0 transi-tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set The EXF2 bit like TF2 can generate an interrupt72 Auto-reload Up or Down CounterTimer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode This feature is invoked by the DCEN Down Counter Enable bit located in the SFR T2MOD Upon reset the DCEN bit is set to 0 so that timer 2 will default to count up When DCEN is set Timer 2 can count up or down depending on the value of the T2EX pin Timer 2 automatically counting up when DCEN 0 In this mode two options areselected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software If EXEN2 1 a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX This transition also sets the EXF2 bit Both the TF2 and EXF2 bits can generate an interrupt if enabled Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 10-2 In this mode the T2EX pin controls the direction of the count A logic 1 at T2EX makes Timer 2 count up The timer will overflow at 0FFFFH and set the TF2 bit This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers TH2 and TL2 respectively A logic 0 at T2EX makes Timer 2 count down The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution In this operating mode EXF2 does not flag an interrupt8 Baud Rate GeneratorTimer 2 is selected as the baud rate generator by setting TCLK andor RCLK in T2CON Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer1 is used for the other function Setting RCLK andor TCLK puts Timer2 into its baud rate generator mode The baud rate generator mode is similar to the auto-reload mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L which are preset by software The baud rates in Modes 1 and3 are determined by Timer 2s overflow rate according to the fol-lowing equation The Timer can be configured for either timer or counter operation In most applications it is con-figured for timer operation CP 0 The timer operation is different for Timer 2 when it is used as a baud rate generator Normally as a timer it increments every machine cycle at 112 the oscillator frequency As a baud rate generator however it increments every state time at 12 the oscillator frequency9 Programmable Clock OutA 50 duty cycle clock can be programmed to come out on P10 This pin besides being a regular IO pin has two alternate functions It can be programmed to input the external clock for TimerCounter 2 or to output a 50 duty cycle clock ranging from 61 Hz to 4 MHz for a 16-MHz operating frequency To configure the TimerCounter 2 as a clock generator bit C T2CON1 must be cleared and bit T2OE T2MOD1 must be set Bit TR2 T2CON2 starts and stops the timer The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers RCAP2H RCAP2L as shown in the following equationIn the clock-out mode Timer 2 roll-overs will not generate an interrupt This behavior is similar to when Timer 2 is used as a baud-rate generator It is possible to use Timer 2 as a baud-rate gen-erator and a clock generator simultaneously Note however that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L10 InterruptsThe AT89S52 has a total of six interrupt vectors two external interrupts and three timer interrupts Timers 0 1 and 2 and the serial port interrupt Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE IE also contains a global disable bit EA which disables all interrupts at once Note that bit position IE6 is unimplemented User software should not write a 1 to this bit position since it may be used in future AT89 products Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON Nei-ther of these flags is cleared by hardware when the service routine is vectored to In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and that bit will have to be cleared in software The Timer 0 and Timer 1 flags TF0 and TF1 are set at S5P2 of the cycle in which the timers overflow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polled in thesame cycle in which the timer overflows11 Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output respectively of an inverting amplifier that can be configured for use as an on-chip oscillator Either a quartz crystal or ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven There are no requirements on the duty cycle of the external clock signal since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop but minimum and imum voltage high and low time specifications must be observed12 Idle ModeIn idle mode the CPU puts itself to sleep while all the on-chip peripherals remain active The mode is invoked by software The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode The idle mode can be terminated by any enabled interrupt or by a hardware reset Note that when idle mode is terminated by a hardware reset the device normally resumes pro-gram execution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset the instruction following the one that invokes idle mode should notwrite to a port pin or to external memory13 Power-down ModeIn the Power-down mode the oscillator is stopped and the instruction that invokes Power-down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt Reset redefines the SFRs but does not change the on-chip RAM The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize AT89S52单片机主要性能与MCS-51单片机产品兼容8K字节在系统可编程Flash存储器1000次擦写周期全静态操作0Hz～33Hz三级加密程序存储器32个可编程IO口线三个16位定时器计数器八个中断源全双工UART串行通道低功耗空闲和掉电模式掉电后中断可唤醒看门狗定时器双数据指针掉电标识符功能特征描述AT89S52是一种低功耗高性能CMOS8位微控制器具有8K 在系统可编程Flash 存储器使用Atmel 公司高密度非易失性存储器技术制造与工业80C51 产品指令和引脚完全兼容片上Flash允许程序存储器在系统可编程亦适于常规编程器在单芯片上拥有灵巧的8 位CPU 和在系统可编程Flash使得AT89S52为众多嵌入式控制应用系统提供高灵活超有效的解决方案AT89S52具有以下标准功能 8k字节Flash256字节RAM32 位IO 口线看门狗定时器2 个数据指针三个16 位定时器计数器一个6向量2级中断结构全双工串行口片内晶振及时钟电路另外AT89S52 可降至0Hz 静态逻辑操作支持2种软件可选择节电模式空闲模式下CPU 停止工作允许RAM定时器计数器串口中断继续工作掉电保护方式下RAM内容被保存振荡器被冻结单片机一切工作停止直到下一个中断或硬件复位为止引脚功能VCC 电源GND 接地P0口 P0口是一个8位漏极开路的双向IO口作为输出口每位能驱动8个TTL逻辑电平对P0端口写1时引脚用作高阻抗输入当访问外部程序和数据存储器时P0口也被作为低8位地址数据复用在这种模式下P0具有内部上拉电阻在flash编程时P0口也用来接收指令字节在程序校验时输出指令字节程序校验时需要外部上拉电阻24 P1口P1 口是一个具有内部上拉电阻的8 位双向IO 口p1 输出缓冲器能驱动4 个TTL 逻辑电平对P1 端口写1时内部上拉电阻把端口拉高此时可以作为输入口使用作为输入使用时被外部拉低的引脚由于内部电阻的原因将输出电流IIL此外P10和P12分别作定时器计数器2的外部计数输入P10T2和时器计数器2的触发输入P11T2EX具体如下表所示在flash编程和校验时P1口接收低8位地址字节引脚号第二功能P10 T2定时器计数器T2的外部计数输入时钟输出P11 T2EX定时器计数器T2的捕捉重载触发信号和方向控制P15 MOSI在系统编程用P16 MISO在系统编程用P17 SCK在系统编程用25 P2口P2 口是一个具有内部上拉电阻的8 位双向IO 口P2 输出缓冲器能驱动4 个TTL 逻辑电平对P2 端口写1时内部上拉电阻把端口拉高此时可以作为输入口使用作为输入使用时被外部拉低的引脚由于内部电阻的原因将输出电流IIL在访问外部程序存储器或用16位地址读取外部数据存储器例如执行MOVX DPTR时P2 口送出高八位地址在这种应用中P2 口使用很强的内部上拉发送1在使用8位地址如MOVX RI访问外部数据存储器时P2口输出P2锁存器的内容在flash编程和校验时P2口也接收高8位地址字节和一些控制信号26 P3口P3 口是一个有内部上拉电阻的8 位双向IO 口p2 输出缓冲器能驱动4 个TTL 逻辑电平对P3 端口写1时内部上拉电阻把端口拉高此时可以作为输入口使用作为输入使用时被外部拉低的引脚由于内部电阻的原因将输出电流IILP3口亦作为AT89S52特殊功能第二功能使用如下表所示在flash编程和校验时P3口也接收一些控制信号引脚号第二功能P30 RXD串行输入P31 TXD串行输出P32 外部中断0 P33 外部中断1 P34 T0定时器0外部输入P35 T1定时器1外部输入P36 外部数据存储器写选通P37 外部数据存储器写选通27 RST复位输入晶振工作时RST脚持续2 个机器周期高电平将使单片机复位看门狗计时完成后RST 脚输出96 个晶振周期的高电平特殊寄存器AUXR 地址8EH 上的DISRTO位可以使此功能无效DISRTO默认状态下复位高电平有效28 ALE地址锁存控制信号ALE是访问外部程序存储器时锁存低8 位地址的输出脉冲在flash编程时此引脚也用作编程输入脉冲在一般情况下ALE 以晶振六分之一的固定频率输出脉冲可用来作为外部定时器或时钟使用然而特别强调在每次访问外部数据存储器时ALE脉冲将会跳过如果需要通过将地址为8EH 的SFR的第0位置 1ALE操作将无效这一位置 1ALE 仅在执行MOVX 或MOVC指令时有效否则ALE 将被微弱拉高这个ALE 使能标志位地址为8EH的SFR的第0位的设置对微控制器处于外部执行模式下无效29 外部程序存储器选通信号是外部程序存储器选通信号当AT89S52从外部程序存储器执行外部代码时在每个机器周期被激活两次而在访问外部数据存储器时将不被激活210 VPP访问外部程序存储器控制信号为使能从0000H 到FFFFH的外部程序存储器读取指令必须接GND为了执行内部程序指令应该接VCC在flash编程期间也接收12伏VPP电压211 XTAL1振荡器反相放大器和内部时钟发生电路的输入端212 XTAL2振荡器反相放大器的输出端3 存储器结构MCS-51器件有单独的程序存储器和数据存储器外部程序存储器和数据存储器都可以64K寻址31 程序存储器如果引脚接地程序读取只从外部存储器开始对于89S52如果接VCC程序读写先从内部存储器地址为0000H～1FFFH开始接着从外部寻址寻址地址为2000HFFFFH32 数据存储器 AT89S52 有256 字节片内数据存储器高128 字节与特殊功能寄存器重叠也就是说高128字节与特殊功能寄存器有相同的地址而物理上是分开的当一条指令访问高于7FH 的地址时寻址方式决定CPU 访问高128 字节RAM 还是特殊功能寄存器空间直接寻址方式访问特殊功能寄存器SFR例如下面的直接寻址指令访问0A0HP2口存储单元MOV 0A0H data使用间接寻址方式访问高128 字节RAM例如下面的间接寻址方式中R0 内容为0A0H访问的是地址0A0H的寄存器而不是P2口它的地址也是0A0H MOV R0 data堆栈操作也是简介寻址方式因此高128字节数据RAM也可用于堆栈空间4 看门狗定时器WDT是一种需要软件控制的复位方式WDT 由13位计数器和特殊功能寄存器中的看门狗定时器复位存储器WDTRST构成WDT 在默认情况下无法工作为了激活WDT户用必须往WDTRST 寄存器地址0A6H中依次写入01EH 和0E1H当WDT激活后晶振工作WDT在每个机器周期都会增加WDT计时周期依赖于外部时钟频率除了复位硬件复位或WDT溢出复位没有办法停止WDT工作当WDT溢出它将驱动RSR引脚一个高个电平输出41 WDT的使用为了激活WDT用户必须向WDTRST寄存器地址为0A6H的SFR依次写入0E1H 和0E1H当WDT激活后用户必须向WDTRST写入01EH和0E1H喂狗来避免WDT溢出当计数达到8191 1FFFH 时13 位计数器将会溢出这将会复位器件晶振正常工作WDT激活后每一个机器周期WDT 都会增加为了复位WDT用户必须向WDTRST 写入01EH 和0E1HWDTRST 是只读寄存器WDT 计数器不能读或写当WDT 计数器溢出时将给RST 引脚产生一个复位脉冲输出这个复位脉冲持续96个晶振周期TOSC其中TOSC 1FOSC为了很好地使用WDT应该在一定时间内周期性写入那部分代码以避免WDT复位42 掉电和空闲方式下的WDT在掉电模式下晶振停止工作这意味这WDT也停止了工作在这种方式下用户不必喂狗有两种方式可以离开掉电模式硬件复位或通过一个激活的外部中断通过硬件复位退出掉电模式后用户就应该给WDT 喂狗就如同通常AT89S52 复位一样通过中断退出掉电模式的情形有很大的不同中断应持续拉低很长一段时间使得晶振稳定当中断拉高后执行中断服务程序为了防止WDT在中断保持低电平的时候复位器件WDT 直到中断拉低后才开始工作这就意味着WDT 应该在中断服务程序中复位为了确保在离开掉电模式最初的几个状态WDT不被溢出最好在进入掉电模式前就复WDT在进入待机模式前特殊寄存器AUXR的WDIDLE位用来决定WDT是否继续计数默认状态下在待机模式下WDIDLE＝0WDT继续计数为了防止WDT 在待机模式下复位AT89S52用户应该建立一个定时器定时离开待机模式再重新进入待机模式5 UART在AT89S52 中UART 的操作与AT89C51 和AT89C52 一样6 定时器0 和定时器1在AT89S52 中定时器0 和定时器1 的操作与AT89C51 和AT89C52 一样7 定时器2定时器2是一个16位定时计数器它既可以做定时器又可以做事件计数器其工作方式由特殊寄存器T2CON中的CT2位选择如表2所示定时器2有三种工作模式捕捉方式自动重载向下或向上计数和波特率发生器如表 3 所示工作模式由T2CON中的相关位选择定时器2 有2 个8位寄存器TH2和TL2在定时工作方式中每个机器周期TL2 寄存器都会加1由于一个机器周期由12 个晶振周期构成因此计数频率就是晶振频率的112表3 定时器2工作模式RCLK TCLK CP TR2 MODE 0 0 1 16位自动重载0 1 1 16位捕捉 1 X 1 波特率发生器X X 0 不用在计数工作方式下寄存器在相关外部输入角T2 发生1 至0 的下降沿时增加1在这种方式下每个机器周期的S5P2期间采样外部输入一个机器周期采样到高电平而下一个周期采样到低电平计数器将加1在检测到跳变的这个周期的S3P1 期间新的计数值出现在寄存器中因为识别1－0的跳变需要2个机器周期24个晶振周期所以最大的计数频率不高于晶振频率的124为了确保给定的电平在改变前采样到一次电平应该至少在一个完整的机器周期内保持不变71 捕捉方式在捕捉模式下通过T2CON中的EXEN2来选择两种方式如果EXEN2 0定时器2时一个16位定时计数器溢出时对T2CON 的TF2标志置位TF2引起中断如果EXEN2 1定时器2做相同的操作除上述功能外外部输入T2EX引脚P111至0的下跳变也会使得TH2和TL2中的值分别捕捉到RCAP2H和RCAP2L中除此之外T2EX 的跳变会引起T2CON 中的EXF2 置位像TF2 一样T2EX 也会引起中断72 自动重载当定时器 2 工作于16 位自动重载模式可对其编程实现向上计数或向下计数这一功能可以通过特殊寄存器T2MOD见表4中的DCEN向下计数允许位来实现通过复位DCEN 被置为0因此定时器2 默认为向上计数DCEN 设置后定时器2就可以取决于T2EX向上向下计数DCEN 0 时定时器2 自动计数通过T2CON 中的EXEN2 位可以选择两种方式如果EXEN2 0定时器2计数计到0FFFFH后置位TF2溢出标志计数溢出也使得定时器寄存器重新从RCAP2H 和RCAP2L 中加载16 位值定时器工作于捕捉模式RCAP2H和RCAP2L的值可以由软件预设如果EXEN2 1计数溢出或在外部T2EXP11引脚上的1到0的下跳变都会触发16位重载这个跳变也置位EXF2中断标志位置位DCEN允许定时器2向上或向下计数在这种模式下T2EX引脚控制着计数的方向T2EX上的一个逻辑1使得定时器2向上计数定时器计到0FFFFH溢出并置位TF2定时器的溢出也使得RCAP2H和RCAP2L中的16位值分别加载到定时器存储器TH2和TL2中T2EX 上的一个逻辑0 使得定时器2 向下计数当TH2 和TL2 分别等于RCAP2H 和RCAP2L中的值的时候计数器下溢计数器下溢置位TF2并将0FFFFH加载到定时器存储器中定时器2上溢或下溢外部中断标志位EXF2 被锁死在这种工作模式下EXF2不能触发中断8 波特率发生器通过设置T2CON中的TCLK或RCLK可选择定时器2 作为波特率发生器如果定时器2作为发送或接收波特率发生器定时器1可用作它用发送和接收的波特率可以不同如图8 所示设置RCLK 和或TCLK 可以使定时器2 工作于波特率产生模式波特率产生工作模式与自动重载模式相似因此TH2 的翻转使得定时器2 寄存器重载被软件预置16位值的RCAP2H和RCAP2L中的值模式1和模式3的波特率由定时器2溢出速率决定定时器可设置成定时器也可为计数器在多数应用情况下一般配置成定时方式CP 0定时器 2 用于定时器操作与波特率发生器有所不同它在每一机器周期112晶振周期都会增加然而作为波特率发生器它在每一机器状态12晶振周期都会增加9 可编程时钟输出可以通过编程在P10 引脚输出一个占空比为50的时钟信号这个引脚除了常规的IO 角外还有两种可选择功能它可以通过编程作为定时器计数器 2 的外部时钟输入或占空比为50的时钟输出当工作频率为16MHZ时时钟输出频率范围为61HZ到4HZ为了把定时器2配置成时钟发生器位CT2CON1必须清0位T2OET2MOD1必须置1位TR2T2CON2启动停止定时器时钟输出频率取决于晶振频率和定时器2捕捉寄存器RCAP2HRCAP2L的重载值如公式所示在时钟输出模式下定时器2不会产生中断这和定时器2用作波特率发生器一样定时器2也可以同时用作波特率发生器和时钟产生不过波特率和输出时钟频率相互并不独立它们都依赖于RCAP2H和RCAP2L10 中断AT89S52 有6个中断源两个外部中断和三个定时中断定时器012和一个串行中断每个中断源都可以通过置位或清除特殊寄存器IE 中的相关中断允许控。

Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerAbstractWith the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices.Index TermsSingle Event Effects, Hardened-By-Design, microcontroller, radiation effects.I. INTRODUCTIONNASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercialstate-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely,cost-effective, and reliable manner.However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed; what types of tests are required for HBD validation?II. TESTING HBD DEVICES CONSIDERATIONSTest methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices?As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library?Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked.How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived.Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies.The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations.III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required.The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation–hardened 8051, that built their 8051 microcontroller using radiationhardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST DEVICESThree devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively.The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set compatible with the MSC-51 family.V. TEST HARDWAREThe 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other componentsof the DUT computer were removed from the immediate area of the irradiation beam.A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup.VI. TEST SOFTWAREThe 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT.All test programs implemented:• An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.• An external real-time clock for data error tag.•A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary.• A "foul-up" routine to reset program counter if it wanders out of code space.• An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured.Interrupt –This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information.Logic –This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register information.Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted.Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted.Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information.VII. TEST METHODOLOGYThe DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer's memory space). Upon awaking from the reset, the DUT computer again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code.The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itselfor the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the post-test functions. During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this reportceased, the Test Controller knew that a SEFI had occurred. This periodic data was called "telemetry". If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through the serial port describing that error, and continued with the test.VIII.DISCUSSIONA. Single Event LatchupThe main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5, 3.3, and 2.5 Volts, as well as the 0.5 Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity.B. Single Event UpsetThe primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some resultsobtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051.With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) component is sitting on top of a "dc-bias" component –presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold.The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated place-and-route of the combinatorial logic paths may have placed dual sensitive nodes close enough.At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this 0.35 μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at 0.5 Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the per-bit memory upset cross section for the CULPRiT devices and the commercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has become sensitive to upset.IX. SUMMARYA detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the commercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results.This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equivalent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application.ACKNOWLEDGEMENTSThe authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).。

附录A 英文原文Design of PWM Controller in a MCS-51 Compatible MCUAuthor . Yue-Li Hu Wei Wang Microelectronic Research Development Center CampusP.O.B.221 149 Yanchang Rd Shanghai 200072 China Introduction PWM technology is a kind of voltage regulation method by controlling the switchfrequency of DC power with fixed voltage to modify the two-end voltage of load. Thistechnology can be used for a variety of applications including motor control temperaturecontrol and pressure control and so on. In the motor control system shown as Fig. 1 throughadjusting the duty cycle of power switch the speed of motor can be controlled. As shown inFig. 2 under the control of PWM signal the average of voltage that controls the speed ofmotor changes with Duty-cycle D t1/T in this Figure thus the motor speed can beincreased when motor power turn on decreased when power turn off.Fig.1: The Relationship between Voltage of Armature and Fig.2 Architecture of PWM Module Therefore the motor speed can be controlled with regularly adjusting the time of turn-onand turn-off. There are three methods could achieve the adjustment of duty cycle: 1 Adjustfrequency with fixed pulse-width. 2 Adjust both frequency and pulse-width. 3 Adjustpulse-width with fixed frequency. Generally there are four methods to generate the PWM signals as the following: 1Generated by the device composed of separate logic components. This method is the originalmethod which now has been discarded. 2 Generated by software. This method need CPU tocontinuously operate instructions to control I/O pins for generating PWM output signals sothat CPU can not do anything other. Therefore the method also has been discarded gradually.3 Generated by ASIC. The ASIC makes a decrease of CPU burden and steady workgenerally has several functions such as over-current protection dead-time adjustment and soon. Then the method has been widely used in many kinds of occasion now. 4 Generated byPWM function module of MCU. Through embedding PWM function module in MCU andinitializing the function PWM pins of MCU can also automatically generate PWM outsignals without CPU controlling only when need to change duty-cycle. It is the method thatwill be implemented in this paper. In this paper we propose a PWM module embedded in a 8051 microcontroller. ThePWM module can support PWM pulse signals by initializing the control register andduty-cycle register with three methods just mentioned above to adjust the duty cycle andseveral operation modes to add flexibility for user. The following section explains the architecture of the PWM module and the architecturesof basic functional blocks. Section3 describes two operation modes. Experimental andsimulation results verifying proper system operation are also shown in that section.Depending on mode of operation the PWM module creates one or more pulse-widthmodulated signals whose duty ratios can be independently adjusted. Implementation of PWM module in MCU Overview of the PWM module A block diagram of PWM module is shown in Fig.3. It is clearly from the diagram thatthe whole module is composed of two sections: PWM signal generator and dead-timegenerator with channel select logic. The PWM function can be started by the user throughimplementing some instructions for initializing the PWM module. In particular the followingpower and motion control applications are supported: DC Motor Uninterruptablel Power Supply UPSThe PWM module also has the following features: Two PWM signal outputs with complementary or independent operation Hardware dead-time generators for complementary mode Duty cycle updates are configurable to be immediated or synchronized to the PWM Fig.3 Architecture of PWM Module Details of the architecture PMW generator The architecture of the 2-output PWM generator shownin Fig.4 is based on a 16-bitresolution counter which creates a pulse-width modulated signal. The system is synthesizedby a system clock signal whose frequency can be divided by 4 times or 12 times throughsetting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON asshown in Fig.4. To PWM0 generator the clock to 16-bit counter will be pre-divided by 4times by default when T3M is set to zero. And the clock will be divided by 12 times whenT3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained indetail in Table 1. Fig .4 Bit Mapping of PWMCON Table 1: The Bit Definition in PWMCONChannel-select logic The follow Fig. 5 shows the channel-select logic which is useful in ComplementaryMode. From this diagram it is clear to know that signal CP and CPWM control the source ofPWMH and PWML. And the details about the two control signals will be discussed in thesection 3 and the architecture of dead-time generator will also be discussed in section 5 forthe continuity of Complementary Mode. Fig. 5 Diagram of Channel-select LogicOperation Mode and Simulation Results The design has two operation modes: Independent Mode and Complimentary Mode. Bysetting the corresponding bit CPWM in register PWMCON shown in Fig.6 user can select oneof the two operation modes. When CPWM is set to zero PWM module will work inIndependent Mode whereas PWM module will work in Complimentary Mode. In thefollowing of this section the two operation mode will be explained respectively in detail andthe simulation results of the PWM module from the Synoposys VCS EDA platform whichverify the design will also be shown.Independent PWM Output Mode An Independent PWM Output mode is useful for driving loads such as the one shown inFigure 6. A particular PWM output is in the Independent Output mode when thecorresponding CP bit in the PWMCON register is set to zero.In this case two-channel PWMoutputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0generator and the signal on pin PWM1/PWML is from PWM0 generator. The separate case isachieved by the channel-select logic shown in Fig. 6. The PWM I/O pins are set toindependent mode by default upon advice reset. The dead-time generator is disabled in theIndependent mode. The simulation result is shown in Figure 6 as the following Fig.6 Tr4 andtr3 are run bits to PWM0 and PWM1 respectively. Actually from this diagram Pin P15/P14 of MCU is used for PWMH/ PWML or normal I/O alternatively. Fig6 the Waveform of PWM Outputs in Independent ModeComplementary PWM Output Mode The Complementary Output mode is used to drive inverter loads similar to the oneshown in Figure 7. This inverter topology is typical for DC applications. In ComplementaryOutput Mode the pair of PWM outputs cannot be active simultaneously. The PWM channeland output pin pair are internally configured through channel-select logic as shown in Figure7.A dead-time may be optionally inserted during device switching where both outputs areinactive for a short period. Fig 7 : Typical Load for Complementary PWM Outputs The Complementary mode is selected for PWM I/O pin pair by setting the appropriateCPWM bit in PWMCON. In this case PSEL is in effect. PWMH and PWML will come fromPWM0 generator when PSEL is set to zero when the signals from PWM1 generator is uselesswhereas PWMH and PWML will come from PWM1 generator when PSEL is set to 1 whenthe signals from PWM0 generator is useless. In the process of producing the PWM outputs inComplementary Mode the dead-time will be inserted to be discussed in the following section.Dead-time Control Dead-time generation is automatically enabled when PWM I/O pin pair is operating inthe Complementary Output mode. Because the power output devices cannotswitchinstantaneously some amount of time must be provided between the turn-off event of onePWM output in a complementary pair and the turn-on event of the other transistor. The2-output PWM module has one programmable dead-time with 8-bitregister.Thecomplementary output pair for the PWM module has an 8-bit down counter that is used toproduce the dead-time insertion. As shown in Figure 8 the dead time unit has a rising andfalling edge detector connected to PWM signal from one of PWM generator. The dead timesis loaded into the timer on the detected PWM edge event. Depending on whether the edge isrising or falling one of the transitions on the complementary outputs is delayed until the timercounts down to zero. A timing diagram indicating the dead time insertion for the pair of PWMoutputs is shown in Figure 8a. Fig 8a Dead-time Unit Block Diagram Fig. 8b the Waveforms of PWM Outputs in Complementary ModeConclusions In this paper we have designed PWM module based on an 8-bit MCU compatible with8051 family. The design can generate 2-channel programmable periodic PWM signals withtwo operation mode Independent Mode and Complementary Mode in which dead-time willbe inserted. The simulation results on the EDA platform have proven its correctness andusefulness. 附录B 汉语翻译基于C51 兼容微处理器单片机的PWM 控制器设计Yue-Li Hu Wei Wa 单片机研究与开发中心Campus P.O.B.221 149Yanchang Rd Shanghai 200072 China 导言PWM 技术，是一种电压调节方法，通过控制具有固定电压的直流电源的开关频率来调整两端负荷电压。

中文3464字毕业设计外文资料翻译题目基于MSP430F149单片机的时钟设计专业机械设计制造及其自动化班级机械1102班学生学号指导教师二〇一五年三月九日SmartGrid,2013,3,91-95doi:10.12677/sg.2013.33016Published Online June 2013Based on MSP430F149 SCM smallest system designand applicationByAE TuumlDepartment of Mechanical and Electronic Engineering, CollegeChina University of Geosciences,430200Abstract:Single chip microcomputer minimum system, or the minimum application system, refers to the element with the least amount of single-chip microcomputer system can work. For the single chip MSP430 series Machine, the smallest system generally includes: single chip microcomputer, the power supply module, crystal vibration module, reset circuit module, JTAG interface circuit. This paper introduces the MSP430F149 single the characteristics of the machine and the minimum system based on MSP430F149 MCU design and its application, and introduces the composition and function of each module. Include digital tube display module, The LED display module, LCD liquid crystal display module, eight independent keyboard and other circuit module and extended application. The minimum system can download, online simulation and debugging, Proved by the experiment principle of correct and reliable, and can be widely used in teaching, scientific research and electronic design field. By loading the corresponding modules can be made into useful products, has the very great practicality.Keywords: MSP430; smallest system; circuit design; simulation; testBased on MSP430F149 SCM smallest system designand applicationIntroductionWith the rapid development of modern electronic technology and computer technology, microcontroller technology has penetrated into every aspect of human life, in automation, intelligent instrumentation, process control and increasing use of household appliances and many other fields, microcontroller family is becoming more and more big, more and more varieties, and in technology have distinguishing feature each, Texas instruments (TI) new MSP430F149 Single-chip low power consumption, powerful, for the majority of hardware designers.Single-chip microcomputer with necessary external device, generally including power supply into the power switch, reset circuit, crystals, input and output circuit can constitute a minimum system, such as simple structureMSP430F149 chip has 60 KB FLASH + 256 bytes, 2 karma, including the basic clock module, the watchdog timer, with three capture/compare registers and PWM output 16-bit timers, with seven capture/compare registers and PWM output, two 16 bit timer interrupt function of 8 bits parallel port, four 8-bit parallel port, analog comparator, 12 bit A/D converter, and the two serial communication interface module, etc. MSP430F149 chip has the following characteristics:(1) Low power consumption, voltage of 2.2 V, 1 MHZ clock frequency, the current activity pattern chip is 200 mu A, closed mode current is only 0.1 A;(2) Efficient 16-bit RISC CPU, 27 instruction, 8 MHZ clock frequency, the instruction cycle time Of 125 ns, the vast majority of instructions completed in one clock cycle;(3) Low voltage power supply, wide working voltage range: 1.8 ~ 3.6 V;(4)Flexible clock system: two external clock and an internal clock; (5)Low clock frequency can realize high-speed communication; (6) With serial online programming ability；(7) interrupt functions; (8) wake up time is short, wake up just from the low power mode6 mu s; (9) ESD protection, strong anti-interference; (10) fan running environment temperature - 40 ~ + 85 ℃, suitable for the industrial environment.Of all peripheral modules MSP430 series MCU control is achieved through special registers, so it is relatively easy to write. When programming development through the special programmer, you can choose to assembly or C language programming, IAR for MSP430 series MCU development the company dedicated C430 languages, can directly by the WORKBENCH and C - SPY compiler debugging, using flexible and simple.1 The minimum system designMinimum system is a necessary to ensure reliable processors work of basic circuit, including power supply module, the module of crystal vibration and reset circuit module, JTAG interface circuit, display module, etc1.1 The power supply moduleThis system need to use the + 5 V and + 3.3 V dc regulated power supply; including MSP430Fl49 and some peripheral devices need to + 3.3 V power supply, the other part need to + 5 V power supply. In this system, in order to + 5 V dc voltage for the input voltage, 3.3 V + linear step-down directly by the + 5 V.1.2 Crystal vibration moduleMSP430 series MCU clock module includes numerical control oscillator (DCO), high-Speed of crystal oscillator and crystal oscillator at low speed clock source. This is to understand System of rapid processing data and low power requirements of contradiction, through the design multiple clock source or for clock design all sorts of different working mode, can solve some Peripheral parts clock requirements of real-time applications, such as low frequency communication, LCD display, timing Device, counter, etc. Digital control oscillator DCO is integrated within the MSP430, in the system need to design high speed crystal oscillator and the low speed crystalLow-speed crystal oscillator (L X F T L) can meet the requirements of low power consumption and the use of 32.768 kHz crystal vibration. Default LFXTL oscillator work in low frequency mode, the 32.768 kHz, but can be by external 450 kHz ~ 8 MHZ crystal vibration at a high speed Oscillation device or ceramic resonator working in high frequency mode, in this system using low frequency mode Type, crystals external 2 33 PF capacitor after XIN and XOUT connected to the MCU. High-speed chip, also known as the second oscillator XT2, it in working for the MSP430F149High frequency mode provides a clock, XT2 up to 8 MHZ. XT2 adopted in the system4 MHZ crystal, XT2 external 2 33 PF capacitor after XT2IN and XT2OUT connection To the MCU.1.3 Reset circuit moduleManual reset is minimal systems commonly used functions, this system adopts the manual reset button switches and RC circuit implementation, the circuit structure is simple.1.4 The JTAG interface circuitJTAG technology is a kind of embedded debugging technology, chip internal encapsulates the special electrical test TAP (test access port), through special JTAG test tools to test and control of internal nodes, At present most of the ARM device support JTAG protocol, standard JTAG interface is 4 line; TMS (test mode selection), TCK (the clock) and TDI (test data serial input), TDO serial output (test data). JTAG interface connection there are two standards that 14 needle JTAG interface MC9328MX1 connection circuit. Is used here consists of three state output 74 hc244d eight-way buffer of 14 needle JTAG interface circuit.2 Application circuit design based on minimum system2.1 digital tube display moduleA digital tube display need 74 hc164 drive, 74 hc164 serial input and parallel output. Its parallel output actually there is a delay, just delay time is small, can be considered as parallel output. Here is the way a serial port 0, 0 is and communication of the shift register. TXD, RXD at this time is not like other ways a send, a receiver, but RXD can also input, output TXD shift pulse.Sending and receiving data must be 8, bit rate fixed is 1/12 of the crystals. When set mode 0, it is automatically put the TXD make shift pulse. In detecting RXD TXD high levels, if high level 74 hc164 study into 1, if it is a low level, enter 0.Receiving process: REN first to buy 1, then 1 TXD, read RXD condition, high level will receive 1, receive low level 0; Then pull down the TXD, after a slight delay TXD again high, read RXD, high level will receive 1, low level 0, and so on.Read until 8 bits. Send SBUF process: is sent automatically. Send 1 RXD high first, TXD again get higher; And TXD become low, send 0 RXD lower first, TXD again get higher; Then the TXD become low, and so on. This process is done automatically, need not special programming. Digital tube look from the front, the decimal point in the lower right foot, the pin above from left to right are respectively under the public side of A and B, F, G of pins from left to right, respectively, E, C, common (decimal).2.2 The LED display modulePick up a few LED through the I/O port, through the programming a simple program, which can realize the LED flashing, so as to achieve the test circuit and chip is normal.2.3 D/A conversion moduleMSP430F149 MCU with 12 bit A/D converter, but no D/A conversion, need external D/A conversion circuit. So choose DAC0832 d/a conversion chip, and UA741 high-gain general amplifier composed of d/a conversion circuit operation. UA741 chip pins as shown in figure 1.DAC0832 is 8 of D/A conversion chip. Complete compatible with microprocessor. The DA chip with its low cost, simple interface, convert the advantages of easy control, widely used in the MCU application system. D/A converter by eight input latch, 8-bit DAC registers, 8 D/A conversion circuit and control circuit.DAC0832 is sampling frequency for 8 D/A conversion chip,Integrated circuit has two levels of input register, DAC0832 chip with double buffer, single buffer and through three kinds of input methods, in order to fit for the needs of the various circuit (such as requirement asynchronous input, synchronous multi-channel D/A conversion, etc.). The 8 bit D/A converter has eight input end (where each input is one of 8 bit binary number), has an analog output. Input can have 28 = 256 different binary configuration, output is one of 256 voltage, the output voltage is not arbitrary value throughout the whole voltage range, and can only be 256 possible values.2.4 LCD display moduleA/D conversion output data, need to use the LCD display.2.5 Eight independent type keyboard moduleThe keyboard in the microcomputer application system, realize the function of the input data, transmit command, and is a major means of human intervention. Keyboard with coding and non coding keyboard, independent type button structure, matrix structure key. First, monitoring any key press, the key of closed or not, reflect on the voltage is present a high level or low level, so through the detection level of high and low status, can confirm button pressed or not. Second, determine which key is pressed.interrupt scanning way. Keyboard circuit used in hc2 74 is a high-speed Si - gate CMOS1 integration chip, the pin compatible with low power consumption. Belong to the Scotty TTL (input channel). The 74 hc21 provides 4 - input and function.2.6 The software designUsing the IAR Embedded Workbench Evaluation for MSP4305.10.1 software programming, the basic idea: the LED lights, digital tube as the main program, the 7 key as interrupt, LCD is used to enter the interrupt and A/D conversion output display output.2.7 extensionsBy extending the mouth can facilitate the single-chip microcomputer and peripheral module, resources, make full use of the chip pin real MSP430 single chip microcomputer powerful function into full play. Loading other modules in the extension mouth, through debugging, testing can produce a corresponding products on the market, strong practicability and wide prospect of market.Load on minimum system for example, a pressure sensor, electronic scale, what you can accomplish through programming, download again due to the low power consumption system, can make it portable, bring great convenience to people's life;On the basis of minimum system loads a high-precision ultrasonic ranging module, also, you can accomplish through programming, download electronic scale, so as to replace the traditional tape, tape can make up for some disadvantages; If combined with speakers, programming downloads, encapsulate the whole system into modules, can be applied to the car, when the car in the process of driving the car away from less than a certain distance, through the voice to remind the driver, please keep the vehicles, and other related applications.3 ConclusionsMinimum system can directly as a core component used in the engineering and scientific research, has good versatility and expansibility. On the basis of the minimum system, can be easily to carry on the secondary development and function extension, can shorten the development cycle, and reduce development costs. This paper realized the basic functionof the minimum system, each module of hardware circuit is introduced. And on this basis to build a simple application platform. The minimum system can be used as learning, practice teaching experiment board. Also can appropriately modify computer applied in electronic design, teaching and scientific research, industrial control and other fields, can also by loading the corresponding module, converted into useful products, put into the market.References:[1] Cao lei. MSP430 microcontroller C program design and practice [M]. BeijingUniversity of aeronautics and astronautics Press, 2007:105-2007.[2] Xiao Xing gong, strong bum then asked xiong-ying wu. MSP430 single chipmicrocomputer based and practice [M].Beijing University of aeronautics and astronautics press, 2008:84-85.[3] Texas Instrument, MSP430x14xFamilyUser’sGuide[S].2003.(.).[4] jian-hua shen. MSP430 series 16 ultra-low power MCU principle and practice [M].Beijing University of aeronautics and astronautics press, 2008:202-202. The Modern Construction of Modern Construction.SmartGrid,2013,3,91-95doi:10.12677/sg.2013.33016Published Online June 2013基于MSP430F149单片机的最小系统设计及其应用AE TuumlDepartment of Mechanical and Electronic Engineering, CollegeChina University of Geosciences, 430200摘要：单片机最小系统，或称为最小应用系统，是指用最少的元件组成的单片机可以工作的系统。

河南理工大学毕业设计（论文）说明书Presented in this paper is a design of pulse measuring instrument based on MCU, as the circuit module plays an important role in the system, such as heart rate acquisition circuit, display circuit and STC89C52 microcontroller through the serial portto realize the connection. This design with STC89C52 microcontroller as the central control unit, through ST188 as infrared photoelectric sensor to collect the pulse signal, after the lm358 for op amp; again through before and after filtering, magnifying, shaping, and get stable signal; functions to achieve the rapid detection of heart. Youcan also through the button to set the pulse value scope; buzzer driver module In the range beyond the scope of the alarm prompt, the measurement results in the liquid crystal display.Experimental results show that the test results of the design and practical requirements are basically the same, STC89C52 MCU strong anti-interference ability and LCD1602 display control the advantages of more convenient so that thesefeatures can be successfully completed. The production cost less than 100 yuan,with low price, easy manipulation, low power consumption, high reliability, very applicable to families and individuals.Heart rate) in professional terms is used to describe the human heart beat cycle. Pulse of modern Chinese will be interpreted as "heart beating frequency value; so the heart rate can also said in a unit of time, heart rhythm speed.Everyone's heart rate signals mostly contains rich physiological and psychological information. This is due to the health of internal organs of the body can reflect in the pulse information. This discovery has gradually attracted the attention of many clinicians. In our country, pulse diagnosis has been regarded as the essence of Chinese medicine; so far the clinical practice has about 2600 years. However due to the use of fingers often there will be some sweat glands refers to pulse diagnosis in the presence of errors can not be ignored; and leads to inaccurate measurement. Then perhaps you would say and the ear vein measurement, instead of the previous is often used. Although by measuring ear ripple come to pulse signal relatively comparison Clean, but because the ear pulse signal is weak, especially when the seasonal changes, the measurement signal is vulnerable to the influence of environmental temperature,resulting in inaccurate measurement values.With the development and progress of world science and technology and economy, cherish life, health care has become a common pursuit of mankind throughout the world. According to the Health Bureau statistics, every year because of cardiovascular and cerebrovascular diseasesdeath of the highest number of human deaths first, not only the high cost of health care, back to the family, the government and the society caused great burden. In recent years, due to the accelerated pace of life, unreasonable eating habits and many junk food impact and other reasons, the incidence of cardiovascular and cerebrovascular is showing a trend of rising year by year. How to scientifically and harmless reduce cardiovascular disease morbidity and mortality, effectively reduce cardiovascular and cerebrovascular diseasesand social Family burden, has become a very serious problem faced by human beings all over the world.World first lever type pulse scanner is Vierordt was founded in 1854. It is a lever and a pressure drum scanner uses the notation to record the pulse waveform, also is the human for the first time through non invasion of recording the human body pulse, then caused a great sensation. However the starting point for the development of domestic relatively is relatively low, in the early 50s of the 20th century Zhu Yancaiwill pulse instrument reference to objective study on the pulse diagnosis in traditional Chinese medicine. In recent years, non invasive vascular function detection gradually attracted the eyes of the medical professionals. Since about 1980, no traumavascular function detection by using the small range, its principle is roughly Based on hemodynamic rheology theory and elastic chamber theory. Characterized in it by the module temperature, blood pressure cuff module, blood oxygen module of multi physiological signal acquisition module combination by of brachial artery blocking opening in the process of finger end temperature signal, oxygen saturation and pulse wave signal changes of the parameters of the, again according to the clinical trial data acquisition and through the method of signal processing and statistical analysis, establishment of vascular function quantitative evaluation formula and blood vessel function evaluation. It has noninvasive, simple operation, accurate, good repeatability and convenient for clinical application and automatically generates diagnosis ofcardiovascular function, health status analysis and gives related medical solution Release.Now pulse testing is no longer confined to the traditional manual testing or stethoscope test, only use electronic devices can be obtained more accurate data. In today's society, most of electronic measuring instruments has been directed towards the digitization, automation development direction. Pulse measuring instrument is not only good performance, simple structure, and has good value of application and popularization. In general, the pulse measurement instrument development is mainly the following trends: first, in the absence of human can automatically analyze the measurement of pulse value; the pulse of the traditional instrument need after experienced doctor pulse signal of the first initial analysis and then make a comprehensive analysis to final To confirm the results, this method of total said tonot only waste a lot of manpower and by factitious error is relatively large. The second: the wide application of digital technology and other advanced technology; pulse measuring instrument integration to want to achieve a higher degree, and are more convenient to carry must rely on the rapid development of digital science and technology; at the same time digital signal processing application will enable interference becomes smaller measurement result ismore accurate. The third: multi function of more and more obvious. The fourth: cheap, easy to carry and application and popularization value better, to the general public convenience.Has always been in the hospital for basis for clinical diagnosis and treatment of most source extracted from the human pulse wave in physiological and pathological information. In China, feeling the pulse is old doctor of traditional Chinese medicineis the most commonly used to diagnose disease, has been in use ever since. The pulse signal emitted by human body contains the velocity of heart rate, full waveform, period and amplitude, a full range of integrated information, in a large extent can reflect human body each part information (for example blood viscosity, blood velocity). Although these biological signals exist in the human body, the signal intensity relative to said is relatively weak; if in a noisy environment effect is more obvious.This graduation design principle is the use of single-chip microprocessorSTC89C52 as the center processor; pulse signal is collected by the sensor, through the microcontroller chip in the interior of the system timer to set the time; finally get the heart rate beat numerical by STC89C52 microcontroller to signal accumulation can be. Normal heartbeat is about 60-100 per minute times, circuit diagram of key module can through the button to set the scope of people's heart rate, above or below the setting range of possible heart there will be risks, buzzer driver module will drive buzzer alarm; the final measurement results Will be displayed on the LCD. The design can by viewing the IR indicates whether the lights and flashing, if sustained, stable flashing that test results are correct and error is small. With the assumption that the display results back and forth rock and numerical difference between the larger, there may exist error. Through the above steps, can roughly determine the body's own health, and is particularly suitable to be used to the individual or family, is also sometimes used in nursing homes and healthcare center.The design of the selection of SCM is STC89C52。

基于MSP430F149单片机的两轮自平衡小车的设计与研究摘要两轮自平衡小车类似于传统的倒立摆，其本身是不稳定的，必须施加强有力的控制手段才能使之稳定，是研究各种控制方法的一个理想平台。

其工作原理是系统通过陀螺仪和加速度传感器整合出当前车身较精确的与垂直方向的偏角和小车的运行加速度，利用光电编码器测得当前运行速度。

依据运动学原理，通过微控制器计算出适当的数据，输出相应占空比的PWM波形驱动电机以适当的速度运行，从而来维持车体的平衡。

本文选用MSP430F149单片机为控制器，光电编码器来测得车体当前速度，MPU-6050测得车体的角加速度和运行加速度，并通过带有减速器的直流电机实现小车的平衡控制。

关键词：两轮自平衡小车，陀螺仪，加速度计，MSP430F149，光电编码器，PWMABSTRACTTwo-wheeled self-balancing car is similar to that of a traditional inverted pendulum, which itself is not stable whom must be exerted strong control to make .It is an ideal platform for the research of various control methods. Its working principle is through the system of gyro and acceleration sensor integrated operation of the body of vehicle acceleration accurately and the angle, measured its speed by the photoelectric encoder. Through the single-chip microprocessor to calculate the appropriate data based on kinematics, and output the corresponding PWM waveform to drive motor running at an appropriate rate in order to maintain body balance. This paper chooses MSP430F149 MCU as the controller, photoelectric encoder to measure the velocity, MPU-6050 as the gyro and acceleration sensor, and the DC motor with reducer to realize the control system of car.Keywords: gyroscope, accelerometer, MSP430F149, photoelectric encoder, PWM，self-balanced two-wheel vehicle目录2 自平衡小车自平衡设计原理 ------------------------------------------ 0自平衡小车直立控制------------------------------------------------------------------------------------------ 0自平衡小车速度控制------------------------------------------------------------------------------------------ 2 ------------------------------------------------------------------------------------------------------------------------- 5 ------------------------------------------------------------------------------------------------------------------------- 7 3 自平衡小车硬件电路的设计 ------------------------------------------ 7 MSP430F149单片机最小系统 ------------------------------------------------------------------------------- 7 ------------------------------------------------------------------------------------------------------------------------- 8 MPU6050电路 ---------------------------------------------------------------------------------------------------- 9供电电源电路-------------------------------------------------------------------------------------------------- 10 4 自平衡小车软件分析设计 ------------------------------------------- 10系统程序结构分析 ------------------------------------------------------------------------------------------- 10 IIC通信程序设计 -------------------------------------------------------------------------------------------- 11计数程序设计-------------------------------------------------------------------------------------------------- 13 PID调节器程序设计----------------------------------------------------------------------------------------- 13卡尔曼滤波器程 ---------------------------------------------------------------------------------------------- 14 5 结论 ------------------------------------------------------------- 16参考文献 ----------------------------------------------------------- 17致谢 ----------------------------------------------- 错误!未定义书签。