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RTL8111E-VB-GRINTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS APPLICATIONSLAYOUT GUIDE(CONFIDENTIAL: Development Partners Only)Rev. 1.325 January 2010Track ID: JATR-2265-11No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, TaiwanTel.: +886-3-578-0211. Fax: +886-3-577-6047Integrated Gigabit Ethernet Controller for PCI Express Applications ii Track ID: JATR-2265-11 Rev. 1.3COPYRIGHT©2010 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.DISCLAIMERRealtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.TRADEMARKSRealtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.LICENSEThis product is covered by one or more of the following patents: US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and US6,327,625.USING THIS DOCUMENTThis document is intended for the software engineer’s reference and provides detailed programming information.Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.REVISION HISTORYRevision Release Date Summary1.0 2009/09/29Firstrelease.1.1 2009/11/06 Added PCI-E differential signal requirements on section2.1 General Guidelines, page3.Added Figure 14 Separate Transformer, page 14.Revised Table 1 Inductor and Capacitor Parts List, page 15.Revised Figure 29 Switching Regulator Efficiency Measurement Checkpoint, page 24.1.2 2009/12/17 Corrected typing errors.1.3 2010/01/25 Revised section 5 Center-Tapping, page 14.Revised section 6.1 Inductor and Capacitor Parts List, page 15.Added Figure 20 L=GLK2510P-2R2M, C=Ceramic 22µF 1206 X5R WISIN (Ripple10.4mV), page 18.Added Figure 23 L=GLK2510P-4R7M, C=Ceramic 22µF 1206 X5R WISIN (Ripple9.2mV), page 20.Revised section 6.5 Power Sequence, page 25.Integrated Gigabit Ethernet Controller for PCI Express Applicationsiii Track ID: JATR-2265-11 Rev. 1.3 Table of Contents1.INTRODUCTION (1)2.DESIGN AND LAYOUT (3)2.1.G ENERAL G UIDELINES (3)2.2.D IFFERENTIAL S IGNAL L AYOUT G UIDELINES (4)2.3.P LACING THE RTL8111E (5)2.4.M AGNETICS (5)2.5.C RYSTAL (5)2.6.F ERRITE B EADS AND D E-C OUPLING C APACITORS (5)3.SIGNAL AND TRACE ROUTING (6)4.GROUND AND POWER PLANE LAYOUT (8)4.1.G ROUND P LANE L AYOUT (8)4.2.P OWER P LANE L AYOUT (10)4.3.F OUR-L AYER B OARD P LANE L AYOUT (11)4.3.1.Signal 1 Plane Layout (Top Layer) (12)4.3.2.Ground Plane Layout (Layer 2) (12)4.3.3.Power Plane Layout (Layer 3) (13)4.3.4.Signal 2 Plane Layout (Bottom Layer) (13)5.CENTER-TAPPING (14)6.SWITCHING REGULATOR (15)6.1.I NDUCTOR AND C APACITOR P ARTS L IST (15)6.2.M EASUREMENT C RITERIA (16)6.3.E FFICIENCY M EASUREMENT (23)6.4.PCB L AYOUT (24)6.5.P OWER S EQUENCE (25)7.PARTS RECOMMENDATIONS (26)7.1.10/100/1000M M AGNETIC (26)7.2.R EFERENCE C LOCK (26)7.3.R ESISTORS (27)7.4.C APACITORS (27)7.5.F ERRITE B EAD (27)7.6.P OWER I NDUCTOR (27)7.7.RJ-45J ACK (27)8.SPECIAL NOTES (28)Integrated Gigabit Ethernet Controller for PCI Express Applicationsiv Track ID: JATR-2265-11 Rev. 1.3 List of FiguresF IGURE 1.S IGNAL T RACE A NGLES (4)F IGURE 2.S IGNAL &T RACE R OUTING (6)F IGURE 3.G ROUND P LANE L AYOUT-1 (8)F IGURE 4.G ROUND P LANE L AYOUT-2 (8)F IGURE 5.G ROUND P LANE S EPARATION (9)F IGURE 6.D ECOUPLED C APACITOR E XAMPLE (10)F IGURE 7.P OWER P LANE (10)F IGURE 8.P OWER S OURCE D ISTRIBUTION (11)F IGURE 9.S IGNAL 1P LANE L AYOUT (T OP L AYER) (12)F IGURE 10.G ROUND P LANE L AYOUT (L AYER 2) (12)F IGURE 11.P OWER P LANE L AYOUT (L AYER 3) (13)F IGURE 12.S IGNAL 2P LANE L AYOUT (B OTTOM L AYER) (13)F IGURE 13.C ENTER-T APPING (14)F IGURE 14.S EPARATE T RANSFORMER (14)F IGURE 15.I NPUT V OLTAGE O VERSHOOT <4V(G OOD) (16)F IGURE 16.I NPUT V OLTAGE O VERSHOOT >4V(B AD) (16)F IGURE 17.C ERAMIC 10µF0603(X5R)(G OOD) (17)F IGURE 18.L=GLK2510P-2R2M,C=C ERAMIC 4.7µF0805X5R TDK(R IPPLE 12.4M V) (17)F IGURE 19.L=GLK2510P-2R2M,C=C ERAMIC 10µF0603X5R YAGEO(R IPPLE 13.2M V) (18)F IGURE 20.L=GLK2510P-2R2M,C=C ERAMIC 22µF1206X5R WISIN(R IPPLE 10.4M V) (18)F IGURE 21.L=GLK2510P-4R7M,C=C ERAMIC 4.7µF0805X5R TDK(R IPPLE 12M V) (19)F IGURE 22.L=GLK2510P-4R7M,C=C ERAMIC 10µF0603X5R YAGEO(R IPPLE 11.2M V) (19)F IGURE 23.L=GLK2510P-4R7M,C=C ERAMIC 22µF1206X5R WISIN(R IPPLE 9.2M V) (20)F IGURE 24.L=GTSD32P-2R2M,C=C ERAMIC 4.7µF0805X5R TDK(R IPPLE 9.2M V) (20)F IGURE 25.C ERAMIC 10µF(Y5V)(B AD) (21)F IGURE 26.E LECTROLYTIC 100µF(R IPPLE T OO H IGH) (21)F IGURE 27.GTSD32P-2R2M(G OOD) (22)F IGURE 28.1µH B EAD (B AD) (22)F IGURE 29.S WITCHING R EGULATOR E FFICIENCY M EASUREMENT C HECKPOINT (24)F IGURE 30.P OWER S EQUENCE (25)Integrated Gigabit Ethernet Controller for PCI Express Applications 1Track ID: JATR-2265-11 Rev. 1.31.IntroductionThe Realtek RTL8111E-VB-GR Gigabit Ethernet controller combines a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the RTL8111E-VB-GR offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection and Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds.The RTL8111E supports the PCI Express 1.1 bus interface for host communications with power management, and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-detect function, and will auto-configure related bits of the PCI power management registers in PCI configuration space. The RTL8111E features embedded One-Time-Programmable (OTP) memory to replace the external EEPROM (93C46/93C56/93C66).Advanced Configuration Power management Interface (ACPI)—power management for modern operating systems that are capable of Operating System-directed Power Management (OSPM)—is supported to achieve the most efficient power management possible. PCI MSI (Message Signaled Interrupt) and MSI-X are also supported.In addition to the ACPI feature, remote wake-up (including AMD Magic Packet™ and Microsoft®Wake-up frame) is supported in both ACPI and APM (Advanced Power Management) environments. To support WOL from a deep power down state (e.g., D3cold, i.e., main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the RTL8111E.The RTL8111E is fully compliant with Microsoft® NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP) Checksum and Segmentation Task-offload (Large send and Giant send) features, and supports IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server.The RTL8111E supports Receive Side Scaling (RSS) to hash incoming TCP connections and load-balance received data processing across multiple CPUs. RSS improves the number of transactions per second and number of connections per second, for increased network throughput.Integrated Gigabit Ethernet Controller for PCI Express Applications 2Track ID: JATR-2265-11 Rev. 1.3Alert Standard Format (ASF 2.0) is also supported to provide system manageability in OS-absent environments. The ASF defines remote control and alerting interfaces that serve managed PCs in OS-absent states. With the ASF capability, we are able to minimize on-site I/T maintenance, to improve system availability, and also to control power management remotely.The RTL8111E supports IEEE 802.3az Draft 2, also known as Energy Efficient Ethernet (EEE). IEEE 802.3az operates with the IEEE 802.3 Media Access Control (MAC) Sublayer to support operation in Low Power Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on both sides of the link to save power.The device also features inter-connect PCI Express technology. PCI Express is a high-bandwidth, low-pin-count, serial, interconnect technology that offers significant improvements in performance over conventional PCI and also maintains software compatibility with existing PCI infrastructure.The RTL8111E is suitable for multiple market segments and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications.Integrated Gigabit Ethernet Controller for PCI Express Applications 3Track ID: JATR-2265-11 Rev. 1.32.Design and LayoutSystem designers should follow basic rules in layout and placement, general termination, power supply filtering, plane partitioning, and EMI reduction in order to optimize designs that use the RTL8111E. Following these rules will greatly contribute to a properly functioning hardware system.This guide has the following goals:(1) Create a low-noise, power-stable environment.(2) Reduce the degree of EMI/EMC and their influence on the RTL8111E.(3) Simplify the task of routing signal traces.2.1.General GuidelinesIn order to achieve maximum performance using the RTL8111E, good design practices are required throughout the process. The following are some recommendations for implementing a high-performance system.•Provide a good power source, minimizing noise from switching power supply circuits (<100mV peak-to-peak)•Verify that critical components such as the clock source and transformer meet application requirements •Keep power and ground noise levels below 100mV peak-to-peak•Use bulk capacitors (4.7µF~10µF) between the power and ground planes•Use 0.1µF de-coupling capacitors to reduce high-frequency noise on the power and ground planes •Keep de-coupling capacitors close to the RTL8111E (within 200 mil)•Provide termination on all high-speed switching signals•Use a smaller package for the capacitor to reduce the package inductanceIntegrated Gigabit Ethernet Controller for PCI Express Applications 4Track ID: JATR-2265-11 Rev. 1.3Use the following signal integrity techniques to reduce crosstalk.•Shorter parallel routes•Thinner dielectrics•Proper termination•Provide a solid ground planePCI Express TX/RX differential pairs should comply with the following requirements:•Differential Return Loss ≥ 10dB (measured within a 50MHz~1.25GHz range)•Common Mode Return Loss ≥ 6dB (measured within a 50MHz~1.25GHz range)•Differential Impedance should be limited from 80 to 120ohms (100ohm recommended)•Only PCB traces are allowed for signal routing (do not use flat/shielded cable)2.2.Differential Signal Layout Guidelines•Keep differential pairs as close as possible and route both traces as identically as possible, meaning width, length, and location•Avoid vias and layer changes if possible•Keep transmit and receive pairs away from each other. Run orthogonally or separate by a ground plane if possible•0.1µF common mode noise filter capacitors should be placed near the RTL8111E chip•Ninety-degree trace angles should be avoided. We recommend that the traces turn at 45° angles as shown in Figure 1. Sharp edges may add unexpected parasitic effects into the circuitry. Reducing the trace length will reduce trace inductance during quick energy burstsA BA BBetterBadFigure 1. Signal Trace AnglesIntegrated Gigabit Ethernet Controller for PCI Express Applications 5Track ID: JATR-2265-11 Rev. 1.32.3.Placing the RTL8111E•The RTL8111E should be placed as close as possible to the magnetics2.4.Magnetics•The 10/100/1000M magnetics should be placed as close as possible to the RJ-45 connector•The magnetics device, or devices with magnetic fields, should be separated and mounted at 90 degrees to each other2.5.Crystal•The Crystal should be placed away from I/O ports, important or high frequency signal traces (Tx, Rx, power), magnetics, and board edges•The outer shield of the Crystal requires good grounding to avoid induction of EMC/EMI•The retaining straps of the OSC, if any, need good grounding2.6.Ferrite Beads and De-Coupling CapacitorsEach PCB design has its unique noise coupling behavior. Ferrite beads are used to suppress power noise. System designers are suggested to provide the option to replace the ferrite beads with 0Ω resistors. Decoupling capacitors should be placed as close as possible to the power pins, such that the distance from the IC power pin to the capacitor is less than 200 mils.Integrated Gigabit Ethernet Controller for PCI Express Applications 6 Track ID: JATR-2265-11 Rev. 1.33. Signal and Trace RoutingNoise, ringing, and data lines should be controlled with proper termination. Power supply pins should be protected by proper filtering techniques. Good routing of traces can reduce propagation delay, crosstalk, and high frequency noise. It will also improve the signal quality to the receiver and reduce transmit signal losses.• Traces routed from the RTL8111E to the 10/100/1000M magnetics, and to the RJ-45 connector, should be as short as possible. The 12cm maximum length between the RTL8111E and magnetics is achievable only when there is no interference. It is also very important to keep all four differential pair signal traces(MDI0+/-, MDI1+/-, MDI2+/-, MDI3+/-) equal in length. The two traces of each pair should be placed close to each other (D1) since they are differential pair signals to each other and provide a strong canceling effect on noise. The width of D1 should be calculated to have 100Ω impedance (Figure 2).Figure 2. Signal & Trace Routing• We suggest that there should be more than 30 mil spacing between different differential pairs tominimize crosstalk coupled from other pairs (D2 in Figure 2). In addition, Ground Plane shielding can be used to separate all four signal pairs. However, a good layout should avoid the following situations: Intersection of any two pairs of signal tracesIntersection of the two signal traces of the same differential pair• To minimize impedance mismatch, we recommend not to use vias on the four differential pairsIntegrated Gigabit Ethernet Controller for PCI Express Applications 7Track ID: JATR-2265-11 Rev. 1.3•Ninety-degree trace corners should be avoided. We recommend that the traces turn at 45° angles as shown in Figure 1 , page 4. Sharp edges may add unexpected parasitic effects into the circuitry.Reducing the trace length will reduce trace inductance during quick energy bursts.•The trace length and the ratio of trace width to trace height above the ground planes should be carefully considered. If running power on the trace is unavoidable, the trace width should be wider than 60 mils, and properly filtered to minimize power noise effects. The clock and other high speed signal traces should be as short and wide as possible (compared to normal digital traces). It is better to have a ground plane under these traces. If possible, use a ground plane to surround them.•It is important to separate Digital Signals (e.g., BOOTROM, Flash, EEPROM) from Analog Signals(e.g., MDI0+/-, MDI1+/-, MDI2+/-, and MDI3+/-, RSET) in order to avoid interference. If it isunavoidable to cross digital signals with analog power, do it at 90° angles.•The power into the RTL8111E digital power pins can be improved with de-coupling capacitors. The Power signal traces (de-coupling cap traces, power traces, grounding traces) should be as short and wide as possible. The vias of the de-coupling capacitor should be large enough in diameter. All analog power pins on the RTL8111E need to be de-coupled with a capacitor. The de-coupling capacitors should be placed as close to the IC as possible and the traces should be kept short.•The PCI-Express signal differential pairs should be 5mils wide, with a spacing of 7mils between them (REFCLK+ & REFCLK-, HSOP & HSON, HSIP & HSIN). The length difference of the signals in a pair should not exceed 5 mils. For example, if HSON is 900 mils and HSOP is 890mils, it may result in data transmit error.Integrated Gigabit Ethernet Controller for PCI Express Applications 8Track ID: JATR-2265-11 Rev. 1.34. Ground and Power Plane Layout4.1. Ground Plane LayoutThere is only one ground plane for analog power (AVDD33), digital power (DVDD33, DVDD10) and PCI-Express power (EVDD10). In the center of the IC, there is an Exposed Pad (EPAD) ground. The size of the center EPAD ground is 4mm x 4mm. The PCB layout requires 9 vias to connect the EPAD to the lower layer ground plane (see Figure 3).Isolated separation between Analog and Digital Ground domains is not recommended since bad ground plane partitioning could cause serious EMI emissions and degrade analog performance due to bouncing noise.Whether there is sufficient space on the PCB for an isolated separation layout must also be taken into consideration. The key point of such a layout is to keep the analog GND return path approximately equal to the common GND. If the system designer is not comfortable doing this, just place a single ground plane with no partition.Figure 3. Ground Plane Layout-1To achieve better ground plane performance, it is recommended to keep the plane as large and uniform as possible. Figure 4 illustrates a not so good (left) and a good ground plane layout (right).Figure 4. Ground Plane Layout-2Integrated Gigabit Ethernet Controller for PCI Express Applications 9Track ID: JATR-2265-11 Rev. 1.3The plane area beneath the magnetics should be left void. The void area is to keep transformer inducednoise away from the power and system ground planes (Figure 5).Figure 5. Ground Plane SeparationThe Chassis Ground as shown in Figure 5 is known as an ‘Isolated Ground’. It connects directly to the RJ-45 connector (fully shielded is recommended). In addition, a 2kV (3kV recommended) high voltage capability capacitor is needed to connect to this chassis ground for ESD protection.It is also important to keep the gap (D in Figure 5) between Chassis GND and System GND wider than 60 mils for better isolation.Integrated Gigabit Ethernet Controller for PCI Express Applications 10Track ID: JATR-2265-11 Rev. 1.34.2. Power Plane LayoutThe digital power plane should be separated from analog areas, which are extremely sensitive to noise. It is recommended to use at least a 4-layer PCB.A low-pass filter combination of a ferrite bead and capacitors should be used to provide a clean, filtered power plane for analog consideration. It is important to avoid using unnecessary power traces to the RTL8111E. If it is unavoidable, try to keep these traces as short and wide as possible and make good use of vias.(a) Decoupled Capacitor ExampleFigure 6. Decoupled Capacitor Example(b) Use a Ferrite Bead or 0 ohm Resistor to Connect Digital and Analog PowerFigure 7. Power PlaneIntegrated Gigabit Ethernet Controller for PCI Express Applications 11Track ID: JATR-2265-11 Rev. 1.3To further improve the performance of the power plane, try to keep the contact area between the RTL8111EVDD pins and power plane as large as possible rather than using small narrow traces (Figure 8).Figure 8. Power Source Distribution• Keep power noise levels below 100mV peak-to-peak in gigabit mode• All 3.3V/1.05V decoupling capacitors shown in the reference schematic should be used in all designs • Keep the analog power (1.05V) plane as whole and as large as possible4.3. Four-Layer Board Plane Layout1. Signal 1 (top layer)2. GND3. Power4. Signal 2 (bottom)Integrated Gigabit Ethernet Controller for PCI Express Applications12Track ID: JATR-2265-11 Rev. 1.34.3.1. Signal 1 Plane Layout (Top Layer)Figure 9. Signal 1 Plane Layout (Top Layer)4.3.2. Ground Plane Layout (Layer 2)Figure 10. Ground Plane Layout (Layer 2)Integrated Gigabit Ethernet Controller for PCI Express Applications13 Track ID: JATR-2265-11 Rev. 1.34.3.3. Power Plane Layout (Layer 3)Figure 11. Power Plane Layout (Layer 3)4.3.4. Signal 2 Plane Layout (Bottom Layer)Figure 12. Signal 2 Plane Layout (Bottom Layer)Integrated Gigabit Ethernet Controller for PCI Express Applications 14Track ID: JATR-2265-11 Rev. 1.35. Center-Tapping•A center-tapped fine-tuned capacitor (C1 Value: 0.4µF~50pF) can improve EMI for single tone noise. The capacitor default is NC • Changing the R1 resistor to a capacitor (Value: 0.4µF~50pF), and fine-tuning the connection to GND can improve EMI for single tone noise. The resistor default is 0 ohmFigure 13. Center-Tapping• When using a separate transformer, the center-tap MUST be aggregated (pins 10, 7, 4, 1) (C26 Value: 0.4µF~50pF) (see Figure 14)Figure 14. Separate TransformerIntegrated Gigabit Ethernet Controller for PCI Express Applications 15Track ID: JATR-2265-11 Rev. 1.36.Switching RegulatorThe RTL8111E incorporates a state-of-the-art switching regulator that requires a well-designed PCB layout in order to achieve good power efficiency and lower the output voltage ripple and input overshoot. Note that the switching regulator 1.05V output pin (REGOUT) must be connected only to DVDD10, AVDD10, and EVDD10 (do not provide this power source to other devices).6.1.Inductor and Capacitor Parts ListTable 1. Inductor and Capacitor Parts ListInductor Type Inductance ESR at 1MHz(mΩ) Max IDC(mA)Variation Output Ripple (mV)GLK2510P-2R2M 2.2µH 791 1000 ≤ 20% (See Figure 18, Figure 19) GLK2510P-4R7M 4.7µH 1745 750 ≤ 20% (See Figure 21, Figure 22) GTSD32P-2R2M 2.2µH 332 1500 ≤ 20% (See Figure 24)Note 1: The ESR is equivalent to RDC or DCR. Lower ESR inductor values will promote a higher efficiency switching regulator.Note 2: The power inductor used by the switching regulator must be able to withstand 600mA of current.Note 3: Typically, if the power inductor’s ESR at 1MHz is below 0.8Ω, the switching regulator efficiency will be above 75%. However the actual switching regulator efficiency should be measured according to the method described in section 6.3 Efficiency Measurement, page 23.Capacitor Type Capacitance ESR at 1MHz (mΩ) Output Ripple (mV)4.7µF 0805 X5R TDK 4.838 40.28 (See Figure 18, Figure 21) 10µF 0603 X5R YAGEO 11.956 58.29 (See Figure 19, Figure 22) 22µF 1206 X5R WISIN 22µF 40.72 (See Figure 20, Figure 23) Note 1: Capacitors (Cin1 & Cin2) are must be ceramic due to their low ESR value. Lower ESR values will yield lower output voltage ripple.Note 2: Only the following combinations of power inductor and capacitor can be used with the RTL8111E.Inductor: 2.2µH, 4.7µH.Capacitor: 4.7µF, 10µF, 22µF.Integrated Gigabit Ethernet Controller for PCI Express Applications 16Track ID: JATR-2265-11 Rev. 1.36.2. Measurement CriteriaIn order for the switching regulator to operate properly, the input and output voltage measurement criteria must be met. From the input side, the voltage overshoot cannot exceed 4V; otherwise the chip may be damaged. Note that the voltage signal must be measured directly at the VDDREG pin, not at the capacitor. In order to reduce the input voltage overshoot, the Cin1 and Cin2 must be placed close to the VDDREG pin. The following figures show what a good input voltage and a bad one look like.Figure 15. Input Voltage Overshoot <4V (Good)Figure 16. Input Voltage Overshoot >4V (Bad)Integrated Gigabit Ethernet Controller for PCI Express Applications 17Track ID: JATR-2265-11 Rev. 1.3From the output side measured at the REGOUT pin, the voltage ripple must be within100mV peak-to-peak. Choosing different types and values of input and output capacitor (Cin1, Cin2; Cout1, Cout2) and power inductor (Lx) will seriously affect the efficiency and output voltage ripple of switching regulators. The following figures show the effects of different types of capacitors on the switching regulator’s output voltage.The blue square wave signal (top row) is measured at the output of the REGOUT pin before the power inductor (Lx). The yellow signal (second row) is measured after the power inductor (Lx), and shows there is a voltage ripple. The green signal (lower row) is the current. Data in the following figures was measured at gigabit speed.Figure 17. Ceramic 10µF 0603 (X5R) (Good)Figure 18. L=GLK2510P-2R2M, C=Ceramic 4.7µF 0805 X5R TDK (Ripple 12.4mV)Integrated Gigabit Ethernet Controller for PCI Express Applications18 Track ID: JATR-2265-11 Rev. 1.3Figure 19. L=GLK2510P-2R2M, C=Ceramic 10µF 0603 X5R YAGEO (Ripple 13.2mV)Figure 20. L=GLK2510P-2R2M, C=Ceramic 22µF 1206 X5R WISIN (Ripple 10.4mV)Integrated Gigabit Ethernet Controller for PCI Express Applications19 Track ID: JATR-2265-11 Rev. 1.3Figure 21. L=GLK2510P-4R7M, C=Ceramic 4.7µF 0805 X5R TDK (Ripple 12mV)Figure 22. L=GLK2510P-4R7M, C=Ceramic 10µF 0603 X5R YAGEO (Ripple 11.2mV)Integrated Gigabit Ethernet Controller for PCI Express Applications20 Track ID: JATR-2265-11 Rev. 1.3Figure 23. L=GLK2510P-4R7M, C=Ceramic 22µF 1206 X5R WISIN (Ripple 9.2mV)Figure 24. L=GTSD32P-2R2M, C=Ceramic 4.7µF 0805 X5R TDK (Ripple 9.2mV)Integrated Gigabit Ethernet Controller for PCI Express Applications 21 Track ID: JATR-2265-11 Rev. 1.3Figure 25. Ceramic 10µF (Y5V) (Bad)A ceramic 10µF (X5R) will have a lower voltage ripple compared to an electrolytic 100µF. The key to choosing a proper output capacitor is to choose the lowest ESR to reduce the output voltage ripple. Choosing a ceramic 10µF (Y5V) in this case will cause malfunction of the switching regulator. Placing several Electrolytic capacitors in parallel will help lower the output voltage ripple.Figure 26. Electrolytic 100µF (Ripple Too High)Integrated Gigabit Ethernet Controller for PCI Express Applications 22Track ID: JATR-2265-11 Rev. 1.3The following figures show how different inductors affect the REGOUT pin output waveform. The typical waveform should look like Figure 27, which has a square waveform with a dip at the falling edge and the rising edge. If the inductor is not carefully chosen, the waveform may look like Figure 28, where the waveform looks like a distorted square. This will cause insufficient current supply and will undermine the stability of the system at gigabit speed. Data in the following figures was measured at gigabit speed.Figure 27. GTSD32P-2R2M (Good)Figure 28. 1µH Bead (Bad)Integrated Gigabit Ethernet Controller for PCI Express Applications 23Track ID: JATR-2265-11 Rev. 1.36.3.Efficiency MeasurementThe efficiency of the switching regulator is designed to be above 75% in gigabit traffic mode. It is very important to choose a suitable inductor before Gerber certification, as the Inductor ESR value will affect the efficiency of the switching regulator. An inductor with a lower ESR value will result in a higher efficiency switching regulator.The efficiency of the switching regulator is easily measured using the following method.Figure 29, page 24, shows two checkpoints, checkpoint A (CP_A) and checkpoint B (CP_B). The switching regulator input current (Icpa) should be measured at CP_A, and the switching regulator output current (Icpb) should be measured at CP_B.To determine efficiency, apply the following formula:Efficiency = Vcpb*Icpb / Vcpa*IcpaWhere Vcpb is 1.05V; Vcpa is 3.3V. The measurements should be performed in gigabit traffic mode.For example: The inductor used in the evaluation board is a GOTREND GTSD32-4R7M:•The ESR value @ 1MHz is approximately 0.712ohm•The measured Icpa is 101mA at CP_A•The measured Icpb is 263mA at CP_BThese values are measured in gigabit traffic mode, so the efficiency of the GOTREND GTSD32-4R7M can be calculated as follows:Efficiency = (1.05V*263mA) / (3.3V*101mA) = 0.823 = 82.3%.We strongly recommend that when choosing an inductor for the switching regulator, the efficiency should be measured, and that the inductor should yield an efficiency rating higher than 75%. If the efficiency does not meet this requirement, there may be risk to the switching regulator reliability in the long run.。
RealtekWLAN中芯片RTL8191资料RTL8191RE单芯片电机及电子学工程师联合会的802.11b/g/n 1T2R WLAN 控制器与PCI Express介面一般描述瑞昱RTL8191RE是一个高度集成的单芯片MIMO（多输入，多出）无线局域网（WLAN）的无线高吞吐量的802.11n规范的解决方案。
它在单一芯片上结合了MAC，基带一个1T2R能力和RF。
该RTL8191RE提供了一个高吞吐量性能无线客户端完整的解决方案。
基带实现的RTL8191RE 1多输入多输出（MIMO）正交频分复用（OFDM）的发射和接收路径2（1T2R），并符合IEEE 802.11n规范兼容。
其功能包括一个空间流的传输，最多两个空间流接待，短期保护间隔（GI）的对400ns，空间蔓延，超过20兆赫和40兆赫带宽的传输。
在接收端，扩展范围和良好的最小灵敏度是由具有接收分集天线实现高达2。
对于旧的相容性，直接序列扩频（DSSS），补码键控（CCK）和OFDM基带处理包括支持所有IEEE 802.11b和802.11g的数据速率。
差分相移键控调制方式，与加扰和DQPSK的DBPSK 能力数据，都可以一起补码键控提供长期或短期序言1，2，5.5的数据传输速率和11Mbps。
高速的FFT / IFFT路径，用的BPSK，QPSK调制，16QAM 的结合，和64QAM调制的子载波的个人和速率兼容删除卷积编码与1 / 2，2 / 3，3 / 4，和5 / 6速率编码，提供了54 Mbps的最大数据传输速率和300为IEEE 802.11g和802.11n的MIMO OFDM技术分别Mbps的。
该RTL8191RE建立在增强信号探测器，频域自适应均衡器和一个软判决Viterbi译码器，以减轻在多个接收的严重的多径效应和相互干扰流。
为了更好的检测质量，收到最大比率，结合多样性（湄公河委员会）申请最多2接收路径的贯彻落实。
亿佰特WiFi模块选型指南及WiFi模块物联网应用案例成都亿百特电子科技有限公司WiFi类模组分别采用UART 、SDIO、USB三种不同接口，内置IEEE802.11协议栈以及 TCP/IP 协议栈，能够实现用户串口数据到无线网络之间的转换。
1.模组分类选型指导说明1.1 E103系列模组选型指导1.1.1 E103系列模组双频模组E103系列双频模组芯片方案分别采用TI第三代Wi-Fi芯片CC3235S和瑞昱半导体的RTL8811CU-CU-CG而进行研发。
符合IEEE802.11 a/b/g/n标准和IEEE 802.11b/g/n/ac标准，具有丰富的接口和强大的处理器，可为高吞吐量性能的集成无线WLAN设备提供了一种E103-W06 E103-RTL8811CU1.1.2 E103系列WiFi+蓝牙双模模组E103系列WiFi+蓝牙双模模组内置方案较为多元化，因此符合的标准协议也较为丰富，目前拥有蓝牙 5.4/5.2/5.1/5.0+WiFi6/WiFi4等不同标准协议规范类产品，且工作在1.1.3 E103系列超低功耗WiFi模组E103系列低功耗WiFi模组工作在2.4~2.4835GHz 频段，符合IEEE 802.11b/g/n协议标准。
模块集成了透传功能，即拿即用，支持串口 AT 指令集用户通过串口即可使用网络访问的功能，广泛应用于穿戴设备、家庭自动化、家庭安防、个人保健、智能家电、配饰与遥控器、1.1.4 E103系列WiFi路由模组E103系列WiFi路由模组目前拥有两款产品，分别为E103-W20（7688）和 E103-W20（7628）。
该类模块是基于联发科 MT7688AN及 MT7628AN为核心的低成本低功耗的物联网模块。
模块引出了 MT7688AN /MT7628AN的所有接口，支持 OpenWrt 操作系统及自定义开发，具有丰富的接口和强大的处理器，可以广泛的应用于智能设备或云服务应用等，并可以自由进行1.1.5 E103系列通用型模组E103系列通用型模组不仅具有丰富的外设接口，还拥有强大的神经网络运算能力和信号处理能力，成本低，且适用于AloT 领域的多种应用场景，例如唤醒词检测和语音命令识别、E103-RTL8189 E103-W05 E103-W01-IPX E103-W01 E103-W101.1.6 E103系列WiFi mesh模组在 EBYTE 的方案中，我们公司支持WIFI Mesh支持有路由组网和无路由组网的模块为E103-W07，E103-W07是一套建立在Wi-Fi协议之上的网络协议。
rtl8211f硬件设计rtl8211f硬件设计【简介】rtl8211f是Realtek（瑞昱）公司推出的一款集成电路芯片，主要用于局域网（LAN）接口的物理层连接。
它提供了高速、高性能的以太网连接解决方案，适用于各种网络设备，如计算机、路由器、交换机等。
【硬件设计】rtl8211f的硬件设计包括电源设计、物理层接口设计和其他外设设计等方面。
一、电源设计rtl8211f的电源设计应符合以下要求：1. 稳定性：为确保芯片正常工作，电源必须提供稳定的直流电压。
2. 电源电压：rtl8211f的推荐电源电压为3.3V。
3. 电流需求：根据实际使用情况，计算出芯片的平均和峰值电流需求，合理设计电源的容量。
4. 滤波和稳压：在电源输入端和芯片之间添加适当的电源滤波电路和稳压电路，以减小电源噪声的影响。
二、物理层接口设计rtl8211f的物理层接口设计应考虑以下因素：1. 电气特性：确保与其他设备的电气接口兼容。
2. 接口标准：rtl8211f支持多种以太网标准，如10BASE-T、100BASE-TX和1000BASE-T。
根据实际需求选择适当的标准接口。
3. 连接器：根据电气接口标准选择合适的接口连接器，如RJ-45。
确保连接器与芯片的引脚对应正确。
4. 信号完整性：考虑信号线的长度和布线方式，确保信号的完整性和稳定性。
可以采用阻抗匹配、差分信号传输等方法提高信号质量。
5. 反射和串扰：对于高速传输的信号线，要防止信号反射和串扰。
可以采用终端电阻、屏蔽和布线分离等方法减小这些影响。
三、其他外设设计rtl8211f作为一个局域网接口芯片，还需要与其他外设进行连接，如MAC控制器和PHY控制器。
1. MAC控制器接口：rtl8211f的MAC控制器通常通过GMII（Gigabit Media Independent Interface）或RGMII（Reduced Gigabit Media Independent Interface）与PHY控制器连接。
RTL8168E集成千兆以太网控制器的PCI Express（W / SPI）概述瑞昱RTL8168E-VB-CG千兆以太网控制器结合三高速IEEE 802.3兼容的媒体存取控制器（MAC），一个三速以太网收发器，PCI Express总线控制器，和嵌入式存储器。
RTL8168E与国家的最先进的DSP技术和混合信号技术，提供高速传输CAT 5类UTP电缆或3类UTP电缆（10Mbps 的）。
如交叉检测和自动校正，极性校正，自适应均衡，串扰消除，回声消除，定时恢复，和纠错功能的实现在高速行驶时提供强大的传输和接收能力。
RTL8168E支持PCI Express 1.1总线接口的主机通信，电源管理，是符合IEEE 802.3u规范的10/100Mbps以太网和千兆以太网的IEEE 802.3ab规格。
它也支持辅助电源自动检测功能，并会自动配置PCI配置空间PCI电源管理寄存器中的相关位。
的的RTL8168E功能的嵌入式一次性可编程（OTP）存储器，更换外部EEPROM（93C46/93C56/93C66）。
RTL8168E支持连接一个64K字节的外部串行外设接口（SPI）闪存。
AT25F512接口允许RTL8168E读取和写入数据，外部SPI闪存设备，并提供64KB的串行编程的快闪记忆体。
高级配置电源管理接口（ACPI）的电源管理作业系统的电源管理（OSPM）的支持，以实现最有效的电源管理能力的现代操作系统是。
PCI MSI（消息信号中断），同时还支持MSI-X。
此外ACPI功能，远程唤醒（包括AMD Magic Packet和微软唤醒帧），支持ACPI和APM（高级电源管理）环境。
为了支持WOL从Deep Power Down状态（例如，D3cold，即主电源关闭，只有辅助的存在），辅助电源必须能够提供所需的功率为RTL8168E。
RTL8168E是完全兼容的：微软NDIS5，NDIS6（IPV4，IPv6，TCP，UDP）的校验和分割任务的卸载（大的发送和巨发送）功能，并支持IEEE 802 IP第2层优先级编码和IEEE 802.1Q 虚拟桥接的地方区域网络（VLAN）。
rtl8189es原理图rtl8189es是一款广泛用于无线网络通信的芯片。
它具有集成的WiFi功能，可用于各种设备，如智能手机、平板电脑、无线路由器等。
以下将详细介绍rtl8189es芯片的原理图，并对其主要组成部分进行解释。
1.数字部分数字部分包括主控芯片、接口电路和存储器等。
主控芯片是这个系统的核心，它负责整个WiFi系统的控制和处理。
它接收和发送WiFi信号，控制无线网络的连接和数据传输。
主控芯片通常是一个单片机或处理器，它可以根据不同的应用需求选择。
接口电路是主控芯片与其他电路之间的桥梁，它包括串行总线、并行总线、时钟信号线等。
这些接口提供数据传输、控制信号和时钟同步等功能。
接口电路的设计需要考虑到主控芯片和其他电路之间的电压和信号兼容性。
存储器用于存储各种配置参数、固件和数据。
它可以是Flash存储器、RAM、EEPROM等。
存储器的选择需要考虑存储容量、读写速度和功耗等因素。
2.射频部分射频部分是实现无线通信的关键部分，它包括天线、射频前端和收发器等。
天线负责接收和发送无线信号，它的设计需要考虑到天线增益、频率范围和尺寸等因素。
射频前端是一系列调制解调器和滤波器等电路，它负责对发送和接收的信号进行处理和调整。
收发器是射频前端的核心部分，它能够将数字信号转换为模拟信号，并进行射频调制和解调。
rtl8189es芯片的原理图还包括电源电路、时钟电路和地线电路等。
电源电路负责为整个系统提供稳定和可靠的电力供应。
时钟电路提供时钟信号，使各个电路能够在统一的时钟周期内同步工作。
地线电路负责连接各个电路的地线，以确保信号的可靠传输和抗干扰能力。
总结起来，rtl8189es的原理图包括数字部分和射频部分。
数字部分包括主控芯片、接口电路和存储器等，主要负责WiFi系统的控制和数据处理。
射频部分包括天线、射频前端和收发器等，负责无线信号的收发和调整。
电源电路、时钟电路和地线电路等提供稳定的电源、时钟和信号传输。
BL- LW085产品规格WLAN 11b/g/n Mini-PCEI模块Version: 1.11:简介:BL-LW085产品是一款标准的2T2R 300M MINI-PCIE接口无线模块,符合IEEE802.11B/G/N支持IEEE 802.11i安全协议,以及IEEE 802.11e标准服务质量,可以与其它符合该标准的无线设备互相联通,支持最新的64/128位WEP数据加密，支持WPA-PSK/WPA2-PSK,WPA/WPA2安全机制,无线传输速率高达300M,是普通11G产品的6倍,可适应不同的工作环境,使台式机或笔记本计算机用户以及其它需要实现无线联网的设备方便地接入无线网络.2:应用范围:笔记本电脑,MID,机顶盒,电子书,硬盘播放器,,PSP,无线ADSL等需要实现无线联网设备3:产品主要特性项目描述支持的协议和标准IEEE 802.11N, IEEE 802.11G IEEE 802.11B接口类型MINI-PCEI频率范围 2.4-2.484GHZ工作信道数14数据调制OFDM/DBPSK/DQPSK/CCK工作模式集中控制式(Infrastructure), 对等式(Ad-Hoc)传输速率300/135/54/48/36/24/18/12/9/6 /1M（自适应）展频技术DSSS（直接序列展频）灵敏度@PER 300/135M:-72dBm@10%PER54M:-74dBm@10%PER11M:-85dBm@8%PER6M: -88dBm@10%PER1M: -90dBm@8%PERRF功率15dBmLED指示状态指示灯传输距离室内最远100米，室外最远300米(因环境而异)支持操作系统XP/VISTA/LINUX/WINCE/WIN7工作电压DC 3.3V +-0.2V DC1.5V +-0.2V使用环境: 工作温度:-10ºC---60ºC存储温度:-40ºC---70ºC工作湿度:10%---90% RH不凝结存储湿度:5%---90% RH不凝结外型尺寸(L*W*H) 26.7MM*30MM*3.2MM 半卡设计主控型号Realtek:Rtl8192CE4:产品原理方框图5:测试参数描述测试项目TX发射功率EVM Freq Err RX接收灵敏度测试数据15.57dbm -30.6dbm +-10PPM -74dbm6:系统支持平台操作系统CPU架构驱动XP/VISTA/WIN7 X86 Platform 支持LINUX2.4/2.6 ARM, MIPSII 支持WINCE5.0/6.0 ARM ,MIPSII 支持7:产品图片正面正面：：反面:8:产品机构尺寸:。
rtl8111e工作原理
RTL8111E是一款由Realtek推出的千兆以太网控制器芯片，它
的工作原理涉及到网络通信、数据传输和硬件控制等方面。
首先，RTL8111E通过PCI Express接口与主板上的北桥或南桥芯片相连，
从而与主机系统进行通信。
它接收来自主机的数据包，并通过内部
的DMA控制器将数据包传输到内部缓冲区进行处理。
在数据包处理
过程中，RTL8111E会进行CRC校验、数据包分类和地址过滤等操作，以确保数据的完整性和安全性。
一旦数据包处理完毕，RTL8111E会将数据包通过PHY芯片转换
成电信号，然后通过网线传输到网络中。
在接收数据时，它会监听
网络中的数据流量，并将接收到的数据包传输到内部缓冲区，然后
通过PCI Express接口传输给主机系统进行处理。
同时，RTL8111E
还负责处理网络中的各种控制信息，包括链路状态、速度协商、流
量控制等，以确保网络连接的稳定和可靠性。
此外，RTL8111E还支持诸如Wake-on-LAN、流量优先级调度、VLAN标记和节能模式等特性，以满足不同应用场景下的需求。
总的
来说，RTL8111E的工作原理涉及到数据处理、数据传输和网络控制
等多个方面，它通过与主机系统和网络的交互，实现了高速、稳定的网络连接。
rtl8111f芯片工作原理rtl8111f是一款高性能的以太网芯片，广泛应用于计算机、网络设备、工业控制等领域。
本文将介绍rtl8111f芯片的工作原理，包括其硬件架构、数据传输过程、寄存器配置以及与软件接口的交互。
一、硬件架构rtl8111f芯片是一款双端口内存控制器芯片，支持10/100/1000Mbps三种传输速率。
芯片内部包含两个独立的MAC引擎和缓存器，每个引擎都有独立的传输接口和数据总线，可以实现并行数据传输，提高数据传输速度。
此外，芯片还包含PHY（物理层）接口，用于与物理介质进行数据交互。
二、数据传输过程rtl8111f芯片的数据传输过程包括物理层、数据链路层和传输层三个层次。
在物理层，芯片通过PHY接口与物理介质进行数据交互，支持以太网标准信号格式。
在数据链路层，芯片对数据进行封装和解封装，并进行错误检测和流量控制。
在传输层，芯片将数据发送到网络中，并接收来自网络的数据包。
在数据传输过程中，芯片的两个独立端口可以同时进行数据传输，实现并行数据传输。
当一个端口接收数据时，另一个端口可以发送数据，从而提高数据传输效率。
同时，芯片还支持半双工和全双工两种通信模式，可以根据实际需求进行选择。
三、寄存器配置rtl8111f芯片的寄存器包括系统寄存器、接口寄存器、控制寄存器、状态寄存器等。
系统寄存器用于配置芯片的基本参数，如工作模式、传输速率等。
接口寄存器用于控制芯片与物理介质的交互，如发送和接收数据等。
控制寄存器和状态寄存器用于获取芯片的工作状态和反馈信息，以便进行故障排查和调试。
四、与软件接口的交互rtl8111f芯片提供了丰富的API接口，用于与软件进行交互。
软件可以通过API接口向芯片发送命令和参数，配置芯片的工作状态和传输速率等。
同时，软件也可以通过API接口获取芯片的工作状态和反馈信息，以便进行故障排查和调试。
此外，软件还可以通过API接口向芯片发送数据包，实现数据的发送和接收。
