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Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.SummaryThis application note describes the DDR2 SDRAM physical layer design using thedirect-clocking technique in a Virtex TM -4 device. The direct-clocking technique utilizes some of the architectural features unique to the Virtex-4 family, for example, the 64-tap absolute delay line provided in each I/O block (IOB).IntroductionThe DDR2 SDRAM memory interface is a source-synchronous interface in which the data and clock/strobe that the external memory device transmits is edge aligned. T o capture this transmitted data in the Virtex-4 device, either the clock/strobe or the data is delayed.In the direct-clocking technique of data capture, each data bit is delayed and is center aligned with respect to the internal FPGA clock. The internal FPGA clock captures the transmitted data. Then each data bit is calibrated on a per-bit basis to the internal FPGA clock with a training pattern that the memory sends. The clock/strobe that the memory transmits is not used in any way by the memory controller. As a result, there are no restrictions on the number of data bits associated with a strobe. Because the strobe does not need to be distributed to the associated data bits, no additional clocking resources are required.Each data line is routed through an IDELAY primitive. A calibration module positions the data eye such that it is centered with respect to the FPGA clock. In addition to accurately positioning the data eye of each data bit in a region that has maximum margin, this technique significantly reduces package skew, clock tree skew, and PCB layout skew. The design and implementation details of the direct-clocking scheme are explained in the following sections.This application note describes the physical layer of the DDR2 SDRAM memory design. The controller design is described in XAPP702: DDR2 Controller Using Virtex-4 Devices .Calibration ProcedureThe calibration procedure begins by executing a write to memory and loading a training pattern in the memory. The training pattern is a continuously oscillating pattern (…0101…). At the start of calibration, the controller performs a continuous read from memory. As a result, acontinuously oscillating pattern is present on all data channels during the calibration procedure.Application Note: Virtex-4 FamilyFigure1 shows a timing diagram of the typical case of the calibration procedure.Figure 1: Timing Diagram Illustrating Typical Case of Calibration ProcedureIn the timing diagram for the typical case shown in Figure1, the FPGA clock edge falls somewhere within the read data valid window. In this case, the controller increments the IDELAY of the read data channel until an edge is found. The edge detection mechanism is executed by storing the initial value of the read data channel and periodically comparing the current sampling value of the channel. An edge is detected when the current sampling value of the channel does not match the stored value.When the edge is found, the read data channel IDELAY is decremented by an amount equal to a quarter clock period of the bit time. This amount is a fixed parameter depending on the operating frequency of the memory controller.Figure2 shows a timing diagram of a clock edge-straddle case, which is one of two corner cases presented in this document. The clock edge-straddle case occurs when edges of two or more read data bits straddle a clock edge.Figure 2: Timing Diagram Illustrating Clock Edge-Straddle CaseAs shown in Figure2, if no corrective action is taken and the calibration algorithm is allowed to proceed, the result is the read data channels that straddle the clock edge develop one bit time of skew with respect to each other. Because the training pattern is an oscillating pattern, the controller detects an edge straddle condition by checking that all the read data channels are either all zeroes or all ones.Under real-world conditions, the data and clock edges jitter in time, and the controller monitors for the straddle condition for 10clock cycles. If a straddle condition is detected, the controller increments the IDELAY modules of all the read data bits until all data bits clear the clock edge. After all data bits clear the clock edge, then the calibration procedure proceeds as in the typical case.Figure3 shows a timing diagram of an edge-alignment case, which is a second corner case. The edge-alignment case occurs when the clock and read data edges are edge aligned.Figure 3: Timing Diagram Illustrating Edge Alignment CaseAs shown in Figure3, jitter on the clock and read data edges can disrupt the calibration algorithm. The jitter condition is detected using the same mechanism as the clockedge-straddle case. To get out of edge alignment, all data bits are incremented by 2taps. After all data bits clear the clock edge, then the calibration proceeds as in the typical case.At the lower extremes of the operating frequency range (that is,150MHz and below), the calibration algorithm can use more than the 64-tap limit provided by the IDELAY module. If the IDELAY module is incremented beyond the 64-tap limit, the IDELAY module rolls over to T ap0. To prevent this rollover from occurring, a tap counter in the calibration module tracks the number of taps incremented and stops the increment when the tap count reaches 55taps. At this point, the calibration module decrements by a quarter clock period.The state transition diagram in Figure4 shows a summary of the calibration algorithm.Figure 4: State Transition Diagram of the Calibration Algorithm ProcedureCalibrationFigure5 shows a block diagram of the implementation of the calibration logic. LogicImplementation ArrayFigure 5: Calibration Logic Block DiagramAs shown in Figure5, the key feature used to implement the calibration procedure is the 64-tap delay line encapsulated in the IDELAY primitive. Each tap in the IDELAY primitive is calibrated to 75ps and is independent of process, temperature, and voltage. The user can program the amount of delay through the IOB in increments of 75ps by either incrementing or decrementing the tap delay line. This incrementing and decrementing action is achieved by manipulating the IDELAY primitive control signals, DL YCE and DL YINC. For more information on how to use the IDELAY primitive, see UG070: Virtex-4 User Guide.Immediately after the design comes out of reset and before the calibration procedure begins, the pattern-calibration write logic writes the calibration pattern to the write data FIFO for use later on in the calibration sequence. The following kinds of patterns are written into the FIFO:•Bit time calibration pattern (…0101…)The bit time calibration pattern is used to shift the position of the read data on each data line (DQ) such that the FPGA clock edge is centered in the DQ data valid window for maximum margin.•Read data FIFO write enable calibration pattern (…A596…)The read data FIFO write-enable calibration calibrates the write-enable signal to the read data FIFOs (rise data and fall data) so that the data that comes out of the read data FIFO is in the correct order.Some time before calibration begins, the controller issues a write to the memory and writes both calibration patterns to their respective memory addresses. Then the controller issues a continuous read to the memory address that stores the calibration pattern.The result is that before calibration begins, a continuously oscillating signal is present on all the DQ lines. Also the IDELAY is initialized to a value equal to a quarter clock period of the operating bit time. For example, if the operating frequency is 230MHz, the IDELAY is initialized to 14taps (4348ps bit time / 4).The calibration procedure is implemented in a time-shared fashion, in which all DQ lines within a DQS group share one calibration module, as illustrated in Figure 6. For example, if thememory used is a 64-bit x8 memory, one calibration module is instantiated for every 8 DQ lines in a DQS group. Since the memory used is a 64-bit-wide memory, there are 8 calibration modules in all.The calibration procedure begins with the first DQ line in the group. When the procedurecompletes for that DQ line, the calibration module repeats the calibration procedure for the next DQ line until all DQ lines are calibrated.Figure 6:Time-Sharing of Calibration Modules within DQS GroupsData Capture and Recapture The delayed data is captured in the input DDR flip-flops using the internal FPGA clock as shown in Figure5, page6.The output of these flip-flops are then stored in two FIFOs – one for rising edge data and the other for falling edge data. These FIFOs are implemented using LUT RAMs. The write enable for these FIFOs is provided by a read enable signal generated by the controller and aligned to the captured read data based on pattern calibration.The DDR2 SDRAM devices do not provide a read valid or read enable signal along with read data. Therefore, the controller generates this read enable signal based on the CAS latency and the burst length.The read enable signal must be asserted during the read preamble and deasserted after the last rising edge of the strobe. The read enable signal must also be aligned to the captured read data at the output of the IDDR flip-flops. For read enable alignment, a known pattern is written to memory after data alignment to the FPGA clock is complete. The known pattern is then read back, and the read enable signal is delayed using shift registers until it is aligned with the captured read data. A read enable signal is generated per byte of data.Figure7 shows the timing diagram for data capture and transfer to FIFOs.Figure 7: Data Capture and Transfer to FIFOsRead Timing Analysis This section presents the read timing analysis of the direct-clocking technique. Read data is captured directly in the FPGA clock domain. As a result, the memory parameter used for the data valid window analysis is the access time (T AC).For this timing analysis, the external memory parameters included are the following:•T AC - Access time of read data (DQ) with respect to clock forwarded to memory by FPGA •T DCD - DCM output duty cycle distortionRead data (DQ) is captured using the FPGA clock and not the memory clock/strobe (DQS). As a result, T AC (access time of data with respect to clock) is included for this analysis. The DQS-to-DQ memory parameters such as T DQSQ and T QHS are not included in this analysis because T AC overrides them.T AC is a general parameter that includes process, voltage, and temperature variations. The calibration used in this design eliminates the variation due to process. The effects of process cannot be separated from the effect of voltage and temperature variations from T AC. Therefore, the entire value of T AC is used in the worst-case timing analysis. For more information, contact the appropriate memory vendor.FPGA parameters considered for this timing analysis are as follows:•T SAMP - Sampling window specified in the Virtex-4 source synchronous data sheet. For details, see DS302: Virtex-4 Data Sheet.•T PACKAGE_SKEW - Package skew for a particular device/package.•T PCB_LAYOUT_SKEW - Skew associated with trace length differences between DQ lines on PCB.•T IDELAYPAT_JIT - Pattern jitter per IDELAY tap specified in the Virtex-4 Data Sheet.T IDELAYPAT_JIT is pattern-dependent jitter that arises from a random data pattern that traverses through the IDELAY. Pattern jitter is 12ps.•T CLOCK_TREE-SKEW - Skew on the global clock tree for IOB flip-flops closely placed withina bank.In a typical case, the maximum number of taps used in the calibration is a half-clock period. However, in a worst-case timing analysis, the corner conditions described in the previous sections must be taken into account. The worst-case conditions must include the maximum skew between two DQ lines within a DQS group given by the specifications, the two extra taps to correct for edge alignment conditions, and any additional skew that arises from package and PCB layout skew. In summary, the worst-case number of taps used in the design is given by the following formula:N MAX_T APS = {(T HALF_CLOCK + T DQSQ + T PACKAGE_SKEW + T PCB_LAYOUT_SKEW) / T IDELAYRESOLUTION} + N EDGE_ALIGN_CORRECT where:•T HALF_CLOCK - Half-clock period•T DQSQ - Maximum skew between DQ lines in a DQS group as defined by DDR2specifications•T PACKAGE_SKEW - Package skew for a particular device/package•T PCB_LAYOUT_SKEW - Skew associated with trace length differences between DQ lines ona PCB•T IDELAYRESOLUTION - Resolution of a tap in the IDELAY•N EDGE_ALIGN_CORRECT - Number of taps incremented to correct for edge alignmentXAPP701 (v2.0) March 12, 11In the read timing analysis listed in Table 1, for an operating frequency of 230MHz, the timing values are as follows:•T HALF_CLOCK is 2173ps.•T DQSQ is 300ps (according to the DDR2 specifications).•T PACKAGE_SKEW and T PCB_LAYOUT_SKEW are both assumed to be 50ps.•T IDELAYRESOLUTION is 75ps.•N EDGE_ALIGN_CORRECT is 2taps.Substituting these timing values into the N MAX_TAPS formula, the maximum number of taps used in this specific case is 36taps.Table 1 lists and describes the uncertainty parameters for a read timing analysis at 230MHz for a -11 device. All parameters are specified in picoseconds. T DAT A_PERIOD is half the clockperiod, minus T DCD . The difference between T DATA_PERIOD and the sum of uncertainties is the valid data window (92ps). The worst-case timing analysis shows 92ps of margin at 230MHz when using a -11 Virtex-4 device.Table 1: Read Timing Analysis at 230MHz for DDR2 Interface in -11 DeviceUncertainty Parameters Value (ps)DescriptionT CLOCK 4347Clock period.T DCD150DCM output duty cycle distortion is subtracted from clock phase (equal to half a clock period) to determine T DA TA_PERIOD .T DAT A_PERIOD 2024Data period is half the clock period, with duty cycle distortion subtracted from it.T AC 1000Data output access time specified by memory vendor.T SAMP500Sampling window specified in the Virtex-4 source synchronous data sheet.T IDELAYPA T_JIT432At 230MHz, the total number of taps in the worst case is 36taps. (See the formula in “Read Timing Analysis”.) Therefore, the worst case IDELAY pattern jitter is 36taps x 12ps per tap = 432ps.T CLOCK_TREE_SKEWClock tree skew is eliminated from the worst-case timing analysis because thecalibration procedure is performed on a per-bit basis.T PACKAGE_SKEWPackage skew is eliminated from the worst case timing analysis because the calibration procedure is performed on a per-bit basis. However, package skew affects the maximum number of taps used. As a result, package skew is included in the calculations ofTIDELAYPAT_JIT. (See the formula in “Read Timing Analysis.”)Reference Design The reference design for the Direct Clocking Data Capture T echnique is integrated with the Memory Interface Generator (MIG) tool. This tool has been integrated with the XilinxCORE Generator TM software. For the latest version of the design, download the IP Update on the Xilinx website at the following URL:/xlnx/xil_sw_updates_home.jspConclusion The Virtex-4 I/O architecture enhances the implementation of source-synchronous memoryinterface controller designs. The architectural features used in the design include the following:•IDELAY block – Continuously calibrated delay elements with small tap resolution.•FIFO16 primitive – Block RAM used as FIFO with no additional CLB resources required forstatus flag generation.•Global clocking – High-speed differential global clocking resources provide a better dutycycle. The number of global clock resources required in a design is reduced as a result ofdifferential clocking.Revision History The following table shows the revision history for this document.T PCB_LAYOUT_SKEW0PCB layout skew is eliminated from theworst-case timing analysis because thecalibration procedure is performed on a per-bitbasis.However, PCB layout skew affects the maximumnumber of taps used. As a result, layout skew isincluded in the calculations of TIDELAYPAT_JIT.(See the formula in“Read Timing Analysis.”) Uncertainties1932–Window92–Table 1: Read Timing Analysis at 230MHz for DDR2 Interface in -11 Device (Continued) Uncertainty ParametersValue(ps)DescriptionDate Version Revision09/09/04 1.0Initial Xilinx release.11/01/04 1.1Revised description under “Data Capture and Recapture” section.Revised Figure5. Reference design is updated on web.07/11/05 1.2Revised Table3, Figure5, and Figure 7. Revised “ReferenceDesign” links. Added new Table1.09/13/05 1.3Updated “Read Timing Analysis” and “Reference Design” sections. XAPP701 (v2.0) March 12, 2007Date Version Revision10/02/06 1.4Updated "Strobe Edge Detection Implementation" “Data Captureand Recapture” and T able 3. Removed Figure 7.03/12/07 2.0•Revised title of document.•Revised “Summary.” and “Introduction.”•Deleted "Strobe Edge Detection" section.•Added new section, “Calibration Procedure.”•Deleted "Strobe Edge Detection Implementation" section.•Added new section, “Calibration Logic Implementation.”•Revised “Data Capture and Recapture” section.•In “Read Timing Analysis” section, revised text and table.•Revised “Conclusion” section.XAPP701 (v2.0) March 12, 13。
第二章物理层2-01 物理层要解决哪些问题？物理层的主要特点是什么？答：物理层要解决的主要问题：（1）物理层要尽可能地屏蔽掉物理设备和传输媒体，通信手段的不同，使数据链路层感觉不到这些差异，只考虑完成本层的协议和服务。
（2）给其服务用户（数据链路层）在一条物理的传输媒体上传送和接收比特流（一般为串行按顺序传输的比特流）的能力，为此，物理层应该解决物理连接的建立、维持和释放问题。
（3）在两个相邻系统之间唯一地标识数据电路。
物理层的主要特点：①由于在OSI之前，许多物理规程或协议已经制定出来了，而且在数据通信领域中，这些物理规程已被许多商品化的设备所采用，加之，物理层协议涉及的范围广泛，所以至今没有按OSI的抽象模型制定一套新的物理层协议，而是沿用已存在的物理规程，将物理层确定为描述与传输媒体接口的机械、电气、功能和过程特性。
②由于物理连接的方式很多，传输媒体的种类也很多，因此，具体的物理协议相当复杂。
2-02 归层与协议有什么区别？答：规程专指物理层协议。
2-03 试给出数据通信系统的模型并说明其主要组成构建的作用。
答：源点：源点设备产生要传输的数据。
源点又称为源站。
发送器：通常源点生成的数据要通过发送器编码后才能在传输系统中进行传输。
接收器：接收传输系统传送过来的信号，并将其转换为能够被目的设备处理的信息。
终点：终点设备从接收器获取传送过来的信息。
终点又称为目的站。
传输系统：信号物理通道。
2-04 试解释以下名词：数据，信号，模拟数据，模拟信号，基带信号，带通信号，数字数据，数字信号，码元，单工通信，半双工通信，全双工通信，串行传输，并行传输。
答：数据：是运送信息的实体。
信号：则是数据的电气的或电磁的表现。
模拟数据：运送信息的模拟信号。
模拟信号：连续变化的信号。
基带信号（即基本频带信号）：来自信源的信号。
像计算机输出的代表各种文字或图像文件的数据信号都属于基带信号。
带通信号：把基带信号经过载波调制后，把信号的频率范围搬移到较高的频段以便在信道中传输（即仅在一段频率范围内能够通过信道）。
2.2 例题分析【例题2-1】在OSI参考模型中，当相邻高层的实体把——传到低层实体后，被低层实体视为______。
A.IDU,PDUB.PDU,IDUC.IDU,SDUD.PDU,SDU【例题2-2】在ISO的OSI参考模型中，提供流量控制功能的层是第(1)______；提供建立、维护和拆除端到端连接的层是(2)______；为数据分组提供在网络中路由功能的是(3）____；传输层提供(4)_____的数据传送；为网络层实体提供数据发送和接收功能和过程的是(5)____。
（1）A．1、2、3层B．2、3、4层C．3、4、5层 D.4、5、6层(2) A.物理层B．数据链路层C．会话层D．传输层(3) A．物理层B．数据链路层C．网络层D．传输层(4) A．主机进程之间B．网络之间C．数据链路之间D．物理线路之间(5) A．物理层B．数据链路层C．网络层D．传输层【例题2-3】TCP/IP参考模型是Internet采用的协议标准，是一个协议系列，由多个处在不同层次的协议共同组成，用于将各种计算机和设备组成实际的计算机网络。
TCP/IP参考模型分成四个层次：分别是主机—网络络层、互联网络层、传输层与应用层。
（1）______属于互联网络层的低层协议，主要用于完成IP地址向物理地址的转换：（2）________主要用于完成物理地址向IP地址的转换，多用在无盘工作站启动时利用物理地址解析出对应的IP地址；（3）________是与IP协议同层的协议，更确切的说是工作在IP协议之上，但又不属于传输层的协议，可用于Internet上的路由器报告差错或提供有关意外情况的信息；(4)________是一种面向连接的传输协议，在协议使用中存在着建立连接、传输数据、释放连接的过程；(5)_________是一种无连接的传输协议，采用这种协议时，每一个数捃包都必须独立地进行路由选择，特别适合于突发性短信息的传输。
A. RARPB. ICMPC. ARPD. IGMPA. RARPB. ARPC.DNSD.BOOTPA. IGMPB. ICMPC. DHCPD. SMTPA. SNMPB. HTTPC. TCPD. UDPA. HTTPB. FTPC. TCPD. UDP【例题2-4】计算机网络提供的服务可以分为有确认服务与无确认服务，二者之间有什么区别？在下列情况中，请说明哪些可能是有确认服务或无确认服务？哪些可？哪些两者皆不可？（1）建立连接（2）数据传输（3）释放连接2.3基础习题一、填空题1.在计算机网络中，_____和______的集合称为网络体系结构。
