Ch32 Lecture-Spr11 - 3

R X32S11参考手册文档编号：RM00002基于Arm○R Cortex○R-M0内核的32位专业电机微控制器版本：V2.0目录1 简介 (16)2 文档约定 (17)2.1 寄存器缩写列表 (17)2.2 词汇表 (17)3 系统和存储器概述 (18)3.1 系统架构 (18)3.2 存储器结构 (18)3.2.1 介绍 (18)3.2.2 存储器映像和寄存器边界地址 (19)3.3 内置SRAM (20)3.4 Flash概述 (20)4 内置Flash存储器（FLASH） (21)4.1 介绍 (21)4.2 Flash主要特征 (21)4.3 Flash功能描述 (21)4.3.1 Flash结构 (21)4.3.2 Flash擦除和编程 (21)4.3.3 解锁Flash (22)4.3.4 Flash擦除流程 (22)4.3.5 FLASH写入流程 (22)4.4 选项字节功能描述 (22)4.5 Flash寄存器 (23)5 电源控制（PWR） (24)5.1 电源 (24)5.2 电源管理器 (24)5.2.1 上电复位（POR）和掉电复位（PDR） (24)5.2.1 可编程电压检测器（PVD） (25)5.3 低功耗模式 (26)5.3.1 睡眠模式 (26)5.3.2 待机模式 (27)5.4 低功耗模式下的自动唤醒（AWU） (27)5.5 电源控制寄存器 (27)5.5.1 PMU配置寄存器（PWR_PMUCON） (27)5.5.2 电源检测阈值配置寄存器（PWR_VDETCFG） (28)5.5.3 PMU中断使能寄存器（PWR_PMUIE） (28)5.5.4 PMU中断标志寄存器（PWR_PMUIF） (28)5.5.5 PMU状态寄存器（PWR_PMUSTA） (29)5.5.6 唤醒标志寄存器（PWR_WAKEIF） (29)6 复位和时钟控制 (31)6.1 复位 (31)6.1.1 系统复位 (31)6.1.2 电源复位 (31)6.2 时钟 (32)6.2.1 HSI时钟 (33)6.2.2 LSI时钟 (33)6.2.3 系统时钟（SYSCLK）选择 (33)6.2.4 RTC时钟 (33)6.2.5 看门狗时钟 (33)6.2.6 时钟输出 (33)6.3 CMU寄存器 (33)6.3.1 写保护寄存器（CMU_WPREG） (33)6.3.2 系统时钟配置寄存器（CMU_SYSCLKCFG） (34)6.3.3 芯片状态指示寄存器（CMU_JTAGSTA） (34)6.3.4 LSI时钟调整寄存器（CMU_LSIADJ） (35)6.3.5 HSI时钟调整寄存器（CMU_HSIADJ） (35)6.3.6 时钟状态寄存器（CMU_CLKSTA） (35)6.3.7 系统时钟分频寄存器（CMU_SYSCLKDIV） (36)6.3.8 CLKOUT时钟选择寄存器（CMU_CLKOUTSEL） (36)6.3.9 CLKOUT时钟分频寄存器（CMU_CLKOUTDIV） (36)6.3.10 内部模块使能控制寄存器0（CMU_CLKCTRL0） (37)6.3.11 内部模块使能控制寄存器1（CMU_CLKCTRL1） (38)6.3.12 FLASH控制寄存器（CMU_FLASHCON） (39)6.3.13 FLASH锁定寄存器（CMU_FLASHLOCK） (39)6.3.14 INFO Flash锁定寄存器（CMU_INFOLOCK） (40)6.3.15 FLASH访问周期配置寄存器（CMU_MULTFUNCFG） (40)6.3.16 芯片版本寄存器（CMU_CHIPID） (40)6.3.17 时钟滤波控制寄存器（CMU_FLTCTR） (41)7 通用和复用功能I/O（GPIO） (42)7.1 介绍 (42)7.2 GPIO主要特征 (42)7.3 GPIO功能复用 (42)7.3.1 通用IO（GPIO） (43)7.3.2 IO引脚复用功能 (43)7.3.3 I/O端口控制寄存器 (44)7.3.4 I/O端口数据寄存器 (44)7.3.5 I/O复用功能输入/输出 (44)7.3.6 外部中断/唤醒线 (44)7.3.7 输入模式配置 (44)7.3.8 输出模式配置 (45)7.3.9 复用功能配置 (46)7.3.10 模拟功能配置 (46)7.4 GPIO寄存器 (47)7.4.1 端口功能配置寄存器1（GPIOx_IOCFG） (47)7.4.2 端口复用功能配置寄存器1（GPIOx_AFCFG1） (48)7.4.3 端口复用功能配置寄存器2（GPIOx_AFCFG2） (48)7.4.4 端口方向配置寄存器（GPIOx_PTDIR） (49)7.4.5 端口上下拉配置寄存器（GPIOx_PUPDN） (49)7.4.6 端口数据寄存器（GPIOx_PTDAT） (49)7.4.7 端口设置寄存器（GPIOx_PTSET） (50)7.4.8 端口复位寄存器（GPIOx_PTCLR） (50)7.4.9 端口翻转寄存器（GPIOx_PTTOG） (51)7.4.10 端口开漏配置寄存器（GPIOx_PTOD） (51)7.4.11 端口高阻控制寄存器（GPIOx_HIIPM） (51)7.4.12 端口电平读取寄存器（GPIOx_IDR） (51)8 嵌套向量中断控制器（NVIC） (52)8.1 NVIC主要特征 (52)8.2 中断和异常向量 (52)9 中断和事件控制器（EXTI） (54)9.1 EXTI简介 (54)9.2 框图 (54)9.3 功能说明 (54)9.4 EXTI寄存器 (55)9.4.1 外部中断边沿配置寄存器（EXTI_EXTIE） (55)9.4.2 外部中断标志寄存器（EXTI_EXTIF） (55)9.4.3 外部中断滤波使能寄存器（EXTI_FIL TEN） (56)9.4.4 外部中断串口数字滤波使能寄存器（EXTI_RXFILTEN） (57)9.4.5 外部中断边沿配置寄存器（EXTI_EXTIE2） (57)9.4.6 外部中断标志寄存器2（EXTI_EXTIF2） (57)9.4.7 外部中断滤波选择寄存器（EXTI_FIL TSEL） (58)10 模拟数字转换器(ADC) (59)10.1 ADC简介 (59)10.2 ADC主要特征 (59)10.3 ADC功能描述 (59)10.3.1 ADC引脚/通道 (60)10.3.2 ADC开关 (61)10.3.3 ADC时钟 (61)10.3.4 通道选择 (61)10.3.5 单次转换模式 (61)10.3.6 连续转换模式 (61)10.3.7 扫描模式 (62)10.4 校准 (62)10.5 可编程的通道采样时间 (62)10.6 ADC寄存器 (63)10.6.1 SADC控制寄存器（ADC_SADCCON） (63)10.6.2 SADC序列转换控制寄存器（ADC_SADCSTR） (64)10.6.3 SADCCLK时钟配置寄存器（ADC_SADCCLK） (64)10.6.4 SADC中断控制寄存器（ADC_SADCIE） (64)10.6.5 SADC中断标志寄存器（ADC_SADCIF） (65)10.6.6 SADC采样时间配置寄存器（ADC_SADCSAMP） (65)10.6.7 SADC采样时间配置寄存器（ADC_SADCSAMP2） (66)10.6.8 SADC触发源及扫描序列长度寄存器（ADC_SADCTRGLEN） (66)10.6.9 SADC序列信道配置寄存器（ADC_SADCSEQCFG） (67)10.6.10 SADC序列数据寄存器（ADC_SADCDAT） (68)10.6.11 SADCx通用数据寄存器（ADC_SADCxDAT） (68)10.6.12 CALDATx校准值寄存器（ADC_SADC_SADC_CALDATx） (68)11 直接存储器访问控制器（DMA） (69)11.1 DMA简介 (69)11.1.1 DMA主要特征 (69)11.2 功能描述 (70)11.3 DMA处理 (70)11.3.1 仲裁器 (70)11.3.2 DMA通道 (70)11.3.3 DMA通道请求列表 (71)11.4 DMA寄存器 (72)11.4.1 DMA中断使能寄存器（DMA_DMAIE） (72)11.4.2 DMA中断标志寄存器（DMA_DMAIF） (72)11.4.3 DMA状态寄存器（DMA_CHNSTA） (73)11.4.4 DMA通道控制寄存器（DMA_CHNxCTL） (73)11.4.5 DMA通道源地址寄存器（DMA_CHNxSRC） (74)11.4.6 DMA通道目的地址寄存器（DMA_CHNxTAR） (74)11.4.7 DMA通道传输数量寄存器（DMA_CHNxCNT） (75)11.4.8 DMA已传输数据个数寄存器（DMA_CHNxTCCNT） (75)11.4.9 DMA通道块传输设置寄存器（DMA_CHNxBULKNUM） (75)12 高级控制定时器（TIM8） (76)12.1 TIM8简介 (76)12.2 TIM8主要特征 (76)12.3 TIM8功能描述 (78)12.3.1 时基单元 (78)12.3.2 计数器模式 (80)12.3.3 重复计数器 (90)12.3.4 时钟选择 (91)12.3.5 捕获、比较通道 (94)12.3.6 输入捕获模式 (96)12.3.7 PWM 输入模式 (97)12.3.8 强制输出模式 (97)12.3.9 输出比较模式 (98)12.3.10 PWM模式 (99)12.3.11 非对称PWM模式 (101)12.3.12 互补输出和死区插入 (104)12.3.13 使用刹车功能 (105)12.3.14 在外部事件时清除OCxREF信号 (108)12.3.15 产生六步PWM输出 (108)12.3.16 单脉冲模式 (110)12.3.17 编码器接口模式 (111)12.3.18 定时器输入异或 (113)12.3.19 与霍尔传感器接口 (113)12.3.20 TIM8定时器和外部触发的同步 (114)12.4 TIM8寄存器 (118)12.4.1 TIM8控制寄存器1（TIM8_CR1） (118)12.4.2 TIM8控制寄存器2（TIM8_CR2） (119)12.4.3 TIM8从模式控制寄存器（TIM8_SMCR） (120)12.4.4 TIM8 DMA/中断使能寄存器（TIM8_DIER） (122)12.4.5 TIM8状态寄存器（TIM8_SR） (123)12.4.6 TIM8事件产生寄存器（TIM8_EGR） (124)12.4.7 TIM8捕获/比较模式寄存器1（TIM8_CCMR1） (126)12.4.8 TIM8捕获/比较模式寄存器2（TIM8_CCMR2） (128)12.4.9 TIM8捕获/比较使能寄存器（TIM8_CCER） (130)12.4.10 TIM8计数器（TIM8_CNT） (133)12.4.11 TIM8预分频器（TIM8_PSC） (133)12.4.12 TIM8自动重装载寄存器（TIM8_ARR） (133)12.4.13 TIM8重复计数寄存器（TIM8_RCR） (134)12.4.14 TIM8捕获/比较寄存器1（TIM8_CCR1） (134)12.4.15 TIM8捕获/比较寄存器2（TIM8_CCR2） (135)12.4.16 TIM8捕获/比较寄存器3（TIM8_CCR3） (135)12.4.17 TIM8捕获/比较寄存器4（TIM8_CCR4） (136)12.4.18 TIM8刹车和死区寄存器（TIM8_BDTR） (136)12.4.19 TIM8捕获/比较寄存器5（TIM8_CCR5） (139)12.4.20 TIM8捕获/比较模式寄存器3（TIM8_CCMR3） (139)12.4.21 TIM8捕获/比较寄存器6（TIM8_CCR6） (140)12.4.22 TIM8捕获/比较模式寄存器（TIM8_CCR1N） (140)12.4.23 TIM8捕获/比较模式寄存器（TIM8_CCR2N） (141)12.4.24 TIM8捕获/比较模式寄存器（TIM8_CCR3N） (141)13 通用定时器（TIMx） (142)13.1 TIMx简介 (142)13.2 TIMx主要功能 (142)13.3 TIMx功能描述 (143)13.3.1 时基单元 (143)13.3.2 时钟的选择 (144)13.3.3 周期定时模式 (144)13.3.4 PWM模式 (145)13.3.5 捕获模式 (148)13.3.6 事件计数模式 (148)13.3.7 中断模式 (149)13.4 TIMx寄存器 (149)13.4.1 定时器控制寄存器（TIMx_TMRCON） (149)13.4.2 预分频寄存器（TIMx_TMRDIV） (150)13.4.3 周期寄存器（TIMx_TMRPRD） (150)13.4.4 捕获数据寄存器（TIMx_TMRCAP） (150)13.4.5 计数寄存器（TIMx_TMRCNT） (150)13.4.6 比较寄存器（TIMx_TMRCMP） (151)13.4.7 定时器中断使能寄存器（TIMx_TMRIE） (151)13.4.8 定时器中断标志寄存器（TIMx_TMRIF） (152)14 运算放大器（PGA/OPA） (153)14.1 运算放大器简介 (153)14.2 运算放大器特征 (153)14.3 运算放大器框图 (153)14.4 运算放大器寄存器 (154)14.4.1 运算放大器控制寄存器（OPA_CR） (154)15 比较器（CMP） (155)15.1 比较器简介 (155)15.2 比较器特征 (155)15.3 比较器开关控制 (155)15.4 比较器器输入和输出 (155)15.5 比较器锁定机制 (155)15.6 比较器轮询功能 (155)15.7 比较器框图 (155)15.8 比较器迟滞功能 (157)15.9 比较器消隐功能 (157)15.10 比较器寄存器 (159)15.10.1 CMP控制寄存器1（CMPx_CR1） (159)15.10.2 CMP控制寄存器2（CMPx_CR2） (160)15.10.3 CMP校正寄存器（CMPx_CAL） (162)15.10.4 轮询寄存器（PLC） (162)15.10.5 寄存器（PLS） (164)16 电机专用协同处理器（ME） (165)16.1 简介 (165)16.2 DIV模块 (165)16.2.1 概述 (165)16.2.2 除法器的使用方法 (165)16.2.3 DIV CR寄存器（DIV_CR） (166)16.2.4 DIV DD寄存器（DIV_DD） (166)16.2.5 DIV DI寄存器（DIV_DI） (167)16.2.6 DIV DQ寄存器（DIV_DQ） (167)16.2.7 DIV DR寄存器（DIV_DR） (167)16.3 SQRT模块 (167)16.3.1 概述 (167)16.3.2 SQRT使用方法 (167)16.3.3 SQRT CR寄存器（SQRT_CR） (168)16.3.4 SQRT DI寄存器（SQRT_DI） (168)16.3.5 SQRT DO寄存器（SQRT_DO） (168)16.4 SIN COS 表 (169)16.4.1 使用方法 (169)16.5 坐标转换 (169)16.5.1 使用方法 (169)16.6 IPD运算 (169)16.6.1 使用方法 (169)16.7 SMO运算 (170)16.7.1 使用方法 (170)16.8 SVPWM运算 (170)16.8.1 使用方法 (170)16.9 中断功能 (170)16.10 ME寄存器 (171)16.10.1 ME控制寄存器（ME_CR） (171)16.10.2 ME Ia寄存器（ME_Ia） (172)16.10.3 ME Ib寄存器（ME_lb） (172)16.10.4 ME Ic寄存器（ME_lc） (172)16.10.5 ME Ialpha寄存器（ME_Ialpha） (173)16.10.6 ME Ibeta寄存器（ME_Ibeta） (173)16.10.7 ME Iq寄存器（ME_Iq） (173)16.10.8 ME Id寄存器（ME_Id） (173)16.10.9 ME Vq寄存器（ME_Vq） (173)16.10.10 ME Vd寄存器（ME_Vd） (174)16.10.11 ME Valpha寄存器（ME_Valpha） (174)16.10.12 ME Vbeta寄存器（ME_Vbeta） (174)16.10.13 ME Angle寄存器（ME_Angle） (174)16.10.14 ME Cos寄存器（ME_Cos） (174)16.10.15 ME Sin寄存器（ME_Sin） (175)16.10.16 ME IPDSin寄存器（ME_IPDSin） (175)16.10.17 ME Kslid寄存器（ME_Kslid） (175)16.10.18 ME Kslf寄存器（ME_Kslf） (175)16.10.19 ME KF寄存器（ME_KF） (175)16.10.20 ME KG寄存器（ME_KG） (176)16.10.21 ME E0寄存器（ME_E0） (176)16.10.22 ME Ealpha寄存器（ME_Ealpha） (176)16.10.23 ME Ebeta寄存器（ME_Ebeta） (176)16.10.24 ME Zalpha寄存器（ME_Zalpha） (177)16.10.25 ME Zbeta寄存器（ME_Zbeta） (177)16.10.26 ME IalphaError寄存器（ME_IalphaError） (177)16.10.27 ME IbetaError寄存器（ME_IbetaError） (177)16.10.28 ME EstIalpha寄存器（ME_EstIalpha） (178)16.10.29 ME EstIbeta寄存器（ME_EstIbeta） (178)16.10.30 ME SMOTheta寄存器（ME_SMOTheta） (178)16.10.31 ME SMOIalpha寄存器（ME_SMOIalpha） (178)16.10.32 ME SMOIbeta寄存器（ME_SMOIbeta） (178)16.10.33 ME BEMFA寄存器（ME_BEMFA） (179)16.10.34 ME BEMFB寄存器（ME_BEMFB） (179)16.10.35 ME IPDTheta寄存器（ME_IPDTheta） (179)16.10.36 ME SVZone寄存器（ME_SVZone） (179)16.10.37 ME FOVM寄存器（ME_FOVM） (179)16.10.38 ME TPWM寄存器（ME_TPWM） (180)16.10.39 ME LSMIN寄存器（ME_LSMIN） (180)16.10.40 ME PDCH1寄存器（ME_PDCH1） (180)16.10.41 ME PDCH2寄存器（ME_PDCH2） (180)16.10.42 ME PDCH3寄存器（ME_PDCH3） (181)16.10.43 ME IER寄存器（ME_IER） (181)16.10.44 ME IFR寄存器（ME_IFR） (182)16.10.45 ME MCYC寄存器（ME_MCYC） (183)17 PID运算单元（PID） (184)17.1 PID简介 (184)17.2 PID使用方法 (184)17.3 PID寄存器 (185)17.3.1 PID CR寄存器（PID_CR） (185)17.3.2 PID REF寄存器（PID_REF） (185)17.3.3 PID FB寄存器（PID_FB） (185)17.3.4 PID OUT寄存器（PID_OUT） (186)17.3.5 PID ERR寄存器（PID_ERR） (186)17.3.6 PID INTG寄存器（PID_INTG） (186)17.3.7 PID KPG寄存器（PID_KPG） (186)17.3.8 PID KIG寄存器（PID_KIG） (187)17.3.9 PID KDG寄存器（PID_KDG） (187)17.3.10 PID KIMULP寄存器（PID_KIMULP） (187)17.3.11 PID DIV寄存器（PID_DIV） (187)17.3.12 PID INTGLIM寄存器（PID_INTGLIM） (188)17.3.13 PID OUTLIM寄存器（PID_OUTLIM） (188)18 实时时钟（RTC） (189)18.1 RTC简介 (189)18.2 主要特性 (189)18.3 功能描述 (189)18.3.1 概述 (189)18.3.2 复位过程 (189)18.3.3 中断功能 (190)18.4 RTC寄存器 (190)18.4.1 RTC控制寄存器（RTC_RTCCON） (190)18.4.2 RTC中断使能寄存器（RTC_RTCIE） (190)18.4.3 RTC中断标志寄存器（RTC_RTCIF） (191)18.4.4 RTC定时器2寄存器（RTC_RTCTMR2） (191)19 独立看门狗（IWDT） (192)19.1 IWDT简介 (192)19.2 IWDT主要特性 (192)19.3 WDT功能描述 (192)19.4 工作模式 (193)19.5 看门狗寄存器 (193)19.5.1 WDT喂狗与时间配置寄存器（WDT_WDTCLR） (193)19.5.2 WDT计数寄存器（WDT_WDTCNT） (193)20 I2C接口 (194)20.1 I2C简介 (194)20.2 I2C主要特点 (194)20.3 框图 (195)20.4 I2C功能描述 (195)20.4.1 串行时钟生成 (195)20.4.2 中断生成 (195)20.4.3 传输模式 (196)20.4.4 模式选择 (204)20.5 I2C寄存器 (205)20.5.1 I2C数据寄存器（I2C_I2CDAT） (205)20.5.2 I2C地址寄存器（I2C_I2CADR） (205)20.5.3 I2C控制寄存器（I2C_I2CCON） (206)20.5.4 状态寄存器（I2C_I2CSTA） (206)21 通用异步收发器（UART） (207)21.1 UART介绍 (207)21.2 UART主要特性 (207)21.3 UART功能概述 (207)21.3.1 UART 特性描述 (208)21.3.2 发送器 (209)21.3.3 接收器 (210)21.3.4 校验控制 (210)21.4 串口通讯模式说明 (211)21.4.1 方式1 (211)21.4.2 方式2 (212)21.4.3 方式3 (212)21.4.4 方式4 (213)21.5 UART中断请求 (214)21.6 UART模式配置 (214)21.7 UART寄存器 (214)21.7.1 UART功能配置寄存器（UART_UARTCON） (214)21.7.2 串口波特率发生寄存器（UART_SREL） (215)21.7.3 串口数据缓冲寄存器（UART_SBUF） (215)21.7.4 UART状态寄存器（UART_UARTSTA） (216)22 版本历史 (217)表3.1 RX32S11存储器映像和外设边界地址 (20)表4.1 Flash结构 (21)表5.1 低功耗模式一览 (26)表5.3睡眠模式进入和唤醒 (26)表5.2待机模式进入和唤醒 (27)表8.1 RX32S11向量表 (52)表10.1 ADC引脚 (60)表10.2 ADC通道 (60)表11.1 DMA通道请求列表 (71)表12.1 计数方向与编码器信号的关系 (111)表12.2 带刹车功能的互补输出通道OCx和OCxN的控制位 (132)表21.1 帧格式 (210)表21.2 UART中断请求 (214)表21.3 UART模式设置（1） (214)表22.1版本历史 (217)图3.1 存储器映像 (19)图5.1 电源框图 (24)图5.2 上电复位和掉电复位波形图 (25)图5.3 PVD门限 (25)图6.1 复位电路框图 (31)图6.2 时钟树 (32)图7.1 I/O端口位基本结构 (43)图7.2 输入浮空/上拉/下拉结构 (45)图7.3 输出框图 (45)图7.4 复用功能框图 (46)图7.5 模拟引脚框图 (47)图9.1 外部中断控制器框图 (54)图10.1 ADC框图 (60)图10.2 校准时序图 (62)图11.1 DMA框图 (69)图12.1 高级控制定时器框图 (77)图12.2 当预分频器的参数从1变成2时，计数器的时序图 (79)图12.3 当预分频器的参数从1变成4时，计数器的时序图 (79)图12.4 计数器时序图，内部时钟分频因子为1 (80)图12.5 计数器时序图，内部时钟分频因子为2 (81)图12.6 计数器时序图，内部时钟分频因子为4 (81)图12.7 计数器时序图，内部时钟分频因子为N (82)图12.8 计数器时序图，当ARPE=0时的更新事件（TIM8_ARR没有预装入） (82)图12.9 计数器时序图，当ARPE=1时的更新事件（预装入了TIM8_ARR） (83)图12.10 计数器时序图，内部时钟分频因子为1 (84)图12.11 计数器时序图，内部时钟分频因子为2 (84)图12.12 计数器时序图，内部时钟分频因子为4 (85)图12.13 计数器时序图，内部时钟分频因子为N (85)图12.14 计数器时序图，当没有使用重复计数器时的更新事件 (86)图12.15 计数器时序图，内部时钟分频因子为1，TIM8_ARR=0x6 (87)图12.16 计数器时序图，内部时钟分频因子为2 (87)图12.17 计数器时序图，内部时钟分频因子为4，TIM8_ARR=0x36 (88)图12.18 计数器时序图，内部时钟分频因子为N (88)图12.19 计数器时序图，ARPE=1时的更新事件（计数器下溢） (89)图12.20 计数器时序图，ARPE=1时的更新事件（计数器溢出） (89)图12.21 不同模式下更新速率的例子，及TIM8_RCR的寄存器设置 (90)图12.22 一般模式下的控制电路，内部时钟分频因子为1 (91)图12.23 TI2外部时钟连接例子 (92)图12.24 外部时钟模式1下的控制电路 (92)图12.25 外部触发输入框图 (93)图12.26 外部时钟模式2下的控制电路 (94)图12.27 捕获、比较通道（如：通道一输入部分） (94)图12.28 捕获/比较通道1的主电路 (95)图12.29捕获/比较通道的输出部分（通道1至3） (95)图12.30 捕获/比较通道的输出部分（通道4和5） (96)图12.31 PWM输入模式时序 (97)图12.32 输出比较模式，翻转OC1 (99)图12.33 边沿对齐的PWM波形（ARR=8） (100)图12.34 中央对齐的PWM波形（APR=8） (101)图12.35 边沿对齐向上计数的PWM波形（ARR=8） (102)图12.36 中央对齐的PWM波形（APR=8） (103)图12.37 带死区插入的互补输出 (104)图12.38 死区波形延迟大于负脉冲 (104)图12.39 死区波形延迟大于正脉冲 (105)图12.40 响应刹车的输出 (107)图12.41 清除TIM8的OCxREF (108)图12.42 产生六步PWM，使用COM的例子（OSSR=1） (109)图12.43 单脉冲模式的例子 (110)图12.44 编码器模式下的计数器操作实例 (112)图12.45 IC1FP1反相的编码器接口模式实例 (113)图12.46 霍尔传感器接口的实例 (114)图12.47 复位模式下的控制电路 (115)图12.48 门控模式下的控制电路 (116)图12.49 触发器模式下的控制电路 (116)图12.50 外部时钟模式2＋触发模式下的控制电路 (117)图13.1 通用定时器框图 (142)图13.2 当预分频器的参数从1变到2时，计数器的时序图 (143)图13.3 当预分频器的参数从1变到4时，计数器的时序图 (144)图13.4 当计数器的值等于设定的周期寄存器溢出时，进入周期中断图 (145)图13.5 向上计数PWM输出波形图 (146)图13.6 向下计数PWM输出波形图 (147)图13.7 中央计数PWM输出波形图 (148)图14.1 运算放大器框图 (153)图15.1 比较器框图 (156)图15.2 比较器迟滞 (157)图15.3 比较器输出遮罩 (158)图16.1 ME框图 (165)图17.1 PID概念图 (184)图18.1 简化的RTC框图 (189)图19.1 看门狗框图 (192)图20.1 模块功能框图 (195)图20.2 I2C总线协议 (205)图21.1 UART框图 (208)图21.2 字长设置 (209)图21.3 方式1时串行发送数据时序 (211)图21.4 方式1时串行接收数据时序 (211)图21.5 方式2时串行发送数据时序 (212)图21.6 方式2时串行接收数据时序 (212)图21.7 方式3时串行发送数据时序 (212)图21.8 方式3时串行接收数据时序 (213)图21.9 方式4时串行发送数据时序 (213)图21.10 方式4时串行接收数据时序 (213)1简介本参考手册用于帮助开发者理解并使用睿兴科技（南京）有限公司（后文简称“睿兴”或“RX”）的芯片。

FMEA编号Number:页码Page:准备人Prepared By：严重度频度数难检度风险优先指数1三极管Q453移位(JT37A2MB)HDMI无联动71.上料未卡好，导致贴片过程中吸著中心偏移2.AOI漏检3.功能测试站漏检61.AOI拦检2.測試站SOP中有要求測試人員注意菜單處是否有綠色底紋的英文3126CLOSE733632IC150 反向(JT37A2 MB)无法烧录6(1)機器拋料(2)生產交接班時OP人員將當天散料A材重新使用脆盤后正常貼片導致打件反向(3)DIP後段功能測試也無法進行攔截。

5裂片---DIP插件---過錫爐---爐後接板---爐後目檢---錫面檢修---錫面目檢---功能測試---零件面目檢---總檢---包裝390CLOSE632363 U51 29-30pin连锡HDMI1无输出7(1)维修时造成的短路不良(2)FT测试站人员漏检(3)总检站人员漏检5维修室-AOI-錫面檢修---錫面目檢---功能測試---零件面目檢---總檢---包裝5175OPEN733635RF端子PIN脚连焊(JT37A2MB)DTV画面不良71.此機種生產時H101位置是由DIP插件，過鍋爐后有幾率連焊2.爐後目檢漏检3.錫面檢修站漏失，未進行拉焊4.錫面目檢漏检5.功能测试站漏检6.总检站漏检5裂片---DIP插件---過錫爐---爐後接板---爐後目檢---錫面檢修---錫面目檢---功能測試---零件面目檢---總檢---包裝3105CLOSE722286IC U1 PIN脚连锡(JT24keypad)按键无作用71.印刷設備擦拭機構出現故障無法自動擦拭，導致印刷短路2.重流AOI站OP漏检3.功能测试站漏检4.总检站漏检4AOI拦检-维修室-重流AOI-錫面檢修---錫面目檢---功能測試---零件面目檢---總檢---包裝4112CLOSE722287CN接口空焊（JT24keypad）按键无作用71元件維修不當少錫，易造成插拔CN1端子時錫裂。

XP-3控制处理器XP-3是强大的遥控处理器主机，其设计目的在于将较小规模的居家和商用安装电子产品的操作自动化并提升性能。

强大的533MHz CPU 及128MB 非易失性闪存，XP-3改进了整体的用户体验比较使用独立遥控器能提供更高水准的控制与自动化。

处理器主机拥有的强大功能彰显卓越价值，傲视同侪——功能包括内置天文时钟用于基于时间的事件，以及支持配合兼容的RTI 遥控器进行ZigBee ®无线发送双向通信。

XP-3为当今复杂精密的电子设备环境带来坚实可靠地控制与自动化。

产品描述XP-3是任何专业安装电子系统的精华组件，确保带来愉悦的用户体验。

XP-3集成在一个RTI 控制解决方案中时，其结果必然是非同凡响的。

XP-3重拳出击，拥有强大的533MHz CPU 与128MB 非易失性闪存。

内置射频接收器，®技术支持双向通信，XP-3可以为用户从支持的第三方设备提供实时反馈，如音乐服务器，灯光，安保以及其他更多。

现在，从这些设备而来的重要数据，用户只要简单地触摸就能获得——从当前歌曲信息到安全系统状态，甚至天气预报！与简单的红外到射频转换器不同，XP-3机中以保证更可靠的传输。

XP-3还拥有众多通常只在高端处理器上才有的功能，如内置天文时钟用途输入/输出端口可作为标准红外发射器输入或可以与配合来感应设备电源状态或通过单向RS-232进行通信。

感应输入可以用作触发环境中其他子系统的宏或事件，如打开车库门统，或任何低电压触发器。

XP-3是价格适中的强大双向控制及自动化的终极之选。

主要功能● 内置2.4GHz 收发器模块（利用Zigbee ®技术）。

● 强大的32位533MHz CPU.● 128Mb 非易失性闪存。

● 三个红外输出端口兼容行业标准红外发射器，增强器与转发器系统。

● 一个多用途输入/输出端口兼容行业标准红外发射器，红外转发系统以及RTI 模块（RS-232与感应）。

CKS32F103R8T6标准型 MCU 系列使用高性能的 ARM® Cortex™-M3 32 位的 RISC 内核，工作频率为 72MHz，内置高速存储器(高达 128K 字节的闪存和 20K 字节的 SRAM)，丰富的增强 I/O端口和联接到两条 APB 总线的外设。

其中包含 2 个 12 位 ADC、3 个通用 16 位定时器和 1 个 PWM 定时器，此外，还包含标准和先进的通信接口：多达 2 个 I2C 接口和 SPI 接口、3 个 USART 接口、1 个 USB 接口和1 个 CAN 接口。

功能■内核：ARM32位Cortex™-M3 内核−最高72MHz工作频率，在存储器的0等待周期访问时可达1.25DMips/MHz (Dhrystone2.1)−单周期乘法和硬件除法■存储器−64KB 或 128KB 程序 Flash−20KB SRAM■时钟、复位和电源管理− 2.0～3.6伏供电和I/O引脚■多达80个快速I/O端口−上电/断电复位(POR/PDR)、可编程电压监测器(PVD)−4～16MHz晶体振荡器−内嵌经出厂调校的8MHz的高速RC振荡器−内嵌带校准的40kHz的低速RC振荡器−产生CPU时钟的PLL−带校准功能的32kHz RTC振荡器■2个12位ADC，1μs转换时间(多达16个输入通道) −转换范围：0至3.6V−双采样和保持功能−温度传感器■DMA：−7通道DMA控制器−支持的外设：定时器、ADC、SPI、I2C和USART ■低功耗−睡眠、停机和待机模式−V BAT为RTC和后备寄存器供电−26/37/51/80个I/O口，所有I/O口可以映像到16个外部中断；几乎所有端口均可承受5V信号■调试模式−串行单线调试(SWD)和JTAG接口■7个定时器−3个16位定时器，每个定时器有多达4个用于输入捕获/输出比较/PWM或脉冲计数的通道和增量编码器输入−1个16位带死区控制和紧急刹车，用于电机控制的PWM高级控制定时器−2个看门狗定时器(独立的和窗口型的)−系统时间定时器：24位自减型计数器■多达9个通信接口−多达2个I2C接口(支持SMBus/PMBus)−多达3个USART接口(支持ISO7816接口，LIN，IrDA接口和调制解调控制)−多达2个SPI接口(18M位/秒)器件对比CKS32F103x8（B）产品功能和外设配置产品型号外围接口CKS32F103C8/CB CKS32F103RB CKS32F103VB 闪存- K 字节64 128 128 128SRAM- K 字节20 20 20定时器通用目的 3 3 3 高级控制 1 1 1 SPI 2 2 2 I2C 2 2 2通信接口USART 3 3 3 USB 1 1 1CAN 1 1 1 GPIO 端口(通道数) 37 51 8012 位同步 ADC 2 2 2(通道数) 10 channels 16 channels 16 channels CPU 频率72 MHz工作电压 2.0V ~3.6V工作温度环境温度：-40℃~ +85℃/-40℃~+105℃结温度：-40℃~+125℃封装LQFP48 LQFP64 LQFP100订购信息托盘装产品型号封装形式盘装数盒装盘盒装数箱装盒箱装数CKS32F103C8T6 LQFP48 250PCS/盘10 盘/盒2500PCS/盒 6 盒/箱15000PCS/箱CKS32F103CBT6 LQFP48 250 PCS/盘10 盘/盒2500PCS/盒 6 盒/箱15000 PCS/箱CKS32F103RBT6 LQFP64 160 PCS/盘10 盘/盒1600 PCS/盒 6 盒/箱9600 PCS/箱CKS32F103VBT6 LQFP100 90 PCS/盘10 盘/盒900 PCS/盒 6 盒/箱5400 PCS/箱目录1．介绍 (1)2. 规格说明 (2)2.1 概述 (2)2.1.1 ARM®的Cortex™-M3 核心并内嵌闪存和 SRAM (2)2.1.2 内置闪存存储器 (2)2.1.3 CRC(循环冗余校验)计算单元 (3)2.1.4 内置 SRAM (3)2.1.5 嵌套的向量式中断控制器(NVIC) (3)2.1.6 外部中断/事件控制器(EXTI) (3)2.1.7 时钟和启动 (3)2.1.8 自举模式 (4)2.1.9 供电方案 (4)2.1.10 供电监控器 (4)2.1.11 调压器 (4)2.1.12 低功耗模式 (5)2.1.13 DMA (5)2.1.14 RTC(实时时钟)和后备寄存器 (5)2.1.15 定时器和看门狗 (6)2.1.16 I2C 总线 (7)2.1.17 通用同步/异步收发器(USART) (7)2.1.18 串行外设接口(SPI) (7)2.1.19 控制器区域网络(CAN) (8)2.1.20 通用串行总线(USB) (8)2.1.21 通用输入输出接口(GPIO) (8)2.1.22 ADC(模拟/数字转换器) (8)2.1.23 温度传感器 (9)2.1.24 串行单线 JTAG 调试口(SWJ-DP) (9)3. 引脚定义 (12)4. 存储器映像 (20)5. 电气特性 (21)5.1.1 最小和最大数值 (21)5.1.2 典型数值 (21)5.1.3 典型曲线 (21)5.1.4 负载电容 (21)5.1.5 引脚输入电压 (22)5.1.6 供电方案 (23)5.1.7 电流消耗测量 (23)5.2 绝对最大额定值 (24)5.3 工作条件 (25)5.3.1 通用工作条件 (25)5.3.2 上电和掉电时的工作条件 (25)5.3.3 内嵌复位和电源控制模块特性 (26)5.3.4 内置的参照电压 (27)5.3.5 供电电流特性 (27)5.3.6 外部时钟源特性 (31)5.3.7 内部时钟源特性 (35)5.3.8 PLL 特性 (36)5.3.9 储存器特性 (36)5.3.10 EMC 特性 (37)5.3.11 绝对最大值(电气敏感性) (38)5.3.12 I/O 端口特性 (39)5.3.13 NRST 引脚特性 (42)5.3.14 TIM 定时器特性 (43)5.3.15 通信接口 (43)5.3.16 CAN(控制器局域网络)接口 (48)5.3.17 12 位 ADC 特性 (48)5.3.18 温度传感器特性 (52)6. 封装特性 (53)6.1 封装机械数据 (53)6.2 热特性 (57)7. 型号命名 (58)8. 版本历史 (59)1．介绍本文给出了 CKS32F103x8 和 CKS32F103xB 标准型 MCU 产品的器件特性。

SLWRB4545AReference Manual BRD4543BThe EZR32HG family of Wireless MCUs deliver a high perform-ance, low energy wireless solution integrated into a small form factor package.By combining a high performance sub-GHz RF transceiver with an energy efficient 32-bit MCU, the family provides designers the ultimate in flexibility with a family of pin-compatible devices that scale from 32/64 kB of flash and support Silicon Labs EZRadio or EZRadioPRO transceivers. The ultra-low power operating modes and fast wake-up times of the Silicon Labs energy friendly 32-bit MCUs, combined with the low transmit and receive power consumption of the sub-GHz radio, result in a solution optimized for battery powered applications.To develop and/or evaluate the EZR32 Happy Gecko the EZR32HG Radio Board can be connected to the Wireless Starter Kit Mainboard to get access to display, buttonsand additional features from Expansion Boards.Rev. 1.0Introduction 1. IntroductionThe EZR32 Happy Gecko Radio Boards provide a development platform (together with the Wireless Starter Kit Mainboard) for the Silicon Labs EZR32 Happy Gecko Wireless Microcontrollers and serve as reference designs for the matching network of the RF inter-face.The BRD4543B is designed to the operate in the US FCC 902-928 MHz band, the RF matching network is optimized to operate in the 915 MHz band with 20 dBm output power.To develop and/or evaluate the EZR32 Happy Gecko the BRD4543B Radio Board can be connected to the Wireless Starter Kit Main-board to get access to display, buttons and additional features from Expansion Boards and also to evaluate the performance of the RF interface.2. Radio Board Connector Pin AssociationsThe figure below shows the pin mapping on the connector to the radio pins and their function on the Wireless Starter Kit Mainboard.GND F9 / NC3v3NC / P36P200Upper RowNC / P38NC / P40NC / P42NC / P44DEBUG.TMS_SWDIO / PF1 / F0DISP_ENABLE / PA1 / F14UIF_BUTTON0 / PC9 / F12UIF_LED0 / PF4 / F10NC / F8DEBUG.RESET / RESETn / F4NC / F2DISP_MOSI / PE10 / F16VCOM.TX_MOSI / PD4 / F6PTI.DATA / RF_GPIO0 / F20DISP_EXTCOMIN / PF3 / F18USB_VBUS5VBoard ID SCLGNDBoard ID SDAUSB_VREGF7 / PD5 / VCOM.RX_MISOF5 / PC8 / VCOM_ENABLEF3 / NCF1 / PF0 / DEBUG.TCK_SWCLKP45 / NCP43 / NCP41 / NCP39 / NCP37 / NCF11 / PF2 / UIF_LED1F13 / PC10 / UIF_BUTTON1F15 / PE12 / DISP_SCLKF17 / PA0 / DISP_SCSF19 / RF_GPIO1 / PTI.SYNCF21 / NCGNDVMCU_INUIF_LED1 / PF2 / P0P201Lower RowUIF_LED0 / PF4 / P2UIF_BUTTON0 / PC9 / P4UIF_BUTTON1 / PC10 / P6GND VRF_INP35 / P7 / PE13P5 / PE12 / DISP_SCLK P3 / PE11P1 / PE10 / DISP_MOSI P33 / RF_GPIO3 P31 / RF_GPIO1 / PTI.SYNC P29 / NCP27 / NC P25 / PC14 * P23 / NC P21 / PF1 / DEBUG.TMS_SWDIO P19 / PC8 / VCOM_ENABLEP17 / NCP15 / PA1 / DISP_ENABLE P13 / PD6P11 / PD5 / VCOM.RX_MISO P9 / PD4 / VOM.TX_MOSI NC / P34RF_GPIO2 / P32PTI.DATA / RF_GPIO0 / P30NC / P28PC15 * / P26NC / P24DISP_EXTCOMIN / PF3 / P22DEBUG.TCK_SWCLK / PF0 / P20NC / P18NC / P16DISP_SCS / PA0 / P14PD7 / P12NC / P10PB11 / P8 * Connection is not enabled by default on the Radio Board.To enable 0 Ohm resistors should be mounted. See the schematic of the Radio Board.Figure 2.1. BRD4543B Radio Board Connector Pin MappingRadio Board Connector Pin Associations3. Radio Board Block DescriptionThe block diagram of the EZR32HG Radio Board is shown in the figure below. For the exact part numbers of the applied components refer to the BRD4543B BOM.Figure 3.1. EZR32HG Radio Board Block Diagram3.1 Wireless MCUThe BRD4543B EZR32 Happy Gecko Radio Board incorporates an EZR32HG320F64R68G Wireless Microcontroller featuring 32-bit Cortex-M0+ core, 64 kB of flash memory and 8 kB of RAM. For additional information on the EZR32HG320F64R68G, refer to the EZR32HG320 Data Sheet.The EZR32HG320F64R68G is built using the Si4468, a high-performance, low-current transciever that is part of Silicon Labs' EZRadio-PRO family. The Si4468 contains an integrated +20 dBm power amplifier that is capable of transmitting from –20 to +20 dBm. For a complete feature set and in-depth information on the transciever, refer to the "Si4463/61/60-C High-Performance, Low-Current Trans-ceiver" Data Sheet.3.2 USBThe BRD4543B Radio Board incorporates a micro USB connector. The 3.3V USB regulator output is are routed back to the WSTK through the Radio Board Connector so the Radio Board can supply power to the Wireless Starter Kit Mainboard.For additional information on EZR32HG USB, refer to the EZR32HG320 Data Sheet.3.3 RF Crystal Oscillator (RFXO)The BRD4543B Radio Board has a 30 MHz crystal mounted. For more details on crystal or TCXO selection for the RF part of the EZR32 devices refer to "AN785: Crystal Selection Guide for the Si4x6x RF ICs".3.4 LF Crystal Oscillator (LFXO)The BRD4543B Radio Board has a 32.768 kHz crystal mounted. For safe startup two capacitors are also connected to the LFXTAL_N and LFXTAL_H pins. For details regarding the crystal configuration, the reader is referred to Application Note "AN0016: EFM32 Oscilla-tor Design Consideration".| Smart. Connected. Energy-friendly.Rev. 1.0 | 33.5 HF Crystal Oscillator (HFXO)The BRD4543B Radio Board has a 24 MHz crystal mounted. For safe startup two capacitors are also connected to the HFXTAL_N and HFXTAL_H pins. For details regarding the crystal configuration, the reader is referred to Application Note "AN0016: EFM32 Oscillator Design Consideration".3.6 RF Matching NetworkThe BRD4543B Radio Board includes a Class E type matching network with a so-called Switched matching configuration where the TX and RX sides are connected together with an additional RF switch, to be able to use one antenna both for transmitting and receiveing. The component values were optimized for the 915 MHz band RF performace and current consumption with 20 dBm output power.For more details on the matching network used on the BRD4543B see Chapter 4.1 Matching Network.3.7 SMA ConnectorTo be able to perform conducted measurements or mount external antenna for radiated measurements, range tests etc., Silicon Labs added an SMA connector to the Radio Board. The connector allows an external 50 Ohm cable or antenna to be connected during de-sign verification or testing.3.8 Radio Board ConnectorsTwo dual-row, 0.05” pitch polarized connectors make up the EZR32HG Radio Board interface to the Wireless Starter Kit Mainboard. For more information on the pin mapping between the EZR32HG320F64R68G and the Radio Board Connector refer to Chapter 2. Radio Board Connector Pin Associations.4. RF SectionThe BRD4543B Radio Board includes a Class E type TX matching network with the targeted output power of 20 dBm at 915 MHz.The main advantage of the Class E matching types is their very high efficiency. They are proposed for applications where the current consumption is most critical, e.g., the typical total EZRadioPRO chip current with Class E type matching is ~75-90 mA at ~20 dBm (using the 20dBm PA output and assuming 3.3 V supply voltage).The main disadvantage of the Class E type matches is the high supply voltage dependency (the power variation is proportional to the square of the supply voltage change: i.e. the decrease in power can be ~6 dB in the 1.8–3.8 V range) and the inaccurate nonlinear power steps. Also their current consumption and the peak voltage on the TX pin are sensitive to the termination impedance variation, and they usually require slightly higher order filtering and thus higher bill of materials cost.The matching network is constructed with a so-called Switched configuration where the TX and RX sides are connected together with an additional RF switch, to be able to use one antenna both for transmitting and receiveing. Careful design procedure was followed to ensure that the RX input circuitry does not load down the TX output path while in TX mode and that the TX output circuitry does not degrade receive performance while in RX mode.For detailed explanation of the Class E type TX matching and the Switched configuration matching procedure the reader is referred to "AN648: Si4063/Si4463/64/67/68 TX Matching". For detailed description of the RX matching the reader is referred to "AN643: Si446x/ Si4362 RX LNA Matching".4.1 Matching NetworkThe matching network structure used on the BRD4543B Radio Board is shown in the figure below.Filter1Figure 4.1. RF Section of the Schematic of the BRD4543B EZR32 Happy Gecko Radio BoardThe component values were optimized for the 915 MHz band RF performace and current consumption with 20 dBm output power. The resulting component values with part numbers are listed in the table below.| Smart. Connected. Energy-friendly.Rev. 1.0 | 5Table 4.1. Bill of Materials for the BRD4543B RF Matching NetworkThe Application Note "AN648: Si4063/Si4463/64/67/68 TX Matching" contains component values for reference matching networks which were developed for the EZRadioPRO Pico Boards. For the WSTK radio boards some fine-tuning of the component values may be necessary due to different parasitic effects (bonding wire, layout etc.). For optimized RF performance the component values listed in the table above may differ from the ones listed in the referred Application Note.For the reader’s specific application and board layout the adjustment of the final matching values might be necessary. The above com-ponent values should be used as starting points and the values modified slightly to zero-in on the best filter response and impedance match to 50 ohm. To minimize the differences due to different layout parasitics Silicon Labs recommends copying the layout of the RF section of the radio board as is. If that is not possible, refer to "AN629: Si4460/61/63/64/67/68 RF ICs Layout Design Guide" for layout design recommendations. | Smart. Connected. Energy-friendly.Rev. 1.0 | 65. Mechanical DetailsThe BRD4543B EZR32 Happy Gecko Radio Board is illustrated in the figures below.2.7 mmFigure 5.1. BRD4543B Top View5 mm ConnectorConnector Figure 5.2. BRD4543B Bottom ViewMechanical DetailsRev. 1.0 | 7EMC compliance 6. EMC complianceThe BRD4543B EZR32 Happy Gecko Radio Board is dedicated for operation in the US FCC 902-928 MHz band. The relevant FCC 15.247 regulation specifies the maximum allowed level of the fundamental power and spurious emissions.In this document the compliance of the Radio Board fundamental and harmonic emissions will be investigated with 915 MHz fundamen-tal frequency (harmonics are measured up to the 10th one).6.1 FCC 15.247 Emission Limits for the 902-928 MHz BandBased on FCC 15.247 the allowed maximum fundamental power for the 902-928 MHz band is 1 W (+30 dBm) for radiated measure-ments.Note: Further in this document EIRP (Effective Isotropic Radiated Power) will be used for the comparison of the radiated limits and measurement results. The 1 W radiated limit is equivalent to +30 dBm EIRP.Outside the allowed frequency bands FCC 15.247 specifies the maximum allowed spurious emission level to be 20 dB below the power of the fundamental, based on either a conducted or radiated measurement. In addition, radiated emissions which fall in the restricted bands defined in FCC 15.205(a) must also comply with the radiated emission limits specified in FCC 15.209(a). Above 960 MHz this is defined as 500 uW (-41.2 dBm EIRP).In case of operating at 915 MHz the harmonics falling into restricted bands are the 3rd, 4th, 5th, 8th, 9th and 10th harmonics.Note: The FCC restricted band limits are radiated limits only. Besides that, Silicon Labs applies those to the conducted spectrum i.e. it is assumed that in case of a custom board an antenna is used which has 0 dB gain at the fundamental and the harmonic frequencies. In that theoretical case, based on the conducted measurement, the compliance with the radiated limits can be estimated.7. RF Performance7.1 Measurement setupThe BRD4543B EZR32 Happy Gecko Radio Board was attached to a Wireless Starter Kit Mainboard (BRD4001 (Rev. A02) ) and its transceiver was operated in continuous carrier transmission mode. The output power of the radio was set to 20 dBm (PA_PWR_LVL = 0x7F, PA_BIAS_CLKDUTY = 0x00 at VRF=3.3 V).7.2 Conducted Power MeasurementsIn case of the conducted measurements the output power was measured by connecting the EZR32HG Radio Board directly to a Spec-trum Analyzer (P/N: MS2692A) through its on-board SMA connector. At 20 dBm output power and 3.3 V supply voltage the measured typical current consumption of the RF section of the board is 90 mA.A typical output spectrum is shown in the figure below.Figure 7.1. Typical Output Spectrum of the BRD4543B Radio BoardAs it can be observed the unwanted emissions are under -50 dBm so the conducted performance is compliant with the -20 dBc limit specified by FCC 15.247 and also with the -41.2 dBm limit in the restricted bands.Note: In practice comercially available whip antennas usually have ~0-2 dB gain at the fundamental and < 0 dB gain at the harmonic frequencies so if the conducted levels are compliant with the emission limits with small margin it is likely that the margin on the harmon-ics radiated by an external whip antenna will be higher. Unfortunately in most cases, the PCB radiation (from traces or and/or compo-nents) is stronger so using shielding, applying larger duty cycle correction (if allowed) or reduction of the fundamental power could be necessary.7.3 Radiated Power MeasurementsFor radiated measurements an external whip antenna (P/N: ANT-916-CW-HWR-SMA) was used. The power supply for the board were two AA batteries (3 V). The batteries were connected to the Wireless Starter Kit Mainboard through its External Power Supply connec-tor with minimal wire length to minimize the wire radiation.The DUT was rotated in 360 degree with horizontal and vertical reference antenna polarizations in the XY, XZ and YZ cuts. The meas-urement axes are as shown in the figure below.Figure 7.2. DUT: Radio Board with Wireless Starter Kit Mainboard (Illustration)The measured radiated powers are shown in the table below.Table 7.1. Maximums of the Measured Radiated Powers of the BRD4543BAs it can be observed the fundamental and all of the harmonics comply with the FCC 15.247 limits with large margin.One may notice that the radiated harmonic levels, in general, are higher compared to the levels expected based on the conducted measurement. Investigations showed that this increase is due to the PCB radiations (components and PCB traces).Note: The radiated measurement results presented in this document were recorded in an unlicensed antenna chamber. Also the radi-ated power levels may change depending on the actual application (PCB size, used antenna etc.) therefore the absolute levels and margins of the final application is recommended to be verified in a licensed EMC testhouse!EMC Compliance Recommendations 8. EMC Compliance Recommendations8.1 Recommendations for FCC ComplianceAs it was shown in the previous chapters the conducted performance of the BRD4543B EZR32 Happy Gecko Radio Board is compliant with the fundamental and harmonic emission limits of the FCC 15.247 regulation in the 915 MHz band with 20 dBm output power. For radiated compliance mounting a shielding can is required due to PCB radiation. With the mounted shielding can all of the harmionics are under the limits with large margins.Document Revision History 9. Document Revision HistoryTable 9.1. Document Revision HistoryBoard Revisions 10. Board RevisionsTable 10.1. BRD4543B Radio Board RevisionsTable of Contents1. Introduction (1)2. Radio Board Connector Pin Associations (2)3. Radio Board Block Description (3)3.1 Wireless MCU (3)3.2 USB (3)3.3 RF Crystal Oscillator (RFXO) (3)3.4 LF Crystal Oscillator (LFXO) (3)3.5 HF Crystal Oscillator (HFXO) (4)3.6 RF Matching Network (4)3.7 SMA Connector (4)3.8 Radio Board Connectors (4)4. RF Section (5)4.1 Matching Network (5)5. Mechanical Details (7)6. EMC compliance (8)6.1 FCC 15.247 Emission Limits for the 902-928 MHz Band (8)7. RF Performance (9)7.1 Measurement setup (9)7.2 Conducted Power Measurements (9)7.3 Radiated Power Measurements (11)8. EMC Compliance Recommendations (13)8.1 Recommendations for FCC Compliance (13)9. Document Revision History (14)10. Board Revisions (15)Table of Contents (16)DisclaimerSilicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. 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Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.Trademark InformationSilicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. 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AN2945Application note STM8S and STM32™ MCUs: a consistent 8/32-bit product linefor painless migrationIntroductionFollowing the market launch of the award winning STM32™ microcontroller,STMicroelectronics completes the renewal of its microcontroller product line with theannouncement of the STM8S family. Significant effort has been made to rationalize theMCU portfolio, in particular by capitalizing on common peripherals and software tools withthe aim to easing product migration.The cost, in terms of both time and money, of maintaining a development team to design ina new MCU family is a major criterion when selecting a microcontroller supplier. It istherefore an advantage to make this kind of non-recurring investment if it applies to a broadrange of MCUs. With an MCU product line ranging from 20 to 144 pins, and memory sizesfrom 2 to 512 Kbytes, the 8-bit STM8S and 32-bit STM32 families bring a lot of flexibilitywhen building a product portfolio. Should an 8-bit application run out of MIPS, there is anupgrade path to the STM32 family. Conversely, if you wish to cut costs on a 32-bit platform,it is relatively simple to switch to the STM8 family.This document presents the similarities and common features of the STM8S and STM32product lines, with a view of helping migration from one family to the other.July 2009Doc ID 15468 Rev 11/18Contents AN2945Contents1Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63System features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.2Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.3Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.4Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.5Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4Software library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172/18 Doc ID 15468AN2945List of tables List of tablesTable 1.STM8 and STM32: core comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2.STM32 SPI register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3.STM8 SPI register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4.Peripherals shared between STM8 and STM32 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5.STM8S/STM32 clock source characteristics (indicative data) . . . . . . . . . . . . . . . . . . . . . . 11 Table 6.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Doc ID 154683/18List of figures AN2945 List of figuresFigure 1.Digital peripheral’s internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2.SPI block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.STM8S and STM32 reset circuitries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4.STM8S code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5.STM32 code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4/18 Doc ID 15468AN2945CoreDoc ID 154685/181 CoreThe STM8™ CPU is a proprietary architecture that maintains the legacy of the previous ST7 core while being a breakthrough in terms of 8-bit CPU efficiency and code density. The STM32 is built around the industry standard ARM ® Cortex™-M3 32-bit core and benefits from the complete ecosystem of development tools and software solutions associated with ARM processors. Although they may be perceived as radically different, these two processors indeed share many architectural similarities summarized in Table 1.Both are based on the Harvard architecture. They have 3-stage pipelined execution thatminimizes the execution time, a clock speed up to 24MHz for the STM8S and up to 72MHz for the STM32 family.They are devised to be highly energy efficient, with several low power modes, and they benefit from memory interfaces wider than the average instruction length (32- and 64-bit wide busses, respectively). This minimizes the number of accesses to the memory bus and thus the consumption related to address bus toggling and non-volatile memory read accesses. Interrupt tail chaining and the Halt/Sleep on exit modes also help avoiding unnecessary stack accesses.Finally, in terms of code density, both have excellent results, owing to the 8-bit CISC instruction set for the STM8S family and, to the 16-bit Thumb-2 mode introduced by the Cortex core for the STM32 family.This short comparison demonstrates that both processors are state-of-the-art in terms of micro-architectural features. The STM8 is at the level of legacy of 16-bit processors, and the Cortex-M3 meets the requirements of applications currently using 32-bit down to mid/high-end 16-bit MCUs. The combination of the STM8 and STM32 therefore establishes aperformance continuum, which is now also supported at tool levels by a third party offering a unified development platform for both product lines.Table 1.STM8 and STM32: core comparisonSTM8Cortex-M3Data path8-bit 32-bit Drhystone MIPS (0WS)0.29 DMIPS 1.22 DMIPS Architecture Harvard Harvard Pipeline Y es, three-stage Y es, three-stage Instruction setCISC RISC Program bus data width 32-bit32-bitPrefetch bufferY es, 2 × 32-bit, internal Y es, 2 × 64-bit, in memory interface Average instruction size 2 bytes2 bytesInterrupt type LatencyVectorized9 cycles, tail chaining supportedVectorized12 cycles, tail chaining supportedLow power modes Slow, Wait for Event or interrupts, Halt, Halt on exit Slow, Sleep (Wait for event or interrupt), Sleep on exit, Deep sleep Debug interface1-wire (SWIM)2-wires or legacy JTAGPeripherals AN2945 2 PeripheralsThe MCU peripherals (also called IPs) are another example of the ST MCU consistencyacross the 8- and 32-bit product lines: most of the basic IPs have been defined andstructured to be portable from one product family to the other. This was done by adaptingsimple, yet effective, 8-bit peripherals to the 32-bit world. It brings the benefits of cost- andpower-effective, easy to understand resources, which are complemented at system level bywider busses and a DMA controller when higher performance is needed. Once the workingprinciple of a peripheral is understood, it is applicable to both the STM8S and STM32families, thus speeding up transition between devices.Figure1 shows a simplified representation of a digital peripheral.The peripheral can be partitioned into two main blocks. First, a kernel that contains the statemachines, counters and any kind of combinatorial or sequential logic necessary to performtasks that do not need the processor, such as low-communication layers, analog front-endmanagement or timing-driven functions. If necessary, the kernel is connected to the externalworld via MCU ports. The external connection may consist of a few I/Os or complex busses.Second, the peripheral is initialized and controlled by the application through registersconnected to an internal bus shared with the other MCU resources. In 8-bit microcontrollers,the processor directly writes to and reads from registers, whereas in 32-bit products, registerread and write operations usually go through a bridge. The main difference between the twofamilies, however, lies in the internal bus specification the peripheral has to comply with.This explains why STM8S and STM32 devices are able to share peripherals: these arebased on the same kernel, and are only tailored to the two different bus interfaces. ARMprocessors and peripherals comply with the AMBA bus specification, with a 32-bit databus, 6/18 Doc ID 15468AN2945PeripheralsDoc ID 154687/18whereas STM8S devices use a simpler, yet efficient, 8-bit bus standard. From the functional point of view, they only differs by:●the register size: 8 vs. 16 or 32-bit●the maximum clock frequency that directly depends on the CPU operating speed ●the DMA that offloads the CPU from simple data management and increases the maximum data throughput●few product-specific functions, such as I/O port managementLet us consider the STM8S and STM32 SPI block diagrams shown in Figure 2. At firstglance, they look identical apart from a few differences in bits highlighted in red in Figure 2, for instance, at the level of the DMA.Now considering the register maps shown in Table 2 and Table 3, they are clearly based on the same design: apart from a few differentiating bits and the register sizes, registers and bits have similar names and locations in registers.Peripherals AN29458/18 Doc ID 15468Table 2.STM32 SPI register map and reset valuesOffsetRegister3130292827262524232221201918171615141312111098765432100x00SPI_CR1ReservedB I D I M O D EB I D I O EC R C E N C R C N E X TD F FR X O N L YS S MS S IL S B F I R S TS P EBR [2:0]M S T R C P O LC P H A Reset Value 00000000000000000x04SPI_CR2ReservedT X E I ER X N E I EE R R I ER e s e r v e d S S O ET X D M A E N R X D M A E N Reset Value 0000000x08SPI_SR ReservedB S YO V RM O D FC R C E R RU D RC H S ID ET X E R X N E Reset Value 000000100x0C SPI_DR Reserved DR[15:0]Reset Value 00000000000000000x10SPI_CRCPR Reserved CRCPOL Y[15:0]Reset Value 00000000000001110x14SPI_RXCRCR Reserved RxCRC[15:0]Reset Value 00000000000000000x18SPI_TXCRCR ReservedTxCRC[15:0]Reset Value 0000000000000x1C SPI_I2SCFGR ReservedI 2S M O DI 2S EI 2S C F GP C M S Y N C R e s e r v e dI 2S S T D C K P O LD A T LE N C H L E N Reset Value00000000000x20SPI_I2SPR ReservedM C K O EO D DI2SDIVReset Value001Table 3.STM8 SPI register map and reset valuesAddress offsetRegister name76543210x00SPI_CR1Reset value LSBFirst0SPE 0BR20BR10BR10MSTR 0CPOL 0CPHA 00x01SPI_CR2Reset value BDM 0BDOE 0CRCEN0CRCNEXT0Reserved0RXONL Y0SSM 0SSI 00x02SPI_ICR Reset value TXIE 0RXIE 0ERRIE 0WKIE 0Reserved0Reserved0Reserved0Reserved00x03SPI_SR Reset value BSY 0OVR 0MODF 0CRCERRWKUP 0ReservedTXE 1RXNE 00x04SPI_DR Reset value MSB 0-0-0-0-0-0-0LSB 00x05SPI_CRCPR Reset value MSB 0-0-0-0-0-1-1LSB 10x06SPI_RXCRCR Reset value MSB 0-0-0-0-0-0-0LSB 00x07SPI_TXCRCR Reset valueMSB 0-0-0-0-0-0-0LSB 0AN2945Peripherals Table4 lists the common peripherals, highlighting the coherency between products atregister, bit and feature level.Table 4.Peripherals shared between STM8 and STM32 devicesPeripheral namesSTM32STM8Independent watchdog (IWDG)Window watchdog (WWDG)Serial peripheral interface (SPI)Inter-integrated circuit (I2C) interfaceUniversal synchronous/asynchronous receiver/transmitter (USART)Advanced-control timers16-bit advanced-control timerGeneral-purpose timer16-bit general-purpose timersBasic timer8-bit basic timerAlthough the timers seem different with many distinct configurations, their architectureacross and within the product families is the same. There are only variations of a singletimer architecture. From the superset, sub-blocks can optionally be stripped to decrease thenumber of capture/compare channels or remove options necessary only for a few specificapplications such as motor control.Doc ID 154689/18System features AN294510/18 Doc ID 154683 System featuresToday’s MCUs are complex SoCs (systems on chip) that not only include a lot of peripherals,but also advanced-system features aiming at reducing the bill of material or enhancing the products’ safety and robustness. This is true for both 8- and 32-bit platforms.3.1 ResetAs shown in Figure 3, the STM8S and STM32 devices have the same reset circuitry, with only slight differences.The NRST pin is both an input and an open-drain output with a built-in pull-up resistor. For EMS (electromagnetic sensitivity) robustness purposes, a filter is inserted to avoid glitch propagation into the digital circuitry. There are three advantages with having a bidirectional reset:●for multi-MCU systems, bidirectional reset ensures than all subprocessors are correctly synchronized at startup or in case of a warm reset●the voltage supervisors (power-on reset and brownout reset) embedded in the MCU can also be used at system level for other ICs●it is of a great help during debugging when spurious internal resets are generatedAN2945System featuresDoc ID 1546811/183.2 ClockFrom the clock system standpoint, the two products have three main clock sources incommon, that share similar electrical characteristics. See T able 5 for details.The oscillator handles both the crystal and resonators, and is called the HSE (for high-speed external). It can also be bypassed to feed the MCU with an external clock. This isused for applications that have stringent requirements in terms of accuracy and stability, forcommunication purposes for instance.An application can run at a high frequency without an external crystal by using the HSI clock(for high-speed internal). This source has a consumption 10 times lower than the HSE and avery low percentage of accuracy error. It can also be used as a PLL input on the STM32 toincrease the internal frequency to up to 64 MHz.Finally, the low-speed internal clock (LSI) is an ultralow internal power source (a few µA),that can be permanently enabled to clock an auto-wakeup peripheral during the Halt or Stopmode. It can also clock a secondary on-board watchdog (refer to Section 3.4: Safety forfurther details), and be used as the CPU clock on the STM8 products. It is not accurate(error of a few tens of percents), but it can be measured periodically using the precise HSIclock to compensate for chip manufacturing variations or the drift due to temperature forinstance.3.3 MemoryBoth product lines are based on non-volatile memories and have an option byte loader. Thismechanism replaces the legacy fuses for MCU power-up configuration: the user can selectseveral options at programming time, which are written alongside the program binary image.Several features are available on all news microcontrollers:●Reset in Halt, Stop or Standby mode: this is to avoid a deadlock situation in case the MCU enters a low power mode by accident, for applications not designed to handlesuch a configuration●Hardware/Software watchdog, to have the possibility of starting the watchdog by hardware, right after the reset sequence●Memory readout protection, to prevent any piracy on the program content●Memory write protection, to protect part of the memory, if it contains a critical code. Usually, this applies to the boot code or an IAP (in application programming) driver Table 5.STM8S/STM32 clock source characteristics (indicative data (1))1.Refer to product datasheet for detailed electrical characteristics.System clock source FrequencyAccuracy errorConsumption STM8S STM32High-speed external (HSE)1-24 MHz 4-16 MHzCrystal dependent, down to a few tens of ppm 1 to 2 mA High-speed internal (HSI)16 MHz 8 MHz1% typical 100 to 250 µA Low-speed internal 110-146 kHz30-60kHz 20 to 50% 1 to 5 µASystem features AN2945 These options allow automatically enabled safety and robustness features, so that theapplication can recover even if a disturbance or an attack occurs before the very firstinstruction is fetched by the CPU.The STM8S and STM32 devices have an embedded boot loader, making it possiblereprogram the internal Flash memory with an on-board serial interface (the UART forinstance). Any PC with a serial COM interface can then be used as a programming tool toprogram or update the Flash and data EEPROM memory content. ST provides a softwareutility to perform all operations supported by the boot loader.3.4 SafetyThe automotive industry first pushed for increasing the reliability of MCU-based electroniccontrols. This has been followed by similar requests from the industrial segments, andhousehold appliances now have to comply with a specific standard, IEC60335-1. Both theSTM32 and STM8S devices are Class B compliant according to this standard. Complianceis obtained by using dedicated self-test libraries certified by an independent test institute,and also with the help of some specific hardware circuitry. Both the software and hardwarecontribute to significantly reduce the development and qualification time of applications withstringent functional safety requirements.●WatchdogsThe MCUs embed two watchdogs:–The Window Watchdog is intended to monitor the main loop and check that loop time is within a given time frame. It runs on the system clock.–In parallel, an independent watchdog can be activated to increase the system’s robustness This watchdog will indeed continue to operate even in the case of amain clock failure (for instance due to a broken crystal).●Clock monitoringThe standard also requires the detection of crystal failure or oscillations at harmonics/subharmonics. This is achieved using the clock system described in Section3.2: Clock,to periodically measure the external crystal or resonator frequency with the internalclock source. Finally, a clock security system (CSS) also monitors the HSE source andautomatically switches back the system clock to the internal HSI clock in case of afailure.12/18 Doc ID 15468AN2945System featuresDoc ID 1546813/183.5 L ow powerOn top of the core’s intrinsic low power modes, both the STM8S and STM32 devices areable to reduce the overall consumption at system-on-chip level.The power consumption in the Run and Wait modes can be reduced by one of the followingmeans:●Slowing down the system clocks: the consumption can thus be adjusted according to the performance required by the application. This is done using the prescalers includedin the clock controller.●Gating the clocks of the peripherals when they are not used to minimize the dynamic consumption related to the clock tree switching activity.The two products embed regulators to supply the internal logic at 1.8V . These regulatorshave a significant operating current in Run mode (a few tens of µA) where they are able todeliver currents in the mA or tens of mA range. In order to further reduce consumption, it ispossible to configure the regulator in low power mode, and minimize its quiescentconsumption, when the current necessary to supply the logic is in the µA range, typicallyduring the Halt or Stop mode. This mode offers the lowest consumption, with a wakeup timeslightly longer than the configuration using the regulator in Run mode.Software library AN294514/18 Doc ID 154684 Software libraryPeripheral compatibility throughout ST’s STM8 and STM32 MCU families promotes platformdesign and helps significantly switch from one product line to the other. When it comes todevelopment time, however, software support is essential. Extensive software libraries areavailable for both the STM8S and STM32 devices, providing the user with a hardwareabstraction layer (HAL) for all MCU resources. Moreover, there is not a single control/statusbit that is not covered by a C function or an API.The software library covers three abstraction levels, and it includes:1. a complete register address map with all bits, bit fields and registers declared in C. Byproviding this map, the software library makes the designers’ task much lighter and,even more importantly so, it gives all the benefits of a bug-free reference mapping file,thus speeding up the early project phase.2. a collection of routines and data structures in API form, that covers all peripheralfunctions. This collection can directly be used as a reference framework, since it alsoincludes macros for supporting core-related intrinsic features and common constantand data type definition. Moreover, it is compiler agnostic and can therefore be usedwith any existing or future toolchain. It was developed using the MISRA C automotivestandard.3.a set of examples covering all available IPs (85 examples so far for the STM32 family,57 for the STM8S family), with template projects for the most common developmenttoolchains. With the appropriate hardware evaluation board, only a few hours areneeded to get started with a brand new microcontroller.It is then up to you to choose how to use the library. Y ou can either pick up the files useful forthe design, use examples to get trained or quickly evaluate the product. Y ou can also usethe API to save development time.Let us now have a look at the few key files and concepts. Two separate libraries support theSTM8S and STM32F devices. In the file names below, you simply need to replace the“stmxxx_” prefix by “stm32f10x ” or “stm8s ” depending on the chosen product.●stmxxx_.hThis file is the only header file that must be included in the C source code, usually inmain.c . This file contains:–data structures and address mapping for all peripherals –macros to access peripheral register hardware (for bit manipulation for instance), plus STM8S core intrinsics – a configuration section used to select the device implemented in the targetapplication. Y ou also have the choice to use or not the peripheral drivers in theapplication code (that is code based on direct access to registers rather thanthrough API drivers)●stmxxx_conf.hThis is the peripheral driver configuration file, where you specify the peripherals youwants to use in your application, plus a few application-specific parameters such as thecrystal frequency.●stmxxx_it.cThis file contains the template IRQ handler to be filled, but this is already the firstdevelopment step!AN2945Software library Once you have understood the above operating principle and file organization, for simpleapplications, you could virtually switch from one product to the other without referring to thereference manual.Let us take a practical example: an SPI peripheral configured in master mode, used to readfrom/write to an external EEPROM.Figure4 and Figure5 below show the initialization code (using the software library) for anSTM8S and an STM32 product, respectively.Figure 4.STM8S code example/* --------------- Initialize SPI in Master mode -------------- */SPI_Init(SPI_FIRSTBIT_MSB,SPI_BAUDRATEPRESCALER_4,SPI_MODE_MASTER,SPI_CLOCKPOLARITY_LOW,SPI_CLOCKPHASE_2EDGE,SPI_DATADIRECTION_1LINE_TX,SPI_NSS_SOFT,0x07); /* CRC Polynomial *//* ------------------------- Enable SPI ----------------------- */SPI_Cmd(ENABLE);Figure 5.STM32 code example/* Private variables --------------------------------------- */SPI_InitTypeDef SPI_InitStructure;/* ---------------------- SPI1 Master ------------------------- */SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;SPI_InitStructure.SPI_Mode = SPI_Mode_Master;SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;SPI_InitStructure.SPI_CRCPolynomial = 7;SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;SPI_Init(SPI1, &SPI_InitStructure);/* ----------------------- Enable SPI1 ------------------------ */SPI_Cmd(SPI1, ENABLE);All parameters are identical, and the procedure is similar with two function calls for bothconfiguration and startup. The main difference lies in the way the parameters are passedinto the function. STM32 devices use a structure passed by address whereas, for STM8Sdevices, parameters are passed directly to minimize the amount of RAM needed during theinitialization phase (this is necessary with devices with down to 1 Kbyte of RAM).Another difference is the possibility, when using STM32 devices, of specifying the data size(8- or 16-bit) for the SPI. In the above example (Figure5), the data size is explicitly defined,however, the library is done so that it can be omitted: if this field is not initialized in thestructure, the 8-bit data size is used by default to maintain compatibility with STM8Sdevices.Doc ID 1546815/18Conclusion AN2945 5 ConclusionThis application note discusses the points that ease the transition from the 8-bit STM8S tothe 32-bit STM32 devices, and vice versa. Based on the 8- to 32-bit core performancecontinuum, the new STM32 and STM8S MCU families have a lot of common features. At theperipheral level, they share standard IPs like timers and communication interfaces. At thesystem level, they have identical features, reducing the external component count (clock andreset systems, safety features, etc).These common features are complemented by a set of software libraries that come as amajor help to get started for new development. The libraries can also serve as foundationsfor a unified development platform supporting both 8- and 32-bit MCUs owing to theabstraction level they both offer.Finally, the common features of the STM8S and STM32 devices with the benefits of theirsoftware libraries maximize design re-use and decrease time to market, specially if theapplication has derivatives with various requirements in terms of processing power,connectivity or control function complexity.16/18 Doc ID 15468AN2945Revision history Doc ID 1546817/186 Revision historyTable 6.Document revision history DateRevision Changes28-Jul-20091Initial release.AN2945Please Read Carefully:Information in this document is provided solely in connection with ST products. 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All other names are the property of their respective owners.© 2009 STMicroelectronics - All rights reservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America18/18Doc ID 15468 Rev 1。