M B芯片手册中文版

屏幕显示控制的专用标准产品CMOS屏幕显示控制芯片——MB900921.描述MB90092是用于显示控制视频中的文字和图像的视频显示控制芯片，内部集成了显示内存(VRAM)、外挂字库接口和视频信号发生器，其外部只需连接少量的电子元件就可以显示汉字和图形。

MB90092提供两种屏幕叠加方法，分别称为“主屏”和“副屏”，二者可单独或相互重叠出现在监视器上。

主屏由12行24个字符组成，允许设置每个字符的数据。

副屏由12行24个字符组成或最多达到16行24个字符。

数据不仅可以在前期配置的每行中被设置，也可以集中地在后期配置的整个屏幕中被设置。

MB90092所支持的字符为24×32点阵的普通字符和8×32点阵的图形字符，这些字符单元可以任意八种不同的颜色显示。

如果主屏中只有图形字符，则有192×384个像素点，在同样的情况下，副屏有192×384个像素点或256×512个像素点。

（实际显示屏由水平方向的像素点的时钟频率和电视系统垂直方向的一定光栅数决定。

）MB90092把RAM作为字库内存，能够显示自由图形。

MB90092总共能够使用16384种类型的字符，包括普通字符和图形字符。

它能够控制外部16M bits的字库内存。

对于视频信号的输出，MB90092具有合成视频信号，Y/C分离视频信号，RGB数字信号输出引脚。

MB90092还具有视频信号输入引脚，允许重叠显示任意一种复合视频信号和Y/C分离视频信号。

2.封装80个引脚的PQFP封装3.特性3.1主屏显示•屏幕显示能力：24字符×12行（达到288字符）•字符点配置：24×32点（每个字符）•字符类型：16384种字符（当使用16M比特的外部时钟）•字符大小：标准，双宽度，双高度，双宽度×双高度，四倍宽度×双高度（每行可设置）•显示位置控制：水平显示位置：1/3字符单元设置垂直显示位置：光栅单元设置行空间控制：光栅单元设置（0~15光栅）•显示优先级控制：副屏显示控制优先级的能力3.2副屏显示屏幕显示位置：可设置的水平和垂直为2个点单元•普通屏幕模式：屏幕显示能力：32字符×12行（达到384字符）56×384点（仅限图形字符）（实际显示屏幕由电视系统和点时钟频率决定）。

RESET and Initialization ProcedureTo ensure proper device function, the power-up and reset initialization default values for the following mode register (MR) settings are defined as:•Gear-down mode (MR3 A[3]): 0 = 1/2 rate •Per-DRAM addressability (MR3 A[4]): 0 = disable •Maximum power-saving mode (MR4 A[1]): 0 = disable •CS to command/address latency (MR4 A[8:6]): 000 = disable •CA parity latency mode (MR5 A[2:0]): 000 = disable •Hard post package repair mode (MR4 A[13]): 0 = disable •Soft post package repair mode (MR4 A[5]): 0 = disablePower-Up and Initialization SequenceThe following sequence is required for power-up and initialization:1.Apply power (RESET_n and TEN should be maintained below 0.2 × V DD while sup-plies ramp up; all other inputs may be undefined). When supplies have ramped to a valid stable level, RESET_n must be maintained below 0.2 × V DD for a minimum of t PW_RESET_L and TEN must be maintained below 0.2 × V DD for a minimum of 700μs. CKE is pulled LOW anytime before RESET_n is de-asserted (minimum time of 10ns). The power voltage ramp time between 300mV to V DD,min must be no greater than 200ms, and during the ramp, V DD must be greater than or equal to V DDQ and (V DD - V DDQ ) < 0.3V . V PP must ramp at the same time or up to 10 minutes prior to V DD , and V PP must be equal to or higher than V DD at all times. The total time for which V PP is powered and V DD is unpowered should not exceed 360 cu-mulative hours. After V DD has ramped and reached a stable level, RESET_n must go high within 10 minutes. After RESET_n goes high, the initialization sequence must be started within 3 seconds. For debug purposes, the 10 minute and 3 sec-ond delay limits may be extended to 60 minutes each provided the DRAM is oper-ated in this debug mode for no more than 360 cumulative hours.During power-up, the supply slew rate is governed by the limits stated in the table below and either condition A or condition B listed below must be met.Table 5: Supply Power-up Slew RateNote: 1.20 MHz band-limited measurement.•Condition A:–Apply V PP without any slope reversal before or at the same time as V DD and V DDQ .8Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization ProcedureTable 4: State Diagram Command DefinitionsNote: 1.See the Command Truth Table for more details.8Gb: x4, x8, x16 DDR4 SDRAM State DiagramFunctional DescriptionThe DDR4 SDRAM is a high-speed dynamic random-access memory internally config-ured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devi-ces, and as eight banks for each bank group (2 bank groups with 4 banks each) for x16devices. The device uses double data rate (DDR) architecture to achieve high-speed op-eration. DDR4 architecture is essentially an 8n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for a device module effectively consists of a single 8n -bit-wide, four-clock-cycle-data transfer at the internal DRAM core and eight corresponding n -bit-wide, one-half-clock-cycle data transfers at the I/O pins.Read and write accesses to the device are burst-oriented. Accesses start at a selected lo-cation and continue for a burst length of eight or a chopped burst of four in a program-med sequence. Operation begins with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BG[1:0]select the bank group for x4/x8, and BG0 selects the bank group for x16; BA[1:0] select the bank, and A[17:0] select the row. See the Addressing section for more details). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst operation, determine if the auto PRECHARGE command is to be issued (via A10), and select BC4 or BL8 mode on-the-fly (OTF) (via A12) if enabled in the mode register.Prior to normal operation, the device must be powered up and initialized in a prede-fined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation.NOTE: The use of the NOP command is allowed only when exiting maximum power saving mode or when entering gear-down mode.8Gb: x4, x8, x16 DDR4 SDRAM Functional Description。

i s c l a i me r : T h i s d o c u m e n t a t i o n i s n o t i n t e n d e d a s a s u b s t i t u t ef o r a n d i s n o t t o b e u s e d f o r d e t e r m i n i ng s u i t a b i l i t y o r r e l i a b i l i t y o f th e s e p r o d u c t s f o r s p e ci f i c u s e r a p p l i c a t i o n sMainRange of productModicon M171/M172Product or component typeProgrammable controllers Product specific applicationHVAC and pumping solution VariantProgrammable Number of inputs/outputs42Discrete input number12Discrete output number 2 for relay outputs SPST with same common2 for relay outputs SPST with independent common2 for relay outputs SPDT with same common3 for relay outputs SPST with independent commonDiscrete output current 1 A for relay SPDT3 A for relay SPSTAnalogue input number12 configurable by pair ComplementaryNumber of port 1 CAN port - screw terminal block1 USB type A - USB type A female1 USB type mini B - USB device port Mini-B2 RS485 - screw terminal block (Modbus serial link or BACnet MS/TP)1 Ethernet - RJ45 (Modbus TCP and BACnet IP with webserver)Input/Output number 12 analog input(s)6 analog output(s)12 digital input(s)12 digital output(s)Discrete input logic Sink or source (positive/negative)Discrete input voltage 24 V AC/DCDiscrete input current 2.5 mAInput impedance 20 kOhmAnalogue input type Direct inputImpedance 0...1500 hOhmImpedance 0...300 daOhmVoltage 0...5 V (absolute or ratiometric)Power consumption in W15 W at 24 V AC/DCRealtime clock Built-in realtime clock at -20...60 °CDisplay type Without displayOvervoltage category IILocal signalling 1 LED red programmable1 LED yellow programmable1 LED green programmable1 LED green powerMounting support DIN railPanel mounting with accessoryWidth144 mmHeight110 mmDepth60.5 mmProduct weight0.385 kgEnvironmentDirectives2006/95/EC - low voltage directive1907/2006/EC - REACH directive2011/65/EU - RoHS directive86/188/EEC - physical agents (noise) directiveStandards EN/IEC 60730Product certifications CECSA (pending)cURus (pending)EAC (pending)Ambient air temperature for operation-20...60 °C conforming to UL 60730-1-20...65 °C with derating conforming to UL 60730-1Ambient air temperature for storage-30...70 °CRelative humidity 5...95 % non-condensingIP degree of protection IP20Pollution degree2Offer SustainabilitySustainable offer status Not Green Premium productRoHS (date code: YYWW)Compliant - since 1530 - Schneider Electric declaration of conformitySchneider Electric declaration of conformityREACh Reference not containing SVHC above the thresholdReference not containing SVHC above the thresholdDIN Rail MountingClips for Panel MountingPanel MountingIncorrect Mounting PositionAssembling a ModuleWiring Sections and Torque A, C, D, E, F, G, HBLogic Controller ConnectorsPower Supply(1)Type T fuse 2 ADigital InputsThe COM_DI terminals are not connected internally. Fast Digital InputsPulse / Frequency counter up to 2 kHz.The Cx terminals are not connected internally.Analog Inputs(1)(CN5 + CN13) Max. current: 50 mA.(2)(CN5 + CN13) Max. current: 150 mA.Analog OutputsAO3, AO4 can be used also as PWM generator, up to 2 kHz.RS 485 - Modbus SL or BACnet MS/TPApply 120 Ω terminal resistance.。

V REFDQ CalibrationThe V REFDQ level, which is used by the DRAM DQ input receivers, is internally gener-ated. The DRAM V REFDQ does not have a default value upon power-up and must be set to the desired value, usually via V REFDQ calibration mode. If PDA or PPR modes (hPPR or sPPR) are used prior to V REFDQ calibration, V REFDQ should initially be set at the midpoint between the V DD,max , and the LOW as determined by the driver and ODT termination selected with wide voltage swing on the input levels and setup and hold times of ap-proximately 0.75UI. The memory controller is responsible for V REFDQ calibration to de-termine the best internal V REFDQ level. The V REFDQ calibration is enabled/disabled via MR6[7], MR6[6] selects Range 1 (60% to 92.5% of V DDQ ) or Range 2 (45% to 77.5% of V DDQ ), and an MRS protocol using MR6[5:0] to adjust the V REFDQ level up and down.MR6[6:0] bits can be altered using the MRS command if MR6[7] is disabled. The DRAM controller will likely use a series of writes and reads in conjunction with V REFDQ adjust-ments to obtain the best V REFDQ , which in turn optimizes the data eye.The internal V REFDQ specification parameters are voltage range, step size, V REF step time, V REF full step time, and V REF valid level. The voltage operating range specifies the minimum required V REF setting range for DDR4 SDRAM devices. The minimum range is defined by V REFDQ,min and V REFDQ,max . As noted, a calibration sequence, determined by the DRAM controller, should be performed to adjust V REFDQ and optimize the timing and voltage margin of the DRAM data input receivers. The internal V REFDQ voltage value may not be exactly within the voltage range setting coupled with the V REF set tolerance;the device must be calibrated to the correct internal V REFDQ voltage.Figure 65: V REFDQ Voltage RangeV DDQV REF rangeV SWING smallV SWING large System variance Total rangeV REF ,maxV REF,min4Gb: x4, x8, x16 DDR4 SDRAM V REFDQ CalibrationFigure 92: Self Refresh Exit with NOP Command&.BW&.BF &.(2'7&RPPDQG $''5&6BQ'RQ¶W &DUH 4Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation。

User ManualV1.4 M aster Series Embedded SystemIntel ® Apollo Lake ProcessorsEfficient, Versatile, and Rugged & ReliablePREFACECopyright NoticeCopyright © 2016-2020 MiTAC Computing Technology Corporation (MiTAC Group). No part of this document may be reproduced, copied, translated, or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the prior written permission of MiTAC Corp., Ltd. All information and specification provided in this manual are for reference only and remain subject to change without prior notice.DisclaimerWe reserve the right to make changes, without notice, to any product, including circuits and/or software described or contained in this manual in order to improve design and/or performance. We assume no responsibility or liability for the use of the described product(s) conveys no license or title under any patent, copyright, or masks work rights to these products, and make no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described in this manual are for illustration purposes only. We make no representation or guarantee that such application will be suitable for the specified use without further testing or modification.Declaration of ConformitySafety InformationSafety PrecautionsFor your safety, please carefully read all the safety instructions before using the device. All cautions and warnings on the equipment should be noted. Keep this user manual for future reference.*Let service personnel to check the equipment in case any of the following problems appear:⏹The power cord or plug is damaged.⏹Liquid has penetrated into the equipment.⏹The equipment has been exposed to moisture.⏹The equipment does not work well or you cannot get it to work according to the user manual.⏹The equipment has been dropped and damaged.⏹The equipment has obvious signs of breakage on the surface.Ordering InformationPacking ListOptional Xpansion Modules MS-01DVI-D10MS-01DPN-D10MS-02COM-D10MS-08DIO-T10CONTENTSPREFACE (2)CHAPTER 1: INTRODUCTION (8)1.1 Overview (8)1.2 Product Features (8)1.3 Hardware Specification (9)1.4 Mechanical Specification (12)1.5 System I/O Placement (13)CHAPTER 2: DIP SWITCH SETTING AND PIN DEFINITION (16)2.1 DIP Switch and Connector Overall Placement (16)2.2 DIP Switch Setting (18)2.3 Connector Pin Definition (19)CHAPTER 3: SYSTEM SETUP (26)3.1 2.5” SATA HDD/SSD Installation (26)3.2 WiFi module Installation (27)3.3 DRAM Installation (28)CHAPTER 4: BIOS SETUP (31)4.1 Main Page (31)4.2 Advance Page (33)4.3 Security Page (42)4.4 Boot Page (46)4.5 Save & Exit Page (47)INTRODUCTIONThis chapter provides the MB1-10AP EmbeddedSystem product overview, including features, hardware and mechanical specifications. 1CHAPTER 1: INTRODUCTIONThis chapter provides the MB1-10AP Embedded System product overview, including features, hardware, mechanical specifications, and I/O placement.1.1 OverviewMiTAC’s MB1-10AP embedded system is the next generation embedded system with Intel® Apollo Lake embedded processor. The efficient performance, OCP/OVP power protection, and expandable design provide the solution for routine tasks and most types of application.1.2 Product FeaturesMB1-10AP Embedded System offers the following features:⏹Intel® Apollo Lake-M N3350/N4200 Processors⏹Support 2 x PoE LAN (Optional)⏹Support HDMI as primary display, and VGA/DisplayPort/DVI-D as second option⏹Fan-less chassis and Expandable module design⏹Support COM/DIO via Xpansion Modules⏹8-24V Wide Power Voltage⏹-25°C to 70°C (For non-PoE SKU, with 0.7m/s Air Flow and Wide TemperatureMemory/Storage)-25°C to 60°C (For PoE SKU, with 0.7m/s Air Flow and Wide TemperatureMemory/Storage)1.3 Hardware Specification*Notes1: Installation in Restricted Access Location (RAL)A restricted access location is a designated area within an incident area (High or Low temperature environment)With authorized people can enter for a period of time and for a specific purpose.1.Access can only be gained by service people or by users who have beeninstructed about the reasons for the Restrictions applied to the location and about any precautions that shall be taken.2.Access is through the use of a tool or lock and key, or other means ofsecurity, and is controlled by the authority Responsible for the location.*Notes2: Please make sure that the power consumption is in the spec of the power supply output capability from AC adaptor (72W or 120W). Please choose the suitable AC adaptor for your application.AC/DC 24V/5A, 120W 3PIN Terminal Block Power Adaptor (For PoE SKU)AC/DC 24V/3A, 72W 3PIN Terminal Block Power Adaptor (For non-PoE SKU)*Note3: Please choose 120W AC adaptor for the Optional Xpansion Module (MS-02COM-D10) COM ports in maximum power loading scenario (12V max. 1A loading).*Note4: Please don’t load the COM power in the hardware configuration and high temperature condition. Don’t operate the machine at maximum operating temperature 70℃(Non-PoE SKU) & 60℃(PoE SKU) with 4*COM 12V*1A loading.*Note 5: The maximum ambient operating temperature is 40°C if the external AC adapter model: EA11011M or EA10681V will be placed in thesame high temperature area with the embedded system.*Note 6: CAUTION - Lithium battery is included in this embedded system. Please do not puncture, mutilate, or dispose of battery in fire. There will be danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by manufacturer. Dispose of used battery according to manufacturer instructions and in accordance with your local regulations.*Note 7: CAUTION - Only allow technically qualified personnel to touch the I/O surface, and only when the unit is well fastened by wall mount, VESA mount, or DIN Rail mount. Please also avoid to contact the I/O surface more than 1 second in high temperature and harsh environment. Not allow to touch aluminum alloy surface at high temperature. The technically qualified personnel also needs to have technical knowledge, operating experiences, and basic knowledge about MB1-10AP product spec.1.4 Mechanical SpecificationMechanical Dimension: 170 mm x 105 mm x 57 mm1.5 System I/O Placement⏹Front I/O:⏹Rear I/O:Xpansion Module (Optional) ConfigurationDIP SWITCH SETTING AND PIN DEFINITIONThis chapter provides information about how to set up thedip switch and use I/Os of MB1-10AP Embedded System hardware. 2CHAPTER 2: DIP SWITCH SETTING AND PIN DEFINITIONThis chapter provides information about how to set up the dip switch, and use internal I/Os of MB1-10AP Embedded System hardware.2.1 DIP Switch and Connector Overall PlacementFront View:Bottom View:2.2 DIP Switch Setting⏹Location #B6ATATX A SW_ATX1CAdd this table in silkscreen TXTDefault ATX mode⏹ Location #B7/B8/B9/B102.3 Connector Pin Definition⏹ Indicator for Realtek RTL8154B LAN⏹ Location #B4 – SATA and SATA PWR Connector3-pin terminal block for DC Input⏹2-pin Remote Power On/Off HeaderMB Side Connector: Molex 151064-0152Suggestive Cable Side Plug: Molex 151100-0002⏹COM1 and COM2 on M/BMB COM1 and COM2 RS232, RS422, RS485 setting is at BIOS setup menuMS-02COM-D10 (Optional)Xpansion Module with 2 x RS232/422/485 (Non-isolation)Support 5V/12V DC Power OutputNotes: Don't support Power HOT switch at SW_PW3 and SW_PW4 in Xpansion Module Below is Xpansion Module with COM3 and COM4: See the power RS232 setting as below table:Default setting is RI signal at A location from SW_RI3 and SW_RI4Power COM setting with RI signal: Default settingSET at A location from SW_RI3 and SW_RI4SET at A location from SW_PW3 and SW_PW4Power 5V setting:SET at C location from SW_RI3 and SW_RI4 SET at A location from SW_PW3 and SW_PW4Power 12V setting:SET at C location from SW_RI3 and SW_RI4 SET at C location from SW_PW3 and SW_PW4Power 12V setting: Change at C location from SW_RI3 and SW_RI4 and at C location from SW_PW3 and SW_PW4MS-08DIO-T10 (Optional)Xpansion Module with 8-bit Optical Isolation DIDO (4 x DI, 4 x DO)SYSTEM SETUPThis chapter provides information about how to set up the MB1-10AP Embedded System hardware installation. 3CHAPTER 3: SYSTEM SETUPThis chapter provides information about how to set up the MB1-10AP Embedded System hardware installation.3.1 2.5” SATA HDD/SSD InstallationPlease follow the instructions to install SATA HDD as below. - Loosen 6 screws from Bottom cover as the arrow locations- Loosen 4 screws as the arrow directions-Move HDD tray as arrow direction-Lift HDD tray about 45 degrees and draw it out-Install 2.5”HDD to the HDD tray3.2 WiFi module Installation-Use mPCIe extension bracket which is in accessories kit to fix half size mPCIe wifi module, and install to the full size mPCIe slot3.3 DRAM Installation-Loosen 4 screws from MB (2 screws from front & rear cover)-Draw the MB sub-assembly out from top cover as arrow direction-Remove the film from top cover & install DIMM to MBBIOS SETUPThis chapter provides information about how to set up BIOS and use BIOS menu items to adjust basic function settings. 4CHAPTER 4: BIOS SETUPThis chapter provides information about how to set up BIOS and use BIOS menu items to adjust basic function settings.4.1 Main Page4.2 Advance Page4.2.1 Intel(R) I210 Gigabit Network Connection4.2.2 Trusted Computing4.2.3 NCT6116D Super IO Configuration4.2.4 Hardware Monitor4.2.5 S5 RTC Wake Setting4.2.6 CPU Configuration4.3 Security Page4.3.1 Secure Boot4.3.2 BIOS Update4.4 Boot Page4.5 Save & Exit Page。

PROGRAM PAGE (80h-10h)The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache reg-ister, and moves the data from the cache register to the specified block and page ad-dress in the array of the selected die (LUN). This command is accepted by the die (LUN)when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busywith a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).To input a page to the cache register and move it to the NAND array at the block andpage address specified, write 80h to the command register. Unless this command hasbeen preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80hto the command register clears all of the cache registers' contents on the selected target.Then write n address cycles containing the column address and row address. Data inputcycles follow. Serial data is input beginning at the column address specified. At any timeduring the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR IN-TERNAL DATA INPUT (85h) commands may be issued. When data input is complete,write 10h to the command register. The selected LUN will go busy(RDY = 0, ARDY = 0) for t PROG as data is transferred.To determine the progress of the data transfer, the host can monitor the target's R/B#signal or, alternatively, the status operations (70h, 78h) may be used. When the die(LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.In devices that have more than one die (LUN) per target, during and following inter-leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) commandmust be used to select only one die (LUN) for status output. Use of the READ STATUS(70h) command could cause more than one die (LUN) to respond, resulting in bus con-tention.The PROGRAM PAGE (80h-10h) command is used as the final command of a two-planeprogram operation. It is preceded by one or more PROGRAM PAGE TWO-PLANE(80h-11h) commands. Data is transferred from the cache registers for all of the ad-dressed planes to the NAND array. The host should check the status of the operation byusing the status operations (70h, 78h).When internal ECC is enabled, the duration of array programming time is t PROG_ECC.During t PROG_ECC, the internal ECC generates parity bits when error detection is com-plete.Figure 44: PROGRAM PAGE (80h-10h) OperationPROGRAM PAGE CACHE (80h-15h)The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to acache register; copies the data from the cache register to the data register; then movesthe data register contents to the specified block and page address in the array of the se-lected die (LUN). After the data is copied to the data register, the cache register is availa-READ FOR INTERNAL DATA MOVE (00h-35h)The READ FOR INTERNAL DATA MOVE (00h-35h) command is functionally identical to the READ PAGE (00h-30h) command, except that 35h is written to the command regis-ter instead of 30h.Though it is not required, it is recommended that the host read the data out of the de-vice to verify the data prior to issuing the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command to prevent the propagation of data errors.If internal ECC is enabled, the data does not need to be toggled out by the host to be corrected and moving data can then be written to a new page without data reloading,which improves system performance.Figure 50: READ FOR INTERNAL DATA MOVE (00h-35h) OperationCycle typeI/O[7:0]RDYFigure 51: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h)Cycle type I/O[7:0]RDYI/O[7:0]RDY4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemoryInternal Data Move OperationsFigure 62: PROGRAM/ERASE Issued to Locked BlockR/B#I/OxtLocked blockREAD STATUSBLOCK LOCK READ STATUS (7Ah)The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection status of individual blocks. The address cycles have the same format, as shown below,and the invert area bit should be set LOW. On the falling edge of RE# the I/O pins output the block lock status register, which contains the information on the protection status of the block.Table 20: Block Lock Status Register Bit DefinitionsFigure 63: BLOCK LOCK READ STATUSBLOCK LOCK READ STATUSBlock addressCLECE#WE#ALERE#I/Ox4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemoryBlock Lock FeatureOTP DATA READ (00h-30h)To read data from the OTP area, set the device to OTP operation mode, then issue the PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area whether the area is protected or not.To use the PAGE READ command for reading data from the OTP area, issue the 00h command, and then issue five address cycles: for the first two cycles, the column ad-dress; and for the remaining address cycles, select a page in the range of 02h-00h-00h through 1Fh-00h-00h. Lastly, issue the 30h command. The PAGE READ CACHE MODE command is not supported on OTP pages.R/B# goes LOW (t R) while the data is moved from the OTP page to the data register. The READ STATUS (70h) command is the only valid command for reading status in OTP op-eration mode. Bit 5 of the status register reflects the state of R/B# (see Status Opera-tions).Normal READ operation timings apply to OTP read accesses. Additional pages within the OTP area can be selected by repeating the OTP DATA READ command.The PAGE READ command is compatible with the RANDOM DATA OUTPUT (05h-E0h)command.Only data on the current page can be read. Pulsing RE# outputs data sequentially.Figure 68: OTP DATA READWE#CE#ALECLERE#R/B#I/OxNote: 1.The OTP page must be within the 02h–1Fh range.4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory One-Time Programmable (OTP) OperationsFigure 77: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUTR/B#I/Ox4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemoryTwo-Plane Operations。

Table 116: Single-Ended Output Slew RateNotes: 1.SR = slew rate; Q = query output; se = single-ended signals.2.In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a bytelane:•Case 1 is defined for a single DQ signal within a byte lane that is switching into a cer-tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig-nals in the same byte lane are static (they stay at either HIGH or LOW).•Case 2 is defined for a single DQ signal within a byte lane that is switching into a cer-tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig-nals in the same byte lane are switching into the opposite direction (from LOW-to-HIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into theopposite direction, the standard maximum limit of 9 V/ns applies.Differential OutputsTable 117: Differential Output LevelsNote: 1.The swing of ±0.3 × V DDQ is based on approximately 50% of the static single-ended out-put peak-to-peak swing with a driver impedance of R ZQ /7 and an effective test load of 50˖ to V TT = V DDQ at each differential output.Using the same reference load used for timing measurements, output slew rate for fall-ing and rising edges is defined and measured between V OL,diff(AC) and V OH,diff(AC) for dif-ferential signals.Table 118: Differential Output Slew Rate Definition8Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Measurement LevelsElectrical Characteristics – Overshoot and Undershoot Specifications Address, Command, and Control Overshoot and Undershoot Specifications Table 111: ADDR, CMD, CNTL Overshoot and Undershoot/SpecificationsFigure 229: ADDR, CMD, CNTL Overshoot and Undershoot DefinitionDD absolute MAX DD absolute MAXSSV o l t s (V )V DD V SS 8Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – Overshoot and Undershoot Specifi-cationsData, Strobe, and Mask Overshoot and Undershoot SpecificationsTable 113: Data, Strobe, and Mask Overshoot and Undershoot/ SpecificationsFigure 231: Data, Strobe, and Mask Overshoot and Undershoot DefinitionDDQ absolute MAX SSQ absolute MIN DDQ absolute MAXSSQ MIN and V o l t s (V )V DDQ V SSQ Electrical Characteristics – AC and DC Output Measurement Levels Single-Ended OutputsTable 114: Single-Ended Output Levels8Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Measurement Levels。

技密AA (工MCUB板使用说明书第1页, 共22页MCUB板使用说明书目录一．MCUB板硬件介绍‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥（2）1、系统组成‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥（2）2、串行通讯模块‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥（3）3、小键盘‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥（3）二、MCUB板外围设备的组成‥‥‥‥‥‥‥‥‥‥‥‥（12）三、MCUB板的性能规格‥‥‥‥‥‥‥‥‥‥‥‥‥‥（12）四、MCUB板输入电源规格‥‥‥‥‥‥‥‥‥‥‥‥‥（13）五、MCUB板的环境规格‥‥‥‥‥‥‥‥‥‥‥‥‥‥（13）六、MCUB板I/O输入规格‥‥‥‥‥‥‥‥‥‥‥‥‥（13）七、MCUB板I/O输出规格‥‥‥‥‥‥‥‥‥‥‥‥‥‥（14）八、MCUB板的外部配线及连接座规格‥‥‥‥‥‥‥‥‥（14）一、MCUB板硬件介绍1、系统组成。

微机MCUB是一块具有高集成度的微机板，集成了电梯中的变频控制，逻辑控制，串行通讯等3大功能，完全替代了GVF-Ⅲ电梯中VG7S、FMT、SCL-A这三个模块。

MCUB板由32位逻辑控制CPU、8位串行通讯CPU、16位变频核心控制和变频管理控制CPU、程序存储器、输入输出、串行通讯口、CAN控制口、PC通讯口和小键盘及数码显示等模块组成。

其外观图（图一）及各部分名称如下所示：（3）（2）（1）（29）（28）（27）（4）（5）（26）（6）（25）（7）（24）（8）3）（13）（23）（9）（22）（10）（21）（11）（20）（19）（12）（13）（14）（15）（16）（17）（）图一（1）主微机68376（2）串行程序在线升级接口：CN302（3）管理DSP在线升级接口：CN4（4）功率模块插接口：CN2（5）功率模块插接口：CN1（6）同步电机编码器扩展接口：CN9（7）核心DSP在线升级接口：CN5（8）变频器操作面板键盘插口：CN3（9）RS232接口：CN12（10）异步电机旋转编码器接口：CN11（11）并联、群控和小区遥监RS485通讯接口：FR（12）板载＋24V继电器：10TZ（13）板载＋48V继电器：15BX（型号：MY4）（14）板载＋48V继电器：50B（型号：MY4）（15）运行接触器驱动端子：Z10（16）抱闸接触器驱动端子：Z15B（17）板载＋48V继电器：40D （型号：MY4）（18）板载＋48V继电器：100R（型号：MY4）（19）板载＋24V继电器：Z100R（20）＋48V信号输出接口：FE（21）＋24V信号输出接口：FD（22）上行强迫减速开关输入接口：SDSU（23）下行强迫减速开关输入接口：SDSD（24）＋48V信号输入接口：FC（25）＋48V信号输入接口：FB（26）＋48V信号输入接口：FA（27）串行通讯接口：SCL（28）小键盘(3键)（29）七段LED显示（3位）2、通讯模块。

Programmable Preamble Modes and DQS PostamblesThe device supports programmable WRITE and READ preamble modes, either the nor-mal 1t CK preamble mode or special 2t CK preamble mode. The 2t CK preamble modeplaces special timing constraints on many operational features as well as being suppor-ted for data rates of DDR4-2400 and faster. The WRITE preamble 1t CK or 2t CK modecan be selected independently from READ preamble 1t CK or 2t CK mode.READ preamble training is also supported; this mode can be used by the DRAM con-troller to train or "read level" the DQS receivers.There are t CCD restrictions under some circumstances:•When 2t CK READ preamble mode is enabled, a t CCD_S or t CCD_L of 5 clocks is notallowed.•When 2t CK WRITE preamble mode is enabled and write CRC is not enabled, a t CCD_Sor t CCD_L of 5 clocks is not allowed.•When 2t CK WRITE preamble mode is enabled and write CRC is enabled, a t CCD_S or t CCD_L of 6 clocks is not allowed.WRITE Preamble ModeMR4[12] = 0 selects 1t CK WRITE preamble mode while MR4[12] = 1 selects 2t CK WRITEpreamble mode. Examples are shown in the figures below.Figure 111: 1t CK vs. 2t CK WRITE Preamble Mode2t CK Mode1t CK Mode8Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS PostamblesFigure 198: Consecutive WRITE (BC4-Fixed) with 1t CK Preamble and Write CRC in Same or DifferentBank GroupCommand CK_t CK_cDQS_t,DQS_c Don’t CareTransitioning Data Bank Group Address Address DQ x4,BC = 4 (Fixed)DQ x8/X16,BC = 4 (Fixed)Notes: 1.BC4-fixed, AL = 0, CWL = 9, Preamble = 1t CK, t CCD_S/L = 5t CK.2.DI n (or b ) = data-in from column n (or column b ).3.DES commands are shown for ease of illustration; other commands may be valid atthese times.4.BC4 setting activated by MR0[1:0] = 10 during WRITE commands at T0 and T5.5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,DM = Disable.6.The write recovery time (t WR) and write timing parameter (t WTR) are referenced fromthe first rising clock edge after the last write data shown at T16.8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation。

概 要l电压输入： 1.8V~3.3Vl工作环境温度：-40℃ to +105℃l处理器： ARM Cortex-M4处理器核心§Cortex-M4F内核，主频高达20MHz§SWD/JTAG仿真调试接口l存储器§160K字节SRAM§4Kbits eFuse§512K字节的Flash闪存l Bluetooth§支持蓝牙5.0核心规范§最大射频数据速率：1Mbps§最大发射功率：7.5dBm§接收灵敏度：-96 dBm@1Mbps§支持多种低功耗状态§支持 GAP, ATT/GATT, SMP, L2CAP §支持蓝牙Meshl丰富的外设§8 x GPIO，Key Scan§ 1 x SPI，2 x I2C§ 5 x PWM§ 2 x UART§IR transceiver§400ksps, 12bit, 4 channel ADC§Low power RTC 接口和尺寸§保持与同类封装模组的引脚兼容性§板载PCB天线§13.5mm x 24.8mm(不含金手指部分)§金手指：2.5mm x 13.73mml丰富的配套软件§支持MXOS自主操作系统§支持天猫精灵蓝牙Mesh接入§支持庆科VBS9010（智家精灵）蓝牙Mesh系统接入 §提供各种典型应用的可量产固件l典型应用§智能家电§智能电工，如插座，排插§特别适合照明类应用，耐高温l订货代号订货代号 说明EMB1087-PZG7 板载PCB天线，-40°C~105°CEMB1087 BLE物联网模组内置超低功耗Cortex-M4F BLE MCUBT 5.0核心规范、超高集成度、丰富的外设，高温环境适用 版本：1.1 日期：2020-08-26 编号：DS0168CN!"#$%&例如 EMB 1 08 7 -P Z G 7 -xxx 产品系列EMB=物联网蓝牙模组产品类型1 = 焊接类无线模组典型目标应用和功能08= 物联网数据应用，8系列主控处理器外形尺寸，增强功能7 = 13.5mm x 24.8mm(不含金手指部分) 10Pin 金手指接口射频接口P = 板载2.4GHz PCB天线PSRAM容量(可选)Z = 不含PSRAMJ = 4M字节的PSRAMFlash容量G = 512K字节的Flash存储工作温度7 = 工业级温度范围，-40°C~105°C可选项TR = 卷带包装（默认使用托盘）如需了解所有相关特性清单（如包装，最小订单量等）和其他方面的信息，请联系就近MXCHIP销售点和代理商。

这片说明文档以下两种型号MCU∙ FM8PS53E : EPROM device （OPT ） ∙ FM8PS53 : Mask ROM device （掩膜）功能特性∙ 只有42个单字指令∙ 除分支指令为两个周期指令以外其余为单周期指令 ∙ PC 寻址范围为13-bit∙ GOTO 指令能跳转到所有的ROM/EPROM 地址空间 ∙ 子程序能返回到所有的ROM/EPROM 地址空间 ∙ 能处理8位数据 ∙ 5级硬件堆栈∙ 运行速度: DC-20 MHz 工作频率∙ ∙ 一个带8位预置器的8位定时/计数器（Timer0)） ∙ 内部上电复位∙ 内含一个低电压检测电路供掉电复位使用∙ 上电复位计数器（PWRT ）和振荡启动计数器（Oscillator Start-up Timer OST ） ∙ 内部振荡器集成了一个看门狗保证了可靠的操作同时软件使能看门狗操作 ∙ 两类双向输入输出I/O 口IOA 和 IOB∙ 通过编程控制I/O 端口的上拉/下拉、开路等状态∙ 一个内部计数中断源；两个外部中断源：INT 管脚,PortB 的输入改变 ∙ 通过INT 管脚或者PortB 的输入改变来实现睡眠唤醒 ∙ 省电睡眠模式∙ 内部有8MHz, 4MHz, 1MHz, 和 455KHzRC 振荡器 ∙ 有可靠的保证使得程序代码不被读出。

∙ 内部RC 振荡器∙ 提供以下振荡源的选择：- ERC: External Resistor/Capacitor Oscillator （外部的RC 振荡器）- IRC/ERIC: Internal or External Resistor/Internal Capacitor Oscillator –（内部电阻内部的电容RC 振荡器或外部的电阻内部的电容RC 振荡器）HF: High Frequency Crystal/Resonator Oscillator （高频率的晶体协振器） LF: Low Frequency Crystal Oscillator （低频率的晶体振荡器） ∙ 工作电压范围：- EPROM : 2.3V - 5.5V - ROM : 2.3V- 5.5V此说明包含了新产品的一些信息、远翔科技保留修改该产品没有在该文当中说明的特性，由于这些新特性导致的问题远翔科技不承担任何责任、代理商没有任何权力诠释这些特性。

Assembly Instructions MP-B2 Mother BoardIntroductionThe MP-B2 Mother Board is a 9 " x 14" double sided plated thru hole board onto which all of the various processor boards are plugged. Provisions have been made for one processor board, up to four memory boards plus two unused slots. This gives the user the ability to handle up to 32K words of memory.The mother board also provides the line buffering and address decoding for up to eight interface boards. Although one of the eight must be the serial control interface, the other seven may be any com-bination of serial (MP-S) and parallel (MP-L) interfaces the user may choose to have. For those demanding even more interfaces the 50-line processor bus may be paralleled onto another MP-B2 Mother Board with power supply expanding the interfacing to one serial control interface, plus any combination of up to fifteen serial (MP-S) and parallel (MP-L) interfaces. Doing this requires a minor modification to the second mother board.When the SWTPC 6800 Computer System is being assembled, work on only one board at a time. Each of the system's boards and their associated parts must not be intermixed to avoid confusion during assembly.PC Board AssemblyNOTE: Since all of the holes on the PC board have been plated thru, it is only necessary to solder the components from the bottom side of the board. The plating provides the electrical connection from the "BOTTOM" to the "TOP" foil of each hole. Unless otherwise noted it is important that none of the con-nections be soldered until all of the components of each group have been installed on the board. This makes it much easier to interchange components if a mistake is made during assembly. Be sure to use a low wattage iron (not a gun) with a small tip. Do not use acid core solder or any type of paste flux. We will not guarantee or repair any kit on which either product has been used. Use only the solder supplied with the kit or a 60/40 alloy resin core equivalent. Remember all of the connections are soldered on the bottom side of the board only. The plated-thru holes provide the electrical connection to the top foil. ( ) Before installing any parts on the circuit board, check both sides of the board over carefully for incomplete etching and foil "bridges" or "breaks". It is unlikely that you will find any but shouldthere be one, especially on the "TOP" side of the board, it will be very hard to locate and correct after all of the components have been installed on the board.( ) Attach all of the resistors to the board. As with all other components unless noted, use the parts list and component layout drawing to locate each part and install from the "TOP" side of the board bending the leads along the "BOTTOM" side of the board and trimming so that 1/16" to 1/8" of wire remains. Solder.( ) Install all of the capacitors on the board. Solder.( ) Install each of the 59, 10-pin Molex male connectors oriented so the shorter pinned side fits into the holes provided on the mother board. These connectors must be inserted from the "TOP" side of the board and must be pressed down firmly against the board. Make sure the body of theconnector seats firmly against the circuit board and that each pin extends completely into theholes on the circuit board. Not being careful here will cause the plug-on boards to be less rigid.Do not solder the pins adjacent the dotted lines shown in the component layout drawing. It issuggested that you solder only the two end pins of each of the fifty-nine connectors until all have been installed; at which time, if everything looks straight and rigid, you should solder the as yet unsoldered pins still excluding the ones adjacent the dotted lines on the component layoutdrawing.( ) Using a pair of wire cutters, cut off the "INDEX" pin on each of the seven main board and eight interface board male connector strips. Each row is pointed out by the word "INDEX" printed right on the "TOP" side of the mother board. Be very careful when doing this. Do not cut off anything other than the "INDEX" pins. You cannot afford to make a mistake here. These "INDEX" locations prevent the various plug-on boards from being plugged on incorrectly later during assembly.( ) Install each of the integrated circuits excluding IC2. As each one is installed make sure it is down firmly against the board and solder only two of the leads to hold the pack in place while the other IC's are being inserted. Be very careful to install each in its correct position. Do not bend theleads on the back side of the board. Doing so makes it very difficult to remove the integratedcircuits should replacement ever be necessary. The semicircle notch or dot on the end of thepackage is used for orientation purposes and must match with the outlines shown on thecomponent layout drawing for each of the IC's. After inserting all of the integrated circuits go back and solder each of the as yet unsoldered pins.( ) Install integrated circuit IC2 on the circuit board. This component must be oriented so its metal face is facing the circuit board with the small metal heatsink sandwiched between the two. The heatsink and IC are secured to the circuit board with a #4-40 x 3/8" screw, lockwasher and nut.The three leads of the integrated circuit must be bent down into each of their respective holes and the heatsink must be orientated as shown in the component layout drawing. Solder.( ) Remove any oxidation from the copper on the two mother board support strips using a piece of Scotchbrite. Take the shorter of the two and position it on the "BOTTOM" side of the motherboard along the main board GND bus and perpendicular to the mother board as indicated in the component layout drawing. It should be oriented with its copper edges against the "BOTTOM"side of the mother board, extending from the first to the seventh main board connection rows.Solder the as yet unsoldered connector pins adjacent the strip making sure the strip is soldered in place as well. Make sure the strip remains firmly against the PC board while soldering. Now take the longer of the two strips and position it against the "BOTTOM" side of the mother boardparallel to and in the center of the +8 UNR interface bus as indicated in the component layout drawing and attach like the first strip. These strips provide rigidity and support for the motherboard and prevent the mother board from bottoming out when the plug-on boards are installed. ( ) Working from the "TOP" side of the circuit board, fill in all of the feed-thru's with molten solder.The feed-thru's are those unused holes o n the board whose internal plating connects the "TOP"and " BOTTOM " circuit connections. Filling these feed-thru's with molten solder guarantees the integrity of the connections and increases the current handling capability. Do not fill in the 16holes on the edge of the board that are to be used for wiring connections.( ) Now that all of the components have been installed on the board, double check to make sure alI have been installed correctly in their proper location.( ) Check very carefully to make sure that all connections have been soldered. It is very easy to miss some connections when soldering which can really cause some hard-to-find problems later during checkout. Also, look for solder "bridges" and "cold" solder joints which are another common pro-blem.This completes the assembly phase for the MP-B2 board. Checkout instructions for the board are provided with the System Checkout Instructions supplied with this kit. The System Checkout Instructions are used after having assembled the processor board, M P-B 2 mother board, serial control interface and the M PM P-P power supply.How It WorksThe only circuitry on the MP-B2 mother board is that tying the various interface cards to the system's interface information bus. IC1 is a non-inverting buffer used to drive selected control lines feeding the interface cards. One of eight decoders IC3 and IC6 decode and enable one of eight interface cards when one of the interface addresses is loaded to the 50-line system information bus.Since the eight bit data bus for the main boards as well as the interface cards is bi-directional, transceiver buffers IC7 and IC8 buffer the incoming and outgoing data to and from the interface data bus to the system's data bus. Gates within NAND gate IC4 and NOR gate IC5 control the direction of data flow within the transceiver/buffers. +5 VDC power for the interface decode/buffer circuitry is provided by voltage regulator IC2. +5 VDC power for all of the plug-on boards, including interfaces, is provided by separate regulators on each board.The following is a brief description of each of the fifty lines on the system information bus:D0 - D7# The D0 - D7# lines carry inverted data bits 0 thru 7 respectively forming 8-bit data words which are exchanged between the various boards within the system.A0 - A15 The A0 - A15 lines carry address bits 0 thru 15 respectively forming a 16-bit address which is used to define either a memory location or interface address.GND The GND line is the system's common or power supply ground point.7- 8VDC UNREG or +8 UNR The 7 - 8 VDC UNREG point is the line to which a +7 to 8 volt DC @10A unregulated power supply should be attached. This voltage is then regulated down to +5 VDC by in dependent regulators on the various boards within the system.-12, +12 The -12 and +12 points are lines to which an isolated ground -12@200 Ma and +12 @200 Ma power supply should be connected. The voltages are necessary forgenerating the currents required by 20 Ma current loop and RS-232 equipment onthe serial interfaces.INDEX The INDEX is an unused bus and is provided so the pin on each of the male connectors may be cut with the corresponding female connector pins plugged,preventing the circuit boards from being plugged on incorrectlyM. RESET#The MANUAL RESET# line when momentarily grounded indirectly resets the registers internal to the processor and interfaces, and loads the ROM storedmini-operating system. This line is normally grounded by depressing the RESETbutton on the system's front panel.NMI# The NMI# is the non-maskable, single level interrupt line feeding the processor board. When momentarily grounded it forces the processor into a push-down stack,store routine, followed by a program jump to a user selected address stored in theoperating system RAM. The NMI# is non-maskable thus, can not be inhibited by theprogrammer thru software.IRQ# The IRQ# is the maskable, single level interrupt request line feeding the processor board. If not inhibited by software it will, when momentarily grounded, force theprocessor into a push-down stack, store routine followed by a program jump to a userselected address stored in the operating system RAM.UD1, UD2 The UD1 and UD2 are user defined lines and have not been assigned a function.ø2 ø2 is one of the two complementary system clock outputs and is used to signal that valid data is on the data lines D0 - D7# when low.VMA# VMA# is the valid memory address line which goes low to confirm that valid memory data is being presented on the sixteen address lines, A0 - A15.R /W The READ/WRITE line establishes the direction of data flow on the eight data lines, D0 -D7. It is high for a read from memory or interface and low for a write to memoryor interface.RESET# The RESET line when low resets the registers internal to the processor and interfaces, and loads the ROM stored mini-operating system. This line is activated bya one-shot on the processor board when the system is first powered up or when M.RESET line is momentarily groundedBA The BUS AVAILABLE line goes high acknowledging a processor halt meaning the processor has stopped and that the system information bus is available for externalcontrol.HALT# The normally high HALT# line when brought low, halts the processor and frees the system information bus for external controlø1 ø1 is the non-overlapping clock complement of ø2. This signal is provided by the MP-A but not by the MP-A2 processor board.110b, 150b 300b, 600b, 1200b These five lines carry the clocks required by the serial interfaces for 110, 150, 300, 600, 1200 baud communication.Attached to the 50-line system information bus are the interface decode and driver circuits. A considerable cost savings is made by providing the address decoding and information bus buffering for all of the interfaces right on the mother board instead of providing it on each of the interface boards individually. Since each of the parallel interfaces require four address locations and the serial two, four addresses are provided for each of the interface positions. They are assigned as shown in the memory map, figure 1. Interface position 1 (8004 - 8007) is reserved for the terminal, control interface. The signals carried on the interface information bus are almost identical to those on the system bus. UD3 and UD4 are here again User Defined data lines and RS0 and RS1 are Register select lines which are identical to address line A0 and A1 respectively.The original MP-B Mother Board decoded the entire 8 K block of memory from 32K thru 40K as being resident on the mother board. Although simpler from a circuitry viewpoint, this technique was wasteful and has been changed on this version, the MP-B2, so that only the 32K thru 36K block has been allocated to the mother board interface addresses. This allows boards outside the interface address range to use the 36K thru 40K memory addresses.The new decoding arrangement also makes it easy to reassign the interface address block to any 4K region from 32K to 64K in 4K increments. Although this isn't allowable when using the MIKBUG® or SWTBUG® monitors, it does have potential when using custom monitors.To relocate the 4K interface address block to something other than the 32K thru 36K hardwired assignment, carefully cut the foil trace going to pin 15 of IC6 on the bottom side of the MP-B2 board. Jumper pin 12 of IC5 to the specified pin of IC6 using the table below:Interface Address Assignment IC6 pin #32K - 36K (8000-8FFF) 1536K - 40K (9000-9FFF) 1440K - 44K (A000-AFFF) 1344K - 48K (B000-BFFF) 1248K - 52K (C000-CFFF) 1152K - 56K (D0D0-DFFF) 1056K - 60K (E000-EFFF) 960K - 64K (F000-FFFF) 7The actual interface card addresses will be the first 32 addresses of each 4K block with four sequential addresses assigned to each card position.If you ever wish to expand your system to two MP-B2 mother boards in order to accommodate more interface cards, you must first modify the second MP-B2 board so it responds to the second set of 32 sequential addresses within the 4 K address block. The second MP-B2 board should also be assigned the same 4 K memory address block as the first MP-B2 board. Modify the second MP-B2 mother board by cutting the foil trace going to pin 4 of IC6 right at IC6. Now run a jumper from pin 4 of IC6 to pin 4 of IC5. The MP-B2 mother boards themselves are interconnected by paralleling the 50-pin buses together using #18 gauge or heavier stranded wire. The wire length should be kept as short as possible and preferably no more than 24 inches in length.NOTE: The MP-A2 Processor board does not generate the ø1 signal described in the mother board bus line definitions when plugged onto the M P-B mother board.MIKBUG ® is a registered trademark of Motorola, Inc.SWTBUG® is a registered trademark of Southwest Technical Products Corp.Resistors___ R1 470 ohm 1/4 watt resistor ___ R7 6.8K ohm 1/4 watt resistor ___ R2 470 ohm 1/4 watt resistor ___ R8 6.8K ohm 1/4 watt resistor ___ R3 470 ohm 1/4 watt resistor ___ R9 1K ohm 1/4 watt resistor ___ R4 470 ohm 1/4 watt resistor ___ R10 470 ohm 1/4 watt resistor ___ R5 470 ohm 1/4 watt resistor ___ R11 1K ohm 1/4 watt resistor ___ R6 470 ohm 1/4 watt resistorCapacitors___ C4 0.1 mfd disk capacitorIntegrated Circuits___IC1 DM8097 / 74367 / 74LS367 ___IC5 7402 Quad NOR Gate___IC2 7805 +5VDC Voltage Regulator ___IC6 74S138 1 of 8 decoder___IC3 74S138 1 of 8 decoder ___IC7 DM8835 / DS8835___IC4 7400 Quad NAND Gate ___IC8 DM8835 / DS8835。

Features◆ Plastic package has Underwriters Laboratory FlammabilityClassification 94V-0◆ Glass passivated chip junctions ◆ High surge overload rating:35A peak ◆Saves space on printed circuit boards◆ High temperature soldering guaranteed:260℃/10 seconds ◆ Add suffix "E" for Halogen Free◆ Halogen-free according to IEC 61249-2-21 definitionMechanical Data◆Case:Molded plastic body over passivated junctions ◆ Terminals: plated leads solderable per MIL-STD-750,Method 2026◆ Mounting Position:Any ◆Weight:0.078 oz.,0.22gMaximum Ratings & Electrical Characteristics(T A =25℃ unless otherwise noted)ParameterSymbol MB2S MB4S MB6S MB8S MB10S Unit Maximum repetitive peak reverse voltage V RRM 2004006008001000V Maximum RMS voltage V RMS 140280420560700V Maximum DC blocking voltageV DC2004006008001000VMaximum Average forward output current (see Fig.1) on glass-epoxy P.C.B on aluminum substratePeak forward surge current 8.3 MS single HALF sine-wav superimposed on rated load (JEDEC Method)A350.5(1)0.8(2)A I F(AV)I FSM p p ()Rating for fusig (t<8.3ms)I 2t A 2sec Maximum instantaneous forward voltage drop per leg at 0.4AMaximum DC reverse current at TA=25℃rated DC blocking voltage per leg TA=125℃R 1.00V585(1)VFμAIR5100θJA R θJA R θJLCj pF Operating junction and storage temperature rangeT J,T STG℃Notes:1. On glass epoxy P.C.B. mounted on 0.05×0.05"(1.3×1.3mm) pads-55 to +15020(1)70(2)℃/W Typical junction capacitance per at 4.0V,1.0MHz 13Typical thermal resistance per leg2. On aluminum substrate P.C.B.whth an area of 0.8×0.8"（20×20mm ）mounted on 0.05×0.05"(1.3×1.3mm) solder padRatings and Characteristics Curves(TA = 25℃ unless otherwise noted)Figure 1.Derating Curve for Output Rectified Current Figure 4.Typical Reverse Leakage Characteristics Per LegFigure 5.Typical Junction Capacitance Per Leg Figure 2.Maximum Non-Repetitive Peak ForwardSurge Current Per LegFigure 3.Typical Forward Voltage Characteristics Per LegMarking。

CBM27数据手册专芯发展 • 用芯服务 • 创芯未来www. corebai. com● 宽压供电范围： 8V (±4V)~36V (±18V) ● 低噪声：90 nV p-p （0.1 Hz 至10 Hz ） ● 高速：2.8 V/µs 压摆率、8 MHz 增益带宽 ● 共模抑制比(CMRR)：130 dB (VCM = ±11 V) ● 高开环增益：1,800,000● CBM27A 和 CBM27G 其他产品特点 ● 最大噪声谱密度CBM27A . . . 3.9 nV/√Hz @ 1 kHz Max CBM27G . . . 5.0 nV/√Hz @ 1 kHz Max ● 低输入失调电压CBM27A . . . 26 μV Max CBM27G . . . 100 μV Max ● 低输入失调电压漂移CBM27A . . . 0.2 μV/°C CBM27G . . . 0.4 μV/°C● 电力采集应用系统● 高精密数据采集系统 ● 自动化测试设备（ATE ）● 音频前置放大器 ● 仪器仪表CBM27提供低电平信号出色的低噪声和高精度放大性能。

产品广泛应用于稳定的积分器、精密求和放大器、精密电压阈值检测器、比较器和专业音频电路，如磁头和麦克风前置放大器。

失调电压低至26 μV ，漂移为0.2 μV/°C ，因而该器件是精密仪器仪表应用的理想之选。

极低噪声（10 Hz 时en=3.5nV/√Hz ）, 低1/f 噪声转折频率(2.7Hz)以及高增益(1800V/mV)，能够使低电平信号得到精确的高增益放大。

8 MHz 增益带宽积和2.8 V/µs 压摆率则可以在高速数据采集系统中实现出色的动态精度。

利用偏置电流消除电路，CBM27可实现±10nA 的低输入偏置电流。

输出级具有良好的负载驱动能力。

CRC Write Data FeatureCRC Write DataThe CRC write data feature takes the CRC generated data from the DRAM controller andcompares it to the internally CRC generated data and determines whether the twomatch (no CRC error) or do not match (CRC error).Figure 108: CRC Write Data OperationWRITE CRC DATA Operation A DRAM controller generates a CRC checksum using a 72-bit CRC tree and forms thewrite data frames, as shown in the following CRC data mapping tables for the x4, x8, andx16 configurations. A x4 device has a CRC tree with 32 input data bits used, and the re-maining upper 40 bits D[71:32] being 1s. A x8 device has a CRC tree with 64 input databits used, and the remaining upper 8 bits dependant upon whether DM_n/DBI_n isused (1s are sent when not used). A x16 device has two identical CRC trees each, one forthe lower byte and one for the upper byte, with 64 input data bits used by each, and theremaining upper 8 bits on each byte dependant upon whether DM_n/DBI_n is used (1sare sent when not used). For a x8 and x16 DRAMs, the DRAM memory controller mustsend 1s in transfer 9 location whether or not DM_n/DBI_n is used.The DRAM checks for an error in a received code word D[71:0] by comparing the re-ceived checksum against the computed checksum and reports errors using theALERT_n signal if there is a mismatch. The DRAM can write data to the DRAM corewithout waiting for the CRC check for full writes when DM is disabled. If bad data iswritten to the DRAM core, the DRAM memory controller will try to overwrite the baddata with good data; this means the DRAM controller is responsible for data coherencywhen DM is disabled. However, in the case where both CRC and DM are enabled via8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature5.CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.6.t CCD_S/L = 5 isn’t allowed in 2t CK preamble mode.7.The write recovery time (t WR) and write timing parameter (t WTR) are referenced fromthe first rising clock edge after the last write data shown at T20.8.When operating in 2t CK WRITE preamble mode, CWL may need to be programmed to avalue at least 1 clock greater than the lowest CWL setting supported in the applicablet CK range, which means CWL = 9 is not allowed when operating in 2t CK WRITE pream-ble mode.Figure 179: WRITE (BC4) OTF to WRITE (BC4) OTF with 1t CK Preamble in Different Bank GroupCommand DQ CK_t CK_cDQS_t,DQS_cBank GroupAddress Address Notes: 1.BC4, AL = 0, CWL = 9, Preamble = 1t CK.2.DI n (or b ) = data-in from column n (or column b ).3.DES commands are shown for ease of illustration; other commands may be valid atthese times.4.BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 andT4.5.CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.6.The write recovery time (t WR) and write timing parameter (t WTR) are referenced fromthe first rising clock edge after the last write data shown at T17.8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation。

MD0011-014Revision APage 1 of 15The MICROS Bump BarMBB-10 and MBB-20 User’s Guide This document describes the MBB features, shows how to adjust the speaker and LED from the keypad, as well as determine the firmware version and how to update if required. Other sections describe how to open the unit and configure the MBB circuit board configuration switches, and to service the unit.Introducing the MICROS Bump Bar (2)Adjusting the LED and Speaker from the Keypad (4)MBB Spare Parts (5)Opening the Micros Bump Bar (8)Specification Summary (13)MBB-10 Bracket Dimensional Drawing (14)MBB-20 Bracket Dimensional Drawing (15)MD0011-014Revision APage 2 of 15Introducing the MICROS Bump BarThe MBB-10 and MBB-20 are shown in the Figure below.Figure 1: The MBB-10 and MBB-20•USB Interface - 6ft cable standard.•Extruded aluminum case /w gasket sealed end caps for spill resistance to IP55 standards.•Magnetic keys offer improved tactile response over a membrane switch and millions of actuations. •Blue LED with adjustable brightness.•Internal speaker with adjustable volume.•The alpha and numeric keys can be reversed to allow the MBB interface cable to exit from the left or right.•Order notification through the speaker and LED. Refer to the PMA forspecific POS software support.MD0011-014Revision APage 3 of 15TemplateEach MBB is supplied with a standard template shown in the illustration. Mounting BracketsEach MBB is supplied with a quick release mounting bracket that can be mounted to a counter, wall surface or current third party KDS mounting hardware. The MBB-20 bracket hole locations are compatible with the QSR bumpbar for easy replacement. Refer to the MICROS Bump Bar PMA for more information about KDS mounting options.Adjustable LED and SpeakerThe MBB includes an internal speaker that serves two functions. The speaker sounds each time a key is pressed. If supported by the KDS software, the unit can also beep when an new order is received from the KDS controller. The keypress and order notification beep volume can be adjusted independently directly from the MBB keypad.Figure 2: MBB Speaker and LEDUSB Interface CableThe MBB-10 and MBB-20 both use a 6 ft. (1.8M) USB Interface Cable. If a longer interface cable is required, you can purchase and install an 11 foot (3.5M) cable, P/N 700503-070. Another option is the Belkin F3U130-16, a 16 ft. USB 1.1 cable extender. The MBB has been tested with two of the extender cables connected to the standard KDS controller. The extender cable (P/N700503-071) does not require an external power supply.MD0011-014Revision APage 4 of 15Adjusting the LED and Speaker from the KeypadThe LED brightness and Speaker volume can be adjusted directly from the keypad at any time. Figure 3, below summaries each adjustment.Figure 3: Adjusting the LED and Speaker volume from the Keypad Adjusting the LED BrightnessTo adjust the LED brightness, press and hold the [1] and [A] keys, then tap the[2] key to cycle through the Off, Normal, and Bright settings.Adjusting the Keypad SpeakerTo adjust the volume, press and hold the [1] and [A] keys, then tap the [B] key to cycle through the Off, Normal, and Loud speaker settings.Adjusting the Order Notification BeepTo adjust the order notification volume, press and hold the [1] and [A] keys then tap the [3] key to cycle through the Off, Normal, or Loud settings.Internal Configuration SwitchesThe MBB circuit board includes two switches that can be set to send lower or upper case characters, or reverse the location of the character and numeric keys for increased mounting flexibility. See Figure 10 for more information. To open the MBB and access the configuration switches, see page8.MD0011-014Revision APage 5 of 15MBB Spare PartsIn addition to a 3.5M USB Interface Cable, several other spare parts are available for the MBB-10 and MBB-20.USB Interface CablesFigure 4, below displays the MICROS Part Numbers for the standard 6 foot (1.8M) and optional 11 foot USB cables. Each cable includes a custom molded water resistant strain relief.See page 8 to open the unit.Figure 4: MBB Upgrade and Replacement USB Interface CablesMD0011-014Revision APage 6 of 15Circuit Board, MICROS BUMPBAR - 700364-101Replacement main board, with firmware. A jumper determines if the board supports the MBB-10 or MBB-20.Figure 5: Micros Bump Bar Circuit BoardBracket, MICROS 20-Key BUMPBAR - 600526-026Mounting bracket for 20 Key MBB. The hole centers are compatible with current 3rd party KDS mounting hardware. Mounting hardware not included.Figure 6: MBB-20 Mounting BracketMD0011-014Revision APage 7 of 15Bracket, MICROS 10-Key BUMPBAR - 600526-025Mounting bracket for 10 Key MICROS Bumpbar. Mounting hardware not included.Figure 7: MBB-10 Mounting BracketCOVER KIT, FLANGE, RIGHT & LEFT, /W SCREWS and GASKETS - 000160-012.Replacement left and right end caps, with gaskets and hardware.Figure 8: MBB Flanges, Left-RightMD0011-014Revision APage 8 of 15Opening the Micros Bump BarThe following procedure applies to both the MBB-10 and MBB-20.1.Be sure to disconnect the USB interface cable from the host KDS controller before you open the unit.2.Refer to Figure 9 and remove the pair of screws from the side where the cable exits.3.Pull the flange and USB cable out far enough to expose the circuit board, then continue to pull out the board until the connectors are exposed. Avoid pulling on the keypad ribbon cable when removing the board .Figure 9: Opening the Micros Bump Bar•Refer to page 9 to set the internal configuration switches.•Refer to page 10 to change the USB Interface Cable.•Refer to page11 to change the MBB circuit board.MD0011-014Revision APage 9 of 15Setting the Internal Configuration SwitchesFigure 10 describes the function of the two switches and single 5-pin header on the MBB Control Board.Figure 10: MBB Control Board Configuration SwitchesSW1 - Selects Normal or Reversed CharactersIn the Normal position, numeric characters appear in the top row, ascending from left to right. Alpha characters appear in the bottom row ascending from left to right.SW1 can be set to the ‘Reversed’ position for flexibility when mounting the MBB. The reversed selection places alpha and numeric characters in descending order from left to right.SW2 - Selects Upper or Lower Case CharactersSW2 selects upper or lower case alpha characters. Lower Case is the default.J2 - Selects MBB-10 or MBB-20 ConfigurationJ2 determines if the board supports the MBB-10 (2x5) or MBB-20 (2x10)format.MD0011-014Revision APage 10 of 15Remove/Replace the USB Cable1.Open the MBB case to access the cable as described on page 8.2.Remove the existing cable from mini-USB Connector J1 and the flange strain relief as shown in the Figure below.Figure 11: Replacing the USB Cable3.Connect the USB Interface cable to J1 and the strain relief in the flange cut-out.4.See page12 to reinstall the circuit board and close the MBB.MD0011-014Revision ARemove the MBB Circuit Board1.Open the MBB to access the main circuit board and USB cable as detailed in Figure 9.2.Refer to Figure 12, below. Move CN1 to the raised position before removing or inserting the keypad cable.Figure 12: Removing/Installing the Keypad Ribbon Cable3.Remove the USB cable from J1.4.Remove the configuration jumper from J2 and transfer it to the sameposition on the new board. As shown in Figure 13, the jumper determines if the board supports the MBB-10 or MBB-20.Figure 13: MBB Circuit Board Configuration Jumper5.Install the USB Interface Cable in J1 and the strain relief in the flange cut-out.6.Install the Keypad Ribbon cable. With CN1 in the raised position, insert thecable into the connector. Move CN1 to the locked position.MD0011-014Revision APage 12 of 15Install the MBB Circuit Board1.Place the MBB Board in the grooves located at the front and rear of the case, then start to slide the board into the case.2.As you slide the board into place, make sure the keypad ribbon cable does not become bunched up around CN1. Figure 14 shows the correct position of the keypad ribbon cable.Figure 14: Installing the MBB Control Board3.Install the molded strain relief in the flange cutout before reinstalling theflange screws.Specification SummarySpecificationsKeyswitch Type Duraswitch PushGate® keys rated for > 30 million actuations. Connectivity USB 1.1 /w 6 ft (1.8M) CableIP (IngressProtection)Rating55Dimensions (w/bracket) MBB-10: 6.22”W x 2.87”D x 1.25”H (158mm x 73mm x 32mm) MBB-20: 9.38”W x 2.87”D x 1.25”H (238mm x 73mm x 32mm)Weight (w/bracket) MBB-10: 0.90 lbs (0.41kg) MBB-20: 1.25 lbs (0.57kg)Environmental Operating Temperature: 0°C to 65°C (32°F to 149°F)Storage Temperature: -25°C to 80°C (-13°F to 176°F)Humidity: 90% relative humidity maxMD0011-014Revision AMD0011-014Revision APage 14 of 15MBB-10 Bracket Dimensional DrawingMD0011-014Revision AMBB-20 Bracket Dimensional Drawing。

Figure 16: RESET Procedure at Power Stable ConditionCKE R TTBG, BACK_t, CK_c Command Td Tc Don’t CareODT Th Ti Tj TkRESET_nTe TaTb Tf V DD , V DDQV PPTg Notes: 1.From time point Td until Tk, a DES command must be applied between MRS and ZQCLcommands.2.MRS commands must be issued to all mode registers that have defined settings.3.In general, there is no specific sequence for setting the MRS locations (except for de-pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,for example).4.TEN is not shown; however, it is assumed to be held LOW.Uncontrolled Power-Down SequenceIn the event of an uncontrolled ramping down of V PP supply, V PP is allowed to be less than V DD provided the following conditions are met:•Condition A: V PP and V DD /V DDQ are ramping down (as part of turning off) from nor-mal operating levels.•Condition B: The amount that V PP may be less than V DD /V DDQ is less than or equal to 500mV .•Condition C: The time V PP may be less than V DD is ื10ms per occurrence with a total accumulated time in this state ื100ms.8Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure•Condition D: The time V PP may be less than 2.0V and above V SS while turning off is ื15ms per occurrence with a total accumulated time in this state ื150ms.Programming Mode RegistersFor application flexibility, various functions, features, and modes are programmable in seven mode registers (MR n ) provided by the device as user defined variables that must be programmed via a MODE REGISTER SET (MRS) command. Because the default val-ues of the mode registers are not defined, contents of mode registers must be fully ini-tialized and/or re-initialized; that is, they must be written after power-up and/or reset for proper operation. The contents of the mode registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers,even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is is-sued. MRS and DLL RESET commands do not affect array contents, which means these commands can be executed any time after power-up without affecting the array con-tents.The MRS command cycle time, t MRD, is required to complete the WRITE operation to the mode register and is the minimum time required between the two MRS commands shown in the t MRD Timing figure.Some of the mode register settings affect address/command/control input functionali-ty. In these cases, the next MRS command can be allowed when the function being up-dated by the current MRS command is completed. These MRS commands don’t apply t MRD timing to the next MRS command; however, the input cases have unique MR set-ting procedures, so refer to individual function descriptions:•Gear-down mode •Per-DRAM addressability •CMD address latency •CA parity latency mode •V REFDQ training value •V REFDQ training mode•V REFDQ training rangeSome mode register settings may not be supported because they are not required by certain speed bins.8Gb: x4, x8, x16 DDR4 SDRAM Programming Mode RegistersFigure 17: t MRD TimingDon’t CareCK_tCK_cCommand Settings CKEAddressNotes: 1.This timing diagram depicts CA parity mode “disabled” case.2.t MRD applies to all MRS commands with the following exceptions:Gear-down modeCA parity latency modeCMD address latencyPer-DRAM addressability modeV REFDQ training value, V REFDQ training mode, and V REFDQ training rangeThe MRS command to nonMRS command delay, t MOD, is required for the DRAM to update features, except for those noted in note 2 in figure below where the individual function descriptions may specify a different requirement. t MOD is the minimum time required from an MRS command to a nonMRS command, excluding DES, as shown in the t MOD Timing figure.Figure 18: tMOD TimingDon’t CareCK_tCK_cCommand Settings CKEAddress Notes: 1.This timing diagram depicts CA parity mode “disabled” case.2.t MOD applies to all MRS commands with the following exceptions:DLL enable, DLL RESET, Gear-down modeV REFDQ training value, internal V REF training monitor, V REFDQ training mode, and V REFDQ training range8Gb: x4, x8, x16 DDR4 SDRAM Programming Mode Registers。