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基于单片机的数字时钟设计--外文翻译

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Chapter10Low-Noise Electronic Imagingwith Double-Gate FETsand Charge-Modulation DevicesYoshiyuki MatsunagaAbstract Virtually complete charge transfer can be achieved with charge coupled devices(CCDs)in the buried channel configuration because the buried channel CCD introduces no transfer noise.However,conventional charge detectors incorporated into CCDs have a comparably large noise,which consists of thermal noise and1/f noise from MOS transistor in the output charge detectors.Highly sensitive double gate charge detectors are presented in this chapter to show the ability of CCD low noise performance of less than1electron rms at room temperature and at video frequency.The concept of double gate charge detection can alternatively be implemented in a pixel incorporating a charge modulation device(CMD),reaching also an effective readout noise level of less than1electron rms.In practice,the CMD shows larger fixed-pattern noise behavior,necessitating supplementary signal processing efforts.10.1IntroductionCharge coupled devices(CCDs)have achieved virtually complete charge transfer by using the buried-channel configuration,resulting in charge transfer inefficiencies of less than10 6.Also,the buried-channel CCD operation introduces no transfer noise.However,conventional charge detection circuits employed in CCDs have a comparatively large noise,which consists of thermal noise and1=f noise from metal oxide semiconductor(MOS)transistors in the charge detectors[1].The detector noise sources degrade the CCD performance significantly.In this chapter,highly sensitive double-gate charge detector devices are presented to exploit the ability of CCD lownoise performance which is one of the most impor-tant characteristics for image sensor applications.Low leakage current CCD sensors with a low-noise charge detector will ideally be almost noiseless photosensors In addition,a new charge-modulation image pixel is presented for applications of the double-gate detectors.P.Seitz and A.J.P.Theuwissen(eds.),Single-Photon Imaging,219 Springer Series in Optical Sciences160,DOI10.1007/978-3-642-18443-710,©Springer-Verlag Berlin Heidelberg2011220Y.Matsunaga 10.2Double-Gate FET Charge DetectorThe primary parameter dominating the noise performance of a charge detector is the effective capacitance at the gate of thefirst transistor,as explained for example in the first chapter of this book.For this reason,a successful strategy for the realization of ultra-low-noise photosensors is the design of charge detectors with very low sensing capacitance,preferentially below1fF.The double-gate FET structure is very useful for this purpose because of both its high sensitivity due to low sensing capacitance and its low noise due to complete charge transfer in the charge detector.The double-gate FET can be implemented either as afloating well or as afloating surface device.10.2.1Floating Well TypeA new high-sensitivity CCD output amplifier called“double-gatefloating well detector”has been fabricated and evaluated.At room temperature,the new detector achieves a charge/voltage conversion gain of76 V/electron and a noise equivalent signal of1.2electrons rms over a3.58MHz video bandwidth.This detector consists of an n-type buried sensing channel and a P-type bulk channel detection transistor crossing underneath the sensing channel,representing the doublegate FET.This structure is very useful for a CCD image sensor which handles a small signal charge of a few thousand photogenerated electrons or holes.10.2.1.1Device StructureAlmost all charge detectors for CCD image sensors arefloating diffusion detectors. Figure10.1shows the top view of the detector incorporated into the end of a CCD register.Signal charges are clocked along the CCD register and transferred out into a CCD sensing channel.Sensing channel potential is modulated by signal charges, and a modulated potential is sensed by the detection MOS transistor’s gate.The output voltage signals are buffered by double stage source followers.The detection sensitivity is determined by the conversion gain for signal charges to the output voltages,that is,by the effective sensing capacitance.However,the sensing capacitance of the conventional detector cannot be suffi-ciently small for the following reasons:First,the sensing channel has a compar-atively large area because it inevitably has a contact hole.Second,the detection transistor gate capacitance must be added to the sensing capacitance.Third,the detector suffers from large kTC noise,corresponding to chargefluctuation in the reset gate OFF period due to reset gate channel thermal noise in the ON period.The newly developed charge detector has low sensing capacitance and a structure that is free from kTC noise.The principle is a combination of an n-type buried sensing channel and a P-channel detection transistor across it,as shown in Fig.10.210Low-Noise Electronic Imaging with Double-Gate FETs221 Fig.10.1Plane view ofconventionalfloatingdiffusion charge detectorFig.10.2Plain view of newfloating well detector[2,3].Figure10.3shows a cross-sectional view of the detection transistor across the sensing channel.A shallow p-well with a sensing channel in it and source/drain p C regions are formed on an n-type substrate.The hole current in the P-channel detection transistor is made toflow not along the silicon–silicon dioxide interface but rather underneath the sensing channel.As a result,suppression of1=f noise which is caused by silicon–silicon dioxide traps can be expected.Charge packets clocked along the CCD channel are transferred into the sensing channel.The charge packets directly modulate the channel conductance in the detection transistor.The sensing capacitance for the detection transistor can be smaller than that for the widely used“floating diffusion detector.”The small sensing capacitance has been achieved by the smaller sensing region,in which the sensing channel and the P-type channel for the detection transistor are crossed.Moreover,a“double-gate structure”is introduced for smaller sensing capacitance.In this structure,a1,000nm222Y.MatsunagaFig.10.3Cross-section offloating well detection transistorFig.10.4Practicalfloating well charge detector fabricated in shallow p-well on n-type substrate thick oxide is employed for the detection transistor’s gate oxide.Aflat potential plate(FPP),which isfloating electrically,is inserted under the detection transistor gate(G).The FPP suppresses the two-dimensional effect which causes a potential pocket in the sensing channel.The transfer loss induced by a potential pocket results in transfer noise in the detector.Figure10.4shows a practical output amplifier for detecting the charge(electron) packets transferred in a three-phase linear CCD which is fabricated in a shallow p-well on the n-type substrate of45 cm resistivity.The potential control gate(G)area with the thick gate oxide layer measures5 5 m2,and the thin gate layer under the FPP is93nm thick.To form the P-type channel for the detection transistor,a local deep boron implantation the sensing channel is required.Figure10.5shows10Low-Noise Electronic Imaging with Double-Gate FETs223 Fig.10.5Potential profilesalong the directionperpendicular to devicesurfacethe potential profiles along the direction perpendicular to the surface.The solid line and the dotted line are those under the FPP and under the output gate(OG), respectively.The abrupt potential profile under the sensing channel is essential for the signal charge in the sensing channel to modulate the detection transistor channel conductance effectively.The source and drain regions of the P-channel detection transistor are made by self-alignment with the output gate(OG),reset gate(RS) and the FPP.The source is connected to the P-channel load transistor made by a junction-type FET incorporated into the same chip.The junction FET is superior for suppressing1=f noise compared to a MOS-FET[4]A charge(electron)packet transferred into the sensing channel through the output gate(OG)is converted to a voltage signal,using thefirststage source-follower which consists of the detection transistor and the load transistor.An output signal is generated using the second stage source-follower constructed with n-channel MOS transistors.To remove the charge(electron)packet from the sensing channel region into reset drain(RD),a positive pulse is applied to the reset gate(RS).Then the sensing channel is completely depleted in a so-called“transfer operation.”Thus,the detector has no reset noise[5–7].10.2.1.2Device SimulationA two-dimensional device simulator was utilized for designing the detector.In a conventional detector,an effective sensing capacitance is determined approximately by the gate oxide capacitance of a detection transistor[2,3].For high sensitivity,low sensing capacitance has been achieved by employing a1 m thick gate oxide for the detection transistor.Figure10.6a shows a simulated potential profile for electrons in the detecting section.A potential pocket is observed at the edge of the output gate(OG).The potential pocket causes not only charge(electron)transfer loss but also transfer noise.To eliminate the pocket,the FPP has been inserted under the potential control gate(G).The potential profile in the new detector with the FPP is shown in Fig.10.6b.The potential pocket vanishes,which enables the new structure to obtain reduced transfer loss sufficient for the realization of a low-noise detector.224Y.MatsunagaFig.10.6Potential profiles along the direction perpendicular to device surface.(a)Detection transistor with only1 m thick gate oxide(b)Detection transistor with FPP10.2.1.3EvaluationThe detector was evaluated at a7.16MHz clock frequency,corresponding to twice the NTSC color subcarrier frequency.The signal duty defined by the signal output period in the clock cycle was approximately70%,which was determined by a40ns positive pulse supplied to the reset gate(RS).The charge/voltage conversion gain of the detector was measured by injecting a series of charges in a packet into the CCD from an injection diode having a capacitance of about1fF.The size of the charge packet was calculated from the reset drain current.The resultant output amplitude was observed through an oscilloscope.The output signal bandwidth is 20MHz under7pF capacitance load.The results of the measurements are shown in Fig.10.7The relation between injection charge quantity and output voltage is linear over a range of charge packets from40to2,000electrons/packet,with a responsivity of76 V/electron.The output noise of the new detector was measured using a spectrum analyzer.Figure10.8shows the noise spectra of the detector,both in reset operation and in transfer operation.In the reset operation,residual charge in the sensing channel includes reset noise(kTC noise),charge due to thermal noise generated in the channel region of the reset gate(RS).Conversely,in the transfer operation,no noise charge exists,because the signal charge in the sensing channel is completely transferred into the reset drain by applying a positive pulse to the reset gate.The1=f noise below2MHz,which is observed in the noise spectrum for the transfer operation,is generated by the detection transistor.The overall RMS noise value in the transfer operation,within the frequency range of 10kHz–3.58MHz,was64 V rms at room temperature.The value for the“floating surface detector”with the FPP structure,which is fabricated on the same substrate for comparison and is described below,was84 V rms under the same measuring conditions.The difference in the noise values is caused by the1=f noise due to silicon–silicon dioxide interface traps.As shown in Fig.10.7,the new detector witha charge/voltage conversion gain as high as76 V/electron,a noise level as low as64 V rms and a70%signal duty ratio,achieves an effective readout noise as low as1.2electrons rms.10Low-Noise Electronic Imaging with Double-Gate FETs225Fig.10.7Charge/voltage conversion characteristics and noise levelsFig.10.8Noise spectra in reset operation and in transfer operation226Y.Matsunaga 10.2.2Floating Surface TypeAn alternative low-noise and wide dynamic range charge detector called“double-gatefloating surface detector”differs from thefloating well type in that the P-channel FET currentflows at the silicon–silicon dioxide interface.An advantage of this type is its high conversion gain due to the small sensing area compared to thefloating well type.The device achieves a charge-to-voltage conversion gain of220 V/electron and a dynamic range of79dB at3.58MHz video bandwidth and at room temperature.This detector shows an effective readout noise of only 0.5electrons rms,so that it can be used as an electron counting detector and the evaluation can be done by directly observing the discrete levels corresponding to the number of signal electrons.The79dB dynamic range is sufficient for a CCD image sensor detector.10.2.2.1Device StructureThe developed charge detector has low sensing capacitance and a structure which is inherently free of kTC noise.The principle is a combination of an n-type buried sensing channel and a P-channel surface detection transistor across it[5–7].Figure10.9shows a cross-sectional view of the detection transistor across the sensing channel.A shallow p-well with a sensing channel in it and source/drain p C regions are formed on an n-type substrate.The shallow p-well under a sensing channel is completely depleted.The P-type channel for the detection transistor lies at the silicon–silicon dioxide interface.The charge packets modulate the channel conductance in the P-channel detection transistor.S G DFig.10.9Crosssection offloating surface detection transistor10Low-Noise Electronic Imaging with Double-Gate FETs227 Fig.10.10Practicalfloatingsurface charge detectorstructureFigure10.10shows a practical output amplifier for detecting the charge(electron) packets transferred in a three-phase linear CCD,which is fabricated in a shallow p-well on the n-type substrate of45 cm resistivity.The potential control gate G area with the thick gate oxide layer measures4 4 m2which is smaller than that of thefloating well type.The thin gate layer under the FPP is120nm thick which is slight thicker than that of thefloating well type.To form the P-type channel for the detection transistor,a local deep phosphorus implant on the sensing channel is required[3,7].A charge(electron)packet is transferred into the sensing channel through the output gate(OG)at the fall time of a¥1clock voltage applied on the last transfer electrode of the CCD.Subsequently,it is converted to a voltage signal using thefirst-stage source-follower,which consists of the detection transistor and a load transistor.The drain of the detection transistor is grounded,and the source voltage of the load transistor is15V.The voltage applied to the potential control gate G is adjusted between30and 80V.An output signal is generated using the second-stage source-follower constructed with n-channel MOS transistors.To remove the charge(electron)packet from the sensing channel region into the reset drain(RD),a positive pulse is applied to the reset gate(RS).This completely depletes the sensing channel in a so-called“transfer operation.”As a consequence,the detector has no reset(kTC)noise[5,6].10.2.2.2Device SimulationA two-dimensional device simulator,handling both signal electrons in a bulk poten-tial well and hole current along the silicon–silicon dioxide interface simultaneously, has been newly developed to analyze thefloating surface detector.The simulations were done along the signal electron transfer direction.Figure10.11a,b shows the potential distributions for no signal charge and for3600-electron signal charge, respectively.The potential level at y D0in Fig.10.11indicates the surface potential. Thefirst maximum potential level along the y axis indicates the buried-channel228Y.MatsunagaFig.10.11Two-dimensional potential distribution at detection section.(a)No signal electron.(b) 3,600signal electronpotential.As shown in Fig.10.4b,the surface potential in the detector section is lowered by signal charge,compared to that for no signal charge.The sensing capacitance is calculated with the amount of signal charge and the difference in the surface potentials between Fig.10.11a,b which corresponds to the charge/voltage conversion gain of the detector.The resultant sensing capacitance is0:22fF= m per FPP length.10.2.2.3EvaluationThe device is evaluated at a7.16-MHz clock frequency,which is twice the NTSC color subcarrier frequency.The signal duty,which is the signal output period to the clock cycle time ratio,is approximately75%,which was determined by a35ns positive reset pulse.The measured charge-to-voltage conversion gain of this detector is shown in Fig.10.12as a solid line.It was measured by injecting a series of charge packets into the sensing channel.The conversion gain is linear over a charge packet range from20to4,500electrons/packet,and it is as high as220 V/electron. The measured conversion gain is higher than that obtained from the simulated sensing capacitance value by about20%.A three-dimensional device simulation may be needed for more accurate estimation,because the difference between the measurement and the calculation can be due to potential distribution perpendicular to the signal electron transfer direction.The output noise of the new detector was measured using a spectrum analyzer. Figure10.13shows noise spectra for the device,both in the reset operation and in the transfer operation.In the reset operation,residual charge in the sensing channel includes reset noise(kTC noise)charge due to the thermal noise generated in the reset gate(RS).Conversely,in the transfer operation,the reset noise is completely suppressed,because no residual charge exists in the sensing channel.The overallFig.10.12Charge/voltageconversion characteristics10-11011021031041110-210-310-4O u t p u t v o l t a g e [V ]Number of electrons[electrons / packet]Fig.10.13Noise spectra offloating surface detector inreset operation and in transferoperationrms noise value,within the frequency range of 10kHz–3.58MHz,is 84 V rms at room temperature.The noise level of 84 V rms and a signal duty ratio of 75%result in an effective readout noise of as low as 0.5electron.Thus,the dynamic range is as wide as 79dB.In the signal range below 20electrons,charge generation by photoelectric conversion effect in the CCD with weak incident light through a neutral density (ND)filter is induced to evaluate the detector,as shown in Fig.10.14.Injection packet size in the sensing channel is known in advance by this method.A signal packet of ten electrons is made by inserting a 10 2ND filter in the light path.The light intensity is set so as to generate 1,000electrons/packet,which is measured using the current meter in the figure.Figure 10.15a shows waveforms of the RS input pulse,a ¥1input pulse,and the resultant output signal.Figure 10.15b is aFig.10.14Evaluation circuitFig.10.15Charge/voltage conversion characteristics.(a)RS,®1input,and resultant signal output.(b)Amplified output voltage around ten signal electronsphotograph of the signal voltage amplified by an external circuit when the average number of electrons in a signal packet is10.The amplified signal is processed through a3.58MHz low-passfilter to remove worthless high-frequency noise. Discrete voltage levels corresponding to around ten electrons are observed.Output levels,which correspond to other than ten electrons,are caused byfluctuation of the incident light.The charge-to-voltage conversion characteristics obtained by observing the discrete levels are shown in Fig.10.16.The conversion gain above 10electrons in Fig.10.16is approximately the same as that in Fig.10.12.The conversion ratio under ten electrons shows less linearity.However,high responsivity is still maintained in the small signal region.21O u t p u t v o l t a g e [m V ]510Packet size [electrons]150Fig.10.16Charge/voltage conversion characteristics obtained by discrete level observationFig.10.17Charge/voltage conversion characteristics.(a )Double-gate transistor.(b )Thin-gate-oxide transistor (c )Thick-gate-oxide transistor10.2.2.4DiscussionThe detection transistor is the P-channel surface transistor with the sensing channel as the buried gate.Here,the gate electrode structures in the transistor are discussed.Figure 10.17a–c shows source-follower diagrams using the double-gate transistor,a thin-gate-oxide transistor,and a thick-gate-oxide transistor,respectively.The oxide thicknesses of the transistors are 120and 1,000nm,respectively.The same voltage as the RD voltage is applied to the buried gate by switching the neighboring RS gate on.Figure 10.18shows the buried-gate voltage versus the output voltage of the source followers.The source-follower gains are obtained by the slopes of curves (a)–(c)in the figure.They are 0.78,0.31,and 0.49,respectively.In the buried-gate voltage range of 13–15V ,the output voltages of types (a)and (b)are saturated.Buried Gate Voltage V IN [V]O u t p u t V o l t a g e V O U T [V ]Fig.10.18Source-follower characteristicsThis shows that the sensing channels are completely depleted.On the contrary,the saturation is not observed in type (c).The source-follower gain of type (c)is smaller than that of type (a)in spite of the thick gate oxide,since the P-type channel is also not flat and the transistor characteristics are degraded.The sourcefollower gain g1is represented as C BC =.C BC C C GC /,where C BC and C GC are buried-gate transistor channel capacitance and gate oxide capacitance,respectively.However,the charge-to-voltage conversion gain g2is proportional to .1=C BC C 1=C GC / C BC =.C BC C C GC /D 1=C GC ,because the depletion-layer depth under the sensing channel reaches to 15 m,and the capacitance between the buried gate and the substrate is negligibly small.So,the relationship between g1and g2is described by the following equation:g2D f g1=.1 g1/g C BC :(10.1)Equation (10.1)shows that the charge-to-voltage conversion gain g2strongly depends on the source-follower gain g1,g2increases dramatically if g1is close to 1.Especially,the charge-to-voltage conversion gain rapidly decreases in the small-signal region.The conversion gain increases seven times by using the double-gate structure compared to the thin-gate-oxide transistor.The conversion gain ratio of the double-gate to thick-gate-oxide transistors is 220W 31D 3:55W 0:50,in good accordance with the g1=.1 g1/ratio of 3.55:0.45.It is clear from the above discussion that the double-gate structure can realize superior high conversion gain detectors.10.3CCD Image Sensor with Double-Gate FETCharge DetectorThe pixel size of the CCD image sensor has been made smaller to reduce chip size for small optical assembly and to realize megapixel sensors for HDTV cameras. It is not acceptable,however,to compromise the sensor performance for a smaller cell size,and in particular,the sensitivity and the dynamic range remain high[1]. In contrast,the buried-channel charge-coupled device achieves complete charge transfer with no transfer noise.Therefore,almost all solid-state image sensors utilize low-noise buried-channel CCD for scanning circuits.In the following we describe a1/3-in interline transfer CCD area image sensor with94-dB dynamic range and1.0-electron rms noisefloating surface detector. With capacitance-coupled negative-feedback configuration,the saturation level of the detector is successfu1ly extended by a factor of5,maintaining the superior low-noise characteristics.Moreover,1=f noise in the output signal,which is a very conspicuous streak noise in the reproduced image in spite of its low-noise power,is successfully suppressed with a novel so-called alternate gain inversion(AGI)signal processing technique.10.3.1Sensor ConstructionFigure10.19shows photographs of the fabricated device chip and the detection transistor.The chip size is7.1mm.H/ 5:1mm(V),and the image size is 4.8mm.H/ 3:6mm(V),which is suitable for a1/3-in lens format.The device is the most popular interline transfer CCD configuration at present,which consists of photodiodes,vertical CCDs(V-CCDs),and a horizontal CDD(H-CCD).For low leakage current noise,the buried photodiode structure,which has a high concentration p C-layer on the n-type storage region,is adopted[7,8].The charge detector at the end of the H-CCD is a double-gatefloating surface detector with an effective readout noise of1.0electron rms.A dynamic range of94dB is obtained by returning the inverted voltage signal onto a feedback gate.The saturation number of electrons is extended to5 104electrons,which corresponds to the saturation charge of the photodiode.The device is fabricated in a shallow p-well on an n-type substrate of47 cm resistivity with1:0 mfine pattern design rule.Two ion-implantation processes are added to the conventional CCD fabrication process.One is a high-energy phosphorous implantation for the sensing channel,and the other is a source/drain boron implantation for the P-channel detection transistor.Fig.10.19Photographs ofsensor chip and enlargeddetector10.3.2Feedback Charge DetectorFigure10.20shows the detector structure.The signal charge(electron)packets are clocked along the H-CCD,and transferred into the detection transistor signal sensing region under the FPP.The detected charges are moved out into a reset drain (RD)by applying a positive pulse on a reset gate(RS).The signal charge in the sensing region modulates the P-channel conductance in the detection transistor.An output signal is generated using two source-follower stages,constructed with n-channel MOS transistors.An inverted signal voltage is applied to the feedback gate of the detection transistor.The feedback amplifier is an inverter and its noise is designed to be much smaller than that of the source followers in order not to add extra noise by the feedback loop.The capacitance-coupled feedback loop allows the dynamic range to be extended.The oxide thickness between the feedback gate and the FPP is approximately1:0 m.Figure10.21shows the increase in the saturation charge by the negative feedback operation.Signal charge Qs is converted into voltage signal Vs by the very low sensing capacitance Ce in the case of the open loop as shown in Fig.10.21a.On the contrary,in the feedback operation,the effective sensing capacitance increases n times by the inverted signal voltage,which is applied to the feedback gate,so that the output signal voltage is compressed,as shown in Fig.10.21b,and the saturation charge increases by a factor of n,as shown in Fig.10.21c.The parameter n is equal to the well-known feedback formula(1C kA),where k and A are the feedbackFig.10.20Detector structureFig.10.21Potential diagrams of sensing channel.(a)Saturation condition in open loop.(b) Compressed condition by negative feedback.(c)Saturation condition in negative feedbackcoefficient and the feedback amplifier gain,respectively.In this detector,k is equal to Cg=.Cg C Cc/,where Cg and Cc are the gate capacitance of the detection transistor and the diffusion capacitance of the n-type sensing channel under the FPP,respectively.It is derived from the partition ratio of the Cg and Cc series capacitances.Noiseless signal charge is converted into the voltage signal S,while the detector noise is N in the open-loop charge detector.By applying the inverted output signal onto the feedback gate,not only the voltage signal but also the detection noise is compressed,and they result in S0and N0.Signal-to-noise ratio S0=N0is equal to。

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外文文献翻译- 基于单片机的频率计设计本科学位论文

外文文献翻译- 基于单片机的频率计设计本科学位论文

原文：This design take at MCS-51 monolithic integrated circuit as the core full use hardware source design's one kind of frequency meter, this frequency meter will be measured first that signal enlargement reshaping processing, turns satisfies TTL/which the monolithic integrated circuit I/O mouth accepts the CMOS compatible signal from monolithic integrated circuit's T1 input port input direct summation pulse number, the monolithic integrated circuit interior timer fixed time is 1S, by now accumulated the pulse number namely for is measured the signal the frequency. Finally passes through monolithic integrated circuit processing to deliver to the lcd liquid crystal display monitor demonstration.Central Processing Unit DesignsThe CPU is the key component of a digital computer. Its purpose is to decode instruction received from memory and perform transfers, arithmetic, logic, and control operations with data stored in internal registers, memory, or I/O interface units. Externally, the CPU provides one or more buses for transferring instructions, data, and control information to and from components connected to it. In the generic computer at the beginning of chapter 1, the CPU is a part of the processor and is heavily shaded. CPUs, however, may also appear in computers. Small, relatively simple computers called microcontrollers are used in computers and in other digital systems to perform limited or specialized tasks. For example, a microcontroller is present in the keyboard and in the monitor in the generic computer; thus, these components are also shaded. In such microcontrollers, the CPU may be quite different from those discussed in this chapter. The word lengths may be short (say, four or eight bits),the number of registers small, and the instruction sets limited. Performance, relatively speaking, is poor, but adequate for the task. Most important, the cost of these microcontrollers is very low, making their use cost effective.In the following pages, we consider two computer CPUs, one for a complex instruction set computer (CISC) and the other for a reduced instruction set computer (RISC). After a detailed examination of the designs, we compare the performance of the two CPUs and present a brief overview of some methods used to enhance that performance. Finally, we relate the design ideas discussed to general digital system design.1、T he complex instruction set computerThe first design we present is for a complex instruction set computer with a non-pipelined datapath and microprogrammed control unit. We begin by describing the instruction set architecture, including the CPU register set, instruction formats, and addressing modes. TheCISC nature of the instruction set architecture is demonstrated by its memory-to-memory access for data manipulation instructions, eight addressing modes, two instruction format lengths, and instructions that require significant sequences of operations for their execution.We design a datapath for implementing the CISC architecture. The datapath is based on the one initially described in Section 7-9 and incorporated into a CPU in section 8-10. modifications are made to the register file, the function unit, and the buses to support the present instruction set architecture.Once the datapath has been specified, a control unit is designed to complete the implementation of the instruction set architecture. The design of the control unit must involve a coordinated definition of both the hardware organization and the microprogram organization. In particular , dividing the microprogram into microroutines, while at the same time designing the sequencer with which they interact, is a key part of the design. Even the instruction fields and opposed are tied to this coordinated effort. Following the definition of the hardware and microcode organizations, we detail essential parts of the microcode and the microroutines for representative operations.Instruction set architectureFigure 10-1 shows the CISC register set accessible to the programmer. All registers have 16 bits. The register file has eight registers, R0 though R7.R0 is a special register that always supplies the value zero when it is used as a source and discards the result when it is used as a destination.In additional to the register file, there is a program counter PC and stack pointer SP. The presence of a stack pointer indicates that a memory stack is a part of the architecture . the final register is the processor status register PSR, which contains information only in its rightmost the five bits; the remainder of the register is assumed to contain zero. The PSR contains thefour stored status bit values Z,N,C,and V in positions 3 through 0, respectively. In additional, a stored interrupt enable bit EI appears in position 4.Table 10-1 contains the 42 operations performed by the instructions. Each operation has a mnemonic and a carefully selected oppose. The operations are divided into four groups based on the number of explicit operands and whether the operation is branch. In addition, the status bits affected by the operation are listed.Figure 10-2 gives the instruction formats for the CPU. The generic instruction format has five fields. The first, OPCODE, specifies of the operation. The next two, MODE and S , are used to determine the addresses of the operands. The last two fields, SRC and DST, are the 3-bit source register and destination register address fields, respectively. In addition, there is an optional second word W that appears with some instructions as an operand or an address, but not with others.The first two bits of OPCODE, IR(15:14), determine the number of explicit operands and how the fields of the format are used. When these bits are 00,either no operand is required or the location of the operand is implied by OPCODE. Only the OPCODE field is needed, as shown in figure 2(b).the four rightmost OPCODE bits can specify up to 16 operands or with implied operand addresses.If IR(15:14) is 01, the instruction has one operand and is a data transfer or data manipulation instruction. Since there is an operand, the MODE field specifies the addressing mode for obtaining it. The single address may involve the DST register address in its formation, so the DST field is also present. The S field and SRC field relate to the presence of two operands and so are not used for the typical single operand instructions. but, the shift instructions require a shift amount to indicate how many bits to shift. For maximum flexibility,this shift amount is treated just like a source operand. As a consequence, the SHA and S fields is a full 16-bit operand, but only values 0 through 15 are meaningful. There are sufficient OPCODE bits for 16 instructions with a single operand.Table 10-2 gives the addressing modes specified by the MODE field. The first two bits of MODE specify four different types of addressing: register, immediate, indexed, and relative to the PC. The third bit of MODE specifies whether the address generated by these modes is used as an indirect address. The one exception to this is direct addressing, which is obtained by applying indirection to the immediate type. Otherwise, if the third bit equals 0, indirect addressing does not apply whereas, if it equals 1, indirect addressing does apply. For the register type of instruction, MONE(2:1)=00 and the W word is not needed. Since the operand or address comes from a register. The third column of the table provides register transfer statements for each of the addressing modes for the one-operand instructions.If IR(15:14) is equal to 10, then the instruction has two addresses used for true operands. All fields of the generic instruction, including S and SRC, are used for this case for all instructions. one of addresses, either the source or the destination, uses the addressing modes. If S=0, then the source uses the addressing mode specified by MODE, and the source is a register. If S=1, then the destination uses the addressing mode, and the source is a register. Register transfer descriptions of the resulting addresses are given in the fourth and fifth columns of Table 2. Again, depending on the contents of the MODE field, the second instruction word W, which is an address or an immediate operand, may or may not be present.Instructions with IR(15:14)=11 are branches. Aside form the S field and the SHA field for shifts, the format is the same as for IR(15:14)=01. For all instructions of this type, the destination address (not the operand) becomes the new address placed in the program counter PC. As a consequence, the register mode is invalid for branch instructions.Before proceeding to the next step, which defines the datapath to support the instruction set architecture, we will briefly note the characteristics of the architecture that define it as CISC or RISC. Most of the operations given in Chapter 9 are included in the instruction set. A number of operations that do not appear are redundant. The same actions can be achieved by using proper addressing modes with instructions that do appear. For example, LD, ST, IN, and OUT can all be achieved by using MOVE instructions in a memory-mapped structure. By looking at the formats for the instructions, we find that most of the instructions can operate directly on operate directly on operands from memory. There are eight addressing modes and two different lengths of instruction formats. In addition, some of the instructions perform complex operations which can be viewed as operations that are likely to take more than one clo ck cycle for the execution step. These characteristics clearly identify this as a CISC architecture.Datapath organizationRather than beginning from scratch, we will reuse the non-pipelined datapath employed with the microprogrammed control in section 8-10, with modifications. That datapath was shown in section 8-10, and the new, modified datapath based on it is given in Figure 10-6. we treat each modification in turn, beginning with the register file.In section 8-10, register R8 was used as a temporary storage location. In the new microprogrammed architecture, there are complex instructions spanning many clock cycles and performing complicated operations. Thus, more temporary storage is needed for use by the microprograms. To meet this need, we expand the register file from 9 registers to 16. the first 8 registers, R0 through R7, are visible to the computer programmer. The second 8 registers, R8 though R15 , are used as temporary storage for the microprogram operands and are hidden from the programmer. Figure 10-3 provides a map of the expanded register file with the temporary registers shaded. As indicated previously, register R0 supplies the constant 0. registers R1 through R7 are available to the programmer for use, and registers R8 through R15 provide general temporary storage for use by microprograms, the last four registers, R12 though R15, have special uses: to keep the microcode simple, standard locations are essential for storing the operands and addresses used by execution microcode for most instructions. thus ,R12 is the location for the source address(SA), R13 for the source data (SD), R14 for the destination address(DA), and R15 for the destination data(DD).We cannot access the eight temporary registers based on the 3-bit register address available in the instruction. To deal with this problem, we provide, first, 4-bit register address from the microinstruction, and second, a microinstruction bit to choose between these addresses and those from the instruction. In addition, the flexibility to allow the register addressed by DST to be a source and by SRC to be a destination is needed to permit results ofoperations to be placed directly in memory. To accomplish these goals, we modify the register file by adding the logic shown in Figure 10-4(a). the instruction set architecture uses two addresses, one for a source a operand and the other for the other source as well as the destination. The register file uses the B address for a source, and the A and D addresses on the file are connected together, giving the same address for the other source and the destination. Although this reduction from three to two addresses is not essential at the mincroinstruction level, it decrease the number of bits needed for register addresses in the microinstruction and matches the use of the register fields in the instruction formats.A quad 2-to-1 multiplexer is attached to each of the two address inputs to the register file, to select between an address from the microinstruction and an address from the instruction. There is a 5-bit field in the microinstruction for the combined destination and source address DSA, in addition to a 5-bit field for theB address SB. The first bit of each of the these fields selects between the register file address in the microinstruction(0) and the register file address in the instruction(1). If an instruction address is selected, whether it is DST or SRC is determined by an additional quad 2-to-1 multiplexer. This multiplexer is controlled by the second bit of the DSA or SB fields, depending on which of them has 1 in the first bit in any microinstruction, thereby ensuring that the proper second bit is used to determine the register address. A 0 is appended to the left of the 3-bit fields DST and SRC to cause them to address R0 through R7. the addition to the first bit, which selects the address source, the addresses from the microinstruction contain four bits so that all 16 registers can be reached. The final change to the register file is to replace the storage elements for R0 in the file with open circuits on the lines that were their inputs and with constant zero valves on the lines that were their outputs. A symbol for the resulting register file is show in Figure 10-4(b).We find that, based on the eight shift instructions provided, the shifter from section 8-10, needs to be modified. The modifications involve the end bits of the shift logic. For logical shifts, a 0 is inserted, as before. For the right arithmetic shift, she sign bit is the incoming bit, and for the left arithmetic shift, 0 is the incoming bit. Rotates require that the bit from the opposite end of the shifter be fed around. Finally, rotates with carry require that the carry flip-flop output be provide as an input on both ends of the shifter.2.SummaryIn this paper．we examined two CPU designs: the CISC and RISC.The CISC control unit includes a stack pointer in addition to the program counter．Control microprograms reside in ROM．and a combination of a multi．plexer and a ROM provides fast instruction decoding．The control unit also has extensive{ump andconditional branching capabilities，including one level of microsubroutines．The microprogram for the control is modularized to permit many microsubroutines to be shared in implementing the microprogram for the instructions．The RISC control unit is pipelined and has special hardware added to deal with branches. Pipelined CPUs have both data and control hazard problems．We examined one of each type of hazard，as well as software and hardware solutions for each．After discussing CISC and RISC performance，we touched on some advanced concepts, including parallel execution units, a combination of microprogrammed control with a pipeline，superpipelined CPUs, superscalar CPUs，and predictive and speculative techniques for high-performance．Finally, we related the design techniques in this paper to more general digital system design．原文翻译：本设计以MCS-51单片机为核心充分利用硬件资源设计的一种频率计，该频率计首先将被测信号放大整形处理，变成满足单片机I/O口接受的TTL/ CMOS 兼容信号从单片机的T1输入口输入直接累加脉冲数，将单片机内部定时器定时为1S，这时累加的脉冲数即为被测信号的频率。

基于单片机的数字钟设计

基于单片机的数字钟设计

毕业设计论文作者学号系部专业题目基于单片机的多功能数字钟设计指导教师评阅教师完成时间：毕业设计(论文)中文摘要毕业设计(论文)外文摘要目录1 绪论51.1背景资料51.1.1设计多功能数字钟的目的51.1.2电子线路CAD与Prote99 SE软件的简介51.1.3单片机简介71.2本设计的主要工作82 系统功能和设计说明92.1总体方案设计92.1.1本课题主要技术要求92.1.2总体方案比较与论证92.1.3总体设计原理方框图102.2 硬件模块电路设计102.2.1电压有效值测量设计102.2.2时钟电路的设计122.2.3温度检测电路设计132.2.4频率测量设计132.2.5键盘显示设计152.2.6报警电路162.2.7单片机最小系统162.3 软件设计192.4测试方法202.5总结21结论23致谢24参考文献241绪论1.1背景资料1.1.1设计多功能数字钟的目的目前市售的电子产品很多,一般只能显示时间信息,功能单一. 但在一些特殊行业，如电力部门，为了工作的便利，要求数字钟不仅能显示时间信息，最好还能直接显示供电情况，电力运行情况。

这样，市场上销售的数字钟就显得功能单一，不能满足需求。

这里我们所要设计的是专门用于电力部门的多功能数字钟。

本文所设计的多功能数字钟是利用单片机技术，采用了几种新型的芯片而共同构成的。

它具有基本的电子时钟，闹钟功能，并且能够显示环境温度，电网电压，电网频率及实现过压欠压报警。

本系统充分挖掘了单片机的资源和运算控制功能，具有功能多，显示全，成本低的特点。

1.1.2电子线路CAD与Prote99 SE软件的简介本设计的电子线路图和PCB线路版图都采用计算机辅助制图，现介绍使用的做图软件及方法。

一、电子线路CAD简介：电子电路CAD技术是电子信息技术发展的杰出成果,它的发展与应用引发了一场工业设计和制造领域的革命。

给企业带来了巨大经济效益。

当今, 电路CAD技术及其应用水平已成为衡量一个国家科技现代化和工业现代化水平的重要标志之一。

数字时钟外文翻译

数字时钟外文翻译

数字时钟外文翻译LED displays using digital tubes offer high brightness and intuitive intelligence。

___ design for a n electronic clock。

using a single-chip puter as the core and a total of seven anode high-brightness LEDs as a display to show week。

hour。

minute。

and second。

The clock can also switch to year。

month。

and day display。

and includes a whole point of music and alarm n。

nally。

it can be used as an electronic watch.The clock circuit is the heart of the computer。

controlling the rhythm of its ___.The design of this nal digital clock system is based on the principle of single-chip technology。

using the AT89C52 single-chip puter as the core controller。

Through the n of hardware and are res。

the clock system has been designed to include a clock module。

alarm module。

ambient temperature n module。

liquid crystal display module。

基于单片机的计算器设计毕业设计+外文文献翻译

基于单片机的计算器设计毕业设计+外文文献翻译

摘要计算器一般是指“电子计算器”,能进行数学运算的手持机器，拥有集成电路芯片，结构简单，功能较弱，但由于它使用方便、操作简单、价格低廉，因而广泛运用于商业交易中，也是必备的办公用品。

近年来随着科技的飞速发展，单片机的应用正在不断深入，同时带动传统控制检测技术日益更新。

在实时检测和自动控制的单片机应用系统中，单片机往往作为一个核心部件来使用，但仅单片机方面的知识是不够的，还应根据具体硬件结构、软硬件结合，来加以完善。

因此，单片机的应用已经越来越贴近生活，用单片机来实现一些电子设计也变得容易起来。

计算器在人们的日常中是比较的常见的电子产品之一。

可是它还在发展之中，以后必将出现功能更加强大的计算器，基于这样的理念，本次设计是用单片机来设计的计算器。

该设计系统是以AT89S52 为单片机，P1 口作为输入端，外接4X4 的键盘。

通过键盘扫描来对输入数的控制，在P0 口、P2 口接了驱动电路，用来保证LCD 的工作正常。

计算器将完成的功能有加，减，乘，除等功能。

关键词：计算器；单片机；LCD；矩阵键盘ABSTRACTCalculator generally refers to the electronic calculator, and the term is introduced to China by the Japanese. The calculator with the IC chip, simple structure, and weak function is able to perform mathematical operations on handheld machine. But it is easy using, simple operation and low price. So it is widely used in commercial transactions, and is also an essential office supplies.With the rapid development of science and technology in recent years, the application of SCM is the deepening and promote the traditional controlling detection technologies that are increasingly updated. In real-time detection and automatic control of microcomputer application system, the microcontroller is often used as a core component to use, but only the knowledge of the microcontroller is not enough, and should be based on the specific hardware architecture, hardware and software combination to make it perfect. So the application of SCM is more and more close to life, so using of single chip to achieve some electronic designs also become easy. In the people daily life the calculator is one of the common electronic products. But it is still in development, it will become more powerful calculator in the future. According to such idea, the design is that SCM design calculator. The design system is based on AT89S52 microcontroller, P0 port as input, external 4X4 keyboard. In P1, P2mouth is connected with the drive circuit to ensure the normal work of LED. The calculator will complete add, subtract, multiply, divide and other function.Keywords: calculator, MCU, LCD, Matrix keyboard前言计算器（calculator;counter）一般是指“电子计算器”，能进行数学运算的手持机器，拥有集成电路芯片，结构简单，功能较弱，但由于它使用方便、操作简单、价格低廉，因而广泛运用于商业交易中，也是必备的办公用品之一。