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14.Hard Processor System I/O Pin MultiplexingThe Intel Agilex SoC has a total of 48 flexible I/O pins that are used for hard processor system (HPS) operation, external flash memories, and external peripheral communication. A pin multiplexing mechanism allows the SoC to use the flexible I/O pins in a wide range of configurations.Related InformationIntel Agilex Hard Processor System Technical Reference Manual Revision History on page 12For details on the document revision history of this chapter14.1. Features of the Intel Agilex HPS I/O BlockThe I/O block provides the following functionality and features:•Dedicated HPS I/O pins—48 pins available for HPS clock, external flash memories and peripherals.Note: The HPS also interfaces with an SDRAM memory controller . This interface is separate from the dedicated pins discussed in this chapter .•I/O multiplexing—Selects pins used by each HPS peripheral —Can expose HPS peripheral interfaces to FPGA logicNote: When routed to the FPGA, some HPS peripherals require additional pipeline support in the connected soft logic. Refer to the relevant HPS peripheral chapter for details.You configure I/O multiplexing when you instantiate the HPS component in Platform Designer.Related InformationExternal Memory Interface Handbook For details about memory I/O pins in the SoC hard memory controller , refer to the Functional Description - HPS Memory Controller chapter of the External Memory Interface Handbook .MNL-1100 | 2021.03.09Send FeedbackISO 9001:2015Registered14.2. Intel Agilex HPS I/O System IntegrationThe HPS I/O block consists of the following sub-blocks:•Dedicated pin multiplexers (MUXes) – MUXes for the dedicated I/O bank •FPGA access pin multiplexers – MUXes for HPS peripheral connections to the FPGA fabric •Register slave interface – Provides access to control registers, which allow the bootloader to initialize I/O pins and HPS peripheral interfaces at system startupRelated InformationIntel Agilex I/O Control Registers on page 18514.3. Functional Description of the HPS I/O14.3.1. I/O PinsThe HPS has 48 dedicated I/O pins. They are divided into four quadrants of 12 signals per quadrant. When you instantiate the HPS component in Platform Designer, you must assign one of the 48 pins as the HPS clock. You can then use the remaining dedicated I/O pins for other common peripherals.You can alternatively route most HPS peripherals (except USB) through the FPGA.Select this routing when you instantiate the HPS Component. For more information,refer to the Intel Agilex HPS Component Reference Manual .Note:When assigning an HPS peripheral to HPS dedicated pins, you must assign all peripheral I/O pins to the same quadrant, except for NANDx16, Trace, and GPIO.Note: Although the HPS dedicated I/O pins are configured through the control registers,software cannot reconfigure the pins after I/O configuration is complete. There is no support for dynamically changing the pin MUX selections for HPS dedicated I/O pins.Related Information•Booting and Configuration on page 512Details about the boot up process for the Intel Agilex HPS •FPGA Access on page 184Information about routing HPS peripheral interfaces to the FPGA •Configuring HPS I/O Multiplexing on page 188Information about configuring the HPS I/O MUXes14.3.2. FPGA AccessMost HPS peripheral interfaces can be connected into the FPGA fabric, instead of to the dedicated I/O pins.HPS peripherals connect to the FPGA fabric through the FPGA access pin MUX. When connected to the FPGA fabric, peripheral interfaces are exposed as ports of the HPS component.14.Hard Processor System I/O Pin MultiplexingMNL-1100 | 2021.03.09Send FeedbackNote: For warm resets, software can set the brgwarmmask registers to prevent theassertion of module reset signals to peripheral modules.When a module that has been held in reset is ready to start running, software can deassert the respective reset signal by writing to the following appropriate register .Modules Module Reset Signal RegisterFPGA fabrics2f_rst -s2f_cold_rst -s2f_watchdog_rst-Debug domain with CoreSight and Trace dbg_rst_ndbgmodrst.dbg_rst dbgmodrst.csdap_rst MPU corereset_n [3:0]mpumodrst.core[3:0]cpuporreset_n [3:0]coldmodrst.cpupor[3:0]l2reset_n coldmodrst.l2DMA dma_rst_n per0modrst.dmadma_ecc_rst_n per0modrst.dmaocpdma_periph_if_rst_n [7:0]per0modrst.dmaif[7:0]SPI Master and Slave spim_rst_n [1:0]per0modrst.spim[1:0]spis_rst_n [1:0]per0modrst.spis[1:0]Ethernet MAC emac_rst_n [2:0]per0modrst.emac[2:0]emac_ecc_rst_n [2:0]per0modrst.emac[2:0]ocpemac_ptp_rst_n per0modrst.emacptpUSB usb_rst_n [1:0]b[1:0]usb_ecc_rst_n [1:0]b[1:0]ocpNAND Flash nand_flash_rst_n per0modrst.nandnand_flash_ecc_rst_n per0modrst.nandocpSD/MMC sdmmc_rst_n per0modrst.sdmmcsdmmc_ecc_rst_n per0modrst.sdmmcocpWatchdog watchdog_rst_n [3:0]per1modrst.watchdog[3:0]Timer l4sys_timer_rst_n [1:0]per1modrst.l4systimer[1:0]sp_timer_rst_n [1:0]per1modrst.sptimer[1:0]I 2C i2c_rst_n [4:0]per1modrst.i2c[4:0]UART uart_rst_n [1:0]per1modrst.uart[1:0]GPIO gpio_rst_n [1:0]per1modrst.gpio[1:0]SoC-to-FPGA Bridge soc2fpga_bridge_rst_n brgmodrst.soc2fpgaFPGA-to-SoC Bridge fpga2soc_bridge_rst_n brgmodrst.fpga2socLightweight SoC-to-FPGA Bridge lwsoc2fpga_bridge_rst_n brgmodrst.lwsoc2fpgaMPFE mpfe_rst_nbrgmodrst.mpfe 13.Reset ManagerMNL-1100 | 2021.03.09Send Feedback。
Table 180.Clock Manager Settings Register.FieldDescription en.emacptpenemac_ptp_clk output enable.en.emac0enen.emac1enen.emac2enEnables clock emac0_clk , emac1_clk and emac2_clk output.Note: There are corresponding ens and enr registers that allow the same fields to be set or cleared on a bit-by-bit basis.bypass.emacptp EMAC PTP clock bypass. This bit indicates if the emac_ptp_clk is bypassed to the input clockreference of the peripheral PLL.•0x0= No bypass occurs•0x1= emac_ptp_clk is bypassed to the input clock reference of the main PLL.Note: There are corresponding bypasss and bypassr registers that allow the same bits tobe set or cleared on a bit-by-bit basis.bypass.emacabypass.emacb Clock Bypass. This bit indicates whetheremaca_free_clk or emacb_free_clk is bypassed to the input clock reference of the main PLL.•0x0= No bypass occurs•0x1= emac*_free_clk is bypassed to the input clock reference of the main PLL.Note: There are corresponding bypasss and bypassr registers that allow the same bits tobe set or cleared on a bit-by-bit basis.emacctl.emac0selemacctl.emac1selemacctl.emac2sel EMAC clock source select. This bit selects the source for the emac*clk as either emaca_free_clk or emacb_free clk •0x0= emaca_free_clk •0x1=emacb_free_clk17.7.2. EMAC FPGA Interface InitializationTo initialize the Ethernet controller to use the FPGA GMII/MII interface, specific software steps must be followed.In general, the FPGA interface must be active in user mode with valid PHY clocks, the Ethernet Controller must be in a reset state during static configuration and the clock must be active and valid before the Ethernet Controller is brought out of reset.1.After the HPS is released from cold or warm reset, reset the Ethernet Controllermodule by setting the appropriate emac* bit in the per0modrst register in theReset Manager .2.Configure the EMAC Controller clock to 250 MHz by programming the appropriate registers in the Clock Manager .3.Bring the Ethernet PHY out of reset to verify that there are RX PHY clocks. For verification, you may have to coordinate with the bring up of transceiver from reset.4.If the PTP clock source is from the FPGA, ensure that the FPGAf2s_ptp_ref_clk is active.5.The soft GMII/MII adaptor must be loaded with active clocks propagating. The FPGA must be configured to user mode and a reset to the user soft FPGA IP may be required to propagate the PHY clocks to the HPS.6.Once all clock sources are valid, apply the following clock settings:a.Program the phy_intf_sel field of the emac* register in the SystemManager to 0x0 to select GMII/MII PHY interface.17.Ethernet Media Access ControllerMNL-1100 | 2021.03.09Send Feedbackb.If the PTP clock source is from the FPGA, set the ptp_clk_sel bit to 0x1 in the emac_global register of the System Manager .c.Enable the Ethernet Controller FPGA interface by setting the emac_* bit in the fpgaintf_en_3 register of the System Manager .7.Configure all of the EMAC static settings if the user requires a different setting from the default value. These settings include the AxPROT[1:0] and AxCACHEsignal values which are programmed in the emac* register of the System Manager .8.After confirming the settings are valid, software can clear the emac* bit in theper0modrst register of the Reset Manager to bring the EMAC out of reset..When these steps are completed, general Ethernet controller and DMA software initialization and configuration can continue.Note: These same steps can be applied to convert the HPS GMII to an RGMII, RMII or SGMII interface through the FPGA, except that in step 5 during FPGA configuration, you would load the appropriate soft adaptor for the interface and apply reset to it as well.The PHY interface select encoding would remain as 0x0. For the SGMII interface additional external transceiver logic would be required. Routing the Ethernet signals through the FPGA is useful for designs that are pin-limited in the HPS.17.7.3. EMAC HPS Interface InitializationTo initialize the Ethernet controller to use the HPS interface, specific software steps must be followed including selecting the correct PHY interface through the System Manager .In general, the Ethernet Controller must be in a reset state during static configuration and the clock must be active and valid before the Ethernet Controller is brought out of reset.1.After the HPS is released from cold or warm reset, reset the Ethernet Controllermodule by setting the appropriate emac* bit in the per0modrst register in theReset Manager .2.Configure the EMAC Controller clock to 250 MHz by programming the appropriate registers in the Clock Manager .3.Bring the Ethernet PHY out of reset to allow PHY to generate RX clocks.There are no registers to verify, but you can create the following custom logic block to cross check:•If the RX clock is routed through FPGA IO—you can use Signal Tap to check, or create a simple counter block with the RX clock as clock source to check if it runs.•If the RX clock is routed as HPS IO—you need to explore if the kernel application code is able to source through RX clock to check its status.4.When all the clocks are valid, program the following clock settings:a.Program the phy_intf_sel field of the emac* register in the SystemManager to 0x1 or 0x2 to select RGMII or RMII PHY interface.b.Disable the Ethernet Controller FPGA interface by clearing the emac_* bit inthe fpgaintf_en_3 register of the System Manager .17.Ethernet Media Access ControllerMNL-1100 | 2021.03.09Send Feedback5.Configure all of the EMAC static settings if the user requires a different setting from the default value. These settings include the AxPROT[1:0] and AxCACHEsignal values, which are programmed in the emac* register of the SystemManager .6.Execute a register read back to confirm the clock and static configuration settings are valid.7.After confirming the settings are valid, software can clear the emac* bit in theper0modrst register of the Reset Manager to bring the EMAC out of reset.When these steps are completed, general Ethernet controller and DMA software initialization and configuration can continue.17.7.4. DMA InitializationThis section provides the instructions for initializing the DMA registers in the proper sequence. This initialization sequence can be done after the EMAC interface initialization has been completed. Perform the following steps to initialize the DMA:1.Provide a software reset to reset all of the EMAC internal registers and logic. (DMA Register 0 (Bus Mode Register) – bit 0). †2.Wait for the completion of the reset process (poll bit 0 of the DMA Register 0 (Bus Mode Register), which is only cleared after the reset operation is completed). †3.Poll the bits of Register 11 (AXI Status) to confirm that all previously initiated (before software reset) or ongoing transactions are complete.Note: If the application cannot poll the register after soft reset (because of performance reasons), then it is recommended that you continue with the next steps and check this register again (as mentioned in step 12 on page 382)before triggering the DMA operations.†4.Program the following fields to initialize the Bus Mode Register by setting values in DMA Register 0 (Bus Mode Register):†•Mixed Burst and AAL •Fixed burst or undefined burst †•Burst length values and burst mode values †•Descriptor Length (only valid if Ring Mode is used)†5.Program the interface options in Register 10 (AXI Bus Mode Register). If fixed burst-length is enabled, then select the maximum burst-length possible on the bus (bits[7:1]).†6.Create a proper descriptor chain for transmit and receive. In addition, ensure that the receive descriptors are owned by DMA (bit 31 of descriptor should be set).When OSF mode is used, at least two descriptors are required.7.Make sure that your software creates three or more different transmit or receive descriptors in the chain before reusing any of the descriptors.†8.Initialize receive and transmit descriptor list address with the base address of the transmit and receive descriptor (Register 3 (Receive Descriptor List Address Register) and Register 4 (Transmit Descriptor List Address Register) respectively).†9.Program the following fields to initialize the mode of operation in Register 6(Operation Mode Register):17.Ethernet Media Access ControllerMNL-1100 | 2021.03.09Send Feedback。
http://www.fuji.co.jp/Copyright © 2007 by Fuji Machine Manufacturing Co., Ltd. All Rights Reserved版本升级报告附加资料 No. 07031A发 行 日： 2007 年 8月 2日对 应 机 型： XP-143E/243E （后期机型） （控制软件）新 版 本 号： V1.51（已发行的版本号：V1.50）下页开始为版本升级报告 No.07031 的附加资料“XP 固有值一览 Type-III V1.51”的内容。
Fuji Machine Mfg.XP 固有値一覧 Type-III V1.512007-12-4現在XP固有值一览表Type-III V1.51//_/_/_/_/_/_/_/ Proper data /_未使用●XP启动时检查范围。
请必须设定在范围以内的值。
即使没有输入范围的记述，在整数型时-2147483648～2147483647，小数型时按整数的11位到小数点以下4位为止，字符串型到31个字符为止。
项目XP-143E XP243E输入范围测定值User编辑重新接通电源解说________MACHINE_TYPE_______=__xpMachineTypeA=121～3---否需要机种选择项目 ＸＰ１４＊：１ ＸＰ２４＊：２ ＸＰ３４＊：３__xpMachineTypeB=444---否需要机种选择项目 全机种：４ 电路板搬运尺寸__xpMachineTypeC=331～3---否需要机种选择项目 TypeI：１ TypeII：２ TypeIII：３__xpMachineTypeD=11没有范围---否需要一般：１ 批量机(1)和试验机(0)的区別，（区别使用的IO）__xpTI1200A=110～1---否１：相机ＴＩ－１２００Ａ__xpSetCVA1Cam=49610～255---否需要相机的设定（高分辨率相机建立与相机相对应的比特)第1比特：相机１第2比特：相机2第3比特：相机3第4比特：相机4第5比特: 将低分辨率相机作为HR-50处理第6比特: 将高分辨率相机作为G20U20处理第7比特: 将低分辨率相机作为XC-56处理__ServoPulseReduce=000～1---否０ ： Pn２０１ ＝ １６３８４ １ ： Pn２０１ ＝ ８１９２__DispMode=000～2---可XP141选择项目 ０:影像处理中一切不显示 １：仅仅在覆盖式中显示 ２：全部显示__CornerRearSide=220～2---否需要参照内侧的Corner Pattern进行补正处理的标记的指定 0：没有Corner Dog 1：Corner Dog __PanelReverseFlow=000～2---否电路板搬运方向的指定 ０：左→右 １：右→左 （与FUJI标准机器同等） ２：右→左__RevolverInterLock=000～2---否需要增加了供料器浮起传感器和变更了吸嘴上升确认传感器 [T1.12ｅ,T1.09h] 变更为0。
