I2S接口规范(可编辑修改word版)

DPL 4519GPRELIMINARY DATA SHEET2MicronasContents Page Section Title4 1.Introduction5 1.1.Features of the DPL 4519G6 1.2.Application Fields of the DPL 4519G7 2.Functional Description7 2.1.Architecture of the DPL 4519G Family 8 2.2.Preprocessing I 2S Input Signals8 2.3.Selection of Internal Processed Surround Signals 8 2.4.Source Selection and Output Channel Matrix 8 2.5.Audio Baseband Processing 8 2.5.1.Main and Aux Outputs 8 2.6.Surround Processing8 2.6.1.Surround Processing Mode 8 2.6.1.1.Decoder Matrix9 2.6.1.2.Surround Reproduction 9 2.6.1.3.Center Modes9 eful Combinations of Surround Processing Modes 10 2.6.2.Examples11 2.6.3.Application Tips for using 3D-PANORAMA 11 2.6.3.1.Sweet Spot 11 2.6.3.2.Clipping11 2.6.3.3.Loudspeaker Requirements 11 2.6.3.4.Cabinet Requirements11 2.6.4.Input and Output Levels for Dolby Surround Pro Logic 11 2.7.SCART Signal Routing 11 2.7.1.SCART Out Select 12 2.7.2.Stand-by Mode 12 2.8.I 2S Bus Interfaces12 2.8.1.Synchronous I 2S-Interface(s)12 2.8.2.Asynchronous I 2S-Interface 12 2.8.3.Multichannel I 2S-Output12 2.8.4.Asynchronous Multichannel I 2S-Input 13 2.9.Digital Control I/O Pins13 2.10.Clock PLL Oscillator and Crystal Specifications 14 3.Control Interface 14 3.1.I 2C Bus Interface14 3.1.1.Device and Subaddresses14 3.1.2.Internal Hardware Error Handling 15 3.1.3.Description of CONTROL Register 15 3.1.4.Protocol Description16 3.1.5.Proposals for General DPL 4519G I 2C Telegrams 16 3.1.5.1.Symbols16 3.1.5.2.Write Telegrams 16 3.1.5.3.Read Telegrams 16 3.1.5.4.Examples163.2.Start-Up Sequence: Power-Up and I 2C ControllingPRELIMINARY DATA SHEET DPL4519GContents, continuedPage Section Title16 3.3.DPL4519G Programming Interface16 er Registers Overview19 3.3.2.Description of User Registers19 3.3.2.1.Write Registers on I2C Subaddress 10hex21 3.3.2.2.Read Registers on I2C Subaddress 11hex21 3.3.2.3.Write Registers on I2C Subaddress 12hex33 3.3.2.4.Read Registers on I2C Subaddress 13hex34 3.4.Programming Tips34 3.5.Examples of Minimum Initialization Codes34 3.5.1.Micronas Dolby Digital chipset (with MAS3528E)35 4.Specifications35 4.1.Outline Dimensions37 4.2.Pin Connections and Short Descriptions40 4.3.Pin Descriptions43 4.4.Pin Configurations45 4.5.Pin Circuits47 4.6.Electrical Characteristics47 4.6.1.Absolute Maximum Ratings48 4.6.2.Recommended Operating Conditions (T A = 0 to 70 °C)48 4.6.2.1.General Recommended Operating Conditions48 4.6.2.2.Analog Input and Output Recommendations49 4.6.2.3.Crystal Recommendations50 4.6.3.Characteristics50 4.6.3.1.General Characteristics51 4.6.3.2.Digital Inputs, Digital Outputs52 4.6.3.3.Reset Input and Power-Up53 4.6.3.4.I2C-Bus Characteristics54 4.6.3.5.I2S-Bus Characteristics56 4.6.3.6.Analog Baseband Inputs and Outputs, AGNDC58 4.6.3.7.Power Supply Rejection58 4.6.3.8.Analog Performance61 5.Appendix A: Application Information61 5.1.Phase Relationship of Analog Outputs62 5.2.Application Circuit64 6.Data Sheet HistoryLicense Notice:“Dolby Pro Logic” and “Dolby Digital” are trademarks of Dolby Laboratories.Supply of this implementation of Dolby T echnology does not convey a license nor imply a right under any patent, or any other industrial or intellec-tual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products. Micronas3DPL 4519GPRELIMINARY DATA SHEET4MicronasSound Processor for Digital and Analog Surround SystemsThe hardware and software description in this docu-ment is valid for the DPL 4519G version A1 and follow-ing versions. 1.IntroductionThe DPL 4519G processor is designed as part of the Micronas chip set for digital and analog Surround Sys-tems i. e. Dolby Digital, MPEG 2 Audio, or Dolby Pro-Logic. The combination of MAS 3528E, DPL 4519G,and MSP 44x0G is a complete 5.1 channel Dolby Digi-tal decoder and playback solution, while DPL 4519G and MSP 44x0G alone, represent a complete Dolby Surround Pro Logic system.The DPL 4519G receives its incoming data via highly flexible I 2S interfaces. The three I 2S input interfaces can be configured as three asynchronous I 2S inputs or two synchronous and one asynchronous interface. In the latter case, the asynchronous interface allows reception of 2-8 channels with arbitrary sample rate ranging from 8 to 48kHz. The synchronization is per-formed by means of an adaptive high-quality sample rate converter.In an application together with the Dolby Digital decoder MAS 3528E, eight channels (left, right, sur-round left, surround right, center, subwoofer, Pro Logic encoded left, Pro Logic encoded right) are fed in and processed in the DPL 4519G.Similar to the multichannel I 2S input interface, the DPL is provided with an 8-channel I 2S output interface,which can be connected to a MSP 44x0G. Therefore all 8 channels can be routed to each output in both ICs.The baseband processing including e.g. balance,bass, treble, and loudness is performed at a fixed sam-ple rate of 48kHz.Fig.1–1 shows a simplified functional block diagram of the DPL 4519G.The DPL 4519G is pin-compatible to members of the MSP 34xx family. This speeds up PCB development for customers using MSPs.The software interface of the DPL 4519G is also largely the same as for members of the MSP family. The ICs are produced in submicron CMOS technology and are available in PQFP80, PLQFP64 and in PSDIP64 packages.Fig. 1–1:Simplified block diagram of the DPL 4519GSCART1SCART2AUXI 2SMain I 2S2I 2S1I 2S3(8-channel)SCART1SCART2SCART4SCART3MONOSubwooferPRELIMINARY DATA SHEETDPL 4519GMicronas 51.1.Features of the DPL 4519G–8-channel asynchonous I 2S input interface (multichannel mode)+ 2 synchronous I 2S input channels (e.g. for MSP and ADR)or3 asynchronous two-channel I 2S input interfaces –Main and AUX channel with balance, bass, treble, loudness, volume –5-band graphic equalizer for Main channel –Dolby Surround Pro Logic Adaptive Matrix –Micronas Effect Matrix–Micronas “3D-Panorama” virtualizer compliant to “Virtual Dolby Surround” technology –Micronas Panorama sound mode (3D Surround sound via two loudspeakers) –Noise Generator–Spatial Effect for Surround –30-ms Surround delay–Surround matrix control: Adaptive/Passive/Effect –Center mode control: Normal/Phantom/Wide/Off–Surround reproduction control: Rear speaker, Front speaker, Panorama, 3D-Panorama –Two digital input/output pins controlled by I 2C busFig.1–2 shows a typical Dolby Digital application using DPL 4519G, MSP 4450G, and MAS3528E.DPL 4519GPRELIMINARY DATA SHEET6Micronas1.2.Application Fields of the DPL 4519GPRELIMINARY DATA SHEETDPL 4519GMicronas72.Functional Description2.1.Architecture of the DPL 4519G FamilyFig.2–1 shows a simplified block diagram of the IC.V o l u meP r e s c a l eD A C A _LD A C A _RI 2S C h a n n e l M a t r i xM a i n C h a n n e l M a t r i x A u x C h a n n e l M a t r i x V o l u m e I 2S I n t e r f a c eI 2S I n t e r f a c eI 2S I n t e r f a c eS C 1_I N _LS C 1_I N _RS C 2_I N _LS C 2_I N _RS C 3_I N _LS C 3_I N _RS C 4_I N _LS C 4_I N _RM O N O _I N P r e s c a l eI 2S _D A _O U T I 2S _D A _I N 1I 2S _D A _I N 3DA s y n c h r o n i z a t i o n(s y n c . 48k H z )(a s y n c . 8-48 k H z )D A C M _L D A C M _RV o l u m e I 2S 1I 2S 3S C 1_O U T _LS C 1_O U T _RS C 2_O U T _LS C 2_O U T _RS C A R T O u t p u t S e l e c tI 2S I n t e r f a c eP r e s c a l eI 2S _D A _I N 2I 2S 2(s y n c . 48k H z )(s y n c . 48k H z )I 2S _C L I 2S _W SI 2S _C L 3I 2S _W S 3(16h e x )(12h e x )(11h e x )(08h e x )(09h e x )(0B h e x )(06h e x )(00h e x )B e e p e rΣΣ(14h e x )F i g . 2–1:S i g n a l f l o w b l o c k d i a g r a m o f t h e D P L 4519G (i n p u t a n d o u t p u t n a m e s c o r r e s p o n d t o p i n n a m e s )S o u r c e S e l e c t8910657L t R tLRS L S RC S U B I 2S _3 R e s o r t i n g M a t r i x(36h e x )D AS C A R T 1 C h a n n e l M a t r i x(0A h e x )(07h e x )S C A R T 1_L /RS u r r o u n d C h a n n e l M a t r i x(48h e x )N o i s e G e n e r a t o r S u r r o u n d P r o c e s s i n gB a l a n c eB a s s /T r e b l e /L o u d n e s s /E q u a l i z e rB a l a n cS u b w o o -f e r L e v e l A d j u s tD A C M _S U BDAB a s s /T r e b l e /L o u d n e s sI n t e r n a l /E x t e r n a l S w i t c h(36h e x )(49h e x )(4A h e x )(4B h e x )(4C h e x )(4D h e x )(2C h e x )(31/32/33h e x )(02/03/04h e x )(01h e x )(20..25h e x )(30h e x )L RS L S R C S U BDPL 4519GPRELIMINARY DATA SHEET8Micronas2.2.Preprocessing I 2S Input SignalsThe I 2S inputs can be adjusted in level by means of the I 2S prescale registers.The I 2S_3 interface is able to receive more than two channels (see Section 2.6. on page 8). The incoming signals can be resorted by a programmable matrix in order to obtain a certain order, which means an unified postprocessing afterwards.Since the I 2S_3 interface is asynchronous, incoming sound signals with arbitrary sample rates in the range of 8-48 kHz are interpolated to 48 kHz by means of an adaptive high quality sample rate converter. Therefore all subsequent processing is calculated on a fixed sampling rate, which even can be synchronized to I2S_WS e.g. to a MSP 4450 being locked to an incom-ing NICAM signal.2.3.Selection of Internal ProcessedSurround SignalsInstead of having an multichannel input via the I2S_3interface, a multichannel signal can be created by an internal Dolby Pro Logic decoder. In that case chan-nels 3..8 of the multichannel input are replaced by the internally generated signals.2.4.Source Selection and Output Channel Matrix The Source Selector makes it possible to distribute all source signals (I 2S input signals) to the desired output channels (Main, Aux, etc.). All input and output signals can be processed simultaneously. Each source chan-nel is identified by a unique source address.For each output channel, the output channel matrix can be set to sound A (left mono), sound B (right mono), stereo, or mono (sound left and right).2.5.Audio Baseband Processing 2.5.1.Main and Aux OutputsThe following baseband features are implemented in the Main and Aux output channels: bass/treble, loud-ness, balance, and volume. A square wave beeper can be added to these outputs. The Main channel addition-ally supports an equalizer function (this is not simulta-neously available with bass/treble).2.6.Surround Processing 2.6.1.Surround Processing ModeSurround sound processing is controlled by three func-tions:The "Decoder Matrix" defines which method is used to create a multichannel signal (L, C, R, S) out of a stereo input.The "Surround Reproduction" determines whether the surround signal “S” is fed to surround speakers. If no surround speaker is actually connected, it defines the method that is used to create surround effects.The “Center Mode” determines how the center signal “C” is to be processed. It can be left unmodified, dis-tributed to left and right, discarded or high pass fil-tered, whereby the low pass signals are distributed to left and right.2.6.1.1.Decoder MatrixThe Decoder Matrix allows three settings:–ADAPTIVE:The Adaptive Matrix is used for Dolby Surround Pro Logic. Even sound material not encoded in Dolby Surround will produce good surround effects in this mode. The use of the Adaptive Matrix requires a license from Dolby Laboratories (See License Notice on page 3).–PASSIVE:A simple fixed matrix is used for surround sound.–EFFECT:A fixed matrix that is used for mono sound and spe-cial effects. With Adaptive or Passive Matrix no sur-round signal is present in case of mono, moreover in Adaptive mode even the left and right output chan-nels carry no signal (or just low frequency signals in case of Center Mode = NORMAL). If surround sound is still required for mono signals, the Effect Matrix can be used. This forces the surround chan-nel to be active. The Effect Matrix can be used together with 3D-P ANORAMA. The result will be a pseudo stereo effect or a broadened stereo imagerespectively.PRELIMINARY DATA SHEETDPL 4519GMicronas 92.6.1.2.Surround ReproductionSurround sound can be reproduced with four choices:–REAR_SPEAKER:If there are any surround speakers connected to the system, this mode should be used. Useful loud-speaker combinations are (L, C, R, S) or (L, R, S).–FRONT_SPEAKER:If there is no surround speaker connected, thismode can be used. Surround information is mixed to left and right output but without creating the illusion of a virtual speaker. It is similar to stereo but an additional center speaker can be used. This mode should be used with the Adaptive decoder Matrix only. Useful loudspeaker combinations are (L, C, R) (Note: the surround output channel is muted).–PANORAMA:The surround information is mixed to left and right in order to create the illusion of a virtual surround speaker. Useful loudspeaker combinations are (L, C, R) or (L, R) (Note: the surround output channel is muted).–3D-PANORAMA:Like PANORAMA with improved effect. This algo-rithm has been approved by the Dolby Laboratories for compliance with the "Virtual Dolby Surround" technology. Useful loudspeaker combinations are (L, C, R) or (L, R) (Note: the surround output chan-nel is muted).2.6.1.3.Center ModesFour center modes are supported:–NORMAL:small center speaker connected, L and R speakers have better bass capability. Center signal is high pass filtered.–WIDE:L, R, and C speakers all have good bass capability.–PHANTOM:No center speaker used. Center signal is distributed to L and R (Note: the center output channel C is muted).–OFF:No center speaker used. Center signal C is dis-carded (Note: the center output channel C is muted).eful Combinations ofSurround Processing ModesIn principle, "Decoder Matrix", "Surround Reproduc-tion", and "Center Modes" are independent settings (all "Decoder Matrix" settings can be used with all "Sur-round Reproduction" and "Center Modes") but there are some combinations that do not create "good"sound. Useful combinations areSurround Reproduction and Center Modes –REAR_SPEAKER:This mode is used if surround speakers are avail-able. Useful center modes are NORMAL, WIDE, PHANTOM, and OFF .–FRONT_SPEAKER:This mode can be used if no surround speaker but a center speaker is connected. Useful center modes are NORMAL and WIDE.–PANORAMA or 3D-PANORAMA:No surround speaker used. Two (L and R) or three (L, R, and C) loudspeakers can be used. Useful center modes are NORMAL, WIDE, PHANTOM, and OFF .Center Modes and Decoder Matrix–PHANTOM:Should only be used together with ADAPTIVE Decoder Matrix.–NORMAL and WIDE:Can be used together with any Surround Decoder Matrix.–OFF:This mode can be used together with the P ASSIVE and EFFECT Decoder Matrix (no center speakerconnected).DPL 4519GPRELIMINARY DATA SHEET10Micronas2.6.2.ExamplesTable 2–1 shows some examples of how these modes can be used to configure the IC. The list is not intended to be complete, more modes are possible.Table 2–1:Examples of Surround ConfigurationsConfigurationsSpeaker Config-uration 1)Surround Processing ModeRegister (4B hex)Decoder Matrix [15:8]Surround Reproduction [7:4]Center Mode [3:0]Stereo Stereo(L,R)−−−Surround Modes as defined by Dolby Laboratories 2)Dolby Surround Pro Logic(L,C,R,S)ADAPTIVE REAR_SPEAKER NORMAL WIDE (L,R,S)ADAPTIVE REAR_SPEAKER PHANTOM Dolby 3 Stereo (L,C,R)ADAPTIVE FRONT_SPEAKER NORMAL WIDE Virtual Dolby Surround(L,R)ADAPTIVE3D_P ANORAMAPHANTOMSurround Modes that use the Dolby Adaptive Matrix 2)3-Channel Virtual Surround (L,C,R)ADAPTIVE3D_P ANORAMANORMAL WIDEPassive Matrix Surround Sound 4-Channel Surround (L,C,R,S)P ASSIVE REAR_SPEAKER NORMAL WIDE 3-Channel Surround(L,R,S)P ASSIVE REAR_SPEAKER OFF 2-Channel Micronas 3D Surround Sound (MSS)(L,R)P ASSIVE 3D_P ANORAMA OFF 3-Channel Micronas 3D Surround Sound (MSS)(L,C,R)P ASSIVE3D_P ANORAMANORMAL WIDESpecial Effects Surround Sound 4-Channel Surround for mono (L,C,R,S)EFFECT REAR_SPEAKER NORMAL WIDE 2-Channel Virtual Surround for mono (L,R)EFFECT 3D_P ANORAMA OFF 3-Channel Virtual Surround for mono(L,C,R)EFFECT3D_P ANORAMANORMAL WIDE1) Speakers not in use are muted automatically.2) The implementation in products requires a license from Dolby Laboratories Licensing Corporation (see note on page3).2.6.3.Application Tips for using 3D-PANORAMA 2.6.3.1.Sweet SpotGood results are only obtained in a rather close area along the middle axis between the two loudspeakers: the sweet spot. Moving away from this position degrades the effect.2.6.3.2.ClippingFor the test at Dolby Labs, it is very important to have no clipping effects even with worst case signals. The I2S-prescale register has to be set to values of max 10hex (16dec). This is sufficient in terms of clipping. However, it was found, that by reducing the prescale to a value lower than 16dec more convincing effects are generated in case of very high dynamic signals. A value of 10dec is a good compromise between overall volume and additional headroom.Test signals: sine sweep with 0dBFS; L only, R only, L&R equal phase, L&R anti phase.Listening tests: Dolby Trailers (train trailer, city trailer, canyon trailer...)2.6.3.3.Loudspeaker RequirementsThe loudspeakers used and their positioning inside the TV set will greatly influence the performance of the vir-tualizer. The algorithm works with the direct sound path. Reflected sound waves reduce the effect. So it’s most important to have as much direct sound as possi-ble, compared to indirect sound.To obtain the approval for a TV set, Dolby Laboratories require mounting the loudspeakers at the front of the set. Loudspeakers radiating to the side of the TV set will not produce convincing effects. Good directionality of the loudspeakers towards the listener is optimal. The virtualizer was specially developed for implemen-tation in TV sets. Even for rather small stereo TV's, suf-ficient sound effects can be obtained. For small sets, the loudspeaker placement should be to the side of the CRT; for large screen sets (or 16:9 sets), mounting the loudspeakers below the CRT is acceptable (large sep-aration is preferred, low frequency speakers should be outmost to avoid cancellation effects). Using external loudspeakers with a large stereo base will not create optimal effects.The loudspeakers should be able to reproduce a wide frequency range. The most important frequency range starts from 160Hz and ranges up to 5kHz.Great care has to be taken with systems that use one common subwoofer: A single loudspeaker cannot reproduce virtual sound locations. The crossover fre-quency must be lower than 120Hz.2.6.3.4.Cabinet RequirementsDuring listening tests at Dolby Laboratories, no reso-nances in the cabinet should occur.Good material to check for resonances are the Dolby Trailers or other dynamic sound tracks.2.6.4.Input and Output Levels forDolby Surround Pro LogicThe nominal input level (input sensitivity) for the I2S-Inputs is −15dBFS. The highest possible input level of 0dBFS is accepted without internal overflow. The I2S-prescale value should be set to values of max 0dB (16dec).With higher prescale values lower input sensitivities can be accommodated. A higher input sensitivity is not possible, because at least 15dB headroom is required for every input according to the Dolby specifications.A full-scale left only input (0dBFS) will produce a full-scale left only output (at 0dB volume). The typical out-put level is 1.37Vrms for DACM_L. The same holds true for right only signals (1.37 Vrms for DACM_R). A full-scale input level on both inputs (Lin=Rin=0dBFS) will give a center only output with maximum level. A full-scale input level on both inputs (but Lin and Rin with inverted phases) will give a surround-only signal with maximum level.For reproducing Dolby Pro Logic according to its spec-ifications, the center and surround outputs must be amplified by 3dB with respect to the L and R output signals. This can be done in two ways:1.By implementing 3dB more amplification for centerand surround loudspeaker outputs.2.By always selecting volume for L and R 3dB lowerthan center and surround. Method 1 is preferable, as method 2 lowers the achievable SNR for left and right signals by 3dB.2.7.SCART Signal Routing2.7.1.SCART Out SelectThe SCART Output Select block includes full matrix switching facilities. The switches are controlled by the ACB user register (see page page30).2.7.2.Stand-by ModeIf the DPL4519G is switched off by first pulling ST ANDBYQ low and then (after >1µs delay) switching off DVSUP and AVSUP, but keeping AHVSUP (‘Stand-by’-mode), the SCART switches maintain their posi-tion and function. This allows the copying from selected SCART-inputs to SCART-outputs in the TV set’s stand-by mode.In case of power on or starting from stand-by (see details on the power-up sequence in Fig. 4–19 on page52), all internal registers except the ACB register (page30) are reset to the default configuration (see Table3–5 on page17). The reset position of the ACB register becomes active after the first I2C transmission into the Baseband Processing part (subaddress 12hex). By transmitting the ACB register first, the reset state can be redefined.2.8.I2S Bus InterfacesThe DPL4519G has two kinds of interfaces: synchron master/slave input/output interfaces running on 48 kHz and an asynchron slave interface.The interfaces accept a variety of formats with different sample width, bit-orientation, and wordstrobe timing. All I2S options are set by means of the MODUS or I2S_CONFIG register.2.8.1.Synchronous I2S-Interface(s)The synchronous I2S bus interface consists of the pins:–I2S_DA_IN1, I2S_DA_IN2/3 (I2S_DA_IN2 in PQFP80 package):I2S serial data input, 16, 18...32 bits per sample.–I2S_DA_OUT:I2S serial data output, 16, 18...32 bits per sample.–I2S_CL:I2S serial clock.–I2S_WS:I2S word strobe signal defines the left and rightsample.If the DPL4519G serves as the master on the I2S interface, the clock and word strobe lines are driven by the DPL4519G. In this mode, only 16, 32 bits per sample can be selected. In slave mode, these lines are input to the DPL4519G and the DPL4519G clock is synchronized to 384times the I2S_WS rate (48kHz). An I2S timing diagram is shown in Fig. 4–21 on page55.2.8.2.Asynchronous I2S-InterfaceThe asynchronous I2S slave interface allows the reception of digital audio signals with arbitrary sample rates from 5 to 50 kHz. The synchronization is per-formed by means of an adaptive sample rate con-verter. No oversampling clock is required.The following pins are used for the asynchronous I2S bus interface (serve only as input):–I2S_WS3–I2S_CL3–I2S_DA_IN2/3 (I2S_DA_IN3 in PQFP80 package). The interface accepts I2S-input streams with MSB first and with sample widths of 16,18...32 bits. With left/ right alignment and wordstrobe timing polarity, there are additional parameters available for the adaption to a variety of formats in the I2S CONFIGURATION reg-ister.2.8.3.Multichannel I2S-OutputBit[0:1] of the I2S CONFIGURATION register (see page20) switches the output to 8 channel multichan-nel output mode. The bit resolution per channel is 32 bit in master mode. While the first two channels can be selected on the source select matrix, channels 3-8 are always connected to the I2S_3 input channels 3-8. Both, master and slave mode is possible, as long as as the wordstrobe has only one positive edge per frame in slave mode.2.8.4.Asynchronous Multichannel I2S-InputThe DPL4519G supports two kinds of asynchronous multichannel input:–the asynchronous I2S_3 interface can be switched to multichannel mode (bit [8] of the I2S CONFIGU-RATION register is set to 1. The number of chan-nels must be even and less or equal eight.–All I2S input lines (I2S_DA_IN1, I2S_DA_IN2 and I2S_DA_IN3 in PQFP80 package) can be switched to asynchronous two channel mode (bit[2] set to 1 in the I2S CONFIGURATION register). The common clock is I2S_WS3 and I2S_CL3. No synchronous I2S interfaces are available in this mode.2.9.Digital Control I/O PinsThe static level of the digital input/output pins D_CTR_I/O_0/1 is switchable between HIGH and LOW via the I2C-bus by means of the ACB register (see page30). This enables the controlling of external hardware switches or other devices via I2C-bus.The Modus Register can set the digital input/output pins to high impedance (see page19). So the pins can be used as input. The current state can be read out of the STA TUS register (see page page21).2.10.Clock PLL Oscillator andCrystal SpecificationsThe DPL4519G derives all internal system clocks from the 18.432MHz oscillator. In I2S-slave mode of the synchronous interface, the clock is phase-locked to the corresponding source.For proper performance, the DPL clock oscillator requires a 18.432-MHz crystal. Note that for the phase-locked modes (I2S-slave), crystals with tighter tolerance are required. The asynchronous I2S3 slave interface uses a different locking mechanism and does not require tighter crystal tolerances.3.Control Interface3.1.I2C Bus Interface3.1.1.Device and SubaddressesThe DPL4519G is controlled via the I2C bus slave interface.The IC is selected by transmitting one of the DPL4519G device addresses. In order to allow up to three DPL or MSP ICs to be connected to a single bus, an address select pin (ADR_SEL) has been imple-mented. With ADR_SEL pulled to high, low, or left open, the DPL4519G responds to different device addresses. A device address pair is defined as a write address and a read address (see Table3–1).Writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condi-tion, reading of the addressed data is completed by sending the device read address and reading two bytes of data. Refer to Section3.1.4. for the I2C bus protocol and to Section3.4. “Programming Tips” on page 34for proposals of DPL4519G I2C telegrams. See Table3–2 for a list of available subaddresses. Besides the possibility of hardware reset, the DPL can also be reset by means of the RESET bit in the CON-TROL register by the controller via I2C bus.Due to the internal architecture of the DPL4519G, the IC cannot react immediately to an I2C request. The typical response time is about 0.3ms. If the DPL can-not accept another complete byte of data until it has performed some other function (for example, servicing an internal interrupt), it will hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by “Wait” in Section3.1.4. The maximum wait period of the DPL during normal operation mode is less than 1ms.3.1.2.Internal Hardware Error HandlingIn case of any internal hardware error (e.g. interruption of the power supply of the DPL), the DPL’s wait period is extended to 1.8ms. After this time period elapses, the DPL releases data and clock lines.Indicating and solving the error status:To indicate the error status, the remaining acknowl-edge bits of the actual I2C-protocol will be left high. Additionally, bit[14] of CONTROL is set to one. The DPL can then be reset via the I2C bus by transmitting the reset condition to CONTROL.Indication of reset:Any reset, even caused by an unstable reset line etc., is indicated in bit[15] of CONTROL.A general timing diagram of the I2C bus is shown in Fig. 4–21 on page55.Table 3–1:I2C Bus Device AddressesADR_SEL Low(connected to DVSS)High(connected to DVSUP)Left OpenMode Write Read Write Read Write Read DPL device address80hex81hex84hex85hex88hex89hexTable 3–2:I2C Bus SubaddressesName Binary Value Hex Value Mode FunctionCONTROL0000 000000Read/Write Write: Software reset of DPL (see Table3–3)Read: Hardware error status of DPLWR_DEM0001 000010Write write address demodulatorRD_DEM0001 000111Write read address demodulatorWR_DSP0001 001012Write write address DSPRD_DSP0001 001113Write read address DSP。

i2s 布线规则摘要：1.了解i2S布线规则的背景和意义2.i2S布线规则的基本原理3.i2S布线规则的具体应用4.违反i2S布线规则可能导致的后果5.遵循i2S布线规则的实践建议正文：随着科技的不断进步，尤其是音频领域的不断发展，i2S（Inter-IC Sound）布线规则应运而生。

这是一种针对数字音频接口的布线规范，旨在提高音频传输的质量和稳定性。

本文将详细介绍i2S布线规则的基本原理、具体应用以及遵循这些规则的重要性。

首先，我们要了解i2S布线规则的背景和意义。

在过去的几十年里，音频传输技术不断发展，从模拟音频到数字音频，人们对音频质量的要求越来越高。

然而，数字音频接口的布线设计却面临着许多挑战，如信号干扰、传输速率受限等。

为了解决这些问题，i2S布线规则应运而生。

它为数字音频接口的布线提供了一套完整的规范，有助于降低信号损失，提高音频传输质量。

接下来，我们来了解一下i2S布线规则的基本原理。

i2S布线规则主要包括以下几个方面：1.平衡传输：通过使用差分信号传输技术，降低共模干扰，提高信号传输的稳定性。

2.阻抗匹配：在发送器和接收器之间采用阻抗匹配技术，以减少信号反射和损失。

3.屏蔽：对音频线进行屏蔽，以防止外部电磁干扰对音频信号的影响。

4.信号接地：合理规划信号接地，降低接地噪声对音频信号的干扰。

5.布线间距：合理设置布线间距，降低相邻信号线之间的干扰。

在实际应用中，遵循i2S布线规则可以带来以下好处：1.提高音频传输质量：遵循i2S布线规则可以降低信号损失，使音频信号更加稳定，从而提高音频质量。

2.减少故障：合理规划布线和接地，可以降低系统故障率，提高设备的可靠性和稳定性。

3.简化维护：遵循i2S布线规则，可以使音频系统的布线更加规范、简洁，降低维护成本和时间。

然而，如果违反i2S布线规则，可能会导致以下后果：1.音频信号质量下降：不合理的布线可能导致信号干扰增加，从而降低音频质量。

I²S和PCMI²S总线规范I²S（Inter-IC Sound Bus）是飞利浦公司为数字音频设备之间的音频数据传输而制定的一种总线标准。

在飞利浦公司的I2S标准中，既规定了硬件接口规范，也规定了数字音频数据的格式。

I2S有3个主要信号：1、串行时钟SCLK，也叫位时钟BCLK，即对应数字音频的每一位数据，SCLK 有1个脉冲。

SCLK的频率=2×采样频率×采样位数。

2、帧时钟LRCK，用于切换左右声道的数据。

LRCK为“0”表示正在传输的是左声道的数据，为“1”则表示正在传输的是右声道的数据。

LRCK的频率等于采样频率。

3、串行数据SDATA，就是用二进制补码表示的音频数据。

有时为了使系统间能够更好地同步，还需要另外传输一个信号MCLK，称为主时钟，也叫系统时钟（Sys Clock），是采样频率的256倍或384倍。

I²S格式的信号无论有多少位有效数据，数据的最高位总是出现在LRCK变化（也就是一帧开始）后的第2个SCLK脉冲处，见下面I²S格式图。

这就使得接收端与发送端的有效位数可以不同。

如果接收端能处理的有效位数少于发送端，可以放弃数据帧中多余的低位数据；如果接收端能处理的有效位数多于发送端，可以自行补足剩余的位。

这种同步机制使得数字音频设备的互连更加方便，而且不会造成数据错位。

随着技术的发展，在统一的I²S接口下，出现了多种不同的数据格式。

根据SDATA数据相对于LRCK和SCLK的位置不同，分为左对齐（较少使用）、I²S 格式（即飞利浦规定的格式）和右对齐（也叫日本格式、普通格式）。

非I²S格式如图：I²S格式如图：对非I²S格式而言，为了保证数字音频信号的正确传输，发送端和接收端应该采用相同的数据格式和长度。

对I²S格式来说数据长度可以不同。

而且帧时钟LRCK 高低电平对应左右声道的意义也不同？注意I²S总线和I²S格式的区别，I²S总线是一种总线标准，I²S格式是飞利浦制定的数据格式。

一、I2S 总线概述音响数据的收集、处理和传输是多媒体技能的重要组成部分。

众多的数字音频体系现已进入消费市场，例如数字音频录音带、数字声响处理器。

关于设备和生产厂家来说，规范化的信息传输结构能够进步系统的适应性。

I2S(Inter —IC Sound) 总线是飞利浦公司为数字音频设备之间的音频数据传输而拟定的一种总线规范，该总线专责于音频设备之间的数据传输，广泛应用于各种多媒体体系。

二、I2S 总线规范I2S 总线具有三条数据信号线：1、SCK: (continuous serial clock) 串行时钟对应数字音频的每一位数据，SCK 都有1 个脉冲。

SCK 的频率=2×采样频率×采样位数。

2、WS: (word select) 字段（声道）选择用于切换左右声道的数据。

WS 的频率＝采样频率。

指令挑选线表明晰正在被传输的声道。

WS 为“1表”示正在传输的是左声道的数据。

WS 为“0表”示正在传输的是右声道的数据。

WS 能够在串行时钟的上升沿或许下降沿发生改动，并且 WS 信号不需要一定是对称的。

在隶属设备端， WS 在时钟信号的上升沿发生改动。

WS 总是在最高位传输前的一个时钟周期发生改动，这样能够使隶属设备得到与被传输的串行数据同步的时刻，并且使接纳端存储当时的指令以及为下次的指令铲除空间。

3、SD: (serial data) 串行数据用二进制补码表明的音频数据。

I2S 格局的信号不管有多少位有效数据，数据的最高位总是被最先传输(在WS 变化(也就是一帧开始)后的第2 个SCK 脉冲处)，因此最高位拥有固定的位置，而最低位的位置则是依赖于数据的有用位数。

也就使得接纳端与发送端的有用位数可以不同。

假如接纳端能处理的有用位数少于发送端，能够抛弃数据帧中剩下的低位数据；假如接纳端能处理的有用位数多于发送端，能够自行补足剩余的位(常补足为零)。

这种同步机制使得数字音频设备的互连更加便利，并且不会形成数据错位。