IRLR8726 规格书

INTRODUCTIONThe 8726C (round plate) and 8726W (rectangular plate) Address-able Remote Lamps, shown in Figure 1, operate as an additional LED indicator for a device in the fire alarm control system’s addres-sable device circuit. The 8726C/8726W can be used when a device already has an accessory. The 8726C/8726W can be installed at any location of an addressable device circuit, and it remotely indicates the status of the device(s) in that same circuit.Mode of OperationThe 8726C/8726W has one mode of operation: Direct Addressing Mode. The two-position jumper P1 must be positioned to set the mode to Direct Addressing.When set and programmed to Direct Addressing Mode, system logic and programming determine when the ILED-H will blink.Controls and IndicatorsIn Direct Addressing mode, the LED on the 8726C/8726W is controlled by logic functions programmed using the CIS-4 Tool. In Direct Addressing mode, the 8726C/8726W blink color (red only) cannot be changed.PROGRAMMINGRefer to Figure 2 for the location of the programming holes and jumper P1.Direct Addressing ModeTo set the 8726C/8726W to Direct Addressing Mode follow the steps listed below:1.Determine a unique address for the 8726C/8726W.2.Set jumper P1 to position 2 and3.3.Connect the 8726C/8726W to the 8720 Programmer/Tester byinserting the plug from the cable provided with the 8720 Programmer/Tester into the programming holes on the 8726C/8726W board.4.Follow the instructions in the 8720 Programmer/Tester Manual, P/N 315-033260FA, to program the 8726C/8726W to the desired address. Record the device address on the label located on the 8726C/8726W front panel.INSTALLATION INSTRUCTIONS AND WIRING FORINTELLIGENT REMOTE LAMPSP/N 8726C AND 8726WFigure 18726C And 8726W Remote LampsSiemens Industry, Inc.Building Technologies Division • Florham Park, NJ Tel: (973) 593-2600 • Fax: (973) 593-6670Web: Figure 28726 Printed Circuit Board5.In the CIS-4 Programming Tool, assign the 8726C/8726W to an output zone. When an Input Group that is assigned to that Output Zone reports an off-normal event, the 8726C/8726W will blink red if the reported event type matches the output type selected for its zone. Refer to the CIS-4 Manual for further information.6.The 8726C/8726W can now be installed and wired to the system.WIRINGWARNING: Disconnect BATTERY and AC prior to working on equipment.Refer to the wiring diagram in Figure 3 below to wire the 8726C/8726W.NOTE: The 8726C/8726W is polarity insensitive. Switching Line1 and Line2 has no effect on performance.Recommended wire size:18 AWG minimum, 14 AWG maximumWire larger than 14 AWG can damage the connector.LINE2LINE1TO ADDRESSABLE DEVICE CIRCUITFigure 3Wiring The 8726C/8726WINSTALLATIONNOTE: Be sure to program the 8726C/8726W before installing the unit.The 8726C/8726W may be placed at any location on the address-able device circuit. Use a single-gang switch box (user supplied) for mounting the 8726W. Use a 4-inch octagonal conduit box (user supplied) for mounting the 8726C. Refer to Figure 4 for typical 8726C/8726W installation.The number of 8726C/8726W modules on the addressable device circuit must be included in the total count of intelligent field devices.For the restriction of the total number of devices in the FDLC loop,refer to the FDLC Installation Instructions, P/N 315-447360FA.ELECTRICAL RATINGSDO NOT USE REAR CONDUIT ENTRYFigure 4Mounting The 8726Wtn e r r u C t u p n I Am 1。

TM87264 Bit Microcontroller GENERAL DESCRIPTIONThe TM8726 is an embedded high-performance 4-bit microcomputer with LCD driver. It contains all the necessary functions, such as 4-bit parallel processing ALU, ROM, RAM, I/O ports, timer, clock generator, dual clock operation, Resistance to Frequency Converter(RFC), EL panel driver, LCD driver, look-up table, watchdog timer and key matrix scanning circuitry in a signal chip.FEATURE1. Low power dissipation.2. Powerful instruction set (178 instructions).z B inary addition, subtraction, BCD adjust, logical operation in direct and index addressing mode.z S ingle-bit manipulation (set, reset, decision for branch).z V arious conditional branch.z16 working registers and manipulation.z T able look-up.z L CD driver data transfer.3. Memory capacity.4096x 16 bits.capacityz R OMz R AM capacity 512 x 4 bits.4. LCD driver output.z9 common outputs and 41 segment outputs (up to drive 369 LCD segments).z1/2 Duty, 1/3 Duty, 1/4 Duty, 1/5 Duty, 1/6Duty, 1/7Duty, 1/8Duty or 1/9Duty is selected by MASK option.z1/2 Bias, 1/3 Bias or 1/4 Bias is selected by MASK option.z S ingle instruction to turn off all segments.z C OM5~9,SEG1~41 could be defined as CMOS or P_open drain type output by mask option.5. Input/output ports.z P ort IOA 4 pins (with internal pull-low), muxed with SEG24~SEG27.z P ort IOB 4 pins (with internal pull-low). muxed with SEG28~SEG31z P ort IOC 4 pins (with internal pull-low, low-level-hold), muxed with SEG32 ~SEG35.IOC port had built in the input signal chattering prevention circuitry.z P ort IOD 4 pins (with internal pull-low), muxed with SEG36 ~ SEG39. IODport had built in the input signal chattering prevention circuitry.6. 8 level subroutine nesting.7. Interrupt function.z E xternal factors 4(INT pin, Port IOC, IOD & KI input).z I nternal factors 4(Pre-Divider, Timer1, Timer2 & RFC).8. Built-in EL-light driver.z E LC, ELP (Muxed with SEG28, SEG29).9. Built in Alarm, clock or single tone melody generator.z B ZB, BZ (Muxed with SEG30, SEG31).10. Built-in resistance to frequency converter.z C X, RR, RT, RH (Muxed with SEG24 ~ SEG27).11. Built in key matrix scanning function.z K1~K16 (Shared with SEG1~SEG16).z K I1~KI4 (Muxed with SEG32 ~ SEG35).12. Two 6-bit programmable timer with programmable clock source.13. Watch dog timer.14. Built-in Voltage doubler, halver, tripler, quartic charge pump circuit.15. Dual clock operationz s low clock oscillation can be defined as X’tal or external RC type oscillator by mask option.z f ast clock oscillation can be defined as 3.58MHz ceramic resonator, internal R or external R type oscillator by mask option.16. HALT function.17. STOP function.APPLICATIONTimer / Calendar/Calculator / Thermometer2 tenx technology, inc.BLOCK DIAGRAM3 tenx technology, inc.4 tenx technology, inc.PAD DIAGRAMThe substrate of chip should be connected to GND.110203040506066PAD COORDINATENo Name X Y No Name X Y1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930313233BAKXINXOUTCFINCFOUTGNDVDD1VDD2VDD3VDD4CUP0CUP1CUP2COM1COM2COM3COM4COM5COM6COM7COM8COM9SEG1(K1)SEG2(K2)SEG3(K3)SEG4(K4)SEG5(K5)SEG6(K6)SEG7(K7)SEG8(K8)SEG9(K9)SEG10(K10)SEG11(K11)72.5072.5072.5072.5072.5072.5072.5072.5072.5072.5089.50204.50319.50434.50549.50669.50789.50909.501029.501149.501269.501389.501509.501629.501677.501677.501677.501677.501677.501677.501677.501677.501677.501229.501114.50999.50884.50769.50654.50539.50424.50309.50194.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.50197.50322.50439.50554.50669.50784.50899.501014.501129.50343536373839404142434445464748495051525354555657585960616263646566SEG12(K12)SEG13(K13)SEG14(K14)SEG15(K15)SEG16(K16)SEG17SEG18SEG19SEG20SEG21SEG22SEG23SEG24/IOA1/CXSEG25/IOA2/RRSEG26/IOA3/RTSEG27/IOA4/RHSEG28/IOB1/ELCSEG29/IOB2/ELPSEG30/IOB3/BZBSEG31/IOB4/BZSEG32/IOC1/KI1SEG33/IOC2/KI2SEG34/IOC3/KI3SEG35/IOC4/KI4SEG36/IOD1SEG37/IOD2SEG38/IOD3SEG39/IOD4SEG40SEG41RESETINTTEST1677.501677.501677.501677.501677.501677.501677.501677.501677.501677.501677.501558.501430.451305.001164.501024.00881.50766.50651.50536.50421.50306.50191.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.501244.501359.501474.501589.501704.501819.501934.502049.502175.002300.002477.002507.502507.502507.502507.502507.502507.502507.502507.502507.502507.502507.502507.502477.002300.002175.002049.501934.501819.501704.501589.501474.501359.505 tenx technology, inc.PIN DESCRIPTIONName I/O DescriptionBAK P Positive Back-up voltage.At Li power mode, connect a 0.1u capacitor to GND.VDD1,2,3,4P LCD supply voltage, and positive supply voltage..In Ag Mode, connect positive power to VDD1..In Li or ExtV power mode, connect positive power to VDD2.RESET I Input pin for external reset request signal, built-in internal pull-down resistor.INT I Input pin for external INT request signal.. Falling edge or rising edge triggered is defined by mask option.. Internal pull-down or pull-up resistor is defined by mask option.TEST Test signal input pin.CUP0,1,2O Switching pins for supply the LCD driving voltage to the VDD1, 2,3,4 pins.. Connect the CUP0, CUP1 and CUP2 pins with non-polarized electrolytic capacitorswhen chip operated in 1/2, 1/3 or 1/4 bias mode.. In no BIAS mode application, leave these pins opened.XIN XOUT IOTime base counter frequency (clock specified. LCD alternating frequency. Alarm signal frequency) or system clock oscillation.. The usage of 32KHz Crystal oscillator or external RC oscillator is defined by mask option.CFIN CFOUT IOSystem clock oscillation for FAST clock only or DUAL clock operation.. The usage of 3.58MHz ceramic/resonator oscillator or external R type oscillator is defined by mask optionCOM1~9O Output pins for driving the common pins of the LCD panel.COM5~9 could be defined as COMS or Open Drain type output. SEG1-41O Output pins for driving the LCD panel segment.IOA1-4I/O Input / Output port A, (muxed with SEG24~27)IOB1-4I/O Input / Output port B, (muxed with SEG28~31)IOC1-4I/O Input / Output port C, (muxed with SEG32~35)IOD1~4 I/O Input / Output port D, (muxed with SEG36~39)CXRR/RT/RH IO1 input pin and 3 output pins for RFC application. (muxed with SEG24~27)ELC/ELP O Output port for El panel driver. (muxed with SEG28~29)BZB/BZ O Output port for alarm, clock or single tone melody generator. (muxed with SEG30~31) K1~K16 O Output port for key matrix scanning.(Shared with SEG1~SEG16)KI1~4 I Input port for key matrix scanning.(Muxed with SEG32~SEG35)GND P Negative supply voltage.ABSOLOUTE MAXIMUM RATINGSGND= 0VName Symbol Range UnitVDD1 -0.3 to 5.5 VVDD2 -0.3 to 5.5 VVDD3 -0.3 to 8.5 VMaximum Supply VoltageVDD4 -0.3 to 8.5 VMaximum Input Voltage Vin -0.3 to VDD1/2+0.3 VVout1 -0.3 to VDD1/2+0.3 VVout2 -0.3 to VDD3+0.3 VMaximum output VoltageVout3 -0.3 to VDD4+0.3 VMaximum Operating Temperature Topg -20 to +70 ℃Maximum Storage Temperature Tstg -25 to +125 ℃6 tenx technology, inc.7 tenx technology, inc.POWER CONSUMPTIONat Ta=-20℃ to 70℃,GND= 0VName Sym. Condition Min.Typ. Max. Unit I HALT1 Only 32.768KHz Crystal oscillator operating, without loading.Ag mode, VDD1=1.5V, BCF = 02 uAHALT mode I HALT2 Only 32.768KHz Crystal oscillator operating, without loading. Li mode, VDD2=3.0V, BCF = 02 uASTOP mode I STOP 1 uA Note : When RC oscillator function is operating, the current consumption will depend on the frequency ofoscillation.ALLOWABLE OPERATING CONDITIONSat Ta=-20℃ to 70℃,GND= 0VName Symb. Condition Min. Max. UnitVDD1 1.2 5.25 V VDD2 2.4 5.25 VVDD3 2.4 8.0 V Supply Voltage VDD4 2.4 8.0 V Oscillator Start-Up Voltage VDDB Crystal Mode 1.3VOscillator Sustain Voltage VDDB Crystal Mode 1.2V Supply Voltage VDD1 Ag Mode 1.2 1.65 V Supply Voltage VDD2 EXT-V, Li Mode 2.4 5.25 V Input “H” Voltage Vih1 VDD1-0.7VDD1+0.7V Input “L” Voltage Vil1 Ag Battery Mode -0.7 0.7 VInput “H” Voltage Vih2 VDD2-0.7VDD2+0.7V Input “L” Voltage Vil2 Li Battery Mode -0.7 0.7 V Input “H” Voltage Vih3 0.8xVDD1VDD1 V Input “L” Voltage Vil3 OSCIN at AgBattery Mode 0 0.2xVDD1VInput “H” Voltage Vih4 0.8xVDD2VDD2 V Input “L” Voltage Vil4 OSCIN at LiBattery Mode 0 0.2xVDD2VInput “H” Voltage Vih5 0.8xVDD2VDD2 V Input “L” Voltage Vil5 CFIN at Li Batteryor EXT-V Mode 0 0.2xVDD2VInput “H” Voltage Vih6 0.8xVDDO VDDO V Input “L” Voltage Vil6 RC Mode 0 0.2xVDDO V Fopg1 Crystal Mode 32 KHZFopg2 RC Mode 10 1000 KHZ Operating Freq Fopg3 CF Mode 1000 3580 KHzALLOWABLE OPERATING FREQUENCYat Ta=-20℃ to 70℃,GND= 0VConditionMax, Operating FrequencyBAK=1.5V (VDD1) 800KHz BAK=3V (VDD2) 4MHz8 tenx technology, inc.INTERNAL RC FREQUENCY RANGEOption Mode BAKMin. Typ. Max.1.5V 200KHz 300KHz 400KHz 250KHz 3.0V 200KHz 250KHz 300KHz 1.5V 450KHz 600KHz 750KHz 500KHz 3.0V400KHz 500KHz 600KHzELECTRICAL CHARACTERISTICSat#1:VDD1=1.2V(Ag); at#2:VDD2=2.4V(Li): at#3:VDD2=4V(Ext-V);Input ResistanceName Symb. Condition Min.Typ.Max. UnitRllh1 Vi=0.2VDD1,#1 10 40 100 KohmRllh2 Vi=0.2VDD2,#2 10 40 100 Kohm “L” Level Hold Tr(IOC) Rllh3 Vi=0.2VDD2,#3 5 20 50 KohmRmad1 Vi=VDD1,#1 200500 1000 KohmRmad2 Vi=VDD2,#2 200500 1000 Kohm IOC Pull-Down Tr Rmad3 Vi=VDD2,#3 100250 500 KohmRintu1 Vi=VDD1,#1 200500 1000 KohmRintu2 Vi=VDD2,#2 200500 1000 Kohm INT Pull-up Tr Rintu3 Vi=VDD2,#3 100250 500 KohmRintd1 Vi=GND,#1 200500 1000 KohmRintd2 Vi=GND,#2 200500 1000 Kohm INT Pull-Down Tr Rintd3 Vi=GND,#3 100250 500 KohmRres1 Vi=GND or VDD1,#110 40 100 KohmRres2 Vi=GND or VDD2,#210 40 100 Kohm RES Pull-Down R Rres3 Vi=GND or VDD2,#310 40 100 KohmDC Output CharacteristicsName Symb. Condition Port Min.Typ.Max. UnitVoh1c Ioh=-200uA,#1 0.8 0.9 1.0 V Voh2c Ioh=-1mA,#2 1.5 1.8 2.1 VOutput ”H” Voltage Voh3c Ioh=-3mA,#3 2.5 3.0 3.5 VVol1c Iol=400uA,#1 0.2 0.3 0.4 V Vol2c Iol=2mA,#2 0.3 0.6 0.9 VOutput ”L” Voltage Vol3c Iol=6mA,#3 COM5~9 SEG1~410.5 1.0 1.5 V9 tenx technology, inc.Segment Driver Output CharacteristicsNameSymb.Condition For Min.Typ.Max. Unit. Static Display ModeVoh1d Ioh=-1uA,#1 1.0 V Voh2d Ioh=-1uA,#2 2.2 VOutput ”H” Voltage Voh3d Ioh=-1uA,#3 3.8 V Vol1d Iol=1uA,#1 0.2 VVol2d Iol=1uA,#2 0.2 VOutput ”L” Voltage Vol3d Iol=1uA,#3 SEG-n 0.2 VVoh1e Ioh=-10uA,#1 1.0 V Voh2e Ioh=-10uA,#2 2.2 VOutput ”H” Voltage Voh3e Ioh=-10uA,#3 3.8 VVol1e Iol=10uA,#1 0.2 VVol2e Iol=10uA,#2 0.2 VOutput ”L” VoltageVol3e Iol=10uA,#3 COM-n 0.2 V1/2 Bias Display ModeVoh12f Ioh=-1uA,#1,#2 2.2 V Output ”H” Voltage Voh3f Ioh=-1uA,#3 3.8 V Vol12f Iol=1uA,#1,#2 0.2 VOutput ”L” Voltage Vol3f Iol=1uA,#3 SEG-n 0.2 VVoh12g Ioh=-10uA,#1,#2 2.2 VOutput ”H” Voltage Voh3g Ioh=-10uA,#3COM-n 3.8 V Vom12g Iol/h=+/-10uA,#1,#2 1.0 1.4 V Output ”M” VoltageVom3g Iol/h=+/-10uA,#3 COM-n 1.8 2.2 V1/3 Bias display ModeVoh12h Ioh=-1uA,#1,#2 3.4 V Output ”H” Voltage Voh3h Ioh=-1uA,#3 5.8 V Vom1h Iol/h=+/-10uA,#1,#2 1.0 1.4 V Output ”M1” Voltage Vom13h Iol/h=+/-10uA,#3 1.8 2.2 VVom22h Iol/h=+/-10uA,#1,#2 2.2 2.6 V Output ”M2” Voltage Vom23h Iol/h=+/-10uA,#3 3.8 4.2 VVol12h Iol=1uA,#1,#2 0.2 V Output ”L” Voltage Vol3h Iol=1uA,#3 SEG-n 0.2 VVoh12i Ioh=-10uA,#1,#2 3.4 V Output ”H” Voltage Voh3i Ioh=-10uA,#3 5.8 V Vom12i Iol/h=+/-10uA,#1,#2 1.0 1.4 V Output ”M1” Voltage Vom13i Iol/h=+/-10uA,#3 1.8 2.2 VVom22i Iol/h=+/-10uA,#1,#2 2.2 2.6 V Output ”M2” Voltage Vom23i Iol/h=+/-10uA,#3 3.8 4.2 VVol12i Iol=10uA,#1,#2 0.2 V Output ”L” VoltageVol3i Iol=10uA,#3 COM-n 0.2 V1/4 Bias display ModeOutput ”H” VoltageVoh12j Ioh=-1uA,#1,#2 4.6 V Output ”M2” Voltage Vom22j Iol/h=+/-10uA,#1,#2 2.2 2.6 VOutput ”L” Voltage Vol12j Iol=1uA,#1,#2 SEG-n 0.2 VOutput ”H” Voltage Voh12k Ioh=-10uA,#1,#2 4.6 VOutput ”M1” Voltage Vom12k Iol/h=+/-10uA,#1,#2 1.0 1.4 V Output ”M3” Voltage Vom22k Iol/h=+/-10uA,#1,#2 3.4 3.8 VOutput ”L” VoltageVol12k Iol=10uA,#1,#2 COM-n 0.2 VTYPICAL APPLICATION CIRCUITMatrixLi power mode, 1/4 Bias, 1/9 Duty10 tenx technology, inc.。

mos管8726参数摘要：1.mos 管简介2.8726 参数概述3.8726 参数详细解读4.8726 参数在实际应用中的意义正文：MOS 管，全称为金属- 氧化物- 半导体场效应晶体管，是一种广泛应用于电子设备中的半导体器件。

它具有高输入阻抗、低噪声、低失真等优点，在电路设计中有着重要地位。

8726 是一种特定的MOS 管型号，具有多种参数。

接下来，我们将详细解读这些参数，并探讨它们在实际应用中的意义。

一、mos 管简介金属- 氧化物- 半导体场效应晶体管（MOSFET）是一种半导体器件，具有高输入阻抗、低噪声和低失真等优点。

它由源极、漏极和栅极三个端口组成，通过改变栅极电压来控制源漏电流的大小。

在电路设计中，MOS 管被广泛应用于放大器、开关、振荡器等电子设备。

二、8726 参数概述8726 是一种N 沟道增强型MOS 管，具有以下主要参数：1.静态漏极电压（VDS）：30V2.最大漏极电流（ID）：26A3.栅极漏极电压（VGS）：-20V to 20V4.输入电容（Ciss）：1.8pF5.导通电阻（RDS(on)）：0.028Ω三、8726 参数详细解读1.静态漏极电压（VDS）：30V静态漏极电压是指在栅极电压为0V 时，漏极所能承受的最大电压。

8726 的静态漏极电压为30V，意味着在正常工作范围内，漏极电压不会超过30V，从而保证了器件的安全稳定运行。

2.最大漏极电流（ID）：26A最大漏极电流是指在栅极电压达到最大值时，漏极所能流过的最大电流。

8726 的最大漏极电流为26A，表明该型号的MOS 管具有较高的电流驱动能力。

3.栅极漏极电压（VGS）：-20V to 20V栅极漏极电压是指在漏极电压不变的情况下，栅极电压的变化范围。

8726 的栅极漏极电压为-20V to 20V，意味着在正常工作范围内，栅极电压可以在-20V 至20V 之间变化。

4.输入电容（Ciss）：1.8pF输入电容是指MOS 管栅极与源极之间的电容。

irlr8726场效应管参数
场效应管（Field Effect Transistor，简称FET）是一种三端
元件，常用于放大或开关电路中。

IRLR8726是一种N沟道场效应管，具有以下参数：
1. 饱和漏-源电压（VDS），这是场效应管在完全导通状态下的
漏-源电压。

对于IRLR8726，这个参数通常在数据手册中给出。

2. 饱和漏-源电流（IDS），这是场效应管在饱和状态下的漏-
源电流。

同样，这个参数也会在数据手册中有详细说明。

3. 静态工作点，静态工作点是指场效应管在特定电压和电流条
件下的工作状态，通常由漏-源电流和漏-源电压来描述。

4. 输入电容（Ciss），这是场效应管的输入电容，影响着场效
应管的高频特性和输入阻抗。

5. 输出电容（Coss），这是场效应管的输出电容，影响着场效
应管的高频特性和输出阻抗。

6. 开关时间，开关时间是指场效应管从完全关断到完全导通的时间，通常由上升时间和下降时间来描述。

7. 最大耗散功率（Pd），这是场效应管可以持续耗散的最大功率，超过这个功率会导致场效应管过热损坏。

以上是IRLR8726场效应管的一些基本参数，这些参数对于设计电路和选择合适的场效应管都非常重要。

当然，实际使用时还需要参考数据手册中的具体参数和曲线图来进行综合考虑。

希望这些信息能够帮助到你。

Application NotesAML 8726-MXUART Interface User GuideAMLOGIC, Inc.3930 Freedom Circle Santa Clara, CA 95054U.S.A.AMLOGIC reserves the right to change any information described herein at any time without notice.AMLOGIC assumes no responsibility or liability from use of such information.Di s t ri bu t et oE md o o r!Table of Content1. GENERAL DESCRIPTION ............................................................................................................................................. 42. OVERVIEW ....................................................................................................................................................................... 43. FEATURES ........................................................................................................................................................................ 44.UART SIGNAL AND PIN MAPPING ............................................................................................................................ 5 4.1. S IGNAL ......................................................................................................................................................................... 5 4.2. P IN M APPING . (5)5. INTERRUPT (6)6. POWER MANAGEMENT ............................................................................................................................................... 77. RESET ................................................................................................................................................................................ 78.BAUD RATE ...................................................................................................................................................................... 8 8.1. I NPUT C LOCK ................................................................................................................................................................ 8 8.2.B AUD R ATE G ENERATION ............................................................................................................................................ 8 9. REGISTER DESCRIPTIONS (9)9.1. UART_A ...................................................................................................................................................................... 9 9.2. UART_B .................................................................................................................................................................... 14 9.3. UART_C .................................................................................................................................................................... 19 9.4. UART_AO ................................................................................................................................................................. 24 10. ADDRESS MAPPING ................................................................................................................................................. 29 11.ANDROID™/LINUX KERNE L (30)11.1. O PERATION M ACRO D EFINITION ............................................................................................................................ 30 11.2.R EGISTER M ACRO D EFINITION (30)Di s t ri bu t et oE md o o r!Revision HistoryRevision Number Revised Date By Changes0.1 Feb. 15, 2012 Kevin Zhu Initial release draft0.2 May. 22,2012 Kevin Zhu UART0~2 renamed to UART_A, UART_B and UART_CDi s t ri bu t et oE md o o r!1. General DescriptionAmlogic AML8726-MX is a highly integrated multimedia application processor SoC for Multimedia Internet Device (MID), tablet and Set Top Box (STB). It integrates a powerful CPU, a 2D/3D graphics subsystem and a state-of-the-art video decoding engine together with all major peripherals.This document is a user guide of universal asynchronous receiver/transmitter (UART) serial ports integrated in AML8726-MX.The guide provides:● An overview of UART interface ● The feature of UART● The UART interface pin selection ● The baud rate generation● The register definition that control and operate UART interface ● AML8726-MX UART in Android/Linux Amlogic porting2. OverviewEach AML8726-MX has four fully functional UARTs which use the same programming model. They are named as UART_A, UART_B, UART_C and UART_AO. The one with ‘AO ’ in the naming are located at the Always-On (AO) power domain, which cannot be powered off unless AML8726-MX is disconnected from power supply.The four UARTs are controlled separately. Each UART has a build-in standalone register set for controlling and data exchange.The UARTs in AML8726-MX can only operate in FIFO mode. UART_A has a 128-byte RX/TX FIFO and UART_B/UART_C/UART_AO has a 64-byte FIFO. If non-FIFO mode is required, the registers of UART should be fine tuned and a polling mechanism should be used to fulfill.Each UART has programmable interrupt generation circuit which will reduce the loading of processor and to improve communication performance.A baud-rate generator is also contained in each UART to provide flexible division of input clock by 1 to (216-1) or 1to (223-1) according to the setting in the internal register.3. FeaturesThe UARTs share the following features:● Each UART independent control register set● Independently controlled transmit and receive interrupts with FIFO threshold ● Programmable serial interface:⏹ 5-, 6-, 7- or 8-bit characters⏹ Even, odd or no parity detection ⏹ 1 stop bit generation⏹ Programmable baud rate● 64-byte transmit and receive FIFO (UART_B/UART_C/UART_AO) ● 128-byte transmit and receive FIFO (UART_A) ● Automatic frame error detection● Programmable RX, TX, RTS, CTS signal polarityDi s t ri bu t et oE md o o r!4. UART Signal and Pin Mapping4.1. SignalEach AML8726-MX UART function module has 4 external signals which can be connected to a series of GPIO pins via pin multiplex mapping circuit. The pins transmit digital CMOS-level signals only.The signals are described in the table below:Table 1. UART Signal DescriptionsName Type Description RX Input Serial data input to the receive shift register and Receive FIFO. TX Output Serial data output to external data set. CTS Input Clear to Send.When asserted, it indicates that the receiver is ready to exchange data.RTS Output Request to Send.When asserted, it notifies the receiver that the sender is ready to exchange data.4.2. Pin MappingIn AML8726-MX, only UART RX and TX signal are available. If CTS and RTS signal are required, please contact with Amlogic Sales.AML8726-MX has 11 GPIO banks. UART_A, UART_B and UART_C are located in Bank X and UART_AO is in the dedicated Bank AO. RX and TX signals of the UART function blocks can be multiplexed to the corresponding bank in pair.The relationship between pins and registers of each UART signal and GPIO bank is shown in the table below:Table 2. UART Signal Pin out MappingUART Module UART Signal Bank X Bank AOUART_AUART_RX_A GPIOX_14 UART_TX_A GPIOX_13UART_CTS_A GPIOX_15 UART_RTS_A GPIOX_16 UART_BUART_RX_B GPIOX_18 UART_TX_B GPIOX_17UART_CTS_B GPIOX_19 UART_RTS_B GPIOX_20 UART_CUART_RX_C GPIOX_22 UART_TX_C GPIOX_21UART_CTS_C GPIOX_23 UART_RTS_C GPIOX_24 UART_AOUART_RX_AO GPIOAO_1 UART_TX_AO GPIOAO_0UART_CTS_AO GPIOAO_2 UART_RTS_AO GPIOAO_3About GPIO function settings, please refer to AML8726-MX GPIO User Guide for detailed description.Di s t ri bu t et oE md o o r!5. InterruptThe UART interrupts are controlled in two levels: CPU and Function.In CPU level, the UART interrupts can be controlled and programmed by using the registers below:Table 3. Interrupt Control Register UART CPU LevelUART Module Offset Bit R/WUART_A 0x2690 bit 26 R UART_A interrupt flag. When interrupt happens, it will beset to 1.0x2691 bit 26 R/W Write 1 to this register bit to clean UART_A interrupt flag.0x2692 bit 26 R/W Interrupt mask. Set to 1 to mask UART_A interrupt (disableUART_A interrupt).0x2693 bit 26 R/W Fast interrupt enable. Set to 1 to enable UART_A interruptmultiplexing to CPU FAST interruptUART_B 0x2698 bit 11 R UART_B interrupt flag. When interrupt happens, it will beset to 1.0x2699 bit 11 R/W Write 1 to this register bit to clean UART_B interrupt flag.0x269A bit 11 R/W Interrupt mask. Set to 1 to mask UART_B interrupt (disableUART_A interrupt).0x269B bit 11 R/W Fast interrupt enable. Set to 1 to enable UART_B interruptmultiplexing to CPU FAST interruptUART_C 0x2698 bit 29 R UART_C interrupt flag. When interrupt happens, it will beset to 1.0x2699 bit 29 R/W Write 1 to this register bit to clean UART_C interrupt flag.0x269A bit 29 R/W Interrupt mask. Set to 1 to mask UART_C interrupt (disableUART_AO interrupt).0x269B bit 29 R/W Fast interrupt enable. Set to 1 to enable UART_C interruptmultiplexing to CPU FAST interruptUART_AO 0x2698 bit 26 R UART_AO interrupt flag. When interrupt happens, it will beset to 1.0x2699 bit 26 R/W Write 1 to this register bit to clean UART_AO interrupt flag.0x269A bit 26 R/W Interrupt mask. Set to 1 to mask UART_AO interrupt(disable UART_AO interrupt).0x269B bit 26 R/W Fast interrupt enable. Set to 1 to enable UART_AO interruptmultiplexing to CPU FAST interruptIn Function Level, the block registers need to be set to enable UART interrupt. ● UART_A: UART_A_CONTROL[27] and [28] must be set to 1. ● UART_B: UART_B_CONTROL[27] and [28] must be set to 1. ● UART_C: UART_C_CONTROL[27] and [28] must be set to 1. ● UART_AO: AO_UART_CONTROL[27] and [28] must be set to 1.For more details and other register setup, please refer to the Register Descriptions section.Di s t ri bu t et oE md o o r!6. Power ManagementThe UARTs in AML8726-MX can be shut down to save power consumption by using the register bits described below:Need verify● UART_A: i n EE domain; ● UART_B: i n EE domain; ● UART_C: in EE domain; ● UART_AO: in AO domain;Setting these bits to 0 will disable the UARTs function blocks and 1 will enable them. After system power-on or reset, UART modules are enabled on default.7. ResetFor the UART module in the AO power domain, it is possible to reset it by programming the register bit 0x0010[17] which is also in AO domain. Setting this bit to 1 will reset the I2C AO function blocks.Note: The receivers and transmitters of UARTs are disabled after system power-on or reset. Therefore software must program the registers to enable them, e.g., bit 12 and 13 in the corresponding control register should be set to 1.Di s t ri bu t et oE md oo r!8. Baud RateA build-in baud rate generator is implemented in AML8726-MX for each UART interface. The generator contains an input clock, a divider circuits and control registers.8.1. Input ClockThe input clock of the generator, named as UART_Clock, is configurable. The exact value of UART_Clock is based on AML8726-MX system software implementation.In Amlogic Android/Linux porting for AML8726-MX, the value of UART_Clock can be obtained by using the following process in software.1. Include clkdev.h at [linux_kernel_root]/arch/arm/include/asm/.2. Include clock.h at [linux_kernel_root]/arch/arm/mach-meson/include/mach/.3. Define a variable type struct clk.4. Define an unsigned int type variable uart_clock_rate.5. Use API clk_get_sys(“clk81”, NULL) to get clock structure.6. Use API clk_get_rate() to get the value of UART_Clock.The sample code is illustrated as below:#include <linux/clk.h> #include <asm/clkdev.h> #include <mach/clock.h>unsigned int uart_clock_rate; struct clk *uart_clockuart_clock = clk_get_sys(“clk81”, NULL); uart_clock_rate = clk_get_rate(uart_clock);8.2. Baud Rate GenerationAfter obtaining the uart_clock_rate, software can use the equation as shown below to generate correct baud rate.● UART_A:oror● UART_B:oror● UART_C:oror● UART_AO:ororDi s t ri bu t et oE md o o r!9. Register DescriptionsThese are 6 registers are defined and implemented in AML8726-MX for each UART. They are all 32-bit.9.1. UART_AWrite Buffer Register (UART_A_WFIFO)UART_A_WFIFO is the data entry of UART_A transmit FIFO. Writing to the register puts a byte data into the top of transmit FIFO. The data at the front of the FIFO transmits automatically until transmit FIFO empty.Table 4. UART_A_WFIFO register definitionName UART_A_WFIFO Offset 0x2130 Width 32-bit Bit R/W Name Default Description 31:8 R - 0 Reserved 7:0 W FIFO_WDATA - Write UART Transmit FIFO. The Write FIFO holds 64 bytesRead Buffer Register (UART_A_RFIFO)UART_A_RFIFO is the data entry of UART Read FIFO. It latches the value of data byte at the front of UART Read FIFO.Table 5. UART_A_RFIFO register definitionName UART_A_RFIFO Offset 0x2131 Width 32-bit Bit R/W Name Default Description 31:8 R - 0 Reserved 7:0 R FIFO_RDATA 0x00 Read a byte from UART FIFO.Di s t ri bu t et oE md o o r!UART_A Mode Register (UART_A_CONTROL)UART_A_CONTROL is a control register.Table 6. UART_A_CONTROL register definitionName UART_A_CONTROL Offset 0x2132 Width 32-bit Bit R/W Name Default Description 31 R/W RTS_INV 0 Invert RTS signal. 0: RTS active LOW. 1: RTS active HIGH 30 R/W ERR_MASK_EN 0 Error Mask enable. 0: disable error mask. 1: enable error mask. 29 R/W CTS_INV 0 Invert CTS signal. 0: CTS active LOW 1: CTS active HIGH. 28 R/W UART_TX_INT_EN 0 Transmit byte interrupt enable. When enabled, an interrupt will begenerated whenever a byte is read from Transmit FIFO. 0: disable transmit byte interrupt 1: enable transmit byte interrupt27 R/W UART_RX_INT_EN 0 Receive byte interrupt enable. When enabled, an interrupt will begenerated whenever a byte is written to Read FIFO. 0: disable receive byte interrupt 1: enable receive byte interrupt26 R/W UART_TX_INV 0 Invert TX signal. 0: TX active HIGH. 1: TX active LOW 25 R/W UART_RX_INV 0 Invert RX signal. 0: RX active HIGH. 1: RX active LOW 24 R/W UART_CLR_ERR 0 Clear error. Writing 1 to this register bit clears error.Note: This bit does not clear to 0 automatically. Please set the bit to 0 after clearing error manually.23 R/W UART_RX_RST 0 Reset receive state machine. Writing 1 to this register bit resetsreceive state machine.22 R/W UART_TX_RST 0 Reset transmit state machine. Write 1 to this register bit resettransmit state machine.21:20 R/W UART_DATA_LEN 00 Character length of data.00: 8-bit 01: 7-bit 10: 6-bit 11: 5-bit19 R/W PARITY_EN 1 Parity enable bit. 0: disable parity bit. 1: enable parity bit 18 R/W PARITY_TYPE 0 Parity type bit. 0: even parity. 1: odd parity 17:16 R/W STOP_BIT_LEN 0 Stop bit length.00: 1 stop bit 01: 2 stop bit 10-11: reserved.15 R/W TWO_WIRE_EN 0 Two-wire mode enables. 0: four-wire mode. 1: Two-wire mode 14 - - 0 Reserved 13 R/W UART_RX_EN 0 Receive enable. 0: disable receive function. 1: enable receivefunction12 R/W UART_TX_EN 0 Transmit enable. 0: disable transmit function. 1: enabletransmit function11:0 R/W BAUD_RATE 0x120 Baud rate setup. Please refer to Baud Rate Generation Sectionfor detail.Di s t ri bu t et oE md o o r!UART_A Status Register (UART_A_STATUS)UART_A_STATUS is a read-only register to indicate the status of UART interface.Table 7. UART_A_STATUS register definition Name UART_A_STATUS Offset 0x2133Width 32-bit Bit R/W Name Default Description31:27 - - 0x00 Reserved26 R UART_RECV_BUSY 0 Receive state machine busy indicator. Being set to 1indicates receive state machine is busy25 R UART_XMIT_BUSY 0 Transmit state machine busy indicator. Being set to 1indicates transmit state machine is busy24 R RECV_FIFO_OVERFLOW 0 Receive FIFO overflow indicator. Being set to 1 indicatesreceive FIFO overflows23 R CTS_LEVEL 0 CTS signal level.22 R TX_FIFO_EMPTY 0 Transmit FIFO Empty indicator. Being set to 1 indicatesTransmit FIFO is empty21 R TX_FIFO_FULL 0 Transmit FIFO Full indicator. Being set to1 indicatesTransmit FIFO is full.20 R RX_FIFO_EMPTY 0 Receive FIFO Empty indicator. Being set to 1 indicatesReceive FIFO is empty19 R RX_FIFO_FULL 0 Receive FIFO Full indicator. Being set to 1 indicatesReceive FIFO is full.18 R TX_FIFO_WERR 0 Transmit FIFO writing error indicator. The bit is set to 1 ifwriting data to Transmit FIFO when Transmit FIFO is full.Note: Please use register UART_A_CONTROL bit 24 toclear this bit. Refer to UART_A_CONTROL registerdefinition.17 R FRAME_ERR 0 Frame Error indicator. The bit is set to 1 if frame errordetected.Note: Please use register UART_A_CONTROL bit 24 toclear this bit. Refer to UART_A_CONTROL registerdefinition.16 R PARITY_ERR 0 Parity Error indicator. The bit is set to 1 if parity errordetected.Note: Please use register UART_CONTROL bit 24 to clearthis bit. Refer to UART_A_CONTROL register definition.15 - - 0 Reserved14:8 R TX_FIFO_DCNT 0 Transmit FIFO data count. The value is the number ofbytes in the Transmit FIFO.7 R - 0 Reserved6:0 R RX_FIFO_DCNT 0 Receive FIFO data count. The value is the number ofbytes in the Receive FIFO.Di s t r i b u t e t o E m d o o r !UART_A Interrupt Control Register (UART_A_MISC)UART_A_MISC is the register to control UART related interrupt.Table 8. UART_A_MISC register definition Name UART_A_MISC Offset 0x2134Width 32-bit Bit R/W Name Default Description31 - - 0 Reserved30 R/W USE old Rx Baud 0 he Rx baud rate generator was re-designed to compute abaud rate correctly. If you want to use the old (stupid) logic,you can set this bit to 1.29 R/W ASYNC_FIFO_PURGE 0 Set to 1 after all UART bytes have been received in order topurge the data into the async FIFO28 R/W ASYNC_FIFO_EN 0 Automatically send to async FIFO module enable1: enable automatic sending0:disable automatic sending27 R/W CTS_FIL_TB_SEL 0 CTS input filter time base selection.A digital signal filter can be used to filter the UART CTS signalinput.The filter has two parameters, the time base and the numberof time base.0: The time base is 111nS.1: The time base is 1uS.26-24 R/W CTS_FIL_SEL 0 CTS input filter times000: No filter.…111: Maximum filter time. The time is 7x 111= 777nS(CTS_FIL_TB_SEL = 0) or 7x 1=7uS (CTS_FIL_TB_SEL = 1)23-20 R/W BAUD_RATE_EXT 0 Extend the baud rate divider to 16-bits together withUART_A_STATUS[11:0]Baud_Rate = {Reg4[23:20],Reg2[11:0]}19 R/W RX_FIL_TB_SEL 0 RX input filter time base selection.A digital signal filter can be used to filter the UART RX signalinput.The filter has two parameters, the time base and the times oftime base.0: The time base is 111nS.1: The time base is 1uS.18:16 R/W RX_FIL_SEL 0 RX input filter times000: No filter.…111: Maximum filter time. The time is 7x 111= 777nS(RX_FIL_TB_SEL = 0) or 7x 1=7uS (RX_FIL_TB_SEL = 1)15:8 R/W XMIT_IRQ_CNT 32 Transmit FIFO threshold.UART generates an interrupt when the number of bytes inTransmit FIFO is below the value of these bits.7:0 R/W RECV_IRQ_CNT 15 Receive FIFO threshold.UART generates an interrupt when the number bytes inReceive FIFO is large than the value of these bits.Di s t ri b u t e t o E m d o o r !UART_A_REG5Table 9. UART_A_REG5 register definition Name UART_A_REG5 Offset 0x2135Width 32-bit Bit R/W Name Default Description31-24 R/W - 0 unused23 R/W USE New Baud rate. 0 Over the years, the baud rate has been extended byconcatenating bits from different registers. To takeadvantage of the full 23-bit baud rate generate (extended to23 bits to accommodate very low baud rates), you must setthis bit. If this bit is set, then the baud rate is configuredusing bits [22:0] below22:0 R/W NEW_BAUD_RATE: 0 If bit[23] = 1 above, then the baud rate for the UART iscomputed using these bits. This was added in MX toaccommodate lower baud rates.Di s t r i b u t e t o E m d o o r !9.2. UART_BWrite Buffer Register (UART_B_WFIFO)UART_B_WFIFO is the data entry of UART_B transmit FIFO. Writing to the register puts a byte data into the top of transmit FIFO. The data at the front of the FIFO transmits automatically until transmit FIFO empty.Table 10. UART_B_WFIFO register definition Name UART_B_WFIFO Offset 0x2137 Width 32-bitBit R/W Name Default Description31:8 R - 0 Reserved7:0 W FIFO_WDATA - Write UART Transmit FIFO.Read Buffer Register (UART_B_RFIFO)UART_B_RFIFO is the data entry of UART Read FIFO. It latches the value of data byte at the front of UART Read FIFO. Table 9. UART_B_RFIFO register definition Name UART_B_RFIFO Offset 0x2138 Width 32-bit Bit R/W Name Default Description 31:8 R - 0 Reserved 7:0 R FIFO_RDATA 0x00 Read a byte from UART FIFO.Di s t r i b u t e t o E m d o o r !UART_B Mode Register (UART_B_CONTROL)UART_B_CONTROL is a control register.Table 10. UART_B_CONTROL register definition Name UART_B_CONTROL Offset 0x2139Width 32-bit Bit R/W Name Default Description31 R/W RTS_INV 0 Invert RTS signal. 0: RTS active LOW. 1: RTS active HIGH30 R/W ERR_MASK_EN 0 Error Mask enable. 0: disable error mask. 1: enable error mask. 29 R/W CTS_INV 0 Invert CTS signal. 0: CTS active LOW 1: CTS active HIGH.28 R/W UART_TX_INT_EN 0 Transmit byte interrupt enable. When enabled, an interrupt will begenerated whenever a byte is read from Transmit FIFO.0: disable transmit byte interrupt1: enable transmit byte interrupt27 R/W UART_RX_INT_EN 0 Receive byte interrupt enable. When enabled, an interrupt will begenerated whenever a byte is written to Read FIFO.0: disable receive byte interrupt1: enable receive byte interrupt26 R/W UART_TX_INV 0 Invert TX signal. 0: TX active HIGH. 1: TX active LOW 25 R/W UART_RX_INV 0 Invert RX signal. 0: RX active HIGH. 1: RX active LOW 24 R/W UART_CLR_ERR 0 Clear error. Writing 1 to this register bit clears error.Note: This bit does not clear to 0 automatically. Please set the bitto 0 after clearing error manually.23 R/W UART_RX_RST 0 Reset receive state machine. Writing 1 to this register bit resetsreceive state machine.22 R/W UART_TX_RST 0 Reset transmit state machine. Write 1 to this register bit resettransmit state machine.21:20 R/W UART_DATA_LEN 00 Character length of data.00: 8-bit01: 7-bit10: 6-bit11: 5-bit19 R/W PARITY_EN 1 Parity enable bit. 0: disable parity bit. 1: enable parity bit 18 R/W PARITY_TYPE 0 Parity type bit. 0: even parity. 1: odd parity17:16 R/W STOP_BIT_LEN 0 Stop bit length.00: 1 stop bit01: 2 stop bit10-11: reserved.15 R/W TWO_WIRE_EN 0 Two-wire mode enables. 0: four-wire mode. 1: Two-wire mode 14 - - 0 Reserved13 R/W UART_RX_EN 0 Receive enable. 0: disable receive function. 1: enable receivefunction12 R/W UART_TX_EN 0 Transmit enable. 0: disable transmit function. 1: enabletransmit function11:0 R/W BAUD_RATE 0x120 Baud rate setup. Please refer to Baud Rate Generation Sectionfor detail.D i s t ri b u t e t o E m d o o r !UART_B Status Register (UART_STATUS)UART_B_STATUS is a read-only register to indicate the status of UART interface.Table 13. UART_B_STATUS register definition Name UART_B_STATUS Offset 0x213AWidth 32-bit Bit R/W Name Default Description31:27 - - 0x00 Reserved26 R UART_RECV_BUSY 0 Receive state machine busy indicator. Being set to 1indicates receive state machine is busy25 R UART_XMIT_BUSY 0 Transmit state machine busy indicator. Being set to 1indicates transmit state machine is busy24 R RECV_FIFO_OVERFLOW 0 Receive FIFO overflow indicator. Being set to 1 indicatesreceive FIFO overflows23 R CTS_LEVEL 0 CTS signal level.22 R TX_FIFO_EMPTY 0 Transmit FIFO Empty indicator. Being set to 1 indicatesTransmit FIFO is empty21 R TX_FIFO_FULL 0 Transmit FIFO Full indicator. Being set to1 indicatesTransmit FIFO is full.20 R RX_FIFO_EMPTY 0 Receive FIFO Empty indicator. Being set to 1 indicatesReceive FIFO is empty19 R RX_FIFO_FULL 0 Receive FIFO Full indicator. Being set to 1 indicatesReceive FIFO is full.18 R TX_FIFO_WERR 0 Transmit FIFO writing error indicator. The bit is set to 1 ifwriting data to Transmit FIFO when Transmit FIFO is full.Note: Please use register UART_B_CONTROL bit 24 toclear this bit. Refer to UART_B_CONTROL registerdefinition.17 R FRAME_ERR 0 Frame Error indicator. The bit is set to 1if frame errordetected.Note: Please use register UART_B_CONTROL bit 24 toclear this bit. Refer to UART_B_CONTROL registerdefinition.16 R PARITY_ERR 0 Parity Error indicator. The bit is set to 1 if parity errordetected.Note: Please use register UART_CONTROL bit 24 to clearthis bit. Refer to UART_B_CONTROL register definition.15 - - 0 Reserved14:8 R TX_FIFO_DCNT 0 Transmit FIFO data count. The value is the number ofbytes in the Transmit FIFO.7 R - 0 Reserved6:0 R RX_FIFO_DCNT 0 Receive FIFO data count. The value is the number ofbytes in the Receive FIFO.Di s t r i b u t e t o E m d o o r !UART_B Interrupt Control Register (UART_B_MISC)UART_B_MISC is the register to control UART related interrupt.Table 11. UART_B_MISC register definition Name UART_B_MISC Offset 0x213BWidth 32-bit Bit R/W Name Default Description31 - - 0 Reserved30 R/W USE old Rx Baud 0 he Rx baud rate generator was re-designed to compute abaud rate correctly. If you want to use the old (stupid) logic,you can set this bit to 1.29 R/W ASYNC_FIFO_PURGE 0 Set to 1 after all UART bytes have been received in order topurge the data into the async FIFO28 R/W ASYNC_FIFO_EN 0 Automatically send to async FIFO module enable1: enable automatic sending0:disable automatic sending27 R/W CTS_FIL_TB_SEL 0 CTS input filter time base selection.A digital signal filter can be used to filter the UART CTS signalinput.The filter has two parameters, the time base and the numberof time base.0: The time base is 111nS.1: The time base is 1uS.26-24 R/W CTS_FIL_SEL 0 CTS input filter times000: No filter.…111: Maximum filter time. The time is 7x 111= 777nS(CTS_FIL_TB_SEL = 0) or 7x 1=7uS (CTS_FIL_TB_SEL = 1)23-20 R/W BAUD_RATE_EXT 0 Extend the baud rate divider to 16-bits together withUART_B_STATUS[11:0]Baud_Rate = [BAUD_RATE_EXT: BAUD_RATE]19 R/W RX_FIL_TB_SEL 0 RX input filter time base selection.A digital signal filter can be used to filter the UART RX signalinput.The filter has two parameters, the time base and the times oftime base.0: The time base is 111nS.1: The time base is 1uS.18:16 R/W RX_FIL_SEL 0 RX input filter times000: No filter.…111: Maximum filter time. The time is 7x 111= 777nS(RX_FIL_TB_SEL = 0) or 7x 1=7uS (RX_FIL_TB_SEL = 1)15:8 R/W XMIT_IRQ_CNT 32 Transmit FIFO threshold.UART generates an interrupt when the number of bytes inTransmit FIFO is below the value of these bits.7:0 R/W RECV_IRQ_CNT 15 Receive FIFO threshold.UART generates an interrupt when the number bytes inReceive FIFO is large than the value of these bits.Di s t r i b u t e t o E m d o o r !。

版本变更记录版本号日期描述V1.0 2022年01月20日EG8026数据手册初稿。

目录目录 (3)1.特点 (5)2.描述 (6)3.应用领域 (6)4.引脚 (7)4.1QFN70封装引脚定义 (7)4.2LQFP80封装引脚定义 (8)4.3引脚描述 (9)5.结构框图 (12)6.典型应用电路 (13)6.1EG8026 QFN70封装应用原理图 (13)6.2EG8026 LQFP80封装应用原理图 (14)6.348V/2KW双向逆变器主板应用图 (15)6.4EG1615 DC/DC控制板原理图 (16)7.电气特性 (17)7.1极限参数 (17)7.2典型参数 (18)8.应用设计 (20)8.1双向逆变器的主拓扑结构 (20)8.2EG8026实现的传统型Boost无桥PFC结构 (21)8.3EG8026实现的DC/AC Inverter结构 (22)8.4PFC和DC/AC Inverter、UPS功能切换 (23)8.5PWM调制方式 (23)8.6输出电压反馈 (24)8.7输出电流反馈 (26)8.8温度反馈 (27)8.9直流母线电压反馈和硬件过压保护 (27)8.10死区时间 (28)8.11H桥的左、右桥臂互换控制 (29)9.保护功能 (30)9.1输出过载保护 (30)9.2输出过流保护 (30)9.3直流母线电压过压保护 (30)9.4PCB过温保护 (30)9.5功率管过温保护 (30)9.6短路保护 (30)9.7MOS管峰值电流保护 (31)10.测试模式 (32)11.通讯功能（UART） (33)11.1串口描述 (33)11.2APP功能 (33)屹晶微电子有限公司11.2.1APP消息发送 (33)11.2.2APP消息接收 (34)11.3CFG功能 (36)11.3.1CFG请求消息 (36)11.3.2CFG应答消息 (36)11.3.30x10服务-会话切换 (37)11.3.40x22服务-读DID (38)11.3.50x2E服务-写DID (38)11.3.60x21 服务-读CFG (39)11.3.70x2D 服务-写CFG (39)11.3.80x2F服务-IO控制 (40)12.封装尺寸 (41)12.1LQFP80 (41)12.2QFN70 (42)屹晶微电子有限公司EG8026芯片数据手册V1.01. 特点集成了DC/AC逆变器和PFC升压两大功能支持UPS功能作逆变器DC/AC时的功能：⏹采用电流模式、中心对齐PWM调制方式，能带感性和容性负载⏹SPWM载波频率20KHz，适合大功率MOS管和IGBT管的应用⏹集成了两路600V半桥高压MOS管驱动器，驱动能力为±2A⏹集成四路独立的MOS管峰值电流保护电路及内置四路200mV基准源的比较器供用户设定保护值⏹集成了四路高速运放及一路高速比较器，两路运放用于交流电流放大器，一路运放用于交流输出电压反馈，一路运放用于短路保护和一路比较器用于限流保护⏹输出电压和输出电流是每个PWM周期实时处理，能实现精确跟踪⏹引脚可配置功能：●H桥左、右桥臂互换控制●4种死区时间可选配置: 300nS、500nS、1uS、1.5uS●2种固定正弦波频率可选配置：50Hz、60Hz●软启动开启和关闭⏹逆变器保护功能：●直流母线电压过压保护●交流输出欠压保护●输出过载保护●输出过流保护●PCB过温保护和IGBT过温保护●输出短路保护⏹串口通讯可设置参数：●50Hz纯正弦波固定频率●60Hz纯正弦波固定频率●交流输出电压●温度保护值●额定功率保护值●额定电流保护值●故障复位⏹串口通讯可读参数：●交流输出电压●交流输出频率●交流输出功率●交流输出电流●直流母线电压●故障代码作PFC升压时的功能：⏹采用传统型Boost无桥PFC结构，平均电流控制算法⏹SPWM载波频率20KHz，适合大功率MOS管和IGBT管的应用⏹升压输出电压由恒功率大小进行自动调节，正常电压为400V，可调电压范围为330V到450V⏹外部可设的硬件输出过压保护⏹交流输入电压欠压保护⏹输出过载和过流保护⏹支持UART串口通讯，实现跟前级DC/DC EG1615芯片进行通讯，读取充电电压和电流等信息⏹PF值可达0.98以上2. 描述EG8026芯片是一款专用于双向逆变器（同一套电路可作逆变器功能，又可作电池充电器功能）中的DC/AC逆变和PFC升压的控制芯片，集成了两路600V半桥高压MOS驱动器，驱动器的输出电流能力为+/-2A，内置四路独立的逐周PWM关断保护，可有效防止在极端情况下过高的峰值电流而损坏MOS的情况，另外提供了两路SD，分别为SD1，和SD2，SD1是驱动器1 HO1和LO1的逐周关断引脚，SD2是驱动器2 HO2和LO2的逐周关断引脚，结合外部比较器和SD功能可实现过流或短路保护等功能。

【itr8402光电开关规格书】一、产品概述itr8402光电开关是一种常见的传感器设备，主要用于检测物体的存在或运动。

它通常由发射器和接收器两部分组成，通过光学原理实现对目标物体的检测。

itr8402光电开关具有高精度、稳定性好、响应速度快等特点，广泛应用于工业自动化生产线等领域。

二、产品规格1. 工作原理：光电传感器2. 工作电压：DC 5V-24V3. 响应时间：≤1ms4. 最大探测距离：10m5. 工作温度：-25℃~+70℃6. 输出类型：NPN/PNP7. 输出状态：常开/常闭8. 外壳材质：金属/塑料9. 防护等级：IP6510. 安装方式：螺纹/法兰/夹紧三、产品特点1. 高精度：itr8402光电开关采用先进的光电传感技术，能够精准快速地检测目标物体，确保生产线运行的稳定性和效率。

2. 稳定性好：经过精密的工艺制造，具有良好的防尘、防水性能，能够在恶劣环境下长时间稳定工作。

3. 响应速度快：响应时间快，能够及时准确地感知目标物体的运动状态，实现精确的控制。

4. 多种输出类型：支持NPN和PNP两种输出类型，可根据实际需求选择常开或常闭输出状态，灵活适应不同的工作场景。

5. 多种安装方式：可选用螺纹、法兰或夹紧等多种安装方式，方便安装和维护。

四、适用领域itr8402光电开关适用于各种工业自动化生产线，包括但不限于机械设备、包装生产线、输送带系统等领域。

可以实现对物体的准确探测和位置识别，广泛应用于自动化控制、物料检测、计数器等功能。

五、注意事项1. 安装时请确保光电开关与目标物体之间无遮挡物，以免影响探测效果。

2. 使用过程中应定期清洁光电开关的感应窗口，避免灰尘和污物影响传感效果。

3. 请根据实际需求选择合适的输出类型和安装方式，以确保光电开关的稳定工作和准确探测。

六、结语itr8402光电开关是一款性能稳定、功能全面的光电传感器，具有高精度、响应速度快等优点，广泛应用于各种工业自动化生产线。

Application NotesAML 8726-MXL/MXSGPIO User GuideRevision 0.3 PRELIMINARYAMLOGIC, Inc.3930 Freedom Circle Santa Clara, CA 95054U.S.A. AMLOGIC reserves the right to change any information described herein at any time without notice.AMLOGIC assumes no responsibility or liability from use of such information.Di st r i b u t et oS ky n o o n !Table of Content1 GENERAL DESCRIPTION ...................................................................................................................................... 42 GPIO BANKS ............................................................................................................................................................. 43 GPIO GENERAL FUNCTIONAL REGISTER ......................................................................................................4 4PIN MULTIPLEXING ............................................................................................................................................... 9 4.1 GPIO F UNCTION S ETTING ..................................................................................................................................... 9 4.2 R EGISTER M ACRO D EFINITION .............................................................................................................................. 9 4.3 D EFAULT F UNCTION .............................................................................................................................................. 9 4.4 P IN M ULTIPLEXING .............................................................................................................................................. 10 4.4.1 GPIO Bank A .............................................................................................................................................. 10 4.4.2 GPIO Bank B .............................................................................................................................................. 10 4.4.3 GPIO Bank C .............................................................................................................................................. 11 4.4.4 GPIO Bank D .............................................................................................................................................. 12 4.4.5 GPIO Bank E .............................................................................................................................................. 12 4.4.6 GPIO Bank X .............................................................................................................................................. 13 4.4.7 GPIO Bank Z .............................................................................................................................................. 14 4.4.8 GPIO Bank AO ........................................................................................................................................... 15 4.4.9 GPIO Bank BOOT ...................................................................................................................................... 16 4.4.10 GPIO Bank CARD ...................................................................................................................................... 17 5 ADDRESS MAPPING . (17)Di st ri bu tet oS ky n o o n !Revision HistoryRevision Number Revised Date By Changes0.3 2013/01/15 Kevin Zhu Initial version releaseDi st ri bu tet oS ky n o o n !1 General DescriptionThis document is a general user guide of Amlogic AML8726-MXL/MXS GPIOs. In this document, it describes:● The selection of GPIO operation mode.● The input and output register of each GPIO. ● GPIO pin multiplex selection2 GPIO BanksAML8726-MXL/MXS GPIOs are organized as 10 banks: 8 general banks and 2 dedicated banks.The 8 general banks are:● Bank A: There are 6 pin outs in this bank between GPIOA_14 and GPIOA_27. ● Bank B: There are 18 pin outs in this bank between GPIOB_2 and GPIOB_23. ● Bank C: There are 10 pin outs in this bank between GPIOC_0 and GPIOC_13. ● Bank D: There are 8 pin outs in this bank between GPIOD_0 and GPIOD_9. ● Bank E: There are 7 pin outs in this bank between GPIOE_0 and GPIOE_11. ● Bank X: There are 23 pin outs in this bank between GPIOX_0 and GPIOX_28. ● Bank Z: There are 13 pin outs in this bank from GPIOZ_0 to GPIOZ_12.● Bank AO: There are 12 pin outs in this bank from GPIOAO_0 to GPIOAO_11.The 2 dedicated banks are:● Bank BOOT: There are 18 pin outs in this bank from BOOT_0 to BOOT_17. In most application, all pins inthis bank are used to connect boot device such as NAND Flash, eMMC or SD card.● Bank CARD: There are 8 pin outs in this bank between CARD_0 and CARD_8. In most application, allpins in this bank are used to connect memory card such SD card.Please avoid using pins in Bank BOOT and CARD as ordinary GPIOs.3 GPIO General Functional RegisterEach GPIO in each bank can be controlled and operated by four register sets:● OEN: It is mode definition register which uses to control the operation mode of each GPIO in the bank.⏹ “1”: Set the pin to input mode. It is the default mode after chip power-on/reset. In this mode, the GPIOis tri-state and input is valid.⏹ “0”: Set the pin to output mode. In this mode, the GPIO voltage level is controlled by OUT registers. ● OUT: It is to setup the output voltage level of each GPIO to logic HIGH or logic LOW.⏹ “1” Set the GPIO to logic HIGH. ⏹ “0” Set the GPIO to logic LOW.● IN: It is used only in input mode. It can be read and the value is the input logic voltage value. ● PU/PD: It is used to enable or disable build-in pull-up or pull-down resister of each GPIO.⏹ “1” Disable pull-up or pull-down resister. When disabled, the GPIO is High-Z. ⏹ “0” Enable pull-up or pull-down resister.The OEN, OUT, IN and PU/PD registers and mapping to each GPIO in each GPIO bank are listed in Table 1.Di st ri bu tet oS ky n o o n !Table 1. GPIO General Function Register Control BitsBGA Ball Number Package Name OEN(Read Write)OUT(Write Only)IN(Read Only)PU/PD(Read Write) IO TypeDefault State after resetBank A A20 GPIOA_14 0x200c bit[14] 0x200d bit[14] 0x200e bit[14] 0x203A bit[14] Tri-State Pull-up C19 GPIOA_15 0x200c bit[15] 0x200d bit[15] 0x200e bit[15] 0x203A bit[15] Tri-State Pull-up B19 GPIOA_16 0x200c bit[16] 0x200d bit[16] 0x200e bit[16] 0x203A bit[16] Tri-State Pull-up C18 GPIOA_19 0x200c bit[19] 0x200d bit[19] 0x200e bit[19] 0x203A bit[19] Tri-State Pull-up B18 GPIOA_25 0x200c bit[25] 0x200d bit[25] 0x200e bit[25] 0x203A bit[25] Tri-State Pull-up A18 GPIOA_270x200c bit[27]0x200d bit[27]0x200e bit[27]0x203A bit[27] Tri-State Pull-up Bank BC17 GPIOB_2 0x200F bit[2] 0x2010 bit[2] 0x2011 bit[2] 0x203B bit[2] Tri-State Pull-Down A17 GPIOB_3 0x200F bit[3] 0x2010 bit[3] 0x2011 bit[3] 0x203B bit[3] Tri-State Pull-Down B17 GPIOB_4 0x200F bit[4] 0x2010 bit[4] 0x2011 bit[4] 0x203B bit[4] Tri-State Pull-Down C16 GPIOB_5 0x200F bit[5] 0x2010 bit[5] 0x2011 bit[5] 0x203B bit[5] Tri-State Pull-Down B16 GPIOB_6 0x200F bit[6] 0x2010 bit[6] 0x2011 bit[6] 0x203B bit[6] Tri-State Pull-Down C15 GPIOB_7 0x200F bit[7] 0x2010 bit[7] 0x2011 bit[7] 0x203B bit[7] Tri-State Pull-Down D17 GPIOB_10 0x200F bit[10] 0x2010 bit[10] 0x2011 bit[10] 0x203B bit[10] Tri-State Pull-Down E17 GPIOB_11 0x200F bit[11] 0x2010 bit[11] 0x2011 bit[11] 0x203B bit[11] Tri-State Pull-Down E16 GPIOB_12 0x200F bit[12] 0x2010 bit[12] 0x2011 bit[12] 0x203B bit[12] Tri-State Pull-Down E15 GPIOB_13 0x200F bit[13] 0x2010 bit[13] 0x2011 bit[13] 0x203B bit[13] Tri-State Pull-Down D15 GPIOB_14 0x200F bit[14] 0x2010 bit[14] 0x2011 bit[14] 0x203B bit[14] Tri-State Pull-Down D14 GPIOB_15 0x200F bit[15] 0x2010 bit[15] 0x2011 bit[15] 0x203B bit[15] Tri-State Pull-Down B15 GPIOB_18 0x200F bit[18] 0x2010 bit[18] 0x2011 bit[18] 0x203B bit[18] Tri-State Pull-Down C14 GPIOB_19 0x200F bit[19] 0x2010 bit[19] 0x2011 bit[19] 0x203B bit[19] Tri-State Pull-Down B14 GPIOB_20 0x200F bit[20] 0x2010 bit[20] 0x2011 bit[20] 0x203B bit[20] Tri-State Pull-Down A14 GPIOB_21 0x200F bit[21] 0x2010 bit[21] 0x2011 bit[21] 0x203B bit[21] Tri-State Pull-Down C13GPIOB_22 0x200F bit[22] 0x2010 bit[22] 0x2011 bit[22] 0x203B bit[22] Tri-State Pull-Down A13GPIOB_230x200F bit[23]0x2010 bit[23]0x2011 bit[23]0x203B bit[23] Tri-State Pull-Down Bank CJ19GPIOC_0 0x2012 bit[0] 0x2013 bit[0] 0x2014 bit[0] 0x203C bit[0] Tri-State (24mA) Pull-Down H19 GPIOC_3 0x2012 bit[3] 0x2013 bit[3] 0x2014 bit[3] 0x203C bit[3] Tri-State Pull-Down H18 GPIOC_4 0x2012 bit[4] 0x2013 bit[4] 0x2014 bit[4] 0x203C bit[4] Tri-State Pull-Down T4 GPIOC_7 0x2012 bit[7] 0x2013 bit[7] 0x2014 bit[7] 0x203C bit[7] Tri-State Pull-Down R5 GPIOC_8 0x2012 bit[8] 0x2013 bit[8] 0x2014 bit[8] 0x203C bit[8] Tri-State Pull-Down T5GPIOC_90x2012 bit[9]0x2013 bit[9]0x2014 bit[9]0x203C bit[9]Tri-StatePull-DownDi st ri bu tet oS ky n o o n !U5 GPIOC_10 0x2012 bit[10] 0x2013 bit[10] 0x2014 bit[10] 0x203C bit[10] Tri-State (24mA) High-Z U4 GPIOC_11 0x2012 bit[11] 0x2013 bit[11] 0x2014 bit[11] 0x203C bit[11] Tri-State (24mA) High-Z AA1 GPIOC_12 0x2012 bit[12] 0x2013 bit[12] 0x2014 bit[12] 0x203C bit[12] Tri-State (24mA) High-Z AA2 GPIOC_130x2012 bit[13]0x2013 bit[13]0x2014 bit[13] 0x203C bit[13] Tri-State (24mA) High-Z Bank DE14 GPIOD_0 0x2012 bit[16] 0x2013 bit[16] 0x2014 bit[16] 0x203C bit[16] Tri-State (24mA) Pull-Down B13 GPIOD_1 0x2012 bit[17] 0x2013 bit[17] 0x2014 bit[17] 0x203C bit[17] Tri-State (24mA) Pull-Down C12 GPIOD_2 0x2012 bit[18] 0x2013 bit[18] 0x2014 bit[18] 0x203C bit[18] Tri-State Pull-Down B12 GPIOD_3 0x2012 bit[19] 0x2013 bit[19] 0x2014 bit[19] 0x203C bit[19] Tri-State Pull-Down C11 GPIOD_4 0x2012 bit[20] 0x2013 bit[20] 0x2014 bit[20] 0x203C bit[20] Tri-State Pull-Down B11 GPIOD_7 0x2012 bit[23] 0x2013 bit[23] 0x2014 bit[23] 0x203C bit[23] Tri-State Pull-Down C10 GPIOD_8 0x2012 bit[24] 0x2013 bit[24] 0x2014 bit[24] 0x203C bit[24] Tri-State Pull-Down B10 GPIOD_90x2012 bit[25] 0x2013 bit[25] 0x2014 bit[25]0x203C bit[25] Tri-State Pull-Down Bank EA10 GPIOE_0 0x2008 bit[0] 0x2009 bit[0] 0x200A bit[0] 0x2039 bit[0] Tri-State Pull-Up C9 GPIOE_1 0x2008 bit[1] 0x2009 bit[1] 0x200A bit[1] 0x2039 bit[1] Tri-State Pull-Up A9 GPIOE_2 0x2008 bit[2] 0x2009 bit[2] 0x200A bit[2] 0x2039 bit[2] Tri-State Pull-Up B9 GPIOE_3 0x2008 bit[3] 0x2009 bit[3] 0x200A bit[3] 0x2039 bit[3] Tri-State Pull-Up C8 GPIOE_4 0x2008 bit[4] 0x2009 bit[4] 0x200A bit[4] 0x2039 bit[4] Tri-State Pull-Up D9 GPIOE_10 0x2008 bit[10] 0x2009 bit[10] 0x200A bit[10] 0x2039 bit[10] Tri-State Pull-Up D8 GPIOE_110x2008 bit[11]0x2009 bit[11]0x200A bit[11] 0x2039 bit[11] Tri-State Pull-Up Bank XA3 GPIOX_0 0x2018 bit[0] 0x2019 bit[0] 0x201a bit[0] 0x203d bit[0] Tri-State Pull-Up B3 GPIOX_1 0x2018 bit[1] 0x2019 bit[1] 0x201a bit[1] 0x203d bit[1] Tri-State Pull-Up A2 GPIOX_2 0x2018 bit[2] 0x2019 bit[2] 0x201a bit[2] 0x203d bit[2] Tri-State Pull-Up B2 GPIOX_3 0x2018 bit[3] 0x2019 bit[3] 0x201a bit[3] 0x203d bit[3] Tri-State Pull-Up B1 GPIOX_4 0x2018 bit[4] 0x2019 bit[4] 0x201a bit[4] 0x203d bit[4] Tri-State Pull-Up C2 GPIOX_5 0x2018 bit[5] 0x2019 bit[5] 0x201a bit[5] 0x203d bit[5] Tri-State Pull-Up C1GPIOX_6 0x2018 bit[6] 0x2019 bit[6] 0x201a bit[6] 0x203d bit[6] Tri-State Pull-Up D3 GPIOX_7 0x2018 bit[7] 0x2019 bit[7] 0x201a bit[7] 0x203d bit[7] Tri-State Pull-Up D2 GPIOX_8 0x2018 bit[8] 0x2019 bit[8] 0x201a bit[8] 0x203d bit[8] Tri-State Pull-Up E3 GPIOX_9 0x2018 bit[9] 0x2019 bit[9] 0x201a bit[9] 0x203d bit[9] Tri-State Pull-Up E2 GPIOX_10 0x2018 bit[10] 0x2019 bit[10] 0x201a bit[10] 0x203d bit[10] Tri-State Pull-Up E4GPIOX_110x2018 bit[11]0x2019 bit[11]0x201a bit[11]0x203d bit[11]Tri-StatePull-UpDi st ri bu tet oS ky n o o n !F4 GPIOX_12 0x2018 bit[12] 0x2019 bit[12] 0x201a bit[12] 0x203d bit[12] Tri-State Pull-Up F5 GPIOX_13 0x2018 bit[13] 0x2019 bit[13] 0x201a bit[13] 0x203d Bit[13] Tri-State Pull-Up G5 GPIOX_14 0x2018 bit[14] 0x2019 bit[14] 0x201a bit[14] 0x203d bit[14] Tri-State Pull-Up H5 GPIOX_15 0x2018 bit[15] 0x2019 bit[15] 0x201a bit[15] 0x203d bit[15] Tri-State Pull-Up H4 GPIOX_16 0x2018 bit[16] 0x2019 bit[16] 0x201a bit[16] 0x203d bit[16] Tri-State Pull-Up E1 GPIOX_23 0x2018 bit[23] 0x2019 bit[23] 0x201a bit[23] 0x203d bit[23] Tri-State Pull-Up F3 GPIOX_24 0x2018 bit[24] 0x2019 bit[24] 0x201a bit[24] 0x203d bit[24] Tri-StatePull-UpF1 GPIOX_25 0x2018 bit[25] 0x2019 bit[25] 0x201a bit[25] 0x203d bit[25] Tri-State Pull-Up F2 GPIOX_26 0x2018 bit[26] 0x2019 bit[26] 0x201a bit[26] 0x203d bit[26] Tri-State Pull-Up G3 GPIOX_27 0x2018 bit[27] 0x2019 bit[27] 0x201a bit[27] 0x203d bit[27] Tri-State Pull-Up G2 GPIOX_280x2018 bit[28]0x2019 bit[28]0x201a bit[28]0x203d bit[28]Tri-State Pull-Up Bank ZE8 GPIOZ_0 0x2008 bit[16] 0x2009 bit[16] 0x200A bit[16] 0x2039 bit[16] Tri-State Pull-Up B8 GPIOZ_1 0x2008 bit[17] 0x2009 bit[17] 0x200A bit[17] 0x2039 bit[17] Tri-State Pull-Up C7 GPIOZ_2 0x2008 bit[18] 0x2009 bit[18] 0x200A bit[18] 0x2039 bit[18] Tri-State Pull-Up B7 GPIOZ_3 0x2008 bit[19] 0x2009 bit[19] 0x200A bit[19] 0x2039 bit[19] Tri-State Pull-Up C6 GPIOZ_4 0x2008 bit[20] 0x2009 bit[20] 0x200A bit[20] 0x2039 bit[20] Tri-State Pull-Up B6 GPIOZ_5 0x2008 bit[21] 0x2009 bit[21] 0x200A bit[21] 0x2039 bit[21] Tri-State Pull-Up A6 GPIOZ_6 0x2008 bit[22] 0x2009 bit[22] 0x200A bit[22] 0x2039 bit[22] Tri-State Pull-Up C5 GPIOZ_7 0x2008 bit[23] 0x2009 bit[23] 0x200A bit[23] 0x2039 bit[23] Tri-State Pull-Up A5 GPIOZ_8 0x2008 bit[24] 0x2009 bit[24] 0x200A bit[24] 0x2039 bit[24] Tri-State Pull-Up B5 GPIOZ_9 0x2008 bit[25] 0x2009 bit[25] 0x200A bit[25] 0x2039 bit[25] Tri-State Pull-Up C4 GPIOZ_10 0x2008 bit[26] 0x2009 bit[26] 0x200A bit[26] 0x2039 bit[26] Tri-State Pull-Up B4 GPIOZ_11 0x2008 bit[27] 0x2009 bit[27] 0x200A bit[27] 0x2039 bit[27] Tri-State Pull-Up C3 GPIOZ_120x2008 bit[28]0x2009 bit[28]0x200A bit[28]0x2039 bit[28]Tri-State Pull-Up Bank AOU20 GPIOAO_0 0xc8100024 bit[0] 0xc8100024 bit[16] 0xc8100028 bit[0] 0x000B bit[0] Tri-State Pull-Up U22 GPIOAO_1 0xc8100024 bit[1] 0xc8100024 bit[17] 0xc8100028 bit[1] 0x000B bit[1] Tri-State Pull-Up U21 GPIOAO_2 0xc8100024 bit[2] 0xc8100024 bit[18] 0xc8100028 bit[2] 0x000B bit[2] Tri-State Pull-Up T21 GPIOAO_3 0xc8100024 bit[3] 0xc8100024 bit[19] 0xc8100028 bit[3] 0x000B bit[3] Tri-State Pull-Up R20 GPIOAO_4 0xc8100024 bit[4] 0xc8100024 bit[20] 0xc8100028 bit[4] 0x000B bit[4] Tri-State Pull-Up R21 GPIOAO_5 0xc8100024 bit[5] 0xc8100024 bit[21] 0xc8100028 bit[5] 0x000B bit[5] Tri-State Pull-Up P20 GPIOAO_6 0xc8100024 bit[6] 0xc8100024 bit[22] 0xc8100028 bit[6] 0x000B bit[6] Tri-State Pull-Up P21GPIOAO_70xc8100024 bit[7]0xc8100024 bit[23]0xc8100028 bit[7]0x000B bit[7]Tri-StatePull-UpDi st ri bu tet oS ky n o o n !T18 GPIOAO_8 0xc8100024 bit[8] 0xc8100024 bit[24] 0xc8100028 bit[8] 0x000B bit[8] Tri-State Pull-Up R18 GPIOAO_9 0xc8100024 bit[9] 0xc8100024 bit[25] 0xc8100028 bit[9] 0x000B bit[9] Tri-State Pull-Up R19 GPIOAO_10 0xc8100024 bit[10] 0xc8100024 bit[26] 0xc8100028 bit[10] 0x000B bit[10] Tri-State Pull-Up P19 GPIOAO_110xc8100024 bit[11]0xc8100024 bit[27]0xc8100028 bit[11] 0x000B bit[11] Tri-State Pull-Up Bank BootN20 BOOT_0 0x2015 bit[0] 0x2016 bit[0] 0x2017 bit[0] 0x203D bit[0] Tri-State Pull-Up N22 BOOT_1 0x2015 bit[1] 0x2016 bit[1] 0x2017 bit[1] 0x203D bit[1] Tri-State Pull-Up N21 BOOT_2 0x2015 bit[2] 0x2016 bit[2] 0x2017 bit[2] 0x203D bit[2] Tri-State Pull-Up M20 BOOT_3 0x2015 bit[3] 0x2016 bit[3] 0x2017 bit[3] 0x203D bit[3] Tri-State Pull-Up M21 BOOT_4 0x2015 bit[4] 0x2016 bit[4] 0x2017 bit[4] 0x203D bit[4] Tri-State Pull-Up L20 BOOT_5 0x2015 bit[5] 0x2016 bit[5] 0x2017 bit[5] 0x203D bit[5] Tri-State Pull-Up L21 BOOT_6 0x2015 bit[6] 0x2016 bit[6] 0x2017 bit[6] 0x203D bit[6] Tri-State Pull-Up K20 BOOT_7 0x2015 bit[7] 0x2016 bit[7] 0x2017 bit[7] 0x203D bit[7] Tri-State Pull-Up K21 BOOT_8 0x2015 bit[8] 0x2016 bit[8] 0x2017 bit[8] 0x203D bit[8] Tri-State Pull-Up K22 BOOT_9 0x2015 bit[9] 0x2016 bit[9] 0x2017 bit[9] 0x203D bit[9] Tri-State Pull-Up J20 BOOT_10 0x2015 bit[10] 0x2016 bit[10] 0x2017 bit[10] 0x203D bit[10] Tri-State Pull-Up J22 BOOT_11 0x2015 bit[11] 0x2016 bit[11] 0x2017 bit[11] 0x203D bit[11] Tri-State Pull-Up J21 BOOT_12 0x2015 bit[12] 0x2016 bit[12] 0x2017 bit[12] 0x203D bit[12] Tri-State Pull-Up H20 BOOT_13 0x2015 bit[13] 0x2016 bit[13] 0x2017 bit[13] 0x203D bit[13] Tri-State Pull-Up H21 BOOT_14 0x2015 bit[14] 0x2016 bit[14] 0x2017 bit[14] 0x203D bit[14] Tri-State Pull-Up G20 BOOT_15 0x2015 bit[15] 0x2016 bit[15] 0x2017 bit[15] 0x203D bit[15] Tri-State Pull-Up K18 BOOT_16 0x2015 bit[16] 0x2016 bit[16] 0x2017 bit[16] 0x203D bit[16] Tri-State Pull-Up J18 BOOT_170x2015 bit[17]0x2016 bit[17]0x2017 bit[17]0x203D bit[17] Tri-State Pull-Up Bank CARDH3 CARD_0 0x201b bit[23] 0x201c bit[23] 0x201d bit[23] 0x203D bit[20] Tri-State Pull-Up H2 CARD_1 0x201b bit[24] 0x201c bit[24] 0x201d bit[24] 0x203D bit[21] Tri-State Pull-Up J3 CARD_2 0x201b bit[25] 0x201c bit[25] 0x201d bit[25] 0x203D bit[22] Tri-State Pull-Up J2 CARD_3 0x201b bit[26] 0x201c bit[26] 0x201d bit[26] 0x203D bit[23] Tri-State Pull-Up J1CARD_4 0x201b bit[27] 0x201c bit[27] 0x201d bit[27] 0x203D bit[24] Tri-State Pull-Up K3 CARD_5 0x201b bit[28] 0x201c bit[28] 0x201d bit[28] 0x203D bit[25] Tri-State Pull-Up L4 CARD_6 0x201b bit[29] 0x201c bit[29] 0x201d bit[29] 0x203D bit[26] Tri-State Pull-Up J5CARD_80x201b bit[31]0x201c bit[31]0x201d bit[31]0x203D bit[28]Tri-StatePull-UpDi st ri bu tet oS ky n o o n !4 Pin MultiplexingMost GPIOs of AML8726-MXL/MXS are multiplexed and have multi-functions. The function of each GPIO is controlled by register. The GPIO and function relationship is defined in all bank pin multiplexing tables.Amlogic provides Software Development Kit (SDK) with Linux Kernel for AML8726-MXL/MXS. In SDK, the GPIO function selection control register is defined as a set of Macro Definition. Each Macro Definition represents a register address of 32-bit data width.4.1 GPIO Function SettingTo set a GPIO pin to a given function, please follow the steps as below: 1. Look up in each bank pin multiplexing tables for the required function.2. According to corresponding abbreviated name of macro definition (REGX[b] or AO_REG[b]), check inTable 2 for its complete name in SDK to access the register. Meanwhile, direct access with address is also possible. For AO_REG, this is the only way since the macro definition for it is currently not defined yet. 3. Set bit [b] in the Macro register/Address to 1 to enable the function. The signal of function will bemultiplexed to the pin defined and can be operated at the position defined in BGA Ball Number column.Note: In principle, only one bit in each GPIO package should be set to 1 in order to enable a specific function. However, in case more than one bit is set, the last function setting is valid in a sequential operation.4.2 Register Macro DefinitionThe register macro definition name mapping in SDK and its address is shown below:Table 2. Register Macro Definition and its AddressName of Macro Definition In SDK Abbreviation in Table 3~8 Address Default Value after power-on/Reset PERIPHS_PIN_MUX_0 REG0 0x202C 0x0000 PERIPHS_PIN_MUX_1 REG1 0x202D 0x0000 PERIPHS_PIN_MUX_2 REG2 0x202E 0x0000 PERIPHS_PIN_MUX_3 REG3 0x202F 0x0000 PERIPHS_PIN_MUX_4 REG4 0x2030 0x0000 PERIPHS_PIN_MUX_5 REG5 0x2031 0x0000 PERIPHS_PIN_MUX_6 REG6 0x2032 0x0000 PERIPHS_PIN_MUX_7 REG7 0x2033 0x0000 PERIPHS_PIN_MUX_8 REG8 0x2034 0x0000 PERIPHS_PIN_MUX_9 REG9 0x2035 0x0000 - AO_REG 0x0005 0x00004.3 Default FunctionAfter power-on/reset, all GPIOs are working as GPIO until they are set. The default value of each pin multiplexing registers is 0.Di st ri bu tet oS ky n o o n !4.4 Pin Multiplexing4.4.1 GPIO Bank AThe GPIO Bank A is not pre-assigned to any specific function and can be multiplexed to any general purpose functions.4.4.2 GPIO Bank BThe GPIO Bank B can be multiplexed to functions as:LCD output: The parallel video data output to LCD panel. It is used to connect LCD panel data port.Table 3. GPIO Bank B Pin Multiplexing TableBGA Ball Number Package Name LCD output C17 GPIOB_2 LCD_R2 REG0[0] A17 GPIOB_3 LCD_R3 REG0[0] B17 GPIOB_4 LCD_R4 REG0[0] C16 GPIOB_5 LCD_R5 REG0[0] B16 GPIOB_6 LCD_R6 REG0[0] C15 GPIOB_7 LCD_R7 REG0[0] D17 GPIOB_10 LCD_G2 REG0[2] E17 GPIOB_11 LCD_G3 REG0[2] E16 GPIOB_12 LCD_G4 REG0[2] E15 GPIOB_13 LCD_G5 REG0[2] D15 GPIOB_14 LCD_G6 REG0[2] D14 GPIOB_15 LCD_G7 REG0[2] B15 GPIOB_18 LCD_B2 REG0[4] C14GPIOB_19 LCD_B3 REG0[4] B14 GPIOB_20 LCD_B4 REG0[4] A14 GPIOB_21 LCD_B5 REG0[4] C13 GPIOB_22 LCD_B6 REG0[4] A13GPIOB_23LCD_B7 REG0[4]Di st ri bu tet oS ky n o o n !The GPIO Bank C can be multiplexed to functions as: ● SPDIF: SDPIF serial digital audio input and output ● PWM: Pulse width modulation output● LVDS TCON-A: The TCON interface for mini-LVDS LCD panel.● HDMI: The control and configuration interface of HDMI TX including I2C interface, CEC and plug-indetection.Table 4. GPIO Bank C Pin Multiplexing TableBGA Ball Number Package Name SPDIF PWM Mini-LVDS TCONHDMI J19 GPIOC_0 PWM_A REG2[0]H19 GPIOC_3 TCON_1_A REG0[13] H18 GPIOC_4 TCON_2_A REG0[14] T4 GPIOC_7 TCON_5_A REG0[17] R5 GPIOC_8 SPDIF_in REG3[23] TCON_6_A REG0[18] T5 GPIOC_9 SPDIF_out REG3[24]TCON_7_A REG0[19]U5 GPIOC_10HDMI_HPD(5V) REG1[22] U4 GPIOC_11 HDMI_SDA(5V) REG1[23] AA1 GPIOC_12 HDMI_SCL(5V) REG1[24] AA2GPIOC_13HDMI_CEC REG1[25]Di st ri bu tet oS ky n o o n !The GPIO Bank D can be multiplexed to functions as: ● PWM: Pulse width modulation output● VGHL/LED_BL: PWM output to control panel VGHL and backlight ● LVDS TCON-B: The TCON interface for TTL LCD panel.Table 5. GPIO Bank D Pin Multiplexing TableBGA Ball Number Package Name PWM VGHL/ LED_BL Mini-LVDS TCONLCD TCON E14 GPIOD_0 PWM_C REG2[2] LCD_VGHL_PWMREG1[29] B13 GPIOD_1 PWM_D REG2[3]LED_BL_PWM REG1[28]C12 GPIOD_2 TCON_0_B REG0[22] TCON_STH1_B REG1[19] B12 GPIOD_3 TCON_1_B REG0[23] TCON_STV1_B REG1[18] C11GPIOD_4TCON_2_B REG0[24] TCON_OEH_B REG1[17] B11 GPIOD_7TCON_5_B REG0[27] TCON_CPH50_B REG1[11] TCON_CPH1 REG1[14] TCON_CPH2 REG1[13] TCON_CPH3 REG1[12] C10 GPIOD_8 TCON_6_B REG0[28] TCON_VCOM_B REG1[20]B10GPIOD_9PWM_A REG3[26]TCON_7_B REG0[29]4.4.5 GPIO Bank EThe GPIO Bank E can be multiplexed to functions as:● Digital Audio In and output: I2S digital audio input/output.Table 6. GPIO Bank E Pin Multiplexing TableBGA Ball Number Package Name Audio InAudio OutA10 GPIOE_0 I2S_IN_CH01 reg9[11]C9 GPIOE_1 I2S_IN_LR_CLK reg9[10] I2S_OUT_LR_CLKreg9[9] A9 GPIOE_2I2S_OUT_MCLKreg9[7] B9 GPIOE_3 I2S_IN_BCLK reg9[6]I2S_OUT_BCLKreg9[5] C8 GPIOE_4I2S_OUT_CH01reg9[4]D9 GPIOE_10 D8 GPIOE_11Di st ri bu tet oS ky n o o n !The GPIO Bank X can be multiplexed to functions as: ● UART: UART port A and B ● SDIO and SDXC● I2C Master and Slave interface ● ISO7816 smart card interface ● PCM interface● Clock out: The output of AML8726-MXL/MXS PLL clock to external peripheral devices.Table 7. GPIO Bank X Pin Multiplexing TableBGA Ball Number Package Name UART-A/BSDIO-A SDXC-A I2C Master I2C Slave ISO7816PCM Clock outA3 GPIOX_0 SD_D0_A REG8[5] SDXC_D0_A REG5[14] B3 GPIOX_1 SD_D1_A REG8[4] SDXC_D1_A REG5[13] A2 GPIOX_2 SD_D2_A REG8[3] SDXC_D2_A REG5[13] B2 GPIOX_3 SD_D3_A REG8[2]SDXC_D3_A REG5[13]B1 GPIOX_4 SDXC_D4_A REG5[12] PCM_OUT REG3[30] C2 GPIOX_5 SDXC_D5_A REG5[12] PCM_IN REG3[29] C1 GPIOX_6 SDXC_D6_A REG5[12] PCM_FS REG3[28] D3 GPIOX_7 SDXC_D7_A REG5[12] PCM_CLK REG3[27]D2 GPIOX_8 SD_CLK_A REG8[1] SDXC_CLK_A REG5[11] E3 GPIOX_9 SD_CMD_A REG8[0]SDXC_CMD_A REG5[10]E2 GPIOX_10E4 GPIOX_11 F4 GPIOX_12 CLK_OUT3 REG3[21]F5 GPIOX_13 UART_TX_A REG4[13]G5 GPIOX_14 UART_RX_A REG4[12] H5 GPIOX_15 UART_CTS_A REG4[11] H4 GPIOX_16 UART_RTS_A REG4[10]E1 GPIOX_23 UART_TX_B REG4[5] ISO7816_CLK REG4[15] F3 GPIOX_24 UART_RX_B REG4[4]ISO7816_DATA REG4[14]F1 GPIOX_25 I2C_SDA REG5[27] I2C_SDA REG5[25] F2 GPIOX_26 I2C_SCK REG5[26] I2C_SCK REG5[24] G3 GPIOX_27 I2C_SDA REG5[31] I2C_SDA REG5[29] G2 GPIOX_28I2C_SCK REG5[30]I2C_SCK REG5[28]Di st ri bu tet oS ky n o o n !The GPIO Bank Z can be multiplexed to functions as: ● ITU601 input: ITU601/656 video input interface● Clock out: The output of AML8726-MXL/MXS PLL clock to external peripheral devices.Table 8. GPIO Bank Z Pin Multiplexing TableBGA Ball Number Package NameITU601 In Clock OutE8GPIOZ_0FIR reg9[18] IDQ reg9[17]B8 GPIOZ_1 HS reg9[16]C7 GPIOZ_2 VS reg9[15] B7 GPIOZ_3 D0 reg9[14] C6 GPIOZ_4 D1 reg9[14] B6 GPIOZ_5 D2 reg9[14] A6 GPIOZ_6 D3 reg9[14] C5 GPIOZ_7 D4 reg9[14] A5 GPIOZ_8 D5 reg9[14] B5 GPIOZ_9 D6 reg9[14] C4 GPIOZ_10 D7 reg9[14] B4 GPIOZ_11 CLK reg9[13]C3GPIOZ_12CLK_OUT reg9[12]Di st ri bu tet oS ky n o o n !The Bank AO GPIO belongs to a special power domain, which is Always-On (AO), in AML8726-MXL/MXS. The AO power domain cannot be powered off unless disconnect AML8726-MXL/MXS from power supply.The GPIO Bank AO can be multiplexed to functions as: ● JTAG: The debug interface of chip.● Remote: The IR remote control analog signal input● UART: A dedicated UART interface in AO power domain ● UART PMIC: Dedicated UART interface for PMIC● I2C Master and Slave: The dedicated I2C Master and Slave interface in AO power domain ● CLOCK OUT: The output of AML8726-MXL/MXS PLL clock to external peripheral devices. ● WD GPIO:Table 9. GPIO Bank AO Pin Multiplexing TableBGA Ball Number Package Name JTAG RemoteUART UART PMICI2C Master I2C Slave Clock OutWD GPIOU20 GPIOAO_0 JTAG_TDO_SYS JTAG_TDO_MEDIAUART_TX_AO AO_REG[12] U22 GPIOAO_1 JTAG_TDI UART_RX_AO AO_REG[11]U21 GPIOAO_2 JTAG_TMS UART_CTS_AO AO_REG[10] UART_TX_PMIC AO_REG[26] I2C_SCK_AO AO_REG[8] I2C_CLK_SLAVE_AOAO_REG[4] T21 GPIOAO_3 JTAG_TCKUART_RTS_AO AO_REG[9]UART_RX_PMIC AO_REG[25] I2C_SDA_AO AO_REG[7] I2C_SDA_SLAVE_AOAO_REG[3] R20 GPIOAO_4 UART_TX_PMIC AO_REG[24] I2C_SCK_AO AO_REG[6] I2C_SCK_SLAVE_AOAO_REG[2] R21 GPIOAO_5 UART_RX_PMIC AO_REG[23]I2C_SDA_AO AO_REG[5]I2C_SDA_SLAVE_AOAO_REG[1]P20 GPIOAO_6 CLK_OUT2 AO_REG[22]WD_GPIO AO_REG[19]P21 GPIOAO_7REMOTE AO_REG[0]T18GPIOAO_8JTAG_TCKenable=AO_REG[14] disable=AO_REG[13]R18 GPIOAO_9 JTAG_TMS enable=AO_REG[14] disable=AO_REG[13]R19 GPIOAO_10 JTAG_TDIenable=AO_REG[14] disable=AO_REG[13]P19 GPIOAO_11 JTAG_TDO enable=AO_REG[14] disable=AO_REG[13]CLK_OUT AO_REG[21]Di st ri bu tet oS ky n o o n !The Bank BOOT is a dedicated GPIO bank to access bootable devices such as NAND Flash, eMMC and SD card. It can be multiplexed to functions as: ● SDIO-C: The SDIO port C interface ● SDXC-C: The SDXC port C interface ● NAND: The NAND flash interface ● eMMC: The eMMC flash interface ● I2C interface● SPI NOR interfaceTable 10. GPIO Bank BOOT Pin Multiplexing TableBGA Ball NumberPackage NameSDIO-C SDXC-CNAND /eMMC NAND RBI2C SPI NORN20 BOOT_0 SD_D0_C reg6[29] SDXC_D0_C reg4[30] NAND_IO_0 reg2[26] I2C_SDA reg3[31] N22 BOOT_1 SD_D1_C reg6[28] SDXC_D1_C reg4[29] NAND_IO_1 reg2[26] I2C_SCL reg3[31]N21 BOOT_2 SD_D2_C reg6[27] SDXC_D2_C reg4[29] NAND_IO_2 reg2[26] M20 BOOT_3 SD_D3_C reg6[26]SDXC_D3_C reg4[29] NAND_IO_3 reg2[26] M21 BOOT_4 SDXC_D4_C reg4[28] NAND_IO_4 reg2[26] L20 BOOT_5 SDXC_D5_C reg4[28] NAND_IO_5 reg2[26] L21 BOOT_6 SDXC_D6_C reg4[28] NAND_IO_6 reg2[26]K20 BOOT_7 SDXC_D7_C reg4[28]NAND_IO_7 reg2[26]K21 BOOT_8NAND_CE0 (bootable) reg2[25]K22 BOOT_9NAND_CE1 reg2[24]J20 BOOT_10 SD_CMD_C reg6[25] SDXC_CMD_Creg4[27] NAND_CE2 reg2[23]NAND_RB0 reg2[17]J22 BOOT_11 SD_CLK_C reg6[24]SDXC_CLK_C (bootable) reg4[26]NAND_CE3 reg2[22] NAND_RB1 reg2[16]J21 BOOT_12 NAND_ALE reg2[21] SPI_NOR_D_A enable=reg5[1] H20 BOOT_13 NAND_CLE reg2[20]SPI_NOR_Q_A enable=reg5[3] H21 BOOT_14 NAND_WEn_CLKreg2[19] SPI_NOR_C_A enable=reg5[2]G20 BOOT_15 NAND_REn_WRreg2[18]K18 BOOT_16 NAND_DQS reg2[27]J18BOOT_17SPI_NOR_CS_n_A enable=reg5[0]Di st ri bu tet oS ky n o o n !。

产品介绍：
IR-CUT双滤光片切换器由一个红外截止滤光片和一个全光谱光学玻璃构成，当白天的光线充分时由专业过滤红外线的镀膜玻璃过滤自然光线中的红外线，它的波长为650nm，让画面色彩纯美更柔和、达到人眼视觉色彩一致。

当夜间光线不足时，它的波长为850nm，使红外截止滤光片自动切换，全光谱光学玻璃开始工作，充分利用到所有光线，从而大大提高了低照性能。

IR-CUT双滤光片切换器，真正解决了CMOS摄像机偏色、失焦的问题，使影像白天色彩逼真、自然，夜晚红外夜视更清晰通透。

真正做到了日夜兼顾。

IR尺寸图：
功能特性：
电磁式IRCUT双滤光切换器！
适用于百万高清像素，网络摄像机，CMOS板等！
内置桐柱，使用上方便快捷！
采用肖特玻璃，画质效果更好！
质量100检测，品质有保障，切换次数在6万以上
耐高温、低温材质，杜绝易裂易爆现象！
IRCUT-FX-CS切换器规格书
IRCUT-FX-M12切换器规格书。

FLEXO® F6Flexible, Semi-RigidWrappable Split Braided TubeF6’s unique split, semi-rigid braided constructionmakes it the ideal solution for situations whereease of installation is of primary importance.The lateral split allows the tube to open upto accommodate a wide variety of bundlingrequirements, and the semi-rigid braidconfiguration simply closes around the entireinstallation without the need for any additionalfasteners (velcro, tape, etc.)edge overlap (at nominal diameter) allows coveragearound inline plugs, connectors and splices.F6 will bend to a tight radius without distortingor splitting open and, unlike full rigid tubing, willnot impair or affect the flexibility of harnesses.Colors Available:Black (BK), Orange (OR), Platinum Gray (PG)& Clear/White (CW).E asy, Cost And LaborEffective InstallationM ore Flexible Than SplitConvoluted Or Spiral Wrap25% Edge OverlapS oft And Quiet In HighVibration UsesC ut And Abrasion ResistantC hemically InertH aloge FreePolyethylene TerepthalateMaterialF6NGrade.008” - .015”Monofilament DiameterTF001F6-WDDrawing NumberHot KnifeCut Cleanly800.323.5140 • 973.300.9242 • fax: 973.300.940929 Brookfield Dr • Sparta, NJ 07871Braided Sleeving ProductsColors Available:4= BK, OR, PG, CW.Nominal DiameterThe large overlap allows easyinstallation over splices andincline connectors withoutexposing wires and cables.NominalSizePart#WallThicknessMonofilamentDiameterBulkBoxBoxABoxBAvailableColorsLbs/100’1/8”F6N0.13.024”.008”10,000’400’100’40.201/4”F6N0.25.025”.010”3,000’200’100’40.603/8”F6N0.38.025”.010”1,000’150’75’4 1.201/2”F6N0.50.025”.010”1,200’150’75’4 1.403/4”F6N0.75.025”.010”500’100’50’4 1.601”F6N1.00.038”.015”400’100’50’4 2.001 1/4”F6N1.25.038”.015”250’75’25’4 2.401 1/2”F6N1.50.038”.015”200’75’25’4 2.702”F6N2.00.038”.015”150’50’25’4 3.60Put-Ups芯天下--/FLEXO® F6Abrasion ResistanceMediumAbrasion Test MachineTaber 5150Abrasion Test WheelCalibrase H-18Abrasion Test Load 500gRoom Temperature 80°FHumidity74%Some Scuffing Visible500 Test CyclesSignificant Wear Is Visible With Several Braid Filaments Broken1,200 Test CyclesMaterial Destroyed 1,950 Test CyclesPre-Test Weight5,365.1 mgPost-Test Weight 4,850 mgTest End Loss Of Mass Point Of Destruction515.1 mg1=No Effect 4=More Affected 2=Little Effect 5=Severely Affected 3=AffectedAromatic Solvents ______________2Aliphatic Solvents ______________1Chlorinated Solvents ____________3Weak Bases __________________1Salts _________________________1Strong Bases___________________2Salt Water 0-S-1926 ____________1Hydraulic Fluid MIL-H-5606 _______1Lube Oil MIL-L-7808 ____________1De-Icing Fluid MIL-A-8243 ________1Strong Acids __________________3Strong Oxidants ________________2Esters/Keytones _______________1UV Light ______________________1Petroleum ____________________1Fungus ASTM G-21 _____________1Halogen Free ________________Yes RoHS ______________________Yes SVHC _____________________NoneRating ___________UL94VOMonofilament Diameter__.008-.015 ASTM D-204Flammability Rating________UL94Recommended Cutting___Hot Knife Colors______________________4 Wall Thickness_________.024-.038Tensile Strength (Yarn)_______6-10ASTM D-2256 LbsSpecific Gravity ASTM D-792__1.38Moisture Absorption_________.1-.2 % ASTM D-570Hard Vacuum Data ASTM E-595TML_______________________19CVCM_____________________.00WVR______________________.16Smoke D-Max _______________56 ASTM E-662Outgassing________________Med Oxygen Index________________21ASTM D-2863© 2011 Techflex, Inc. - Any unauthorized reproduction, in whole or part, in any medium whatsoever, without the express written permission of Techflex, Inc. is strictly forbidden.T echflex product names and logos are registered trademarks of T echflex, Inc., unless otherwise attributed. The contents and illustrations contained herein are believed to be reliable. T echflex makes no warranties as to their accuracy or completeness and disclaims any liability in connection with their use. T echflex’s only obligations are those in standard terms ofsale for these products and T echflex will not be liable for any consequential or other damages arising due to misuse of these products or typographical errors or omissions.Users should make their own evaluation to determine the suitability of these products for their unique and specific applications.09-11Melt Point ASTM D-2117482°F (250°C)Maximum ContinuousMil-I-23053257°F (125°C)Minimum Continuous-94°F (-70°C)芯天下--/。

激光二极管43■激光二极管◆主要阵容 ＜可见光激光二极管＞特点廉价型紧凑型标准型宽广的工作温度范围封装尺寸　④ t1.8 mm Frame② φ3.8 mm Can① φ5.6 mm Can横向振荡模式单一模式工作温度 (°C) –10～+60–40～+85波长R: 638 nmGH1631AA8C 100 mW (CW)GH0631IA5G 150 mW (CW)GH0631IA2GC 180 mW (CW)★GH0632BA2G 200 mW (CW)G: 520 nm –☆GH05280E5G 80 mW (CW)☆GH05280E2K 80 mW (CW)– *1B: 450 nm–☆GH04580A5G 80 mW (CW)　GH04580A2G 80 mW (CW)– *1　*1 计划今后将提供工作温度范围更广的产品系列。

＜红外发光二极管＞特点高光束级高输出脉冲30W 级脉冲90W 级封装尺寸① φ5.6 mm Can横向振荡模式单一模式复合模式工作温度 (°C) –10 ～ +70–40 ～ +85波长IR: 830 nm ★GH0832FA2G250 mW (CW)–––IR: 850 nm–★GH0852WA2G700 mW (CW)––IR: 905 nm ––★GH09W30A2G30 W (Pulse)★GH09W90A2G90 W (Pulse)IR: 940 nm★GH0942FA2G250 mW (CW)★GH0942WA2G700 mW (CW)––＜红外护眼激光二极管 *2＞特点可靠性高，护眼封装尺寸　⑥ φ5.6 mm eye-safe横向振荡模式复合模式工作温度 (°C) –10 ～ +70波长IR: 850 nm☆GH4854B3TG 410 mW(CW)IR: 940 nm★GH4944D3TG 430 mW (CW)*2　对眼睛更加安全的激光＜凡例＞　GHxxxxxxxx xx mW (CW)上段：型号名称下段：25°C 时的额定光输出值44◆规格＜激光二极管＞(Tc = 25°C)封装尺寸型号波长(带域)λp(nm)绝对最大额定值*1特性内置监视器PD端子连接用途Po(mW)Top(°C)Po(mW)Ith(mA)Iop(mA)Vop(V)ηd(mW/mA)λp(nm)θ// *2(°)θ⊥*2(°)①φ5.6 mm Can☆GH0401FA2K405155–10 ～ +75150401305 1.7405919○4传感器等GH04W10A2GC3500 ～ +50300140325 4.5 1.840614*341*3–9GH04580A2G45085–10 ～ +70802284 5.1 1.34501024–8显示器等☆GH05030D2L50535–10 ～ +6030307560.65505823–12☆GH05130G2K51535–10 ～ +60303085 6.50.555157.522○4☆GH05280E2K52085–10 ～ +608065180 6.50.7520723○4☆GH0521DA2G135130100300 6.80.6522.5–8☆GH06330A2G63830–10 ～ +60303050 2.3 1.4638716–8GH0631IA2GC185–20 ～ +6018070215 2.55 1.158139★GH0632BA2G210–40 ～ +852******* 2.65–15GH0637AA2G700–10 ～ +40700110810 2.461635★GH0652CA2G650220–40 ～ +9020055220 2.6–650812.5–9GH06P25A1C660100–10 ～ +709540122 2.4 1.1661–––3GH0832BA1K830210–10 ～ +7020035215 2.1 1.1830918○4传感器等★GH0832FA2G26025045255 2.2 1.15815–8★GH0852WA2G850700–10 ～ +70700275975 1.8185017458★GH09W30A2G905Pulse40W–40 ～ +85Pulse30W70030A11 1.149051520–8激光雷达等★GH09W90A2GPulse120WPulse90W(tbd)(tbd)(tbd)(tbd)(tbd)★GH0942FA2G940260–10 ～ +70250(tbd)(tbd)(tbd)(tbd)940(tbd)(tbd)–8传感器等★GH0942WA2G700700315800 1.811035②φ3.8 mm Can☆GH04580A5G45085–10 ～ +70802284 5.1 1.34501024–8显示器等☆GH05280E5G52085–10 ～ +608065180 6.50.7520723–8☆GH0521DA5G135–10 ～ +50130100300 6.80.6522.5–8GH0631CA5G638125–10 ～ +60120701952.5–638915–8GH0631IA5G185******** 1.157.5③φ3.3 mm CanGH06510F4A66010–10 ～ +7071726 2.20.856601328○1传感器等GH07P28F4C785150–10 ～ +7010035135 2.41784816–3④t1.8 mm FrameGH1631AA8C638100–10 ～ +6010050130 2.45 1.2638815–6显示器等GH16P32B8C660100–10 ～ +709042120 2.3 1.166619.315–6⑤t1.2 mm Frame GH16320AUL63820–10 ～ +40201850 2.50.6635836–11显示器等＜护眼的激光二极管*4＞(Tc = 25°C)封装尺寸型号波长(带域)λp(nm)绝对最大额定值*1特性内置监视器PD端子连接用途Iop(A)Top (°C) Iop(mA)Ith(mA)φe(mW)Vop(V)ηd(mW/mA)λp(nm)θ// *2(°)θ⊥*2(°)⑥φ5.6 mm eye-safe☆GH4854B3TG8501–10 ～ +7080025041020.75850100100–8传感器等★GH4944D3TG9401–10 ～ +70800160430 1.750.679408585*1　绝对最大额定值是在任何情况下都不能超过的极限，不管是在测试还是实际使用中。

Part Part Status Package VBRDSS (V)VGs Max (V)CircuitIRFH8334PBF-1Active and Preferred PQFN 5 x 6 B/E3020DiscreteIRF3717PBF-1Active and Preferred SO-82020Discrete IRLB8314Active and Preferred TO-220AB3020Discrete IRLML0030PBF-1Active Micro 3/ SOT-233020Discrete IRFR8314Active and Preferred D-Pak3020DiscreteIRF7457PBF-1Active SO-82020Discrete IRLMS1503PBF-1Active TSOP-6 (Micro 6)3020DiscreteIRF8788PBF-1Active SO-83020DiscreteIRF7809AVPBF-1Active SO-83012DiscreteIRF8707PBF-1Active SO-83020DiscreteIRF8113PBF-1Active SO-83020Discrete IRFH3707PBF-1Active and Preferred PQFN 3 x 33020IRF7811AVPBF-1Active SO-83020DiscreteIRF7807VD1PBF-1Active SO-83020with Schottky IRFH4226Active and Preferred PQFN 5 x 6 B/E2520Discrete IRFH4209D Active PQFN 5 x 6 B/E2520Discrete IRLS3813Active and Preferred D2-Pak3020DiscreteIRL6283M Active and Preferred DirectFET MD2012Discrete IRFHM4231Active and Preferred PQFN 3.3 x 3.32520DiscreteIRF8736PBF-1Active SO-83020Discrete IRLML2502TRPBF-1Active Micro 3/ SOT-232012Discrete IRLML2803TRPBF-1Active Micro 3/ SOT-233020Discrete IRLML2402TRPBF-1Active Micro 3/ SOT-232012DiscreteIRF7821PBF-1Active SO-83020DiscreteIRF8252PBF-1Active SO-82520DiscreteIRF8714PBF-1Active SO-83020DiscreteIRF7807VPBF-1Active SO-83020DiscreteIRF7805ZPBF-1Active SO-83020DiscreteIRF7807PBF-1Active SO-83012DiscreteIRF7832PBF-1Active SO-83020DiscreteIRF7805PBF-1Active SO-83012DiscreteIRF7455PBF-1Active SO-83012DiscreteIRF7413PBF-1Active SO-83020DiscreteIRF7456PBF-1Active SO-82012DiscreteIRF7401PBF-1Active SO-82012DiscreteIRF8721PBF-1Active SO-83020Discrete IRFH8303Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH8201Active and Preferred PQFN 5 x 6 B/E2520Discrete IRFHM8235Active and Preferred PQFN 3.3 x 3.32520Discrete IRFHM8228Active and Preferred PQFN 3.3 x 3.32520Discrete IRFHM8342Active and Preferred PQFN 3.3 x 3.33020Discrete IRFHM8337Active and Preferred PQFN 3.3 x 3.33020Discrete IRFHM8330Active and Preferred PQFN 3.3 x 3.33020Discrete IRFHM4226Active and Preferred PQFN 3.3 x 3.32520Discrete IRFHM8334Active and Preferred PQFN 3.3 x 3.33020Discrete IRFHM4234Active and Preferred PQFN 3.3 x 3.32520Discrete IRFH4213D Active and Preferred PQFN 5 x 6 B/E2520with Schottky IRFH4210D Active and Preferred PQFN 5 x 6 B/E2520with Schottky IRF1503S Active D2-Pak3020DiscreteIRF2903ZS Active and Preferred D2-Pak3020DiscreteIRFH4213Active and Preferred PQFN 5 x 6 B/E2520Discrete IRFH4210Active and Preferred PQFN 5 x 6 B/E2520DiscreteIRF3717Active and Preferred SO-82020Discrete IRFH4234Active and Preferred PQFN 5 x 6 B/E2520Discrete IRFHM8326Active and Preferred PQFN 3.3 x 3.33020DiscreteIRF8301M Active and Preferred DirectFET MT3020DiscreteIRL7833S Active and Preferred D2-Pak3020DiscreteIRL3713S Active and Preferred D2-Pak3020Discrete IRFH4201Active and Preferred PQFN 5 x 6 B/E2520Discrete IRFHM8329Active and Preferred PQFN 3.3 x 3.33020Discrete IRFH8307Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH8202Active and Preferred PQFN 5 x 6 B/E2520Discrete IRFH8316Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH8321Active and Preferred PQFN 5 x 6 B/E3020DiscreteIRF6892S Active and Preferred DirectFET S3C2516DiscreteIRF6893M Active and Preferred DirectFET MX2516with Schottky IRLH6224Active and Preferred PQFN 5 x 6 B/E2012DiscreteIRF7601Active Micro 82012Discrete IRFH8311Active and Preferred PQFN 5 x 6 B/E3020Discrete IRLTS6342Active and Preferred TSOP-6 (Micro 6)3012Discrete IRFTS8342Active and Preferred TSOP-6 (Micro 6)3020DiscreteIRF6810S Active and Preferred DirectFET S12516DiscreteIRF6898M Active and Preferred DirectFET MX2516with Schottky IRF8327S Active and Preferred DirectFET SQ3020DiscreteIRF8304M Active and Preferred DirectFET MX3020DiscreteIRF8308M Active and Preferred DirectFET MX3020DiscreteIRF8302M Active and Preferred DirectFET MX3020with Schottky IRF8306M Active and Preferred DirectFET MX3020with Schottky IRLU7843Active I-Pak3020Discrete IRLU2703Active I-Pak3016Discrete IRFU3707Z Active I-Pak3020Discrete IRFU3709Z Active I-Pak3020Discrete IRLU3802Active I-Pak1212Discrete IRLU3103Active I-Pak3016Discrete IRLU8743Active and Preferred I-Pak3020Discrete IRFH8330Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH8324Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH8318Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH8325Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH8337Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH8334Active and Preferred PQFN 5 x 6 B/E3020DiscreteIRF6894M Active and Preferred DirectFET MX2516with Schottky IRF6811S Active and Preferred DirectFET SQ2516DiscreteIRL6342Active and Preferred SO-83012Discrete IRLR6225Active and Preferred D-Pak2012Discrete IRLHS6342Active and Preferred PQFN 2 x 23012Discrete IRFHS8342Active and Preferred PQFN 2 x 23020Discrete IRFML8244Active and Preferred Micro 3/ SOT-232520Discrete IRFHS8242Active and Preferred PQFN 2 x 22520Discrete IRLML6346Active and Preferred Micro 3/ SOT-233012Discrete IRLML6344Active and Preferred Micro 3/ SOT-233012DiscreteIRLR3717Active D-Pak2020Discrete IRLHS6242Active and Preferred PQFN 2 x 22012DiscreteIRF6728M Active DirectFET MX3020with Schottky IRLHM620Active and Preferred PQFN 3.3 x 3.32012Discrete IRLHM630Active and Preferred PQFN 3.3 x 3.33012Discrete IRFHM830D Active and Preferred PQFN 3.3 x 3.33020with Schottky IRFHM830Active and Preferred PQFN 3.3 x 3.33020Discrete IRFHM831Active and Preferred PQFN 3.3 x 3.33020Discrete IRLML6246Active and Preferred Micro 3/ SOT-232012Discrete IRLML6244Active and Preferred Micro 3/ SOT-232012DiscreteIRF6201Active and Preferred SO-82012Discrete IRFH6200Active and Preferred PQFN 5 x 6 B/E2012Discrete IRFH5250D Active and Preferred PQFN 5 x 6 B/E2520with Schottky IRFH5304Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH5302D Active and Preferred PQFN 5 x 6 B/E3020with Schottky IRFH5302Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH5301Active and Preferred PQFN 5 x 6 B/E3020DiscreteIRF6798M Active and Preferred DirectFET MX2520with Schottky IRF6711S Active and Preferred DirectFET SQ2520Discrete IRLML2030Active and Preferred Micro 3/ SOT-233020Discrete IRLML0030Active and Preferred Micro 3/ SOT-233020Discrete IRFH5306Active and Preferred PQFN 5 x 6 B/E3020Discrete IRFH5250Active and Preferred PQFN 5 x 6 B/E2520Discrete IRFH5300Active PQFN 5 x 6 B/E3020Discrete IRLB3813Active and Preferred TO-220AB3020DiscreteIRF6718L2Active and Preferred DirectFET L62520Discrete IRLB8743Active and Preferred TO-220AB3020Discrete IRLB8748Active and Preferred TO-220AB3020Discrete IRLB8721Active and Preferred TO-220AB3020Discrete IRFH7936Active PQFN 5 x 6 A3020Discrete IRFH3702Active PQFN 3 x 33020Discrete IRFH7932Active PQFN 5 x 6 A3020Discrete IRFH3707Active PQFN 3 x 33020Discrete IRFH7914Active PQFN 5 x 6 A3020Discrete IRFH7934Active PQFN 5 x 6 A3020DiscreteIRF6729M Active DirectFET MX3020with Schottky IRF8734Active and Preferred SO-83020Discrete IRLR8256Active and Preferred D-Pak2520Discrete IRLR8726Active and Preferred D-Pak3020Discrete IRLR8729Active and Preferred D-Pak3020Discrete IRLR8259Active and Preferred D-Pak2520DiscreteIRF1324Active and Preferred TO-220AB2420DiscreteIRF6717M Active and Preferred DirectFET MX2520DiscreteIRF8252Active and Preferred SO-82520DiscreteIRF8788Active and Preferred SO-83020DiscreteIRF1324S-7P Active and Preferred D2-Pak 7-Lead2420DiscreteIRF6795M Active and Preferred DirectFET MX2520with Schottky IRF6797M Active and Preferred DirectFET MX2520with Schottky IRF6724M Active DirectFET MX3020DiscreteIRF6710S2Active and Preferred DirectFET S12520DiscreteIRF6633A Active DirectFET MU2020DiscreteIRF7607Active Micro 82012DiscreteIRF6721S Active DirectFET SQ3020DiscreteIRF3704ZS Active D2-Pak2020DiscreteIRF8714Active and Preferred SO-83020DiscreteIRF6714M Active and Preferred DirectFET MX2520DiscreteIRF8721Active and Preferred SO-83020Discrete IRLR8743Active and Preferred D-Pak3020Discrete IRLR8721Active and Preferred D-Pak3020DiscreteIRF8736Active and Preferred SO-83020DiscreteIRF8707Active and Preferred SO-83020DiscreteIRF6713S Active and Preferred DirectFET SQ2520DiscreteIRF6715M Active and Preferred DirectFET MX2520DiscreteIRF6726M Active DirectFET MT3020DiscreteIRF6727M Active and Preferred DirectFET MX3020with Schottky IRF6725M Active DirectFET MX3020DiscreteIRF7862Active and Preferred SO-83020DiscreteIRF6712S Active and Preferred DirectFET SQ2520DiscreteIRF6716M Active and Preferred DirectFET MX2520DiscreteIRF2903Z Active and Preferred TO-220AB3020DiscreteIRF7413Z Active SO-83020DiscreteIRF6622Active DirectFET SQ2520DiscreteIRF6629Active DirectFET MX2520DiscreteIRF6618Active DirectFET MT3020DiscreteIRF6638Active DirectFET MX3020DiscreteIRF6628Active DirectFET MX2520DiscreteIRF6678Active DirectFET MX3020DiscreteIRF6612Active DirectFET MX3020DiscreteIRF6611Active DirectFET MX3020DiscreteIRF6636Active DirectFET ST2020DiscreteIRF6631Active DirectFET SQ3020DiscreteIRF6621Active DirectFET SQ3020DiscreteIRF6619Active DirectFET MX2020DiscreteIRF6633Active DirectFET MP2020DiscreteIRF6635Active DirectFET MX3020DiscreteIRF6617Active DirectFET ST3020DiscreteIRF6609Active DirectFET MT2020DiscreteIRF6620Active DirectFET MX2020DiscreteIRF6637Active DirectFET MP3020DiscreteIRF6623Active DirectFET ST2020Discrete IRFR3709ZC Active D-Pak3020Discrete IRFR3709Z Active D-Pak3020DiscreteIRF7807Z Active SO-83020DiscreteIRF7834Active SO-83020DiscreteIRF8113Active SO-83020DiscreteIRF7805Z Active SO-83020Discrete IRLMS1503Active TSOP-6 (Micro 6)3020Discrete IRLMS2002Active TSOP-6 (Micro 6)2012Discrete IRLMS1902Active TSOP-6 (Micro 6)2012DiscreteIRL3803VS Active D2-Pak3016DiscreteIRL3803V Active TO-220AB3016DiscreteIRF7832Active SO-83020DiscreteIRF7456Active SO-82012DiscreteIRF3709ZS Active D2-Pak3020Discrete IRLR8103V Active D-Pak3020DiscreteIRF7811AV Active SO-83020DiscreteIRL2203NS Active D2-Pak3016DiscreteIRL3803S Active D2-Pak3016DiscreteIRF7807VD1Active SO-83020with Schottky IRF7463Active SO-83012Discrete IRLL3303Active SOT-2233016DiscreteIRF3709S Active D2-Pak3020Discrete IRLR2703Active D-Pak3016DiscreteIRF7809AV Active SO-83012DiscreteIRF7807D1Active SO-83012with Schottky IRF7807Active SO-83012Discrete IRLR3103Active and Preferred D-Pak3016DiscreteIRF7455Active SO-83012DiscreteIRL3103S Active D2-Pak3016DiscreteSI4410DY Active SO-83020DiscreteIRF7402Active SO-82012DiscreteIRF7831Active SO-83012DiscreteIRF3709ZCS Active D2-Pak3020Discrete IRFR3708Active D-Pak3012Discrete IRLL2703Active SOT-2233016DiscreteIRF7401Active SO-82012DiscreteIRF7805Active SO-83012Discrete IRLR7821Active D-Pak3020DiscreteIRF9410Active SO-83020DiscreteIRF7807V Active SO-83020DiscreteIRF7458Active SO-83030DiscreteIRF7457Active SO-82020DiscreteSI4420DY Active SO-83020Discrete IRFR3303Active D-Pak3020Discrete IRLR3802Active D-Pak1212DiscreteIRF7403Active SO-83020DiscreteIRF7821Active SO-83020DiscreteIRF7413Active SO-83020Discrete IRFR3707Z Active D-Pak3020Discrete IRLR7807Z Active and Preferred D-Pak3020Discrete IRFR3704Z Active D-Pak2020Discrete IRLR7843Active D-Pak3020DiscreteIRF7807A Active SO-83012DiscreteIRL3713Active and Preferred TO-220AB3020DiscreteIRL8113Active and Preferred TO-220AB3020DiscreteIRL8113S Active and Preferred D2-Pak3020Discrete IRLML2402Active Micro 3/ SOT-232012Discrete IRLML2502Active Micro 3/ SOT-232012Discrete IRFP3703Active TO-247AC3020Discrete IRLML2803Active Micro 3/ SOT-233020DiscreteIRF3709Active TO-220AB3020DiscreteIRL7833Active TO-220AB3020DiscreteIRF3709Z Active TO-220AB3020DiscreteIRF1503Active TO-220AB3020Discrete IRL2703Active TO-220AB3016Discrete IRF3708Active TO-220AB3012Discrete IRF3707ZS Active D2-Pak3020Discrete IRLR7833Active D-Pak3020Discrete IRF3704ZCS Active D2-Pak2020Discrete IRLR3715Z Active D-Pak2020Discrete IRF7201Active SO-83020Discrete IRL3803Active TO-220AB3016Discrete IRL3103Active TO-220AB3016Discrete IRF3703Active TO-220AB3020Discrete IRL2203N Active TO-220AB3016DiscreteRDS(on) Max 10V (mOhms)Qg Typ (nC)ID @ TC = 25C (A)Power Dissipation @ TC = 25C (W) 91544304.4222.44017112527.0 2.62.2361271257.028100.0 6.42.8444111.9 6.25.62412.4 5.41725.09.52.416110461.1742601251.9555.02471950.75105.0211633.49.772294.817.08.0250.0 3.32.69.19.32.735.08.78.19.56.818.012.04.034.022.07.537.011.052.06.541.032.08.58.31.1119.02801560.9556.03241567.77.750305.29.0653416.010.0282012.4 5.435256.69.355332.216.0105399.07.143284.48.263281.3525.0100961.137.02661253.3130.01902002.4160.02602901.3526.010089 1.136.0100104 4.422.04.68.26027 4.720.07037 1.551.019289 3.832.0150140 3.075.0200200 0.9546.0326156 6.113.05733 1.350.01561.0552.02.9530.012059 4.919.48354 1.717.012542 1.625.01686986.01055214.02.130.01699611.019.0 4.85.27.420 1.135.021378 7.39.26042 2.228.0170100 2.528.0150891.835.01901042.525.0140753.334113140 45101438 9.59.63950 6.5176179276088 1933.32969 3.139113135 6.69.35635 4.114.09054 3.119.012059 5.015.08254 12.8 4.73527 9.07.14430 1.326.016054 3.711.0743211.048.01006311.01916.08.71924.0 5.413.0 4.3212.96.84.221.01208914.0229.6 2.528.01407552.0403741.04037 4.313.04037 3.815.04037 7.87.347273.58.9130.0155.0100250 1.439.04.516.02.526.02.129.0100100 1.8537.0100110 1.350.0197783.813.08442 100.0 1.027.0 2.68.17.84526 1.1552.01.450.01.9557.0260230 0.7064.0270833.236.01501404.815.09275 8.77.66265 4.817.0767.19.6423.334.010412.4 5.4298.78.3353.520.0761.842.01901043.520.05.710.08163 5.815.08675 8.910.05855 8.76.85748 1.5160.03533001.2546.0220962.735.02.844.01.0180.0429300 1.835.0160751.445.0210892.533.015089 5.98.83715 5.611.0694222.07.311.060427.98.767578.78.12.129.016689 8.58.33.139.0160135 8.48.565654.817.011.9 6.23.021.09542 1.640.018078 1.751.0180891.749.0180892.236.01701003.330.04.913.0361.639.0782.4160.0260290 10.09.56.311.034 2.134.0100 2.246.089 2.930.089 2.531.0962.243.0893.330.089 2.637.0894.518.042 7.812.042 9.111.742 2.238.0895.611.089 1.847.089 8.111.042 2.046.089 2.728.0897.711.0895.711.0426.517.08679 6.517.08679 13.87.24.529.06.024.06.818.0100.0 6.415.0 2.04.75.550.7140200 5.550.7140200 4.034.06.541.06.317.08779 9.027.0898917.07.040.0116170 6.093.31402009.58.034.031.034.09.027.090120 45.010.0223841.012.019.033.34669 7.537.012.022.06411013.530.014.03.640.06.317.08779 12.524.06187 45.09.332.022.010.010.06575 30.018.09.59.039.07.028.09.052.031.019.3335727.08488 22.038.09.19.311.044.09.59.65650 13.87.04340 8.49.36048 3.334.016114012.03.075.0200200 6.023.0105110 6.023.01051102.68.02.8209.0210230 250.03.39.027.090120 3.832.0150140 6.317.087793.3130.0240330 40.010.02445 12.024.06287 9.59.75957 4.538.0140140 7.98.76757 11.07.24940 30.019.07.06.093.3120150 12.022.05683 2.8209.02102307.040.0100130Rth(JC) (K/W)Qual Level MSL Package Class4.1Industrial1Surface Mount without Leads 50 (JA)Industrial1Surface Mount with Leads1.2Industrial Thru-Hole100 (JA)Industrial1Surface Mount with Leads1.2Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads75 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads7.5Industrial1Surface Mount without Leads 50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads2.7Industrial1Surface Mount without Leads1Industrial1Surface Mount without Leads0.64Industrial1Surface Mount with Leads1.97Industrial1Surface Mount Can - DirectFET 4.3Industrial1Surface Mount without Leads 50 (JA)Industrial1Surface Mount with Leads75 (JA)Industrial1Surface Mount with Leads230 (JA)Industrial1Surface Mount with Leads230 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads50 (JA)Industrial1Surface Mount with Leads0.80Industrial1Surface Mount without Leads 0.80Industrial1Surface Mount without Leads 4.1Industrial1Surface Mount without Leads 3.7Industrial1Surface Mount without Leads 6.2Industrial1Surface Mount without Leads 5.0Industrial1Surface Mount without Leads 3.8Consumer1Surface Mount without Leads3.2Industrial1Surface Mount without Leads4.5Consumer1Surface Mount without Leads 4.4Industrial1Surface Mount without Leads 1.3Industrial1Surface Mount without Leads 1.00Industrial1Surface Mount without Leads 0.75Industrial1Surface Mount with Leads0.51Industrial1Surface Mount with Leads1.4Industrial1Surface Mount without Leads 1.2Industrial1Surface Mount without Leads 50 (JA)Consumer1Surface Mount with Leads4.6Industrial1Surface Mount without Leads 3.4Consumer1Surface Mount without Leads 1.4Industrial1Surface Mount Can - DirectFET 1.04Industrial1Surface Mount with Leads0.45Industrial1Surface Mount with Leads0.80Industrial1Surface Mount without Leads 3.8Consumer1Surface Mount without Leads 0.80Industrial1Surface Mount without Leads0.80Industrial1Surface Mount without Leads1.7Consumer1Surface Mount without Leads2.3Consumer1Surface Mount without Leads3.0Consumer1Surface Mount Can - DirectFET1.8Consumer1Surface Mount Can - DirectFET2.4Industrial1Surface Mount without Leads 70 (JA)Consumer1Surface Mount with Leads1.3Industrial1Surface Mount without Leads 62.5 (JA)Consumer1Surface Mount with Leads 62.5 (JA)Consumer1Surface Mount with Leads6.3Consumer1Surface Mount Can - DirectFET 1.6Consumer1Surface Mount Can - DirectFET 3.0Consumer1Surface Mount Can - DirectFET 1.2Consumer1Surface Mount Can - DirectFET 1.4Consumer1Surface Mount Can - DirectFET 1.2Consumer1Surface Mount Can - DirectFET 1.66Consumer1Surface Mount Can - DirectFET 1.05Industrial Thru-Hole3.3Industrial Thru-Hole3Industrial Thru-Hole1.9Industrial Thru-Hole1.7Industrial Thru-Hole1.8Industrial Thru-Hole1.11Industrial Thru-Hole3.6Consumer1Surface Mount without Leads 2.3Consumer1Surface Mount without Leads1.7Consumer1Surface Mount without Leads2.3Consumer1Surface Mount without Leads 4.7Consumer1Surface Mount without Leads 4.1Consumer1Surface Mount without Leads2.3Consumer1Surface Mount Can - DirectFET3.9Consumer1Surface Mount Can - DirectFET 50 (JA)Consumer1Surface Mount with Leads2.0Industrial1Surface Mount with Leads13Industrial1Surface Mount without Leads 13Industrial1Surface Mount without Leads 100 (JA)Consumer1Surface Mount with Leads13Industrial1Surface Mount without Leads 100 (JA)Consumer1Surface Mount with Leads100 (JA)Consumer1Surface Mount with Leads1.69Industrial1Surface Mount with Leads13Industrial1Surface Mount without Leads 1.66Consumer1Surface Mount Can - DirectFET 3.4Industrial1Surface Mount without Leads 3.4Industrial1Surface Mount without Leads 3.4Industrial1Surface Mount without Leads3.4Industrial1Surface Mount without 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Tel (718) 956-8900•Fax (718) 956-9040(800) 221-5510•kec@31-07 20th Road –Astoria,NY 11105-2017RoHS COMPLIANT ~ISO 9001 CERTIFIED®5mm SPACINGCAT.A CURRENTNO.POSITIONS DIM.RATING87252.394 (10.0)10 Amps87263.591 (15.0)3.5mm SPACINGCAT.A CURRENTNO.POSITIONS DIM.RATING87222.276(7.0)6 Amps87233.413(10.5)use.They may be interlocked to achieve the required number of positions.The header pins,for both the 6 and 10 Amp models are positions required and insert into PC board.The modular terminal block can be plugged into the header strip at anytime.•Space saving low profile design •Easy access horizontal wire entry•Convenient screw head access on top of terminal block •Headers mount easily in pre-drilled or stamped holes •Wire guards help prevent damage to conductors•Accepts #22-16 AWG wire•Because of accumulating tolerances,werecommend a maximum of 24 positions per row •Header strips and terminal blocks sold separatelyMATERIAL:Contact: Brass,Tin Plate Header Pins:Brass,Tin PlateHousing:Blue PBT,UL Rated 94V-0Screw:Steel,Zinc Plate & Clear Chromate (captivated)ELECTRICAL:Dielectric Strength:2500VInsulation Breakdown:1500V AC/min .Rated voltage:250V.138 [3.5].268 [6.8].375 [9.5].024[0.61]A.069[1.75].394[10.0].358 [9.1].531 [13.5].197 [5.0].098 [2.5]A.436[11.1].028 [0.71].148[3.8].051 [1.30].039 [0.99].138 [3.5].073[1.9].473[12.0].197 [5.0].148[3.8].502[12.8].078[2.0].051 [1.30]CAT.NO.8727CAT.NO.8724Recommended Mtg.Hole Size: .047(1.19)Pin Header Strips (24 pins per strip)Pin Header Strips (24 pins per strip)Recommended Mtg.Hole Size:.059 (1.50)SPECIFICATIONSHORIZONTAL ENTRYHORIZONTAL ENTRYMECHANICAL:Operating Temp:22°F to 248°F (-30°C to 120°C)Peak Temp:+393°F (+200°C)•Use header strip to connect to PCB•Use header strip to connect to PCBNOTES872387228724872687258727分销商库存信息:KEYSTONE-ELECTRONICS872587228726 872387248727。

mos管8726参数
MOS管8726是一种金属氧化物半导体场效应管（MOSFET），常用于功率放大、开关和调节电路中。

以下是关于MOS管8726的一些参数的解释：
1. 器件类型，MOS管8726是一种N沟道增强型MOSFET，具有负电压栅极和正电压源极。

2. 最大漏极电流（ID），这是MOS管8726能够承受的最大漏极电流。

超过此电流可能导致器件损坏。

3. 最大漏极-源极电压（VDS），这是MOS管8726能够承受的最大漏极-源极电压。

超过此电压可能导致器件损坏。

4. 最大栅极-源极电压（VGS），这是MOS管8726能够承受的最大栅极-源极电压。

超过此电压可能导致器件损坏。

5. 阻态漏极电阻（RDS(on)），这是MOS管8726在导通状态下的漏极-源极电阻。

较低的RDS(on)值意味着较小的导通电阻，从而减少功耗和发热。

6. 栅极电荷（Qg），这是MOS管8726栅极电荷的总量。

较小的Qg值意味着更快的开关速度和更低的开关损耗。

7. 栅极阈值电压（Vth），这是MOS管8726的栅极电压与漏极电流之间的临界电压。

当栅极电压高于此值时，MOS管开始导通。

8. 漏极电流温度系数（ID Temperature Coefficient），这是MOS管8726漏极电流随温度变化的比例。

了解此系数可以帮助设计者在不同温度下预测器件的性能。

需要注意的是，以上只是MOS管8726的一些常见参数，具体的参数取决于制造商和型号。

如果你需要更具体的参数，请提供更详细的型号或参考相关的器件手册。