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Input/Output and Measurement ModulesThe rear of the SyncSystem 4380A is shown below. Modules can be operated in any of the six slots. The unit will automatically detect and configure the system based on the modules(s) installed. The module slots are identified by slot number so the operator can identify the modules' physical location in the chassis.Pulse Output Modules4394A: Pulse output (e.g., PPS, DC-IRIG), 4 ports, BNC(F)The 4394A module provides 4 pulse output ports. The output type of each port is individually user configurable. Users can change the signal types (PPS / DC IRIG), the PPS signal parameters, and the IRIG signal parameters. The 4394A module is tied to the UTC Epoch only.DescriptionSFP Ports (future use)10 MHz InputUSBEthernet GNSS Antenna In put6 hot-swappable expansion slotssupport a broad range of input/output modules4334A: Pulse output (e.g., PPS, DC-IRIG) - UTC Time and GPS TimeThe 4334A module provides two 1PPS outputs and two DC IRIG (B000) outputs.Outputs 1 and 2 are 1PPS and outputs 3 and 4 are DC IRIG. Users can changethe signal types (PPS/DC IRIG/Havequick), the PPS signal parameters, theIRIG signal types on individual output ports with 4 independent epochs, orHavequick (UTC Only). Users can select the output voltage on each port (0-3V or0-5V) based on the configuration. By default, the module ships set to 3V.4344A: 1PPS-10V Output ModuleThe factory default for this module provides four 1PPS outputs at 10V 0-PK. Valid PPS settings are 1PPS to 10MPPS. This module also allows configuration of the pulse period, pulse width and PPS rates.4391A/4331A : Code GeneratorsThe 4391A/4331A Code Generators can generate user defined bit streams witha known relationship to UTC. The code generation segment uses the local UTC estimate and a user-generated data file and produces a bit stream (derived from the user-generated file) whose first bit is aligned to within 1 ns of the local UTC estimate. On the 4391A Ports 1 and 2 are TTL into 50Ω and Ports 3 and 4 are >2.4V peak-to-peak into 50Ω (NRZ). On the 4331A Ports 1 - 4 are RS422 (1.5 V to 5.5V into 100Ω differential Triax). All 4 ports of each module are in phase.4391A: Code Generator Module4331A: RS-422 Code Generator Module4376A: Pulse Output Module (e.g., PPS, DC-IRIG), RS-422 (4 outputs), DB15(F) The 4376A module factory default for this module provides four 1PPS outputsusing a DB15 type connector. Users can change the PPS signal parameters onindividual signal outputs.4335A: Pulse, Timecode, Have Quick Output ModuleThe 4335A module provides two 1PPS outputs and two DC IRIG (B000) Outputs.Outputs 1 and 2 are 1PPS and Outputs 3 and 4 are DC IRIG. The output types areuser selectable/programmable. Users can change the signal types (PPS/DC IRIG/Havequick), the PPS signal parameters, the IRIG signal types on individual outputports with 4 independent epochs, or Havequick (UTC Only). Users are able toselect the output voltage on each port (0-3V or 0-5V) based on the configuration.Frequency Output ModulesThe SyncSystem 4380A supports a variety of frequency outputs modules. All mod-ules are all hot-swappable and do not require end user programming or configura-tion. The modules operate in any of the 6 module slots and output 10 MHz, 5 MHz or 1 MHz at +13 dbm.4395B-1: 1 MHZ Module4395B-5: 5 MHz Module4395B-10: 10 MHz ModuleAM IRIG Modules Array 4387A: Amplitude Modulated (AM) IRIG ModuleThis module provides four Amplitude Modulated (AM) IRIG Outputs or the NASA36Serial Time Code. Valid AM IRIG Codes are A (130, 133, 137), B (120, 123, 127), E (111,112, 121), G (141, 142, 147), and H (111, 112, 121, 122, 127). The default time code isB120. The 4387A-6V module provides 6 Vpp output signals.4337A and 4338A: Epoch Adjusted Timecode (AM) IRIG ModulesThis 4337A module provides four Amplitude Modulated (AM) IRIG Outputs tied to a single epoch where as the 4338A moduleallows each port to have its own unique epoch. The epoch can be user defined, UTC (default) [±offset], GPS time, or a configuredtime zone. Valid AM IRIG Codes are A (130, 133, 137), B (120, 123, 124, 127), E (111, 112, 121), G (141, 142, 147), and H (111, 112,121, 122, 127). The default time code is B120. B120 and B124 support the IEEE-1344 Control Functions.The [+/- offset] option with the UTC epoch allows users to add or subtract between 1 minute and 23 hours and 59 minutes fromthe current UTC Time. The GPS epoch outputs the GPS time scale (UTC with the current # of leap-seconds removed).A Time Zone Epoch can be specified and the IRIG Outputs will be set to that Time Zone and if the Control Function is set to 1344 the offset bits will indicate the direction and amount of time off from UTC (except for the three time zones occurring 45 minutes after the hour) and the Time Zones east of the GMT meridian (positive) or west of the GMT meridian (negative). For local offset control bits to be correct, hours must be between -15 and +15, minutes must be 0 or 30, and seconds must be zero. When a local time zone is specified, daylight savings time rules (if any) are applied automatically.each port.Communication/Telecom Modules4374A: T1/E1 Telecom ModuleThe 4374A module produces a 1.544 Mbps T1 (DS-1) or 2.048 Mbps compatibleoutput. Each port can independently be set to one of four output configurationoptions:0: B8ZS, ESF packets1: 1.544 MHz Square Wave2: B8ZS, D4 packets, All 1's3: B8ZS, D4 packets4: E1 HDB3 Framing5: 2.048 MHz Square Wave4332A: Time-of-Day (TOD) ModuleThis 4-port module can be used to serve as a reference input to devices such as the BlueSky™ GNSS Firewall, TimeProvider ® 4100, or other hardware. The outputs from this module support two sets of differential signals: 1PPS and Time-of-Day (TOD) as a serial time code. The default output format for the TOD card is ITU G8271.The 1PPS signal is on Pins 3 and 6 (Ground on Pins 4 and 5) and the TOD Signal ison Pins 7 and 8 on each RJ-45 connection.Input and Measurement Modules4382A: Phase Input Measurement ModuleThe 4382A is a four-channel phase measurement module capable of measuring the phase of 5 MHz or 10 MHz signals to high precision. The 4382A includes a multiple mixer measurement system all contained on a single plug-in card. The 4382A module measures the phase difference between an RF signal from the clock under test and a reference RF signal. The 4382A module can be configured to use the internal timebase of the SyncSystem 4380A or one of the four ports of the module can be configured as the reference RF signal. The SyncSystem 4380A uses measured IF phase differences tocompute input phase at a resolution of better than 100 femtoseconds.4393A Time Interval Counter (TIC) ModuleThis module has four input ports that can be used to measure the time interval between the internal 1PPS and up to four external sources and will work in any of the 6 module slots. The averaging period for the measurements is configurablefrom 1, 10, 20, 60, to 300 seconds.4383A: Time Interval Counter (TIC) ModuleThis module has four input ports that can be used to recover time from an IRIGtime source. Ports 1 and 2 support DC IRIG (Default B007) and Ports 3 and 4 sup-port AM IRIG (Default B127).The Microchip name and logo and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are property of their respective companies.© 2022, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. 4/22 DS00004401A。
CG英语词汇Aa copy a 拷贝aaaa 美国广告代理商协会abc 美国广播公司account executive 业务代表account planners 业务企划人员action photography 带动作的摄影actors 职业演员adat 数位式录音带additive proccess 追加过程aDVertisingage 《广告年代》杂志agency commission 广告公司佣金agenda 议程表alternative locations 候选（备用）外景照片 american federation of musican 美国音乐家协会american federation of televis 美国广播电视演艺人员协会amsaudiofile 数位录音工作站anachronisms 事态连贯性analog sound mixing consoles 类比型（非数位化）混音机animated graphics 单格动画图形animated titles 动画式片头animation 动画animatic stand 动画摄制固定架animation storyboard 仿录脚本animators 动画家arrangement 编曲art director 艺术指导asa 感光度（感光速度系数）assistant camera person 助理摄影师assistant director 助理导演association of independentcommercial producers.aicp 独立广告影片制作人协会aUDIO 声部audio master 声音母带audio mixer 混音师audio post-production 声部后制作audition 试镜会authority 权威人士Bbackdrops 背景布幕backlit 后面打光barcode number 片边条码barcode standard 条码格式barn doors 遮光板best boy 灯光助理billdding package 套装议价组合billboards 户外看板bin monitor 显像储藏室bisociation 异类联想blow-up 放大blue danube 蓝色多瑙河blue-sereen photography 蓝幕摄影boom person 吊杆控制员boom up 把摄影机升高Ccamera car 摄影车camera dolly 摄影机移动台车camera person 摄影师Campbell 汤府公司Carnation 康乃馨cartooning 卡通casting 演员试镜casting director 演员指导CBS 哥伦比亚广播公司Cecil B.DeMILe 迪麦而制作公司cel animation 赛璐璐动画celluloid 赛璐璐片CGI 电脑影像合成chain of command 指挥系统changing bag 暗袋checklist for bidding 议价核对清单chicago tribune 芝加哥谈论报chief electrician 首席灯光师choreography 舞术编排Cineon digital Film System 数位化影像系统click track 节拍音轨clip 画面段commercial-program 广告形式的电视节目compact disc CD雷射唱片comparison commercial 比较唱片composers 作曲者composite photograph 修饰过的写真照片 compositing 影像合成computer animation 电脑动画Computer Graphic Imaging CGI电脑影像处理conforming the picture 套剪图象copywrite 文案人员cost-plus-fixed-fee C+FF成本加固定费用 Cost Summary Forms 价目总表crane operator 摄影升降机操作员creative director CD创意总监DDemo 音乐样本带demographic segments 人口区隔demonstration commercial 展示广告Demonstrations and comparisons 展示与比较diffusion filters 柔焦滤镜或柔光镜Digital Audio Tape DAT数位录音带Digital Video Effect DVE数位影像效果digital audio workstations 数位录音工作站 digital film system 数位化影像系统digitized computerization 数位化电脑处理 digitizing 数位化diopters 屈光镜director costs 直接成本direct-response 直接回应director 导演director of photography DP摄影导演dissolves 溶接dolly grip 摄影机车台场务dolly in 整部摄影机向前移动dolly moves 前后移动dolly track 摄影机移动轨道doubles 替身演员diubling 替身戏down-the-line-renewnals 续约费用Eedge numbers 片边号码Edit Decision List EDL剪辑点决定表 edit-and-assemble monitor 剪辑及组合用的监视器editing 剪辑editors 剪辑师electrician 灯光师electronic chips 电脑晶片electronic pen 电子感应笔electronic pixels 电子像素erasa-and-reuse 洗掉再重录emotional response 情感反应emulsions 感光乳剂exaggeration 夸张效果exposed negative film can 曝过光的底片盒Ffade in 淡入fade out 淡出Federal Communications Commission FCC 联邦传播委员会Federal Trade Commission FTC联邦贸易委员会fiber optics 光线film library 影片资料库film magazine 摄影机片盒film scanner 底片扫描机film stocks 底片材料、拍摄片Final 最后成本明细表fine-tuning 微调finishing 最后完成作业finishing facilities 后制单位first bid 包工议价first cut 首次剪辑first generation 原版flying camera people 空中摄影师focus 焦距focus groups 小组讨论（分组座谈会）Foote Cone & Belding 富康广告公司forum 讨论会frame-by-frame filmmakers 逐格影片制作人free-lance casting director 自由的演员指导 Free-lancers 自由工作者full animation 完全动画full-scale occean liner 比例1比1的外海邮轮futuristic 未来Ggaffer （鱼叉人），灯光师的俗称General Foods 通用食品公司General Mills 通用磨坊公司generator plot 概括性的创意构想generator operator 发电机操作员generator truck 发电机卡车gobos 旗板graphic demonstration 图象展示graphics estimating sheets 影像估价单Green Giant 绿巨人Hhair stylist 美发师hangs wallpaper 壁挂纸head electrician 首席灯光师head-to-head-comparison 面对面的直接比较high -angle lights 高角度灯光high-definition TV HDTV 高解析度电视系统high-lights 强光high-speed strobe-lighr flash 高速频闪闪光灯home economist 食品料理专家house location 外景房屋huge bellows cameras 有蛇腹的相机IILM 光影魔幻产业公司Illusrating slogans with images 以影音特效强化标语immediate sales 立即性销售in real time 等速或即时informercials 资讯式广告inherent drama 商品兴俱来的戏剧性In-house aDVertising departments 客户公司内部的广告部门in-house production unit 广告公司内部的拍摄单位inkers 动画扫图员 inside props 棚内道具师instant production 即席制作internal costs 内部成本international Alliance of Theatrical stage Employee IATSE国际戏剧雇员联盟interview commercial 访问式广告影片Jj.Walter Thompson 智威汤逊广告公司jerky motions 把场景急拉的动作jingle 含有品牌象薇的广告音乐或声音Kkem flat-bed editing table kem平面式剪辑台 key frame 主要画格KeyCode.Kodak 柯达底片边缘印的条码key frame 主要画格Kodak Keykode Numbers 柯达片边条码系统Llevel angle 水平角度Lexus 凌志汽车library music 音乐资料库light meter 测光表line up 校准lines 台词lip sync dialogue 对嘴旁白lip-syncing 对嘴live-action 实景live-action filming 实景拍摄片制作live-action photography 实景摄影live-action shooting 实景拍摄local-access cable channels 地区性有线频道 location search 勘景log 拍摄日志long shot 远景镜头Low angle 低角度Lucas Films 卢卡斯影业Mmagnetic tape 磁性录音带makeup artist 美容师manipulation 操纵markup 固定利润matte 影像形板Maysles Films 梅思利电影公司memory-hook 回马枪memory-jogger 回马枪Merrill Lynch 美林动画metamorphic animation 变形动画metamorphosis 变形micro-markets 微众市场mixer 混音师modeling 模型制作montage 蒙太奇morph 型变MOS 不需要现场收音的无声取景motion board 活动脚本或动作脚本motion capture 动作资料截取motion cintrol 电脑控制拍摄系统motion picture film 动画影片motion tests 动作测试motor home 移动居住车mouse 滑鼠mouthpiece 发言人multi-city bidding 多城市竟标music bookends 音乐书签music first 以音乐为优先Musical Instrument DigitaL Interface MIDI 电子乐器一的数位介面NNational Association of Broadc 国家广播电子技师协会National Cash Register 国家收银机公司NBC 国家广播公司negative conformer 底片组合员New Yorker 《纽约客》杂志NG 不好的镜头Nikon camera 尼康相机nonlinear editing 非线性剪辑Oofff-camera 镜外表演off-key 走调offline system 线外系统offline system 线外剪辑系统one-stop operation 一贯作业 on camera 镜内表演on-camera SAG rates 电影演员同业公会规定的上镜费on location 出外景online editing 线上剪辑one-light 单一光度one-light film print 单光影片洗印one-stop operation 一次作业opaquer 著色人员open camera 公开摄影optical house 视觉效果工作室optical printer 光学印片室original arrangment 编曲著作original recording 录音著作original score 总谱制作out-of-pocket 现款支付outside props 棚外道具师outtakes 借用镜头PPacific Data Images 太平洋影像公司pegs 过场用之画面pencil test 铅笔测试稿perceived value 知觉价值personalities 知名人士Personality testimonials 名人见证petsuasion 说服photo CD 影像光碟pickup footage 从旧有的广告借凑而来的影片Pictures first 以画面为优先pixels 像素playback 播放playback person 录影机播放员post-scoring 后制配乐posttesting 后测pre-lite 预先排演pre-production meeting 拍制前会议pre-production stage 制前阶段prescoring music 拍摄前配乐pretesting 前测price-quote 报价或喊价printed circuiry 印刷电路producer 广告公司的制片，制作人product shot 商品展示镜头production assistant P.A制作助理production boutique 制片工作室production notes 制作住记production package 制作议价组合production specification sheets 制作分工明细表promotions 促销prop people 道具师peoperties 舞台道具props 道具public-domain music 大众共有或版权公有的音乐publisher's fee 发行费用pulldowm 抓片Rranddom access 随机存取Random Access Memory RAM随机存取记忆体raster 屏面Read Only Memory ROM唯读记忆体real opinions 真实反应的意见real people 消费大众或一般人Real people reactions and opinions 消费大众的真实反应及意见recordist 录音师reebok 锐跑reflections 反光rendering 算图rental facilities 出租公司residual 后续付款Rhapsody in blue 《蓝色狂想曲》Rhythm and Hues 莱休电脑动画公司right-to-work 自由工作权Ripomatic/stealomatic storyboard 借境脚本 Roll camera 开动摄影机rotoscope 逐格帖合的重覆动画动作rough cut 粗剪Ssample reels 作品集scencs 场景scenics artist 布景设计师scratch track 临时音轨 Screen Actors Guild SAG电影演员同业公会 Screen Extra's Guild SAG电影临时演员同业公会scripts 剧本script clerk 场记set construction costs 搭景费用set designer 布景设计师set dresser 布影装饰师shadows 阴影shape library 清晰对焦shooting board 模型资料库shooting day 制作脚本拍片日shooting in two 一次两画格的方式拍摄shot list 拍摄程序表shutter 快门sides 台词表silent scenes 无声场景silent takes 无声取景slate 开拍板Slice-of-life episodes 生活片段式对白snapshot 快照拍摄Solid State ScreenSound 数位录音工作站 song-and-dance 歌舞片sound people 音效人员sound stage 隔音场sound take 有声摄影special effects person 特殊效果人员special-effects 特效specification sheet 职责明细表speed 运转正常splice 捻接Sprint 斯布林特电话公司stand-in 替身Stand-up presenters 播报员推荐standing sets 常备的布景配置star personality 知名人物stereo-mixing 立体声混音sticks 排字手托stills 剧照still photos 静态照片stock footage 底片材料、库存影片stop-motion 单格拍制story line 故事情节storyboard 故事脚本strobe-lighe photography 频闪闪光灯摄影法Subaru autombile 速霸陆汽车Super 16mm format 超16厘米底片规格sync sound 同步收音synchronized 同步Tthe screening room 试播室takes 取景镜头talent reports 劳务报价单teamsters 卡车驾驶员Teamsters Union 卡车驾驶员工会telepromrter 读稿机test commercial 测试性广告testimonial release print 电影院放映片three-dimensional 3D三度空间tight close-up 大特写time-code 时码tissue sheets 薄绵纸top light 顶光tracing paper 扫图纸track left 摄影机左移track right 摄影机右移track time 音轨时限trade 通路Tri-X 柯打tri-x底片trim 剪修trims 修剪下来的片头尾turnarounds 转场UUnique Selling Proposition 独特的销售主张VVIDEO 视觉或影像部分video master 影像母带Video Tape Recording person 录音带录制员 vignetters 集锦式快接画面处理virtual reality 虚拟实境visual timeline 视觉时间尺visually oriented 视觉导向voiceover announcer 旁白播音员Wwardrobe attendant 服装师West and brady 威布广告公司wild wall 活动墙板window burn-in 叠印框wire-frame 立体线稿words-and-music 旁白加音乐Words First 以文案为优先YYoung Rubican 扬雅广告公司Zzoom 变焦zoom in 镜头向前推进附录：2D Solid 二维实体3D Array 三维阵列3D Dynamic View 三维动态观察3d objects 三维物体3D Orbit 三维轨道3D Viewpoint 三维视点3dpoly 三维多段2D Solid 二维实体3D Array 三维阵列3D Dynamic View 三维动态观察3d objects 三维物体3D Orbit 三维轨道3D Viewpoint 三维视点3dpoly 三维多段线3dsin 3DS 输入3DSolid 三维实体3dsout 3DS 输出abort 中断absolute coordinates 绝对座标abut 相邻accelerator key 快速键access 存取acisin ACIS 输入ACIS 汇入acisout ACIS 输出ACIS 汇出action 动作active 作用中adaptive sampling 最适取样add 加入Add a Printer 新增印表机Add mode 添加模式Add Plot Style Table 添加打印样式表Add Plotter 添加打印机Add to Favorites 增加我的最喜爱ADI ADI(Autodesk 设备接口)ADI (Autodesk 设备介面)adjacent 相邻Adjust 调整Adjust Area fill 调整区域填满AdLM (Autodesk License Manager) AdLM （Autodesk 许可管理器）Administration dialog box 管理对话方块Advanced Setup Wizard 进阶安装精灵Aerial View 鸟瞰视景affine calibration 关系校正alert 警告alias 别名aliasing 锯齿化align 对齐aligned dimension 对齐标注alignment 对齐allocate 配置Altitude 高度ambient color 环境颜色ambient light 环境光源angular dimension 角度标注angular unit 角度单位annotation 注解anonymous block 匿名图块anti-aliasing 消除锯齿aperture 锁点框apparent intersections 外观交点append 附加Application key 应用程式码appload 载入应用程式Apply 套用approximation points 近似点arc 弧Architectual Ticks 建筑斜线area 区域,面积Argument 引数Arrange icons 排列图示array 阵列arrowhead 箭头ASCII ASCII （美国标准信息交换码）ASCIIaseadmin ASE 管理aseexport ASE 输出aselinks ASE 链接aserows ASE 行aseselect ASE 选择ASE 选取asesqled SQL 编辑ASE SQL 编辑器Aspect 纵横向间距aspect ratio 纵横比assign 指定Assist 辅助associative dimension 关联式标注associative hatches 关联式剖面线attach v. 贴附attdef 属性定义attdisp 属性显示attedit 属性编辑attenuation 衰减attenuation of light 光源衰减attext 属性萃取attredef 属性重新定义attribute definition 属性定义Attribute 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呼叫callback 回覆callback 回覆camera 照相机camera angle 相机角度Cancel 取消cap 封口cascade 重叠排列case 大小写cast 投射catalog 目录cell 储存格Center 中心center mark 中心点标记centerline 中心线centroid 矩心chamfer 倒角change 变更。
计算机编译的名词解释计算机编译是指将人类编写的高级语言程序翻译成计算机能够理解和执行的机器语言的过程。
在计算机科学中，编译器是实现这个过程的关键工具。
本文将对计算机编译的相关名词进行解释，以帮助读者更好地理解这一概念。
一、编译器（Compiler）编译器是一种程序，它将高级语言的源代码转换为目标代码，使计算机能够直接执行。
编译器通常包含以下几个主要的组件：1. 词法分析器（Lexer）：也称为扫描器，负责将源代码分解成一个个记号（Token）。
记号是语言中的最小单位，例如关键字、标识符、运算符等。
2. 语法分析器（Parser）：语法分析器根据语言的语法规则，将记号组织成一棵由语法构成的语法树（Parse Tree）。
语法树表示了源代码的结构。
3. 语义分析器（Semantic Analyzer）：语义分析器对语法树进行检查，以确保源代码的语义正确。
它会检查变量的声明与使用是否匹配、类型转换是否正确等。
4. 目标代码生成器（Code Generator）：目标代码生成器将语法树转换为计算机能够执行的目标代码。
目标代码可以是二进制文件、字节码或其他形式的中间表示。
二、解释器（Interpreter）解释器是一种执行高级语言程序的程序。
与编译器不同，解释器不会直接将源代码转换为目标代码，而是逐行解释并执行源代码。
解释器通常包含以下几个主要的组件：1. 词法分析器（Lexer）：与编译器的词法分析器相同，将源代码分解成记号。
2. 语法分析器（Parser）：解释器的语法分析器根据语言的语法规则，将源代码解析为语法树。
但与编译器不同，解释器不会生成目标代码。
3. 解释器核心（Interpreter Core）：解释器核心逐行读取语法树，并实时解释和执行源代码。
它会根据不同的语法规则执行相应的操作。
三、即时编译（Just-in-Time Compilation）即时编译是一种将高级语言程序动态转换为机器代码的技术。
编译原理第四版课后答案1. What are the three basic phases of a compiler and what are their main functions?- The three basic phases of a compiler are lexical analysis, syntax analysis, and code generation.- The main function of lexical analysis is to read the source code and break it into individual tokens, such as keywords, identifiers, numbers, and symbols.- The main function of the syntax analysis is to parse the tokens and verify that they form valid syntax according to the grammar rules of the programming language.- The main function of code generation is to convert the parsed tokens into executable code in a target programming language or machine code.2. What is lexical analysis and what are its main tasks?- Lexical analysis is the first phase of a compiler, which reads the source code and breaks it into individual tokens.- The main tasks of lexical analysis include tokenization, where the source code is divided into meaningful units called tokens, such as keywords, identifiers, numbers, and symbols; removal of comments, where any comments in the source code are ignored; and removal of white spaces, where unnecessary spaces, tabs, and line breaks are eliminated.3. What is a parser and what is its main function?- A parser is a component of the compiler that performs syntax analysis, also known as parsing.- Its main function is to analyze the structure of the tokens generated by the lexical analysis phase and verify that they form avalid syntax according to the grammar rules of the programming language.- The parser constructs a derivation tree or a parse tree to represent the structure of the code and checks for syntax errors, such as missing or misplaced tokens.4. What is the difference between a compiler and an interpreter?- A compiler is a program that translates the entire source code of a programming language into an equivalent target code or machine code before execution.- An interpreter, on the other hand, does not translate the entire source code into machine code before execution. Instead, it reads and executes the source code line by line, translating and executing each line as it encounters it.- In terms of efficiency, a compiled program tends to run faster than an interpreted program because the compiled code is already in machine language, whereas the interpreted code needs to be translated and executed at runtime.5. What are the advantages and disadvantages of using an interpreted language?- Advantages of using an interpreted language include faster development time, as there is no need to compile the entire code before execution; easier debugging, as errors can be detected and fixed immediately; and platform independence, as the interpreter can run on different operating systems without the need to compile separate binaries.- Disadvantages of using an interpreted language include slower execution speed compared to compiled languages; lower performance, as the interpreter needs to translate and execute eachline at runtime; and potential security risks, as the interpreted code can be easily accessed and modified.6. What is meant by bytecode and what is its role in interpreter-based execution?- Bytecode is a low-level representation of the source code that is generated by a compiler or an interpreter. It is a set of instructions that can be executed by a virtual machine.- In interpreter-based execution, the source code is first compiled into bytecode, which is a platform-independent representation of the code. The interpreter then reads and executes the bytecode on the virtual machine, providing a compromise between compilation and interpretation.- Bytecode allows for faster execution compared to interpreting the source code directly, as the bytecode is already in a form that can be executed by the virtual machine.7. What is code optimization and why is it important?- Code optimization is the process of improving the efficiency and performance of the generated code by the compiler.- It is important because optimized code can run faster and consume less memory, resulting in improved overall performance of the program.- Code optimization techniques include constant folding, loop unrolling, dead code elimination, and register allocation, among others.8. What is a symbol table and what is its purpose?- A symbol table is a data structure that is used by a compiler to store information about the variable and function namesencountered in the source code.- Its purpose is to keep track of the properties and attributes of each symbol, such as its data type, memory location, scope, and visibility.- The symbol table is used by various phases of the compiler, such as the lexical analyzer, parser, and code generator, to perform tasks such as name resolution, type checking, and memory management.9. What is the role of an assembler in the compilation process?- An assembler is a program that converts assembly language code into machine code.- In the compilation process, the assembler is responsible for translating the assembly language code written by the programmer into machine code that can be executed directly by the computer hardware.- The assembler performs a one-to-one mapping of assembly instructions to their corresponding machine code instructions, and also resolves symbolic addresses and labels used by the programmer.10. What is the difference between a single-pass compiler and a multi-pass compiler?- A single-pass compiler is a compiler that reads the source code of a program once and generates the corresponding executable code in a single pass or iteration.- A multi-pass compiler, on the other hand, requires multiple passes or iterations over the source code in order to generate the executable code.- Single-pass compilers are generally simpler and require less memory, but they are unable to perform certain optimizations orglobal analysis that requires information from the entire source code. Multi-pass compilers are more powerful and can perform more complex optimizations and analysis, but they are typically slower and require more memory.。
小学下册英语第5单元期末试卷英语试题一、综合题(本题有100小题，每小题1分，共100分.每小题不选、错误，均不给分)1.I admire people who __________ because they are __________.2.What is the opposite of happy?A. SadB. AngryC. ExcitedD. Tired3.My cousin is interested in ____ (robotics).4. A chemical reaction can release or absorb ______.5.Which shape has four equal sides?A. RectangleB. TriangleC. CircleD. SquareD6.My friend is a ______. He enjoys sports.7.We can ___ a fun game. (play)8.What is the capital of Italy?A. ParisB. RomeC. MadridD. Athens9.The store opens _____ (early/late) in the morning.10.What do we call the science of rocks?A. BiologyB. GeologyC. ChemistryD. PhysicsB11.I see birds flying south in ______ (秋天).12. A __________ is a reaction that absorbs heat from the surroundings.13.My favorite _____ is a colorful butterfly.14.What is the capital of France?A. BerlinB. MadridC. ParisD. Rome15.My sister is a _____ (美术家) who loves to paint.16.The puppy is very ________.17.I have a toy _______ that glows in the dark and lights up my whole room.18.Certain types of flowers bloom only in ______ weather. (某些类型的花仅在寒冷的天气中开放。
城轨1304班顾浩1信号系统常用中英文对照表缩写中文英文 AAC 交流电 Alternating Current ADM 管理服务器 Administration Server ADP 活动距离验证 Activation Distance Proving AID 经核准的输入数据Approved Input DataALARP 合理,实现低水平As Low As Reasonably Practicable AM 列车自动驾驶(列车驾驶模式) Automatic train operation (mode) AR 自动折返 Automatic Reversal Operation ARS 进路自动排列 Automatic Route Setting ATC 列车自动控制Automatic Train Control ATO 列车自动驾驶 Automatic Train Operation ATP 列车自动防护 Automatic Train Protection ATR 列车自动调整 Automatic Train Regulation ATS 列车自动监督 Automatic Train Supervision AX 安全型继电器Safety Type Relay AZS 计轴系统 Axle Counting System BBA 应答器天线 Balise AntennaBAS 设备监控系统 building automation system By 旁路(列车驾驶模式) Bypass (train operation mode) CCBTC 基于通信的列车控制系统 Communication Based Train Control CCT 组合 CDMA / TDMA Combined CDMA / TDMA CH 通道ChannelCIS 计算机联锁系统 Computer Interlocking System CM 配置管理Configuration Management CNR 车组号报告SQL 脚本 SQL-script for crew number report COM 通信系统, 通信服务器 CommunicationSystem,Communicator Workstation COCC 中心OCC Central operation control centreCOTS 商业化的现货供应 Commercial Off The Shelf CPU 中央处理单元Central Processing Unit CRC 循环冗余码 Cyclic Redundant Code CTCS 中国列车控制系统 Chinese train control system CU 运算单元 Computing unitDDB 数据库DatabaseDC 直流电Direct currentDCS 数字通信系统Data Communication SystemDEK 43 计轴车轮传感器Axle Counter Wheel SensorDPS 车辆段服务对话框Depot Service DialogDRB 无司机折返按钮Driverless Return ButtonDRI 无司机折返表示器Driverless Return IndicationDTI 发车表示器Departure (Dwell) Time IndicationEEB 紧急制动Emergancy BrakeECC 元件(单元)控制计算机Element control computerECC-CU 元件控制计算机-运算单元Element control computer computingunitEIM ECC 元件接口模块元件控制计算机Element interface module elementcontrol computerEIRP 有效全向辐射功率Effective Isotropic Radiated Power EMC 电磁兼容Electromagnetic compatibilityEMP 紧急停车按钮Emergency Stop PlungerEN 欧洲标准European standardEP 电空制动Electro Pneumatic BrakeEPS 紧急电源(包括UPS) Emergency Power Supply (incl.Uninterrupted Power Supply (UPS)) ETCS 欧洲列车控制系统European Train Control SystemFFALKO 时刻表验证和时刻表生成Timetable Validation and TimetableConstructionFAS 防灾报警系统Fire Alarming SystemFEP 前端处理器Front End ProcessorFOC 光缆Fibre Optic CablesFTA 故障树分析Fault Tree AnalysisGGB 中国国家标准National Standards, ChinaGONG 声音模拟Sound animationHHMI 人机界面Human Machine InterfaceHW 硬件HardwareII/O 输入/输出Input/outputIBP 综合后备盘Instancy Back-Up PanelICD 接口控制数据库Interface Control DatabaseICF 接口控制表Interface Control FormIF 接口InterfaceIL 联锁InterlockingIL bus 联锁总线Interlocking busILD 联锁对话框Interlocking DialogINOM 输入/输出操作模块Input/output operating module IntlC 联锁内核Interlocking coreIOC 输入输出计算机Input Output ComputerIP 互联网协议Internet ProtocolJ --- ---K --- ---LLAN 局域网Local Area NetworkLCC 生命周期成本Life Cycle CostLCD 液晶显示器Liquid Crystal DisplayLED 发光二极管Light-Emitting DiodeLEU 轨旁电子单元Lineside Electrical UnitLIDI 列表显示List displayLLC 逻辑链路控制Logical Link ControlLoT 列车列表List of TrainsLOW 车站操作员工作站Local Operator WorkstationLRU 现场可更换单元Line Replaceable UnitMMA 移动授权Move AuthorityMAATR ATR对话框Mask program for ATRMAFPL 时刻表操作对话框Mask program for timetable operation MAL 移动授权限制Move Authority LimitMARP 记录和回放对话框Mask program for record andplaybackMASCRIP 报告处理对话框Mask program for reportsMASTW 联锁指令对话框Mask program for interlockingcommandsMAZLV TMM对话框Mask program for TMMMMI 人机界面Man-machine interfaceMSC interface 平交道口信号接口signal interface for level crossings MSTP 多业务传输平台Multi-Service Transmission Platform MT 城市轨道交通Mass transitMean Time Between FailureMTBF 平均故障间隔时间, 平均无故障时间MTBRSF 平均安全侧故障间隔时间Mean Time Between Right SideFailureMean Time Between Service Failure MTBSF 平均运行故障间隔时间,平均无故障运行时间MTBWSF 平均危险侧故障间隔时间Mean Time Between Wrong SideFailureMTTR 平均故障修复时间Mean Time To RepairMVB 多功能车辆总线Multifunction Vehicle BusNNRM 非限制人工驾驶模式Non Restrictricted Train OperationModeOOBCU 车载控制单元On-Board Control UnitOBCU_ITF 车载控制单元接口元件Interface component of OBCU OBCU_ATO 车载ATO ATO on-board control unitOBCU_ATP 车载ATP ATP on-board control unitOCC 控制中心Operation Control CentreODD 车载诊断数据(报文) On-board Diagnose DataODI 操作和显示接口Operation and display interfaceOLM 光连接模块Optical link moduleOOE 车载运营事件(报文) On-board Operational EventOOS 车载运营状态(报文) On-board Operational StatusOPD 车载屏蔽门(报文) On-board platform doorOPG 测速电机(里程脉冲发生器)Odometer pulse generatorOPR 车载位置报告(报文) On-board Position ReportOPS 操作OperationsOSI 开放系统互联Open System InterconnectionOSP 运营停车点Operational Stop PointOTN 开放传输网络Open Transport NetworkPPA 车站广播系统Public AddressingPC 个人计算机Personal ComputerPC(Interlocking ) 道岔控制Point ControlPCI 外围设备互连Peripheral component interconnect PDI 站台发车计时器Platform Departure IndicatorPDI(software) 过程数据接口协议Process data interfacePEACC+ 符合CENELEC和CMM要求的西门子研发流程Product Engineering according to CENELEC and CMMPESB 站台紧急停车按钮Platform Emergancy Stop Button PIIS 乘客导向系统(轨旁)Passenger Information and IndicationSystem (trackside)PIS 乘客信息系统(车载)Passenger Information System(onboard)PMA 定期维修分析Preventative Maintenance Analysis POM 道岔操作模块Point operating modulePOP 防护点Point of ProtectionPOR 限制点Point of RestrictionPPP 点对点协议Point to Point ProtocolPSC 电源控制Power Supply ControlPSD 站台屏蔽门Platform Screen DoorPSM 输入校验分配程序Program to coordinate and check allinputsPSY 电源Power SupplyQRRAMS 可靠性,可用行,可维护性和安全性Reliability, Availability, Maintainability and SafetyRAP 记录与回放Record and PlayRC 进路控制Route ControlRDCS 无线数据通信系统Radio Data Communication System RM 限制人工驾驶模式Restricted Manual (train operationmode)RP 参考点Reference pointRPS 背投系统Rear Projection SystemRSF 安全侧故障Right Side FailureRS 车辆Rolling StockRTU 远程终端单元Remote Terminal UnitSS&D 服务与诊断系统Service and Diagnostic SystemSC 信号控制Signal ControlSCA 电力监控系统SCADASCADA 电力监控系统Supervisory Control And DataAcquisitionSIC 车站接口箱Station Interface CaseSicas SICAS 微机联锁系统Siemens computer aided signalling Sicas ECC SICAS 单元控制计算机Siemens Computer Aided Signalling,Element Control ComputerSicas ECC ODI SICAS ECC 操作和显示接口Siemens Computer Aided Signalling,Element Control Computer Operationand Display InterfaceSIG 信号设备供货商的统称Signalling; the lot who is supplyingthe signalling equipmentSIM 信号接口管理Signalling Interface Management SIMIS 西门子的故障-安全微机系统Fail-safe microcomputer system fromSiemensSLC 西门子(中国)有限公司Siemens Limited ChinaATPM/SM ATP监督的人工驾驶模式(列车驾驶模式) Supervised manual train operation (train operation mode)SN 西门子标准Siemens StandardSNMP 简单网络管理协议Simple Network ManagementProtocolSOM 信号操作模块Signal operating moduleSR 车站报告的SQL脚本SQL-script for station reportSSCX 西门子信号有限公司Siemens Signalling Company Ltd.(Xi’an)STO 半自动列车驾驶Semi-Automatical Train Operation SV 电源Power supplySVPRN 打印机管理器程序Printer managerSW 软件SoftwareTT&S 培训与模拟Training and SimulationTB 中国铁道部标准Standards of MoR, ChinaTCC 轨道交通路网管理服务中心Traffic Control CentreTCB 轨旁接线箱Trackside Connection BoxTCP 传输控制协议Transmission Control ProtocolTDB 线路数据库Track Data BaseTDST 时间有关的饱和传输Time Dependent Saturation Transfer TEL 通信系统(列车无线接口)Telecommunication (Interface to trainradio)TGI 列车运行图Train Graph IndicationTIMS 列车信息管理系统Train information management system TMM 列车移动监督(对话框)Train Movement Monitoring (Dialog) TMS 列车管理信息系统Train Integrated Management System TMT 列车监视和追踪Train Monitoring and TrackingTPC 牵引功率控制Traction Power ControlTrainguard MT 西门子的基于移动闭塞的ATC系统Siemens Moving Block based ATC SystemTRC 列车排路计算机Train Routing ComputerTRN 培训TrainingTRPR 透明报文处理Transparent telegram processingTSR 临时限速Temporary Speed RestrictionTT 时刻表TimetableTTCO 时刻表比较Timetable ComparisonTTM 时刻表管理Timetable ManagementTTR 车次报告的SQL脚本SQL-script for train trip reportTTS 列车和轨道数据库服务器Train and Track Database Server TVD 轨道空闲检查Track Vacancy DetectionTVDS 轨道空闲检查状态Track Vacancy Detection StatusTVS 轨道空闲状态Track Vacancy StatusTVP 轨道空闲处理Track Vacancy ProcessingUUNOM 通用输入/输出操作模块Universal input/output OperatingModuleUPS 不间断电源Uninterrupted Power SupplyUTO 无人自动驾驶Untended Train OperationVV 版本VersionV AU 计轴处理板Axle Counter Processing Board VICOS 车辆和基础设施控制和操作系统Vehicle and Infrastructure Control andOperation SystemVLAN 虚拟局域网Virtual Local Area NetworkVTB (移动闭塞下的)可变列车闭塞Variable Train BlockWWAN 广域网Wide Area NetworkWCC 轨旁通信控制器Wayside Communication Controller WCU Trainguard MT轨旁控制单元Trainguard MT Wayside Control Unit WCU_ATP WCU的A TP元件ATP Component of WCUWCU_TTS WCU的TTS元件TTS Component of WCUWLAN 无线局域网Wirelss Local Area NetworkWMA 轨旁移动授权Wayside Move Authority WOBCOM 轨旁和车载通信通道Wayside and on-board communicationchannelWOD 轨旁运营数据(报文) Wayside Operational DataWOMAN 线路地图管理程序Worldmap managerWSF 危险侧故障Wrong Side FailureXX11 透明图形接口Transparent graphic interface ---Y ---ZZP 43 计轴传感器Axle Counter HeadZZA PIIS和DTI处理Process for PIIS and DTI。
code-generator⽣成代码⼀、⽣成代码如下package mainimport ("flag""fmt"crdv1beta1 "/cnych/controller-demo/pkg/apis/stable/v1beta1""k8s.io/apimachinery/pkg/api/errors""k8s.io/apimachinery/pkg/util/runtime""k8s.io/apimachinery/pkg/util/wait""k8s.io/client-go/tools/cache""k8s.io/client-go/util/workqueue""os""os/signal""path/filepath""syscall""time""/golang/glog""k8s.io/client-go/tools/clientcmd""k8s.io/client-go/util/homedir""k8s.io/klog"clientset "/cnych/controller-demo/pkg/client/clientset/versioned""/cnych/controller-demo/pkg/client/informers/externalversions"informers "/cnych/controller-demo/pkg/client/informers/externalversions/stable/v1beta1")type Controller struct {informer informers.CronTabInformerworkqueue workqueue.RateLimitingInterface}var (onlyOneSignalHandler = make(chan struct{})shutdownSignals = []os.Signal{os.Interrupt, syscall.SIGTERM}kubeconfig *string)// SetupSignalHandler 注册 SIGTERM 和 SIGINT 信号// 返回⼀个 stop channel，该通道在捕获到第⼀个信号时被关闭// 如果捕捉到第⼆个信号，程序将直接退出func setupSignalHandler() (stopCh <-chan struct{}) {// 当调⽤两次的时候 panicsclose(onlyOneSignalHandler)stop := make(chan struct{})c := make(chan os.Signal, 2)// Notify 函数让 signal 包将输⼊信号转发到 c// 如果没有列出要传递的信号，会将所有输⼊信号传递到 c；否则只传递列出的输⼊信号signal.Notify(c, shutdownSignals...)go func() {<-cclose(stop)<-cos.Exit(1) // 第⼆个信号，直接退出}()return stop}func main() {if home := homedir.HomeDir(); home != "" {kubeconfig = flag.String("kubeconfig", filepath.Join(home, ".kube", "config"), "(optional) absolute path to the kubeconfig file") } else {kubeconfig = flag.String("kubeconfig", "", "absolute path to the kubeconfig file")}flag.Parse()// 处理信号量stopCh := setupSignalHandler()// 处理⼊参cfg, err := clientcmd.BuildConfigFromFlags("", *kubeconfig)if err != nil {glog.Fatalf("Error building kubeconfig: %s", err.Error())}crontabClient, err := clientset.NewForConfig(cfg)if err != nil {glog.Fatalf("Error building example clientset: %s", err.Error())}// informerFactory ⼯⼚类，这⾥注⼊我们通过代码⽣成的 client// clent 主要⽤于和 API Server 进⾏通信，实现 ListAndWatchcrontabInformerFactory := externalversions.NewSharedInformerFactory(crontabClient, time.Second*30)// 实例化⾃定义控制器controller := NewController(crontabInformerFactory.Stable().V1beta1().CronTabs())// 启动 informer，开始List & Watchgo crontabInformerFactory.Start(stopCh)if err = controller.Run(2, stopCh); err != nil {klog.Fatalf("Error running controller: %s", err.Error())}}func NewController(informer informers.CronTabInformer) *Controller {//使⽤client 和前⾯创建的 Informer，初始化了⾃定义控制器controller := &Controller{informer: informer,// WorkQueue 的实现，负责同步 Informer 和控制循环之间的数据workqueue: workqueue.NewNamedRateLimitingQueue(workqueue.DefaultControllerRateLimiter(), "CronTab"), }("Setting up crontab event handlers")// informer 注册了三个 Handler（AddFunc、UpdateFunc 和 DeleteFunc）// 分别对应 API 对象的“添加”“更新”和“删除”事件。
机电工程英语词典以下为您提供 20 个关于机电工程的相关内容，包括英语释义、短语、单词、用法和双语例句：---## 单词 1: Motor （[ˈməʊtə(r)] ）**英语释义**：A machine that converts electrical energy into mechanical energy to produce movement.**短语**：electric motor（电动机）**用法**：作名词，指“发动机；马达；电动机”**双语例句**：The motor of the car broke down.（汽车的发动机坏了。
）This electric motor is very powerful.（这台电动机功率很大。
）## 单词 2: Generator （[ˈdʒenəreɪtə(r)] ）**英语释义**：A machine that converts mechanical energy into electrical energy.**短语**：power generator（发电机）**用法**：作名词，指“发电机；发生器”**双语例句**：The generator provides electricity for the entire factory.（这台发电机为整个工厂供电。
）A wind generator can produce clean energy.（风力发电机可以产生清洁能源。
）## 单词 3: Circuit （[ˈsɜːkɪt] ）**英语释义**：A closed path through which an electric current flows.**短语**：electric circuit（电路）**用法**：作名词，指“电路；巡回；一圈”**双语例句**：There is a fault in the circuit.（电路有故障。
《计算机英语（第4版）》练习参考答案Unit One: Computer and Computer ScienceUnit One/Section AI.Fill in the blanks with the information given in the text:1. Charles Babbage; Augusta Ada Byron2. input; output3. VLSI4. workstations; mainframes5. vacuum; transistors6. instructions; software7. digit; eight; byte8. microminiaturization; chipII.Translate the following terms or phrases from English into Chinese and vice versa:1. artificial intelligence 人工智能2. paper-tape reader 纸带阅读器3. optical computer 光计算机4. neural network 神经网络5. instruction set 指令集6. parallel processing 并行处理7. difference engine 差分机8. versatile logical element 通用逻辑元件9. silicon substrate 硅衬底10. vacuum tube 真空管11. 数据的存储与处理the storage and handling of data12. 超大规模集成电路very large-scale integrated circuit13. 中央处理器central processing unit14. 个人计算机personal computer15. 模拟计算机analogue computer16. 数字计算机digital computer17. 通用计算机general-purpose computer18. 处理器芯片processor chip19. 操作指令operating instructions20. 输入设备input deviceIII.Fill in each of the blanks with one of the words given in the following list, making changes if necessary:We can define a computer as a device that accepts input, processes data, stores data, and produces output. According to the mode of processing, computers are either analog or digital.They can also be classified as mainframes, minicomputers, workstations, or microcomputers.All else (for example, the age of the machine) being equal, this categorization provides somespeed, size, cost, and abilities.indication of th e computer’sEver since the advent of computers, there have been constant changes. First-generation computers of historic significance, such as UNIVAC(通用自动计算机), introduced in the early 1950s, were based onvacuum tubes. Second-generation computers, appearing in the early 1960s, were those in which transistors replaced vacuum tubes. In third-generation computers, dating from the 1960s,integrated circuits replaced transistors. In fourth-generation computers such as microcomputers, which first appeared in the mid-1970s, large-scale integration enabled thousands of circuitsto be incorporated on onechip. Fifth-generation computers are expected to combine very-large-scale integration with sophisticated approaches to computing, including artificial intelligence and true distributed processing.IV. Translate the following passage from English into Chinese:计算机将变得更加先进，也将变得更加容易使用。
编译原理名词解释1. 词法分析器（Lexer）：也称为扫描器（Scanner），用于将源代码分割成一个个单词（Token）。
2. 语法分析器（Parser）：将词法分析器生成的单词序列转换成语法树（Parse Tree）或抽象语法树（Abstract Syntax Tree）。
3. 语法树（Parse Tree）：表示源代码的语法结构的树状结构，它由语法分析器根据语法规则生成。
4. 抽象语法树（Abstract Syntax Tree）：比语法树更加简化和抽象的树状结构，用于表示源代码的语义结构。
5. 语义分析器（Semantic Analyzer）：对抽象语法树进行语义检查，并生成中间代码或目标代码。
6. 中间代码（Intermediate code）：一种介于源代码和目标代码之间的中间表示形式，可以被不同的优化器和代码生成器使用。
7. 目标代码生成器（Code Generator）：将中间代码转换成特定目标平台的机器代码。
8. 优化器（Optimizer）：用于对中间代码进行优化，以提高代码的执行效率和资源利用率。
9. 符号表（Symbol Table）：用于存储程序中的标识符（变量、函数等）的信息，包括名称、类型等。
10. 语言文法（Grammar）：定义了一种语言的语法规则，常用的形式包括上下文无关文法和正则文法。
11. 上下文无关文法（Context-free Grammar）：一种形式化的语法表示方法，由产生式和非终结符组成，描述一种语言的句子结构。
12. 语言解释器（Interpreter）：将源代码逐行解释执行的程序，不需要生成目标代码。
13. 回溯法（Backtracking）：一种递归式的算法，用于在语法分析过程中根据产生式进行选择。
14. 正则表达式（Regular Expression）：用于描述一类字符串的表达式，可以用于词法分析中的模式匹配。
15. 自顶向下分析（Top-down Parsing）：从文法的起始符号开始，按照语法规则逐步构建语法树的过程。
A Code-Generator Generator for Multi-Output InstructionsHanno Scharwaechter,Rainer Leupers, Gerd Ascheid and Heinrich MeyrIntegrated Signal Processing SystemsRWTH Aachen University,Germany Jonghee M.Y oun and Yunheung Paek Software Optimization&RestructuringResearch GroupSeoul National University,KoreaABSTRACTWe address the problem of instruction selection for Multi-Output Instructions(MOIs),producing more than one result.Such inher-ently parallel hardware instructions are very common in the area of Application Specific Instruction Set Processors(ASIPs)and Digi-tal Signal Processors(DSPs)which are frequently used in System-on-Chips as programmable cores.In order to provide high-level programmability,and consequently guarantee widespread accep-tance,sophisticated compiler support for these programmable cores is of high importance.Since it is not possible to model Multi-Output Instructions as trees in the compiler’s Intermediate Rep-resentation(IR),traditional approaches for code selection are not sufficient.Extending traditional code-generation approaches for MOI-selection is essentially a graph covering problem,which is known to be NP-complete.We present a new heuristic algorithm incorporated in a retargetable code-generator generator capable of exploiting arbitrary inherently parallel MOIs.We prove the concept by integrating the tool into the LCC compiler which has been tar-geted towards different Instruction Set Architectures based on the MIPS architecture.Several network applications as well as some DSP benchmarks were compiled and evaluated to obtain results. Categories and Subject DescriptorsC.3[Special Purpose and Application Based Systems]:[Micro-processor/Microcomputer Systems]General TermsDesignKeywordsCompiler/Architecture Co-Design,Code-Selection,ASIP,ISS 1.INTRODUCTIONDesign and development of embedded processors are usually done under very tight constraints.The processors have to handle high data rates either in digital signal or network protocol processing, consume as little power as possible and have to be programmable in order to guarantee reusability towards different applications.There-fore,particularly in protocol processing,Application Specific In-struction Set Processors(ASIPs)are more and more applied as Intellectual Property-blocks in System-On-Chips,since they offer a good compromise between efficiency andflexibility.Typically, ASIPs provide a set of special instructions,tailored to the needs of their target applications.The predominant feature of these instruc-tions is inherent parallelism.The instructions comprise several par-allely executed operations like ADD,MUL,MAC etc.and producePermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on thefirst page.To copy otherwise,to republish,to post on servers or to redistribute to lists,requires prior specific permission and/or a fee.CODES+ISSS’07,September30–October3,2007,Salzburg,Austria. Copyright2007ACM978-1-59593-824-4/07/0009...$5.00.multiple results at the same time.Consequently they are referred to as Multi-Output Instructions(MOIs).Figure1:IR-Patterns for Different InstructionsIt is exactly this property which makes the difference between MOIs and other kinds of instructions.Whereas simple instructions (figure1(a))and chained instructions(figure1(c))can be repre-sented as tree patterns in the IR,MOIs will always have a fanout larger than one(figure1(b)).In the area of digital signal processing,MOIs are already a nat-ural way to increase code performance.Prominent examples are instructions to support access of different memory banks at the same time.For example in Sony pDSP processor,an instruction such as PLDXY r1,@a,r2,@b can load variables a and b from memory into registers r1and r2simultaneously.These instructions can access memory faster by performing loads and stores in par-allel on partitioned memory banks using parallel data and address buses.Designers for embedded DSPs prefer such techniques over more complicated hardware mechanisms.By the encapsulation of parallel operations in hardware instructions,impressive speedups can also be obtained for protocol processing without sacrificing too muchflexibility for the implementation of applications[22]. However,the increasing complexity of network protocols makes it prohibitively difficult to implement them in assembly language. Sophisticated compiler support is therefore strongly demanded in order to guarantee fast application development and consequently consumer acceptance for a processor.This implies the problem of handling MOIs by a compiler which is currently not possible,since typical compilers rely on tree parsing[1]during the code selection phase.If the target processor architecture contains inherently par-allel instructions,the code produced by tree parsing may strongly deviate from the optimum.The reason for this is that the scope of tree parsing is restricted to Data-flow Trees(DFTs).Consequently, instructions comprising functionality that exceeds the scope of one DFT cannot be matched by tree parsing,as their associated IR-patterns features a fan-out larger than one.In order to overcome this,the scope has to be extended at least to the size of a basic block which is then represented as a Data-flow Graph(DFG).Unfortu-nately,pattern matching on DFGs is NP-complete in general[24]. Usual approaches to solve this problem rely on Compiler Known Functions(CKFs)and Inline Assembly.In both cases,the applica-tions have to be modified manually which may lead to overhead for big applications.Additionally,the extremely heterogeneous landscape of applica-tion specific architectures demands for highlyflexible programming tools.Such architectures are usually developed in an iterative man-ner during which the architecture is incrementally refined.Obvi-ously,compilers have to be easily retargetable in order to support ar-bitrary kinds of instruction sets during the processor development. There exists several code-generator generators(such as Burg[9], Iburg[8],Olive[23])which produce code-selector descriptions in C.Such code-selector descriptions can be very comfortably inte-grated into existing compiler backends.Basically,such a code-generator generator accepts a tree grammar as input which mod-els the instruction set of the underlying target architecture in terms of IR-patterns.Based on this grammar,C code for instruction se-lection is produced.Since this tree grammar only comprises tree patterns,the produced code-selectors lack of capability to exploit Multi-Output Instructions.In this paper a new tool is presented that extends the concept of tree-based code-selector generators towards a graph-based code-selector generator called Cburg.Cburg extends the concept of the mentioned traditional tools in the way that the grammar is changed and a graph-based matching algorithm is produced such that Multi-Output Instructions can be modeled and matched.Thereby,manual insertion of inline assembly or CKFs into the application is omitted. The concept is proven by integrating Cburg into the LCC compiler [3]which has been targeted for an extended ASIP based on the MIPS architecture[19].The remainder of this paper is organized as follows:In the follow-ing section2,related work on code selection for embedded proces-sors is mentioned and our contribution is put into the context.Sec-tion3explains the developed heuristic algorithm to exploit MOIs during the code selection phase.Subsequently,the retargetable im-plementation of the algorithm is introduced in section4and experi-mental results are presented in section5.The paper concludes with section6.2.RELATED WORKDue to the limitations of tree parsing,several contributions have been published in the past,dealing with a generalization of tree-based code selection.In[7],optimal graph-based code selection is described for regular data path architectures without instruction level parallelism.However,ASIPs mostly feature irregular Instruc-tion Set Architectures(ISAs)comprising parallel instructions.Es-pecially for the domain of signal processing,where it is most nat-ural to have MOIs,further approaches have been developed for irregular architectures.Araujo presents a solution to effectively break up the DFG into expression trees while taking irregular reg-ister architectures into account[2].It is shown in[15]that tree parsing leads to suboptimal results in the presence of MOIs.To overcome this,a new technique based on the splitting of instruc-tions into register transfer primitives and recombining these prim-itives in an optimal manner using integer linear programming is proposed.Liao solves the same problem by augmenting a binate covering formulation[16].Unfortunately,Liao does not provide results on the applicability of their algorithm.Furthermore,both approaches[15,16]feature exponential runtime in the worst case based on the size of considered DFGs.This might be disadvanta-geous for large benchmarks.Liem[17]has proposed a graph-based instruction selection methodology that features aflexible pattern representation style.This style includes data-flow,control-flow and mixed data/control-flow informations.In[6],a code selec-tion methodology is described for complete functions in order to take controlflow into account.A Static Single Assignment(SSA)-Representation is used as IR and the pattern matching is solved nu-merically.As the code selection was tested for a Very Long Instruc-tion Word(VLIW)-processor,instruction level parallelism in terms of MOIs is not an issue for this approach.The most recent ap-proach to graph-based code selection is presented in[4].The paper targets code selection algorithms for hardware accelerators based on unate covering.As the authors only consider single connected IR-patterns,Multi-Output Instructions are not in the paper’s scope. In contrast,Multi-Output Instructions can also comprise multiple independent patterns on IR-level.Summarized,the existing approaches either feature exponential runtime on the size of considered DFGs or do not consider inher-ent instruction parallelism producing multiple results.Our contri-bution within this paper is the presentation of a new tool called Cburg.Cburg is very similar to well known code-selector genera-tors like Iburg or Olive.The difference between Cburg and other tools isfirstly the kind of accepted input grammar and secondly, the produced algorithm to match IR-patterns.In contrast to other tools,Cburg’s grammar is not restricted to tree patterns and there-fore capable to model arbitrary inherently parallel instruction pat-terns.Furthermore,Cburg produces C-code for a graph-based in-struction selection algorithm based on the received grammar such that the matching scope for pattern matching is not limited to single statement trees.The algorithm’s average runtime is linear w.r.t.the size of input DFGs.This approach results in an easily retargetable graph-based code-selector which enables compiler designers to pro-vide quickly new compiler backends for irregular instruction sets.3.CODE SELECTION ALGORITHM During code selection each DFT is processed by two phases:the matcher and the cover phase.The matcher traverses the DFT in bottom-up manner and applies a tree grammar in order to annotate at each visited node rules,according costs and resulting nontermi-nals(NTs)that can be used to match it.The cover algorithm then traverses the DFT in top-down manner and takes advantage of the annotated information for the selection of the rule with minimal costs for each node.For every hardware instruction,rules exist in the tree grammar of the form:NT→opcode(op1,...op n)|{z}simple rule{costs}={actions}.(1)In(1),opcode designates the rule’s operator(MUL,ADD, etc.)which is used as its IR-node name at the same time and {op1...op n}represent the operands of the rule.Additionally, rules typically comprise costs and action-sections.As the names imply,costs are computed in the costs-section and the action-section contains C code to emit assembly or lowered IR code. Since this presentation is not sufficient for Multi-Output Instruc-tions,Cburg’s grammar extends this concept of rules in the way that rules have the form:NT1,NT2,···→opcode1(op1,...)|{z}split rule,opcode2(op1,...)|{z}split rule, (2)In(2),multiple nonterminals NT1,NT2...are produced by a complex rule.The complex rule comprises several rules as pre-sented in(1)as well as costs-and action-sections which are not shown in(2).Before starting to explain the algorithm,the terminologies which will be used throughout the remainder of this document are defined. A•rule:represents an instruction pattern in the tree grammar,•simple rule:represents a typical tree pattern like ADD, MUL,MAC,•complex rule:consists of several simple rules,•split rule:is a simple rule that is a member of a complex rule.As shown infigure2,the presented algorithm consists of5major phases:Split Rule Extraction,Pattern Matching,Split Rule Identi-fication,Candidate Set Selection and Pre-Cover.First,all complex rules in the tree grammar are analyzed and split up into their split rules(subsection3.1).These split rules are used to find candidate nodes in the IR,representing operations that are part of some MOI.The labeler(subsection3.1)annotates simple rules and all split rules at each candidate node where they match.After annotating the rules,a split rule map is created which contains split rules and related ing this map,candidate node sets are identified for every complex rule,such that a clear picture exists about all possible covering solutions.During the subsequent set se-lection phase(subsection3.2),the dataflow of the different nodeFigure2:Algorithm Overviewsets is examined in order to eliminate invalid sets.Furthermore, the remaining sets are evaluated by a new cost metric which has been introduced to compare the costs of simple and split rules.In case of overlapping candidate sets,additionally the most valuable sets have to be selected.This decision is mapped to the problem offinding the Maximum Weighted Independent Set(MWIS)of a graph.Finally,the resulting candidate sets for all complex rules are selected and checked whether every candidate can be really cov-ered by the associated complex rule(subsection3.3).At the end, a normal cover algorithm can process the output of the presented heuristic,emitting valid assembly code.3.1Labeling&Split Rule IdentificationIn contrast to normal tree-parsers which annotate at each node for every nonterminal only those rules with minimal costs,the devel-oped labeler annotates additionally all matched split rules at each node regardless of their costs and nonterminals.For this,split rules are extracted from each complex rule and rule numbers are assigned to them which act as identifiers.Figure3gives an example about this procedure.In the upper half offigure3,a tree grammar is given by its simple and complex rules.These rules are annotated at the nodes of the IR tree in the lower half offigure3.At nodes5and 10both split rules and simple rules are annotated,each of which is producing the same nonterminal.For sake of simplicity,costs and produced nonterminals are not presented within thisfigure.After the labeling phase,a split rule map is created that stores node–split rule combinations.Succeeding phases can use the information of this map tofigure out candidate node sets for every split rule,e.g. node5is a candidate for split rule11.3.2Candidate Set SelectionDuring the candidate selection phase the best candidate node sets (CS)for all MOIs are identified and evaluated.For this purpose, the information of the split rule map is applied.A candidate set of a MOI contains all valid combinations of nodes for this instruction.A valid node combination designates a set of candidate nodes each of which is matched by a different split rule of the same complex rule. Since candidate nodes can also be complete tree patterns like MAC, only the root nodes are stored inside a candidate set:Root nodes are those nodes which have no successor node inside their pattern.For the example given infigure3,the only node set for complex rule10 is{5,10}.The number of node sets is further reduced by checking data dependencies in the DFG between candidate nodes and elimi-nating node sets containing dependent nodes.The remaining node sets are evaluated in order to maximize the benefit of code selection. The set evaluation takes place in relation to the other available rules for a certain node.The basis for this evaluation is obviously the cost metric of the rules.Unfortunately,the typical cost evaluation of tree patterns is also not sufficient for the evaluation of MOIs.Tra-ditional cost metrics for rules concern onlyfixed costs of rules like the number of emitted instructions.However,applying complex rules affects several statement trees and therefore,causesdifferentFigure3:Labelingcosts in different statement trees at the same time which depend strongly on the ongoing matching situation.Such costs can be de-scribed as dynamic or opportunity costs which are orthogonal to the fixed costs of simple rules.3.2.1Cost Computation for Complex RulesIf an IR-node can be matched by a simple rule(rule smpl)and a split rule(rule split)which are reduced to the same nonterminal, Cburg compares the costs of the simple rule and the costs of the split rule to determine the best covering solution for this node.The cost computation of a complex rule(rule cplx),consists of two parts: Saved Costs and Duplication Costs:Saved Costs.C saved(CS)designates the difference offixed costs between a covering solution with simple rules and a solution with a complex rule for a certain candidate set:C saved(CS)=(Xnodes∈CSC fix(rule smpl))−C fix(rule cplx)where Cfix describes thefixed costs of arbitrary rules(sim-ple/complex),producing the same nonterminal.Duplication Costs.C dup(CS)are produced by the appearance of Common Subexpres-sions(CSEs)inside of a node pattern in the IR that can be covered by a split rule.Split rule patterns(SRP)can express arbitrary tree patterns like MAC or other chained instructions,consisting of sev-eral sub-nodes.The set of sub-nodes can be separated into the root node(R)and the child nodes(K).In contrast to the root node whose result represents the result of the SRP,every child node has exactly one successor inside the pattern of the split rule.If a CSE is covered by a child node of an SRP its result is not available anymore for suc-cessor nodes outside the SRP since chained instructions compute only one result.Therefore,the node has to be duplicated in order to compute the result and maintain the validity of the produced as-sembly code.Accordingly,we defineK(CS)={node|node∈{SRP}∧node=R}CSE(CS)={node∈K(CS)|node is a CSE}C dup(CS)=Xnode∈CSE(CS)(Xfan out(node)C fix(rule smpl))Here,fan out denotes the number of outgoing edges of a node∈K(CS)emanating the SRP.For each of these edges, C fix(rule smpl)represents the costs of the according simple rule that produces the required nonterminal for the successor node.Opportunity Costs.C opp(CS)of a candidate set are the costs that denominate the overall cost-difference between the application of a complex rule and an alternative covering by a set of simple rules for the nodes in the CS:C opp(CS)=C saved(CS)−C dup(CS).Split Rule Costs.Finally,the costs of the split rule are calculated by the average op-portunity costs of the complex rule’s candidate set:C(rule split)=C fix(rule split)−C average opp(CS) where C fix(rule split)are thefixed costs of the split rule.Further-more,the average opportunity costs C average opp(CS)of a candi-date set CS are computed as:C average opp(CS)=C opp(CS)/num split(CS), where num split(CS)is the number of split rules of a candidate set.3.2.2Benefit OptimizationAfter the candidate validation,the candidate sets cannot be further reduced and the remaining nodes have to be covered by the accord-ing complex rules.Nevertheless,it might happen that intersections between candidate sets occur.This is the case when a node is a candidate for several MOIs and consequently is listed in several candidate sets.We call such nodes shared nodes.Since nodes can only be covered by one rule,the covering decision for shared nodes has to ensure that the benefit in terms of costs is maximized.The problem offinding an optimal solution for the covering of shared nodes can be reduced to the problem offinding a Maximum Weighted Independent Set(MWIS)in a weighted undirected graph G=(V,E,W)without loops and multiple edges.In G,V des-ignates the set of vertices,E the set of edges and W is the vertex weighting function.An independent set in a graph is a collection of vertices that are mutually non-adjacent.The problem offinding an independent set of maximum cardinality is one of the fundamental combinato-rial problems and known to be NP-complete even when all nodes have uniform weights[10].Due to this,we applied a heuristic called GWMIN2[21].Generally,GWMIN2belongs to the class of minimum-degree greedy algorithms that construct an independent set by selecting some vertex of minimum degree,removing it and its neighbors from the graph and iterating on the remaining graph until it is empty.Such algorithms run in linear time in the number of vertices and edges.GWMIN2selects in each iteration a vertex v,such thatW(v)Pw∈N+G(v)W(w),∀u∈V(3)is maximized.In[21]it is proven that the resulting independent set has at least a weight ofX v∈VW(v)2Pu∈N+G(v)W(u).The notation N G(v)designates the neighborhood of a vertex v in G and N+G(v)the set{v}∪N G(v).Application of MWISP for Benefit Maximization.For the benefit maximization in the presence of overlapping MOIs, a graph G=(V,E,W)is constructed.In G,every vertex v∈V represents a complex rule and the associated weight W(v)is equal to its benefit.Basically,the benefit of a MOI is com-puted as the negated sum over all costs of comprised split rules: (−1)PC rulesplit(CS).In between two vertices of G an edge exists,if and only if the associated MOIs have one or more candi-date IR-nodes in common.The algorithm now simply selects those non-adjacent vertices with the highest weight(benefit)in a greedy manner and eliminates them including their edges form the graph G.3.3Pre-Cover PhaseIn the last phase of the algorithm,the node selection has to be evaluated and pre-covered before the original cover phase starts, since split rules do not necessarily offer minimal costs for every producible nonterminal at a candidate node.Consequently,due to different nonterminal requirements of subsequent IR-nodes,a can-didate node might not be covered by a split rule although the split rule has minimal costs regarding its produced nonterminal.In this case,it must be ensured that all other nodes of the same candidate set are also not covered by their split rules.This is achieved by pre-covering the IR.During this,the cover phase of a tree pattern matcher is simulated and in case a candidate node is not covered by a split rule,all nodes of the according candidate set are re-matched by simple rules.Figure4:Pre-Covering NodesFigure4(a)shows an example of such a situation.It presents a set of IR-trees which are already labeled,and also a selected set of candidate nodes which are marked by their associated split rules 11and12offigure3.In Figure4(b),split rule12is not used for covering,since the succeeding rule consumes a nonterminal that is cheaper produced by simple rule2.However split rule11is used for covering at the same time.To solve this antagonism,the split rules are eliminated and all candidate nodes are re-matched by simple rules as presented infigure4(c).Now,the IR-trees can be traversed by the cover phase and the assembly code is emitted.3.4Complexity AnalysisThe basis of the code selection algorithm introduced in section3, relies on a depth-first traversal of a DF G=(V,E)in O(V+E) time in the labelling phase.Additional cost computations in order to maximize the benefit of code selection are applied at each node. These computations can be split into two parts:the computation of C saved and C opp.Whereas the former can be computed linearlydependent on the number of candidate nodes for all MOIs,the lattercomputation takesO(XCS⊆V,V∈DF GXCSE⊂CS|Adj(CSE(CS))|)time.In worst case,this might evolve to an exponential runtime, if every node v∈V is a CSE and at the same time covered by a split rule.Furthermore,in case of overlapping MOI patterns–the MWISP is solved by a greedy heuristic that runs in linear time,de-pendent on the amount of overlapped MOIs.Thefinal pre-cover phase visits all nodes in every candidate set once.Thereby its com-plexity can be expressed asO(XCS⊆V,V∈DF G|CS|)which also equals a linear runtime.Overall,the worst case runtime is exponential on the number of CSEs covered by split rules,but it is linear on the size of considered DFGs.4.RETARGETABLE CODE SELECTIONWITHIN CBURGApart from efficient code selection in the presence of MOIs,retar-getable compilation is the second aspect that this paper targets.Re-targetable compilation for high-level languages like C/C++is one of the major challenges in ASIP architecture exploration.Nonethe-less,iterative architecture exploration approaches demand for very flexible software development tools,in order to explore many archi-tecture design alternatives within short time.In this context,many design platforms including retargetable compilers have been de-veloped in the past[11,12,20,14].As presented infigure5(a), designflow iterations comprise usually the compilation,simula-tion and profiling of C/C++applications for a certain virtual ar-chitecture prototype.Based on the profiling results,bottlenecks are identified,the instruction pipeline isfine-tuned and customized instructions are added to stepwise improve the architecture’s effi-ciency.The new instructions are declared to the compiler in order to evaluate their benefit for the targeted applications during the next compilation-simulation cycle.Whereas simple instructions can be declared within the tree grammar of the code selector,MOIs are typically implemented as CKFs or inline assembly as they cannot be targeted by the compiler.This implies the manual modification of the application and the compiler,respectively which leads to high overhead for large applications.Since usually only the bottlenecks itself are implemented through MOIs,further utilization of the de-veloped MOIs stays unexplored and reusability towards different applications cannot be ensured.To support a maximum of different compilation frameworks and to overcome the compiler-related limitations within architecture ex-ploration,the described code selection algorithm has been incorpo-rated into a retargetable code-generator generator called Cburg. Cburg is based on Olive[23]which takes a configurationfile as input and produces a set of data structures and code-generation functions for a certain target ISA.However,in contrast to Olive, Cburg’s code selection algorithm works on DFGs rather on DFTs as described in section3.Cburg’s configurationfile is very similar to Olive.Thefile contains the description of the target ISA in terms of IR-patterns as well as a set of functions,necessary to access the compiler’s IR.The IR-patterns represent the grammar that is used to identify patterns in the compiler’s IR and map them to adequate assembly language or lowered IR.Rules inside this grammar have the form of both,rule2 and rule1(see section3).The generated data structures and func-tions provide the complete methodology based on the described al-gorithm.Compiler designers can use these to comfortably implement a code selection algorithm for arbitrary target machines with MOIs. Thereby it is possible to declare every kind of hardware instruc-tion to the compiler and the necessity to manually modify source applications or the compiler itself is omitted(figure5(b)).Figure5:Traditional vs.New Design Flow5.EXPERIMENTAL RESULTSIn order to evaluate the quality of the proposed code selection methodology to facilitate a more efficient instruction set design, Cburg has been integrated into the Little C Compiler(LCC)[3].As the target architecture,the MIPS architecture[19]has been used. Based on the MIPS ISA,new MOIs have been developed.The nomenclature of each MOI mirrors through the concatenation of instruction names,the parallel operations inside the MOI.For ex-ample,an instruction”lwlw”describes the simultaneous execution of two”lw”which is a simple load in the MIPS ISA.The bench-mark suite comprises typical symmetric encryption algorithms as the Data Encryption Standard(3DES),and the Advanced Encryp-tion Standard(AES)[5].and an internet protocol stack that com-prises an IPv6-layer including authentication,encryption as well as an Ethernet layer.Additionally,an Adaptive Differential Pulse Code Modulation(ADPCM)DSP-application taken from the DSP-Stone benchmark suite[18]has been examined.To develop new MOIs,all benchmarks have been profiled with afine-grained pro-filer[13]to identify execution hot spots and promising candidate instructions.Several MOIs have been developed giving special attention to the symmetric encryption algorithms,i.e.AES and 3DES.Since symmetric encryption is one of the major bottlenecks of IPv6processing[?],it was also expected that such MOIs will affect the overall performance of the protocol stack,too.From the profiling results,it turned out that shift(sll/srl),xor and load (lw)operations are most frequently used in the encryption algo-rithms.Consequently,the developed MOIs are based on these in-structions.First,all MOIs have been applied ter3and more MOIs have been combined.Table1provides an overview of the obtained experimental results.The best results have been achieved with the MOIs”lwsll”(+16.96%speedup/−13.99%code size)for3DES and”lwxor”(+12.83%speedup/−9.96%code size)for AES,respectively.Overall performance improvements of +24.07%(3DES),+21.76%(AES)and+17.21%(IP stack)were possible.Obviously,the MOIs did not lead to notable improve-ments for the ADPCM benchmark,since its operator usage signifi-cantly differs from those of encryption and protocol processing.6.CONCLUSIONThe presented code-generator generator Cburg,offers a new methodology to exploit MOIs during architecture explorations.In-stead of handcoding error prone inline assembly or CKFs,system designers can model all developed instructions in one grammarfile which is fed into the compiler’s code-selector.As a consequence, compiled applications comprise automatically all customized in-structions without any manual modification.Thereby the benefit of newly added MOIs can be faster evaluated.Furthermore,the evalu-ation is not restricted to isolated code fragments.Instead,the whole application is examined at once which leads to much more accurate results regarding usability and achieved code quality.Shorter de-sign cycles and time-to-market periods are the consequence.The general problem of code selection for MOIs relies on the fact, that at each IR-node,locally,a decision has to be made which af-fects the global result of the pattern matching process.The de-scribed formulas of subsection3.2.1provide Cburg with a powerful cost metric that is able to evaluate the quality of local decisions for the global result by taking so called opportunity costs of complex。
