AD8293G80ARJZ-R2中文资料

SPECIFICATION SHEETRobotsSCARASpecification Sheet | Page 1 of 2High performance and long reach for high-payload applications.Powerful performance with minimal overshoot — powered by Epson’s proprietary Residual Vibration TechnologyEasy to use — intuitive Epson RC+® development software makes it easy to create high performance solutionsOutstanding acceleration/deceleration rates — smooth start/stop motion to optimize cycle timesHigh-speed cycle times — maximize parts throughputIdeal for heavy payloads and high inertia applications — 800 and 1,000 mm reaches available, payload up to 20 kg, max. inertia up to 1.0 kg*m2Integrated options — vision, designed specifically for robot guidance; plus, parts feeding, fieldbus interface solutions, RC+ 7.0 API software for open-platform functionality, teach pendants and customizable GUIs ISO 4 Clean models available — for critical dust-free applicationsEasy setup — built-in camera cable for optional vision system; top-of-arm electrical and pneumatic layout with screw holes to mount additional equipment No battery required for encoder — minimizes downtime and eliminates the cost for battery replacement and installationLS20-B SCARA RobotSpecification Sheet | Page 2 of 2Specifications and terms are subject to change without notice. EPSON and Epson RC+ are registered trademarks, EPSONExceed Your Vision is a registered logomark and Better Products for a Better Future is a trademark of Seiko Epson Corporation. IntelliFlex is a trademark of Epson America, Inc. SmartWay is a registered trademark of the U.S. Environmental ProtectionAgency. All other product and brand names are trademarks and/or registered trademarks of their respective companies. Epson disclaims any and all rights in these marks. Copyright 2020 Epson America, Inc. Com-SS-Oct-13 CPD-58973 4/20Epson America, Inc.3840 Kilroy Airport Way, Long Beach, CA 90806Epson Canada Limited 185 Renfrew Drive, Markham, Ontario L3R 6G3 www.epson.caContact:1 Cycle time based on round-trip arch motion (300 mm horizontal, 25 mm vertical) with2 kg payload (path coordinates optimized for maximum speed). 2 SmartWay is an innovative partnership of the U.S. Environmental Protection Agency that reduces greenhouse gases and other air pollutants and improves fuel efficiency.See the latest innovations from Epson Business Solutions at /forbusiness。

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如需了解更详细的价格,封装,最小起订量,库存数量，性能,技术参数,替代产品等信息,请访问我公司首页,使用站内搜索工具查询或联系我公司业务代表!公司主页：电话：0662-669217AD790AQ 59.28元/个AD790JN 31.90元/个AD790JNZ 28.94元/个AD790JR 31.90元/个AD790JR-REEL 31.90元/个AD790JR-REEL7 31.90元/个AD790JRZ 28.94元/个AD790JRZ-REEL 28.94元/个AD790JRZ-REEL 728.94元/个AD8561AN 15.05元/个AD8561ANZ 13.88元/个AD8561AR 15.05元/个AD8561AR-REEL 15.05元/个AD8561AR-REEL7 15.05元/个AD8561ARU-REEL 15.05元/个AD8561ARUZ 13.80元/个AD8561ARUZ-REEL 13.80元/个AD8561ARZ 13.80元/个AD8561ARZ-REEL 13.80元/个AD8561ARZ-REEL7 13.80元/个ADAU1513ACPZ 24.57元/个ADAU1513ACPZ-RL 24.57元/个ADAU1513ACPZ-RL7 24.57元/个EVAL-SSM2319Z 389.22元/个EVAL-SSM2335Z 393.90元/个SSM2335CBZ-REEL 4.91元/个SSM2335CBZ-REEL7 4.91元/个EVAL-SSM2335Z 393.90元/个SSM2335CBZ-REEL 4.91元/个SSM2335CBZ-REEL7 4.91元/个AD8564AN 32.06元/个AD8564ANZ 29.09元/个AD8564AR 32.06元/个AD8564AR-REEL 32.06元/个AD8564AR-REEL7 32.06 元/个AD8564ARU-REEL 32.06 元/个AD8564ARUZ-REEL 29.09元/个AD8564ARZ 29.09元/个AD8564ARZ-REEL 29.09 元/个AD8564ARZ-REEL7 元/个 AD8611AR 17.39元/个AD8611AR-REEL 17.39 元/个 AD8611AR-REEL7 17.39元/个 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1/12L9823April 2003s OUTPUTS CURRENT CAPABILITY UP TO 0.5As CASCADABLE SPI CONTROL FOR OUTPUTSs RESET FUNCTION WITH RESET SIGNAL OR UNDERVOLTAGE AT V DDsPROGRAMMABLE INTRINSIC OUTPUT VOLTAGE CLAMPING AT TYP. 50V FOR INDUCTIVE SWITCHINGs OVERCURRENT SHUTDOWN WITH LATCH-OFF FOR EVERY WRITE CYCLE (SFPD = LOW)s INDEPENDENT THERMAL SHUTDOWN OF OUTPUTS (SOA PROTECTION)s OUTPUT STATUS DATA AVAILABLE ON THE SPI USING 8-BIT I/O PROTOCOL UP TO 3.0MHZ s LOW STANDBY CURRENT WITH RESET = LOW (TYP 35µA @ VDD)s OPEN LOAD DETECTION (OUTPUTS OFF)s SINGLE V DD LOGIC SUPPLYs HIGH EMS IMMUNITY AND LOW EME (CONTROLLED OUTPUT SLOPES)sFULL FUNCTIONALITY OF THE REMAINING DEVICE AT NEGATIVE VOLTAGE DROP ONOUTPUTS (-1,5V OR -3,0A)sOUTPUT MODE PROGRAMMABLE FOR SUSTAINED CURRENT LIMIT OR SHUTDOWNDESCRIPTIONL9823 is a Octal Low-Side Driver Circuit, dedicated for automotive applications. Output voltage clamping is provided for flyback current recirculation, when in-ductive loads are driven. Chip Select and cascadable Serial 8-bit Interface for outputs control and diagnos-tic data transfer.Octal Low-Side Driver for bulb, resistive and inductive loads withserial input control, output protection and diagnosticL9823PIN FUNCTIONN°Pin Description1Out 7Output 72Out 6Output 63SCLK SCLK. The system clock pin (SCLK) clocks the internal shift registers of the L9823. The serial input pin (SI) accepts data into the input shift register on the falling edge of the SCLK signal whilethe serial output pin (SO) shifts data information out of the shift register on the rising edge of theSCLK signal. False clocking of the shift register must be avoided to guarantee validity of data. Itis essential that the SCLK pin be in a logic low state whenever chip select bar pin (CSB) makesany transition. For this reason, it is recommended though not necessary, that the SCLK pin bekept in a low logic state as long as the device is not accessed (CSB in logic high state). WhenCSB is in a logic high state, any signal at the SCLK and SI pin is ignored and SO is tri-stated(high-impedance).4SI SI. This pin is for the input of serial instruction data. SI information is read in on the falling edge of SCLK. A logic high state present on this pin when the SCLK signal rises will program aspecific output OFF, and in turn, turns OFF the specific output on the rising edge of the CSBsignal. Conversely, a logic low state present on the SI pin will program the output ON, and inturn, turns ON the specific output on the rising edge of the CSB signal. To program the eightoutputs of the L9823 ON or OFF, an eight bit serial stream of data is required to be entered intothe SI pin starting with Output 7, followed by Output 6, Output 5, etc., to Output 0. For each riseof the SCLK signal, with CSB held in a logic low state, a databit instruction (ON or OFF) isloaded into the shift register per the databit SI state. The shift register is full after eight bits ofinformation have been entered. To preserve data integrity, care should be taken to not transitionSI as SCLK transitions from a low-to-high logic state.5GND GND6GND GND7GND GND8GND GND9SO SO. The serial output (SO) pin is the tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CSB pin goes to a logic low state. The SO datareports the drain status, either high or low. The SO pin changes state on the rising edge of SCLKand reads out on the falling edge of SCLK. When an output is OFF and not faulted, thecorresponding SO databit is a high state. When SO an output is ON, and there is no fault, thecorresponding databit on the SO pin will be a low logic state. The SI / SO shifting of data followsa first-in-first-out protocol with both input and output words transferring the Most Significant Bit(MSB) first. The SO pin is not affected by the status of the Reset pin.10CSB CSB. The system MCU selects the L9823 to be communicated with through the use of the CSB pin. Whenever the pin is in a logic low state, data can be transferred from the MCU to the L9823and vise versa. Clocked-in data from the MCU is transferred from the L9823 shift register andlatched into the power outputs on the rising edge of the CSB signal. On the falling edge of theCSB signal, drain status information is transferred from the power outputs and loaded into thedevice's shift register. The CSB pin also controls the output driver of the serial output pin.Whenever the CSB pin goes to a logic low state, the SO pin output driver is enabled allowinginformation to be transferred from the L9823 to the MCU. To avoid any spurious data, it isessential that the high-to-low transition of the CSB signal occur only when SCLK is in a logic lowstate.11Out 5Output 512Out 4Output 413Out 3Output 32/123/12L9823ABSOLUTE MAXIMUM RATINGSFor voltages and currents applied externally to the device. Exceeding limits may cause damage to the device .14Out 2Output 215SFPDSFPD. The Short Fault Protect Disable (SFPD) pin is used to disable the overcurrent latch-OFF.This feature allows control of incandescent loads where in-rush currents exceed the device's analog current limits. Essentially the SFPD pin determines whether the L9823 output(s) will instantly shutdown upon sensing an output short or remain ON in a current limiting mode of operation until the output short is removed or thermal shutdown is reached. If the SFPD pin is tied to VDD the L9823 output(s) will remain ON in a current limited mode of operation upon encountering a load short to supply. If the SFPD pin is grounded, a short circuit will immediately shutdown only the output affected. Other outputs not having a fault condition will operate normally.16VDD VDD 17GND GND 18GND GND 19GND GND 20GND GND21NC Not Connected22ResetReset. The Reset pin is active low and used to clear the SPI shift register and in doing so sets all output switches OFF. With the device in a system with an MCU; upon initial system power up,the MCU holds the Reset pin of the device in a logic low state ensuring all outputs to be OFF until the VDD pin voltages are adequate for predictable operation. After the L9823 is Reset, the MCU is ready to assert system control with all output switches initially OFF. The Reset pin is active low and has an internal pull-down incorporated to ensure operational predictability should the external pull-down of the MCU open circuit. The internal pull-up is to afford safe and easy interfacing to the MCU. The Reset pin of the L9823 should be pulled to a logic low state for a duration of at least 160ns to ensure reliable Reset.23Out 1Output 124Out 0Output 0N°Pin DescriptionPIN FUNCTION (continued)L98234/12Note1)All inputs are protected against ESD according to MIL 883C; tested with HBM C = 100pF, R = 1500Ω at ±2KV. It corresponds to a dissipated energy E ≤ 0.2mJ (data available upon request).2)Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3.3)Max. output clamp energy at T j = 150°C, using single non-repetitive pulse of 500mATHERMAL DATAELECTRICAL CHARACTERISTCS (4.5V ≤ V≤ 5.5V; -40°C ≤ T ≤ 150°C; unless otherwise specifiedABSOLUTE MAXIMUM RATINGS (continued)L9823 ELECTRICAL CHARACTERISTCS (continued)5/12L9823ELECTRICAL CHARACTERISTCS (continued)Outputs Control Tables :Outputs:SI-bit01Output on off 6/12L9823 Output Control register structure :Power outputs characteristicsfor flyback current, outputs short circuit protection and diagnosticsFor output currents flowing into the circuit the output voltages are limited. The typical value of this voltage is 50V. This function allows that the flyback current of a inductive load recirculates into the circuit; the flyback energy is absorbed in the chip.Output short circuit protection SFPD = Low (dedicated for loads without inrush current): when the output current exceeds the short circuit threshold, the corresponding output overload latch is set after a delay time t dly SCB and the output is switched off. The delay timer is started after each rise of CSB and valid datas are transfered to the output control register. If the short takes place after the delay time has elapsed the shutdown is immediate (with-in 15µs).Output short circuit protection SFPD = High (dedicated for loads with inrush current, as lamps): when the load current would exceed the short circuit limit value, the corresponding output goes in a current regulation mode. The output current is determined by the output characteristics and the output voltage depends on the load re-sistance. In this mode high power is dissipated in the output transistor and its temperature increases rapidly. When the power transistor temperature exceeds the thermal shutdown threshold, the overload latch is set and the corresponding output switched off.For the load diagnostic in output off condition each output features a diagnostic current sink, of typ 60µA. FUNCTIONAL DESCRIPTIONGeneralThe L9823 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using the Serial Peripheral Interface = SPI protocol. The power outputs features voltage clamping function for flyback current recirculation and are protected against short circuit to Vbat.The diagnostics recognizes two outputs fault conditions: 1) overcurrent and thermal overload in switch-ON con-dition and 2) open load or short to GND in switch-OFF condition for all outputs. The outputs status can be read out via the serial interface.The chip internal Reset is a OR function of the external Reset signal and internally generated undervoltage Re-set signal.7/12L9823Output Stages ControlEach output is controlled with its latch and with a common Reset line, which enables all outputs.The control data are transmitted via the SI input, the timing of the serial interface is shown in Fig. 1.The device is selected with low CSB signal and the input data are transferred into the 8 bit shift register at every falling SCLK edge. The rising edge of the CSB latches the new data from the shift register to the drivers.The SPI register data are transferred to the output latch at rising CSB edge. The digital filter between CSB and the output latch ensures that the data are transferred only after 8 SCLK cycles or multiple of 8 SCLK cycles since the last CSB falling edge. The CSB changes only at low SCLK.DiagnosticsThe output voltage at all outputs is compared with the diagnostic threshold, typ 0,55 • V DD = V DG. Diagnostic Table for outputs:Output Output-voltage Status-bit Output-mode off> DG-threshold high correct operationoff< DG-threshold low fault condition 2)on< DG-threshold low correct operationon> DG-threshold high fault condition 1)Fault condition 1) "output short circuit to Vbat" : For SFPD = Low the output was switched on and the voltage at the output exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the output has been switched off. The diagnostic bit is high.: For SFPD = High the output was switched on and the voltage at the output exceeds the diagnostics threshold. The output operates in current regulation mode or has been switched off due to thermal shutdown. The status bit is high.Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and the voltage at the output drops below the diagnostics threshold, because the load current is lower than the output diagnostic cur-rent source, the load is interrupted. The diagnostic bit is low.At the falling edge of CSB the output status data are transferred to the shift register. When SCB is low, data bits contained in the shift register are transferred to SO output at every rising SCLK edge.8/12L98239/12L9823APPLICATIONS INFORMATIONThe typical application diagram for parallel Input SPI control is shown in Figure 4.For higher current driving capability more outputs of the same kind can be paralleled. In this case the maximum flyback energy should not exceed the limit value for single output.The immunity of the circuit with respect to the transients at the output is verified during the characterization for Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test Pulses are coupled to the outputs with 200pF series capacitor. The correct function of the circuit with the Test Pulses coupled to the outputs is verified during the characterization for the typical application with R = 16Ω to 200Ω, L= 0 to 600mH loads. All outputs withstand testpulses without damage.10/12L982311/12L9823Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronics®2003 STMicroelectronics - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.12/12。

DescriptionIntended for analog and digital satellite receivers, this single low noise block converter regulator (LNBR) is a monolithic linear and switching voltage regulator, specifically designed to provide the power and the interface signals to an LNB down converter via coaxial cable. The A8293 requires few external components, with the boost switch and compensation circuitry integrated inside of the device. A high switching frequency is chosen to minimize the size of the passive filtering components, further assisting in cost reduction. The high levels of component integration ensure extremely low noise and ripple figures. The A8293 has been designed for high efficiency, utilizing the Allegro ® advanced BCD process. The integrated boost switch has been optimized to minimize both switching and static losses. To further enhance efficiency, the voltage drop across the tracking regulator has been minimized.For DiSEqC™ communications, several schemes are available for generating tone signals, all the way down to no-load, and using either the internal clock or an external time source.Features and Benefits▪ 2-wire serial I 2C™ -compatible interface: control (write) and status (read)▪ LNB voltages (7 programmable levels) compatible with all common standards▪ Tracking switch-mode power converter for lowest dissipation ▪ Integrated converter switches and current sensing ▪ Provides up to 700 mA load current▪ Static current limit circuit allows full current at startup and 13→18 V output transition; reliably starts wide load range ▪ Push-pull output stage minimizes 13→18 V and 18→13 V output transition times for highly capacitive loads▪ Adjustable rise/fall time via external timing capacitor ▪ Built-in tone oscillator, factory-trimmed to 22 kHz facilitates DiSEqC™ tone encoding, even at no-load ▪ Four methods of 22 kHz tone generation, via I 2C™ data bits and/or external pin ▪ Auxiliary modulation input ▪ LNB overcurrent with timer▪Diagnostics for output voltage level, input supply UVLOSingle LNB Supply and Control V oltage RegulatorContinued on the next page…Functional Block DiagramA8293L1Packages:20-contact, 4 × 4 mmMLP/QFN (suffix ES)28 contact, 5 × 5 mm MLP/QFN (suffix ET)Package Thermal Characteristics*Package R θJA (°C/W)PCB ES 37 (estimated)4-layer ET324-layer* Additional information is available on the Allegro website.Selection GuidePart Number Packing 1DescriptionA8293SESTR-T 27 in. reel, 1500 pieces/reel12 mm carrier tape ES package, MLP/QFN surface mount 4 mm × 4 mm × 0.75 mm nominal height A8293SETTR-T 2,37 in. reel, 1500 pieces/reel12 mm carrier tapeET package, MLP/QFN surface mount 5 mm × 5 mm × 0.90 mm nominal height1Contact Allegro for additional packing options.2Leadframe plating 100% matte tin.3This variant is in production but has been determined to be NOT FOR NEW DESIGN. This classi fi cation indicates that saleof this device is currently restricted to existing customer applications. The variant should not be purchased for new design ap-plications because obsolescence in the near future is probable. Status date change September 21, 2010.A comprehensive set of fault registers are provided, which comply with all the common standards, including: overcurrent, thermal shutdown, undervoltage, and power not good.The device uses a 2-wire bidirectional serial interface, compatible with the I 2C™ standard, that operates up to 400 kHz.The A8293 is supplied in two lead (Pb) free MLP/QFN packages: ES, 20-contact, 4 mm × 4 mm, 0.75 nominal overall height, and ET, 28-contact, 5 mm × 5 mm, 0.90 nominal overall height.Description (continued)Absolute Maximum RatingsCharacteristic SymbolConditionsRating UnitsLoad Supply Voltage, VIN pin V IN 30V Output Current*I OUTInternally Limited A Output Voltage; LNB and BOOST pins –1 to 33 V Output Voltage; LX pin –1 to 30V Output Voltage; VCP pin –1 to 41 V Logic Input Voltage, EXTM pin –0.3 to 5 V Logic Input Voltage, other pins –0.3 to 7 V Logic Output Voltage–0.3 to 7 V Operating Ambient Temperature T A –20 to 85 °C Junction Temperature T J (max) 150°C Storage TemperatureT stg –55 to 150°C*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed thespecified current ratings, or a junction temperature, T J , of 150°C.PAD1514131211123456789102019181716L N BG N DL XV I NN CN CG N DV R E GS D A A D D FLOAT GND NC SCL IRQBOOST VCP TCAP FLOAT EXTMTerminal List TableName Number FunctionES ET ADD 1011Address selectFLOAT 4, 155, 22These pins must not be connected to anything; do not ground these pins BOOST 11Tracking supply voltage to linear regulator EXTM 56External modulation input GND 7, 148, 19Signal ground GNDLX 1927Boost switch ground IRQ 1114Interrupt request LNB 2028Output voltage to LNB LX 1826Inductor drive point NC 6, 13, 164, 7, 13, 15-18, 20, 21, 23, 24No connectionPAD Pad PadExposed pad; connect to the ground plane, for thermal dissipation SCL 1212I 2C™-compatible clock input SDA 910I 2C™-compatible data input/outputTCAP 33Capacitor for setting the rise and fall time of the LNB output VCP 22Gate supply voltage VIN 1725Supply input voltage VREG89Analog supplyDevice Pin-out Diagram(Top View)PAD 21201918171615123456789101112131428272625242322L N BG N D L XL XV I N N C N CF L O A TG N DV R E GS D A A D D S C L N C I R Q NC NC GND NC NC NC NC BOOST VCP TCAP NC FLOAT EXTM NCES PackageET PackageELECTRICAL CHARACTERISTICS at TA= 25°C, V IN = 9 to 16 V, unless noted otherwise1Characteristics Symbol Test Conditions Min.Typ.Max.Units GeneralSet-Point Accuracy, Load and Line Regulation Err Relative to selected V LNB target level,I LOAD = 0 to 450 mA–3.0–+3.0%Supply Current I IN(Off)ENB bit = 0, LNB output disabled, V IN = 12 V––10.0mA I IN(On)ENB bit = 1, LNB output enabled,I LOAD = 0 mA, V IN = 12 V––19.0mABoost Switch On Resistance R DS(on)BOOST I LOAD = 450 mA–300–mΩSwitching Frequency f SW320352384kHz Switch Current Limit I LIMSW V IN = 9 V, V OUT = 19.0 V– 2.7–ALinear Regulator Voltage Drop∆V REG V BOOST – V LNB, no tone signal,I LOAD = 450 mA–800–mVTCAP Pin CurrentI CHG TCAP capacitor (C7) charging–12.5–10–7.5μA I DISCHG TCAP capacitor (C7) discharging7.51012.5μAOutput Voltage Rise Time2t r(VLNB)For V LNB 13 →18 V; C TCAP = 5.6 nF,I LOAD = 450 mA–500–μsOutput Voltage Pull-Down Time2t f(VLNB)For V LNB 18 →13 V; C LOAD = 100 μF,I LOAD = 0 mA–12.5–msOutput Reverse Current I RLNB ENB bit = 0, V LNB = 33 V , BOOST capacitor(C5) fully charged–15mARipple and Noise on LNB Output3V rip,n(pp)20 MHz BWL; reference circuit shown inFunctional Block diagram; contact Allegro foradditional information on application circuitboard design–30–mV PPProtection CircuitryOutput Overcurrent Limit4I LIMLNB V BOOST – V LNB = 800 mV–700800mA Overcurrent Disable Time t DIS–48–ms VIN Undervoltage Lockout Threshold V UVLO V IN falling7.057.357.65V VIN Turn On Threshold V IN(th)V IN rising7.407.708.00V Undervoltage Hysteresis V UVLOHYS–350–mV Thermal Shutdown Threshold2T J–165–°C Thermal Shutdown Hysteresis2∆T J–20–°C Power Not Good Flag Set PNG SET With respect to V LNB778593% Power Not Good Flag Reset PNG RESET With respect to V LNB829098% Power Not Good Hysteresis PNG HYS With respect to V LNB–5–% ToneTone Frequency f TONE202224kHz Tone Amplitude, Peak-to-Peak V TONE(pp)I LOAD = 0 to 450 mA, C LOAD = 750 nF400620800mVContinued on the next page…Tone Duty Cycle DC TONE I LOAD = 0 to 450 mA, C LOAD = 750 nF 405060%Tone Rise Time t rTONE I LOAD = 0 to 450 mA, C LOAD = 750 nF 51015μs Tone Fall Time t fTONE I LOAD = 0 to 450 mA, C LOAD = 750 nF51015μs EXTM Logic Input V EXTM(H) 2.0––VV EXTM(L)––0.8V EXTM Input Leakage I EXTMLKG–1–1μAI 2C™-Compatible Interface Logic Input (SDA,SCL) Low Level V SCL(L)––0.8V Logic Input (SDA,SCL) High Level V SCL(H) 2.0––V Logic Input Hysteresis V I2CIHYS –150–mV Logic Input CurrentI I2CI V I2CI = 0 to 7 V –10<±1.010μA Logic Output Voltage SDA and IRQ V t2COut(L)I LOAD = 3 mA ––0.4V Logic Output Leakage SDA and IRQ V t2CLKG V t2COut = 0 to 7 V––10μA SCL Clock Frequency f CLK ––400kHz Output Fall Timet fI2COut V t2COut(H) to V t2COut(L)––250ns Bus Free Time Between Stop/Start t BUF 1.3––μs Hold Time Start Condition t HD:STA 0.6––μs Setup Time for Start Condition t SU:STA 0.6––μs SCL Low Time t LOW 1.3––μs SCL High Time t HIGH 0.6––μs Data Setup Timet SU:DAT 100––nsData Hold Timet HD:DAT For t HD:DAT (min) , the master device must provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the SCL signal falling edge 0–900ns Setup Time for Stop Condition t SU:STO 0.6––μs I 2C™ Address SettingADD Voltage for Address 0001,000Address10–0.7V ADD Voltage for Address 0001,001Address2 1.3– 1.7V ADD Voltage for Address 0001,010Address3 2.3– 2.7V ADD Voltage for Address 0001,011Address43.3–5.0V1Operation at 16 V may be limited by power loss in the linear regulator.2Guaranteed by worst case process simulations and system characterization. Not production tested.3LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the Application Schematic and PCB layoutrecommendations. Not production tested.4Current from the LNB output may be limited by the choice of Boost components.ELECTRICAL CHARACTERISTICS (continued) at T A = 25°C, V IN = 9 to 16 V, unless noted otherwise 1CharacteristicsSymbol Test ConditionsMin.Typ.Max.Units I 2C™ Interface Timing DiagramHIGH LOW SDA SCLProtectionThe A8293 has a wide range of protection features and fault diag-nostics which are detailed in the Status Register section.Boost Converter/Linear RegulatorThe A8293 solution contains a tracking current-mode boost converter and linear regulator. The boost converter tracks the requested LNB voltage to within 800 mV, to minimize power dissipation. Under conditions where the input voltage, V BOOST , is greater than the output voltage, V LNB, the linear regulator must drop the differential voltage. When operating in these conditions, care must be taken to ensure that the safe operating temperature range of the A8293 is not exceeded.The boost converter operates at 352 kHz typical: 16 times the internal 22 kHz tone frequency. All the loop compensation, current sensing, and slope compensation functions are provided internally.The A8293 has internal pulse-by-pulse current limiting on the boost converter and DC current limiting on the LNB output to protect the IC against short circuits. When the LNB output is shorted, the LNB output current is limited to 700 mA typical, and the IC will be shut down if the overcurrent condition lasts for more than 48 ms. If this occurs, the A8293 must be reenabled for normal operation. The system should provide sufficient time between successive restarts to limit internal power dissipation; a minimum of 2 s is recommended.At extremely light loads, the boost converter operates in a pulse-skipping mode. Pulse skipping occurs when the BOOST voltage rises to approximately 450 mV above the BOOST target output voltage. Pulse skipping stops when the BOOST voltage drops 200 mV below the pulse skipping level.In the case that two or more set top box LNB outputs are con-nected together by the customer (e.g., with a splitter), it is pos-sible that one output could be programmed at a higher voltage than the other. This would cause a voltage on one output that is higher than its programmed voltage (e.g., 19 V on the output of a 13 V programmed voltage). The output with the highest voltage will effectively turn off the other outputs. As soon as this voltage is reduced below the value of the other outputs, the A8293 output will auto-recover to their programmed levels.Charge Pump.Generates a supply voltage above the internal tracking regulator output to drive the linear regulator control. Slew Rate Control. During either start-up, or when the output voltage at the LNB pin is transitioning, the output voltage rise and fall times can be set by the value of the capacitor connected from the TCAP pin to GND (C TCAP or C7 in the Applications Schematic). Note that during start-up, the BOOST pin is pre-charged to the input voltage minus a voltage drop. As a result, the slew rate control for the BOOST pin occurs from this voltage.The value of C TCAP can be calculated using the following for-mula:C TCAP = (I TCAP × 6) / SR ,where SR is the required slew rate of the LNB output voltage,in V/s, and I TCAP is the TCAP pin current specified in the data sheet. The recommended value for C TCAP, 10 nF, should provide satisfactory operation for most applications. However, in some cases, it may be necessary to increase the value of C TCAP to avoid activating the current limit of the LNB output. One such situa-tion is when two set-top boxes are connected in parallel. If this is the case, the following formula can be used to calculate C TCAP:C TCAP≥ (I TCAP × 6)(2 × C BOOST) / I LIMLNB ,C TCAP≥ (10 μA × 6)(2 × 100 μF) / 500 mA = 24 nF .The minimum value of C TCAP is 2.2 nF. There is no theoretical maximum value of C TCAP however too large a value will prob-ably cause the voltage transition specification to be exceeded. Tone generation is unaffected by the value of C TCAP .Pull-Down Rate Control.In applications that have to operate at very light loads and that require large load capacitances (in the order of tens to hundreds of microfarads), the output linear stage provides approximately 40 mA of pull-down capability. This ensures that the output volts are ramped from 18 V to 13 V in a reasonable amount of time.ODT (Overcurrent Disable Time)If the LNB output current exceeds 700 mA, typical, for more than 48 ms, then the LNB output will be disabled and the OCP bit will be set.Short Circuit HandlingIf the LNB output is shorted to ground, the LNB output current will be clamped to 700 mA, typical. If the short circuit condition lasts for more than 48 ms, the A8293 will be disabled and the OCP bit will be set.Auto-RestartAfter a short circuit condition occurs, the host controller should periodically reenable the A8293 to check if the short circuit hasFunctional Descriptionbeen removed. Consecutive startup attempts should allow at least 2 s of delay between restarts.In-Rush CurrentAt start-up or during an LNB reconfiguration event, a tran-sient surge current above the normal DC operating level can be provided by the A8293. This current increase can be as high as 700 mA, typical, for as long as required, up to a maximum of48 ms.Tone GenerationThe A8293 solution offers four options for tone generation, providing maximum flexibility to cover every application. The EXTM pin (external modulation), in conjunction with the I2C™ control bits: TMODE (tone modulation) and TGATE (tone gate), provide the necessary control. The TMODE bit controls whether the tone source is either internal or external (via the EXTM pin). Both the EXTM pin and TGATE bit determine the 22 kHz con-trol, whether gated or clocked.Four options for tone generation are shown in figure 1. Note that when using option 4, when EXTM stops clocking, the LNB volts park at the LNB voltage, either plus or minus half the tone signal amplitude, depending on the state of EXTM. For example, if the EXTM is held low, the LNB DC voltage is the LNB pro-grammed voltage minus 325 mV (typical).EXTM TMODE TGATE ToneEXTM TMODETGATE ToneEXTM TMODE TGATE ToneEXTM TMODE TGATE ToneOption 1 – Use internal tone, gated by the TGATE bit. Option 2 – Use internal tone, gated by the EXTM pin. Option 3 – Use external tone, gated by the TGATE bit. Figure 1. Options for tone generationI 2C™-Compatible InterfaceThis is a serial interface that uses two bus lines, SCL and SDA,to access the internal Control and Status registers of the A8293.Data is exchanged between a microcontroller (master) and theA8293 (slave). The clock input to SCL is generated by the master,while SDA functions as either an input or an open drain output,depending on the direction of the data.Timing ConsiderationsThe control sequence of the communication through the I 2C™-compatible interface is composed of several steps in sequence: 1. Start Condition. Defined by a negative edge on the SDA line,while SCL is high.2. Address Cycle. 7 bits of address, plus 1 bit to indicate read (1)or write (0), and an acknowledge bit. The first five bits of the address are fixed as: 00010. The four optional addresses, de-fined by the remaining two bits, are selected by the ADD input. The address is transmitted MSB first.3. Data Cycles. Write – 6 bits of data and 2 bits for addressing four internal control registers, followed by an acknowledge bit. See Control Register section for more information. Read – Two status registers, where register 1 is read first, followed by register 2, then register 1, and so on. At the start of any read sequence, register 1 is always read first. Data is transmitted MSB first.4. Stop Condition. Defined by a positive edge on the SDA line,while SCL is high. Except to indicate a Start or Stop condi-tion, SDA must be stable while the clock is high. SDA canonly be changed while SCL is low. It is possible for the Start or Stop condition to occur at any time during a data transfer. The A8293 always responds by resetting the data transfer sequence. The Read/Write bit is used to determine the data transfer direc-tion. If the Read/Write bit is high, the master reads the contents of 1 2 3 4 5 6 7 8 9SCL1 2 3 4 5 6 7 8 9SCL1 2 3 4 5 6 7 8 9SCL Write to RegisterRead One Byte from RegisterRead Multiple Bytes from RegisterFigure 2. I 2C™ Interface. Read and write sequences.register 1, followed by register 2 if a further read is performed. If the Read/Write bit is low, the master writes data to one of the two Control registers. Note that multiple writes are not permitted. All write operations must be preceded with the address.The Acknowledge bit has two functions. It is used by the mas-ter to determine if the slave device is responding to its address and data, and it is used by the slave when the master is reading data back from the slave. When the A8293 decodes the 7-bit ad-dress field as a valid address, it responds by pulling SDA low during the ninth clock cycle.During a data write from the master, the A8293 also pulls SDA low during the clock cycle that follows the data byte, in order to indicate that the data has been successfully received. In both cas-es, the master device must release the SDA line before the ninth clock cycle, in order to allow this handshaking to occur.During a data read, the A8293 acknowledges the address in the same way as in the data write sequence, and then retains control of the SDA line and send the data from register 1 to the master. On completion of the eight data bits, the A8293 releases the SDA line before the ninth clock cycle, in order to allow the master to acknowledge the data. If the master holds the SDA line low dur-ing this Acknowledge bit, the A8293 responds by sending the data from register 2 to the master. Data bytes continue to be sent to the master until the master releases the SDA line during the Acknowledge bit. When this is detected, the A8293 stops sending data and waits for a stop signal. Interrupt RequestThe A8293 also provides an interrupt request pin, IRQ, which is an open-drain, active-low output. This output may be connect-ed to a common IRQ line with a suitable external pull-up and can be used with other I 2C™-compatible devices to request attention from the master controller.The IRQ output becomes active when either the A8293 first recognizes a fault condition, or at power-on, when the main sup-ply, V IN , and the internal logic supply, V REG , reach the correct operating conditions. It is only reset to inactive when the I 2C™ master addresses the A8293 with the Read/Write bit set (caus-ing a read). Fault conditions are indicated by the TSD, VUV , and OCP bits, and are latched in the Status register. See the Status register section for full description.The DIS and PNG status bits do not cause an interrupt. The PNG bit is continually updated, apart from the DIS bit, which changes when the LNB is either disabled, faulted, or is enabled. When the master recognizes an interrupt, it addresses allslaves connected to the interrupt line in sequence, and then reads the status register to determine which device is requesting atten-tion. The A8293 latches all conditions in the Status register until the completion of the data read. The action at the resampling point is further defined in the Status Register section. The bits in the Status register are defined such that the all-zero condition in-dicates that the A8293 is fully active with no fault conditions. When V IN is initially applied, the I 2C™-compatible interface does not respond to any requests until the internal logic supply V REG has reached its operating level. Once V REG has reached this point, the IRQ output goes active, and the VUV bit is set. After the A8293 acknowledges the address, the IRQ flag is reset. After the master reads the status registers, the registers are updated with the VUV reset.Status Register 1Address Start R Stop1 2 3 4 5 6 7 8 9SCL IRQFaultEventReloadStatus RegisterRead after InterruptFigure 3. I 2C™ Interface. Read sequences after interrupt request.Control Registers (I2C™-Compatible Write Register) All main functions of the A8293 are controlled through the I2C™-compatible interface via the 8-bit Control registers. As the A8293 contains numerous control options, it is necessary to have two control registers. Each register contains up to 6 bits of data (bit 0 to bit 5), followed by 2 bits for the register address (bit 6 and bit 7). The power-up states for the control functions are all 0s.The following tables define the control bits for each address and the settings for output voltage:Table 1. Control Register Address (I1, I0) = 00 Bit Name Function0VSEL0See table 3, Output Voltage Amplitude Selection 1VSEL12VSEL23VSEL30: LNB = Low range1: LNB = High range4ODT 1 (recommended): The ODT functions are always enabled, but setting 1 recommended at all times.5ENB0: Disable LNB Output1: Enable LNB Output6I0Address Bit: 07I1Address Bit: 0Bit 0 VSEL0 These three bits provide incremental control over the voltage on the LNB output.Bit 1 VSEL1 The available voltages provide the necessary levels for all the common standards Bit 2 VSEL2 plus the ability to add line compensation in increments of 333 mV. The voltage levels are defined in table 3, Output V oltage Amplitude Selection.Bit 3 VSEL3 Switches between the low level and high level output voltages on the LNB output.0 selects the low level voltage and 1 selects the high level. The low-level center voltageis 12.709 V nominal and the high level is 18.042 V nominal. These may be increasedin steps of 333 mV using the VSEL2, VSEL1 and VSEL0 control register bits.Bit 4 ODT The overcurrent disable timer is always enabled.Bit 5 ENB Enables the LNB output. When set to 1 the LNB output is switched on. When set to 0, the LNB output is disabled.Bit 6 I0 AddressBit 7 I1 AddressTable 2. Control Register Address (I1, I0) = 10 and 11Bit Name Function0: External Tone0TMODE1: Internal Tone0: Tone Gated Off1TGATE1: Tone Gated On2-Not Used (0 recommended)3-Not Used4-Not Used5-Not Used6I0Address Bit: 07I1Address Bit: 1Bit 0 TMODE Tone Mode. Selects between the use of an external 22 kHz logic signal or the use of the internal 22 kHz oscillator to control the tone generation on the LNB output. A 0selects the external tone and a 1 selects the internal tone. See the Tone Generationsection for more informationBit 1 TGATE Tone Gate. Allows either the internal or external 22 kHz tone signals to be gated, unless the EXTM is selected for gating. When set to 0, the selected tone (viaTMODE) is off. When set to 1, the selected tone is on. See Tone Generation Sectionfor more information.Bit 2 – Not Used.Bit 3 – Not Used.Bit 4 – Not Used.Bit 5 – Not Used.Bit 6 I0 Address.Bit 7 I1 Address.Table 3. Output Voltage Amplitude Selection VSEL3VSEL2VSEL1VSEL0LNB (V) 000012.709 000113.042 001013.375 010014.042 100018.042 101018.709 101119.042Status Registers (I2C™-Compatible Read Register)The main fault conditions: overcurrent (OCP), undervoltage (VUV) and overtemperature (TSD), are all indicated by setting the relevant bits in the Status registers. In all fault cases, once the bit is set, it remains latched until the A8293 is read by the I2C™ master, assuming the fault has been resolved.The current status of the LNB output is indicated by the dis-able bit, DIS. The DIS bit is set when either a fault occurs or if the LNB is disabled intentionally. This bit is latched, and is reset when the LNB is commanded on again. The power not good (PNG) is the only bit which may be reset without an I2C™ read sequence. Table 4 summarizes the condition of each bit when set and how it is reset.As the A8293 has a comprehensive set of status reporting bits, it is necessary to have two Status registers. When performing a multiple read function, register 1 is read followed by register 2, then register 1 again and so on. Whenever a new read function is performed, register 1 is always read first.The normal sequence of the master in a fault condition will be to detect the fault by reading the Status registers, then rereading the Status registers until the status bit is reset indicating the fault condition is reset. The fault may be detected either by continuously polling, by responding to an interrupt request (IRQ), or by detect-ing a fault condition externally and performing a diagnostic poll of all slave devices. Note that the fully-operational condition of the Status registers is all 0s, to simplify checking of the Status bit.Table 4. Status Register Bit SettingStatus Bit Function SetReset Condition–Not used–Not usedDIS LNB disabled, either intentionally ordue to faultLatched LNB enabled and no faultOCP Overcurrent Latched I2C™ read and fault removed PNG Power not good Non-latched LNB volts in range–Not used–Not usedTSD Thermal shutdown Latched I2C™ read and fault removed VUV Undervoltage Latched I2C™ read and fault removedTable 5. Status Register 1Bit Name Function0DIS LNB output disabled1–Not Used2OCP Overcurrent3–Not Used4PNG Power Not Good5–Not Used6TSD Thermal Shutdown7VUV V IN UndervoltageBit 0 DIS LNB Output Disabled. DIS is used to indicate the current condition of the LNB output. At power-on, or if a fault condition occurs, DIS will be set. This bit changingto 1 does not cause the IRQ to activate because the LNB output may be disabled in-tentionally by the I2C™ master. This bit will be reset at the end of a write sequenceif the LNB output is enabled.Bit 1 – Not used.Bit 2 OCP Overcurrent. If the LNB output detects an overcurrent condition, for greater than48 ms, the LNB output will be disabled. The OCP bit will be set to indicate that anovercurrent has occurred and the disable bit, DIS, will be set. The Status register isupdated on the rising edge of the 9th clock pulse in the data read sequence, where theOCP bit is reset in all cases, allowing the master to reenable the LNB output.If the overcurrent timer is not enabled, the device operate in current limit indefinitelyand the OCP bit will be set. If the overcurrent condition is removed, the OCP bit willautomatically be reset. Note that if the overcurrent operates long enough, and a ther-mal shutdown occurs, the LNB output will be disabled and the TSD bit will be set.Bit 3 – Not used.Bit 4 PNG Power Not Good. Set to 1 when the LNB output is enabled and the LNB voltage is below 85% of the programmed voltage. The PNG is reset when the LNB volts arewithin 90% of the programmed LNB voltage.Bit 5 – Not used.Bit 6 TSD Thermal Shutdown. 1 indicates that the A8293 has detected an overtemperature condition and has disabled the LNB output. The disable bit, DIS, will also be set.The status of the overtemperature condition is sampled on the rising edge of the 9thclock pulse in the data read sequence. If the condition is no longer present, then theTSD bit will be reset, allowing the master to reenable the LNB output if required. Ifthe condition is still present, then the TSD bit will remain at 1.Bit 7 VUV Undervoltage Lockout. 1 indicates that the A8293 has detected that the input sup-ply, V IN is, or has been, below the minimum level and an undervoltage lockout hasoccurred disabling the LNB outputs. The disable bit, DIS, will also be set and theA8293 will not reenable the output until so instructed by writing the relevant bit intothe control registers. The status of the undervoltage condition is sampled on the risingedge of the 9th clock pulse in the data read sequence. If the condition is no longerpresent, then the VUV bit will be reset allowing the master to reenable the LNB out-put if required. If the condition is still present, then the VUV bit will remain at 1.。

Document Number: MC33883Rev 9.0, 1/2007Freescale Semiconductor Advance Information* This document contains certain information on a new product.Specifications and information herein are subject to change without notice.© Freescale Semiconductor, Inc., 2007. All rights reserved.H-Bridge Gate Driver ICThe 33883 is an H-bridge gate driver (also known as a full-bridge pre-driver) IC with integrated charge pump and independent high-•V CC •V CC2••••••••Figure 1. 33883 Simplified Application Diagram33883Analog Integrated Circuit Device Data33883INTERNAL BLOCK DIAGRAMINTERNAL BLOCK DIAGRAMFigure 2. 33883 Simplified Internal Block DiagramUndervolt-age/Over-voltageG_ENIN_HS1IN_LS1IN_HS2IN_LS2GATE_LS1SRC_HS1GATE_HS CP_OUTLR_OUTGATE_LS2SRC_HS2GATE_HS Pulse GeneratorV DD / V CC Level ShiftPulse GeneratorV DD / V POS Level ShiftIN OUCon-trol a nd LogicLinearReg V CC2EN GND +5.0 V+14.5 V V DDHIGH- AND LOW-SIDECharge PumpEN GNDC2V POSV CCC1V CC2V CCV CCV CC2VCC VCC2CP_OUTLR_OUT V CC, V CC2V DDC2C1BRG_ENPulse GeneratorV DD / V CC Level ShiftPulse GeneratorV DD / V POS Level ShiftGND CONTROL WITH CHARGE PUMPCP_OUTV CCOutputDriverIN OUCP_OUTV CCOutputDriverIN OULR_OUTOutputDriverIN OULR_OUTOutputDriverCon-trol a nd LogicCon-trol a nd LogicCon-trol a nd LogicBRG_ENBRG_ENBRG_ENHIGH-SIDE CHANNELLOW-SIDE CHANNELHIGH-SIDE CHANNELLOW-SIDE CHANNELGND2GND2GND1GND GND_GND2GND_AT SD 1Thermal ShutdownT SD 1T SD 1T SD 2Thermal ShutdownT SD 2T SD 2Analog Integrated Circuit Device Data 33883TERMINAL CONNECTIONSFigure 3. 33883 20-SOICW Terminal ConnectionsTable 1. 20-SOICW Terminal DefinitionsA functional description of each terminal can be found in the FUNCTIONAL TERMINAL DESCRIPTION section beginning on page 10.TerminalTerminal Name Formal Name Definition1VCC Supply Voltage 1Device power supply 1.2C2Charge Pump Capacitor External capacitor for internal charge pump.3CP_OUT Charge Pump Out External reservoir capacitor for internal charge pump.4SRC_HS1Source 1 Output High Side Source of high-side 1 MOSFET 5GATE_HS 1Gate 1 Output High Side Gate of high-side 1 MOSFET.6IN_HS1Input High Side 1 Logic input control of high-side 1 gate (i.e., IN_HS1 logic HIGH = GATE_HS1 HIGH).7IN_LS1Input Low Side 1Logic input control of low-side 1 gate (i.e., IN_LS1 logic HIGH = GATE_LS1 HIGH).8GATE_LS1Gate 1 Output Low Side Gate of low-side 1 MOSFET. 9GND1Ground 1Device ground 1.10LR_OUT Linear Regulator Output Output of internal linear regulator.11VCC2Supply Voltage 2Device power supply 2.12GND_A Analog GroundDevice analog ground.13C1Charge Pump Capacitor External capacitor for internal charge pump.14GND2Ground 2Device ground 2.15GATE_LS2Gate 2 Output Low Side Gate of low-side 2 MOSFET.16IN_LS2Input Low Side 2Logic input control of low-side 2 gate (i.e., IN_LS2 logic HIGH = GATE_LS2 HIGH). 17IN_HS2Input High Side 2 Logic input control of high-side 2 gate (i.e., IN_HS2 logic HIGH = GATE_HS2 HIGH).18GATE_HS 2Gate 2 Output High Side Gate of high-side 2 MOSFET. 19SRC_HS2Source 2 Output High Side Source of high-side 2 MOSFET.20G_ENGlobal EnableLogic input Enable control of device (i.e., G_EN logic HIGH = Full Operation, G_EN logic LOW = Sleep Mode).Analog Integrated Circuit Device Data33883ELECTRICAL CHARACTERISTICS MAXIMUM RATINGSELECTRICAL CHARACTERISTICSMAXIMUM RATINGSTable 2. Maximum RatingsAll voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.RatingSymbolValueUnitELECTRICAL RATINGS Supply Voltage 1V CC -0.3 to 65V Supply Voltage 2 (1)V CC2-0.3 to 35V Linear Regulator Output VoltageV LR_OUT -0.3 to 18V High-Side Floating Supply Absolute Voltage V CP_OUT -0.3 to 65V High-Side Floating Source VoltageV SRC_HS-2.0 to 65V High-Side Source Current from CP_OUT in Switch ON State I S 250mA High-Side Gate VoltageV GATE_HS -0.3 to 65V High-Side Gate Source Voltage (2)V GATE_HS - V SRC_HS -0.3 to 20V High-Side Floating Supply Gate Voltage V CP_OUT - V GATE_HS -0.3 to 65V Low-Side Gate Voltage V GATE_LS -0.3 to 17V Wake-Up Voltage V G_EN -0.3 to 35V Logic Input VoltageV IN -0.3 to 10V Charge Pump Capacitor Voltage V C1-0.3 to V LR_OUTV Charge Pump Capacitor Voltage V C2-0.3 to 65V ESD Voltage (3)Human Body Model on All Pins (V CC and V CC2 as Two Power Supplies) Machine ModelV ESD1V ESD2±1500±130VNotes1.V CC2 can sustain load dump pulse of 40 V, 400 ms,2.0 Ω.2.In case of high current (SRC_HS >100 mA) and high voltage (>20 V) between GATE_HSX and SRC_HS an external zener of 18 V isneeded as shown in Figure 14.3.ESD1 testing is performed in accordance with the Human Body Model (C ZAP =100 pF, R ZAP =1500 Ω), ESD2 testing is performed inaccordance with the Machine Model (C ZAP =200 pF, R ZAP =0Ω).Analog Integrated Circuit Device Data 33883ELECTRICAL CHARACTERISTICSMAXIMUM RATINGSPower Dissipation and Thermal Characteristics Maximum Power Dissipation @ 25°C Thermal Resistance (Junction to Ambient)Operating Junction Temperature Storage TemperatureP D R θJA T J T STG 1.25100-40 to 150-65 to 150W °C / W °C °C Peak Package Reflow Temperature During Reflow (4), (5)T PPRTNote 5°CNotes4.Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits maycause malfunction or permanent damage to the device.5.Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package ReflowTemperature and Moisture Sensitivity Levels (MSL),Go to , search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.Table 2. Maximum RatingsAll voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.RatingSymbolValueUnitAnalog Integrated Circuit Device Data33883ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSTable 3. Static Electrical CharacteristicsCharacteristics noted under conditions V CC = 12 V, V CC2 = 12 V, C CP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitOPERATING CONDITIONSSupply Voltage 1 for Output High-Side Driver and Charge Pump V CC 5.5–55V Supply Voltage 2 for Linear Regulation V CC2 5.5–28V High-Side Floating Supply Absolute VoltageV CP_OUTV CC +4–V CC + 11 but < 65VLOGICLogic 1 Input Voltage (IN_LS and IN_HS) V IH 2.0–10V Logic 0 Input Voltage (IN_LS and IN_HS) V IL ––0.8V Logic 1 Input Current V IN = 5.0 VI IN+200–1000µAWake-Up Input Voltage (G_EN)V G_EN 4.55.0V CC2V Wake-Up Input Current (G_EN) V G_EN = 14 VI G_EN–200500µAWake-Up Input Current (G_EN) V G_EN = 28 V I G_EN2––1.5mALINEAR REGULATOR Linear RegulatorV LR_OUT @ V CC2 from 15 V to 28 V, I LOAD from 0 mA to 20 mA V LR_OUT @ I LOAD = 20 mAV LR_OUT @ I LOAD = 20 mA, V CC2 = 5.5 V, V CC = 5.5 V V LR_OUT12.5V CC2 - 1.54.0–––16.5––VCHARGE PUMPCharge Pump Output Voltage, Reference to VCC V CC = 12 V, I LOAD = 0 mA, C CP_OUT = 1.0 µF V CC = 12 V, I LOAD = 7.0 mA, C CP_OUT = 1.0 µF V CC2 = V CC = 5.5 V, I LOAD = 0 mA, C CP_OUT = 1.0 µF V CC2 = V CC = 5.5 V, I LOAD = 7.0 mA, C CP_OUT = 1.0 µF V CC = 55 V, I LOAD = 0 mA, C CP_OUT = 1.0 µF V CC = 55 V, I LOAD = 7.0 mA, C CP_OUT = 1.0 µFV CP_OUT7.57.02.31.87.57.0––––––––––––VPeak Current Through Pin C1 Under Rapidly Changing VCC Voltages (see Figure 13, page 17)I C1-2.0– 2.0AMinimum Peak Voltage at Pin C1 Under Rapidly Changing VCC Voltages (see Figure 13, page 17)V C1MIN -1.5––VAnalog Integrated Circuit Device Data 33883ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSSUPPLY VOLTAGEQuiescent VCC Supply Current V G_EN = 0 V and V CC = 55 V V G_EN = 0 V and V CC = 12 V IV CCSLEEP––––1010µAOperating VCC Supply Current (6)V CC = 55 V and V CC2 = 28 V V CC = 12 V and V CC2 = 12 VIV CCOP––2.20.7––mAAdditional Operating V CC Supply Current for Each Logic Input Terminal ActiveV CC = 55 V and V CC2 = 28 V (7)IV CCLOG––5.0mAQuiescent VCC2 Supply Current V G_EN = 0 V and V CC = 12 V V G_EN = 0 V and V CC = 28 V IV CC2SLEEP––––5.05.0µAOperating VCC2 Supply Current (6) V CC = 55 V and V CC2 = 28 V V CC = 12 V and V CC2 = 12 VIV CC2OP––––129.0mA Additional Operating VCC2 Supply Current for Each Logic Input Terminal ActiveV CC = 55 V and V CC2 = 28 V (7) IV CC2LOG–– 5.0mAUndervoltage Shutdown VCC UV 4.0 5.0 5.5V Undervoltage Shutdown VCC2 (8)UV2 4.0 5.0 5.5V Overvoltage Shutdown VCC OV 576165V Overvoltage Shutdown VCC2OV229.53135VOUTPUTOutput Sink Resistance (Turned Off)I discharge LSS = 50 mA , V SRC_HS = 0 V (8)R DS––22ΩOutput Source Resistance (Turned On)I charge HSS = 50 mA, V CP_OUT = 20 V (8)R DS––22ΩCharge Current of the External High-Side MOSFET Through GATE_HSn Terminal (9)I CHARGE HSS–100200mAMaximum Voltage (V GATE_HS - V SRC_HS ) INH = Logic 1, I S max = 5.0 mAVMAX––18VNotes6.Logic input terminal inactive (high impedance).7.High-frequency PWM-ing (» 20 kHz) of the logic inputs will result in greater power dissipation within the device. Care must be taken to remain within the package power handling rating.8.The device may exhibit predictable behavior between 4.0 V and 5.5 V.9.See Figure 5, page 12, for a description of charge current.Table 3. Static Electrical Characteristics (continued)Characteristics noted under conditions V CC = 12 V, V CC2 = 12 V, C CP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbol Min Typ Max UnitAnalog Integrated Circuit Device Data33883ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSTable 4. Dynamic Electrical CharacteristicsCharacteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, -40°C ≤ T A ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitTIMING CHARACTERISTICSPropagation Delay High Side and Low SideC LOAD = 5.0 nF, Between 50% Input to 50% Output (10) (see Figure 4) t PD–200300nsTurn-On Rise TimeC LOAD = 5.0 nF, 10% to 90% (10), (11) (see Figure 4) t R–80180ns Turn-Off Fall TimeC LOAD = 5.0 nF, 10% to 90% (10), (11) (see Figure 4)t F–80180ns10.C LOAD corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side. 11.Rise time is given by time needed to change the gate from 1.0 V to 10 V (vice versa for fall time).Analog Integrated Circuit Device Data 33883TIMING DIAGRAMSTIMING DIAGRAMSFigure 4. Timing Characteristics50%50%t fIN_HS GATE_HS 50%50%t pdt pdt ror IN_LS or GATE_LSAnalog Integrated Circuit Device Data33883FUNCTIONAL DESCRIPTION INTRODUCTIONFUNCTIONAL DESCRIPTIONINTRODUCTIONThe 33883 is an H-bridge gate driver (or full-bridge pre-driver) with integrated charge pump and independent high- and low-side driver channels. It has the capability to drivelarge gate-charge MOSFETs and supports high PWM frequency. In sleep mode its supply current is very low.FUNCTIONAL TERMINAL DESCRIPTIONSUPPLY VOLTAGE TERMINALS (VCC AND VCC2)The VCC and VCC2 terminals are the power supply inputs to the device. V CC is used for the output high-side drivers and the charge pump. V CC2 is used for the linear regulation. They can be connected together or independent with different voltage values. The device can operate with V CC up to 55 V and V CC2 up to 28 V.The VCC and VCC2 terminals have undervoltage (UV) and overvoltage (OV) shutdown. If one of the supply voltage drops below the undervoltage threshold or rises above the overvoltage threshold, the gate outputs are switched LOW in order to switch off the external MOSFETs. When the supply returns to a level that is above the UV threshold or below the OV threshold, the device resumes normal operationaccording to the established condition of the input terminals.INPUT HIGH- AND LOW-SIDE TERMINALS (IN_HS1, IN_HS2, AND IN_LS1, IN_LS2)The IN_HSn and IN_LSn terminals are input control terminals used to control the gate outputs. These terminals are 5.0 V CMOS-compatible inputs with hysteresis. IN_HSn and IN_LSn independently control GATE_HSn and GATE_LSn, respectively.During wake-up, the logic is supplied from the G_EN terminal. There is no internal circuit to prevent the external high-side and low-side MOSFETs from conducting at the same time.SOURCE OUTPUT HIGH-SIDE TERMINALS (SRC_HS1 AND SRC_HS2)The SRC_HSn terminals are the sources of the external high-side MOSFETs. The external high-side MOSFETs are controlled using the IN_HSn inputs.GATE HIGH- AND LOW-SIDE TERMINALS (GATE_HS1, GATE_HS2, AND GATE_LS1, GATE_LS2)The GATE_HSn and GATE_LSn terminals are the gates of the external high- and low-side MOSFETs. The external high- and low-side MOSFETs are controlled using the IN_HSn and IN_LSn inputs.GLOBAL ENABLE (G_EN)The G_EN terminal is used to place the device in a sleep mode. When the G_EN terminal voltage is a logic LOW state, the device is in sleep mode. The device is enabled and fully operational when the G_EN terminal voltage is logic HIGH, typically 5.0 V.CHARGE PUMP OUT (CP_OUT)The CP_OUT terminal is used to connect an external reservoir capacitor for the charge pump.CHARGE PUMP CAPACITOR TERMINALS (C1 AND C2)The C1 and C2 terminals are used to connect an external capacitor for the charge pump.LINEAR REGULATOR OUTPUT (LR_OUT)The LR_OUT terminal is the output of the internal regulator. It is used to connect an external capacitor.GROUND TERMINALS (GND_A, GND1 AND GND2)These terminals are the ground terminals of the device. They should be connected together with a very low impedance connection.FUNCTIONAL DESCRIPTIONFUNCTIONAL TERMINAL DESCRIPTIONTable 5. Functional Truth TableConditions G_EN IN_HSn IN_LSn Gate_HSn Gate_LSn Comments Sleep0x x00Device is in Sleep mode. The gates are at low state.Normal11111Normal mode. The gates are controlled independently.Normal10000Normal mode. The gates are controlled independently. Undervoltage1x x00The device is currently in fault mode. The gates are atlow state. Once the fault is removed, the 33883 recoversits normal mode.Overvoltage1x x00The device is currently in fault mode. The gates are atlow state. Once the fault is removed, the 33883 recoversits normal mode.Overtemperatureon High-Side Gate Driver 11x0x The device is currently in fault mode. The high-side gateis at low state. Once the fault is removed, the 33883recovers its normal mode.Overtemperatureon Low-Side Gate Driver 1x1x0The device is currently in fault mode. The low-side gateis at low state. Once the fault is removed, the 33883recovers its normal mode.x = Don’t care.FUNCTIONAL DEVICE OPERATIONFUNCTIONAL DEVICE OPERATIONDRIVER CHARACTERISTICSFigure 5 represents the external circuit of the high-side gate driver. In the schematic, HSS represents the switch that is used to charge the external high-side MOSFET through the GATE_HS terminal. LSS represents the switch that is used to discharge the external high-side MOSFET through the GATE_HS terminal. A 180K Ω internal typical passivedischarge resistance and a 18 V typical protection zener are in parallel with LSS. The same schematic can be applied to the external low-side MOSFET driver simply by replacing terminal CP_OUT with terminal LR_OUT, terminal GATE_HS with terminal GATE_LS, and terminal SRC_HS with GND.Figure 5. High-Side Gate Driver Functional SchematicThe different voltages and current of the high-side gate driver are illustrated in Figure 6. The output driver sources a peak current of up to 1.0 A for 200 ns to turn on the gate. After 200 ns, 100 mA is continuously provided to maintain the gate charged. The output driver sinks a high current to turn off the gate. This current can be up to 1.0 A peak for a 100 nF load.Note G ATE_HS is loaded with a 100 nF capacitor in thechronograms. A smaller load will give lower peak and DC charge or discharge currents.Figure 6. High-Side Gate Driver ChronogramsHSSCP_OUTI GATE_HSI charge HSS I discharge LSSGATE_HS1LSSSRC_HS1180k Ω18VHSSpulse_IN LSS_INHSSDC_ININ_HS11.0 A Peak1.0 A Peak100 mA Typical1.0 A Peak100 mA Typical-1.0 A PeakIN_HS1HSSpulse_INHSS DC_INLSS_INI discharge LSSI GATE_HSI charge HSSFUNCTIONAL DEVICE OPERATIONOPERATIONAL MODESOPERATIONAL MODESTURN-ONFor turn-on, the current required to charge the gate source capacitor C iss in the specified time can be calculated as follows:I P = Q g / t r = 80 nC/ 80 ns ≈ 1.0 A Where Q g is power MOSFET gate charge and t r is peakcurrent for rise time.TURN-OFFThe peak current for turn-off can be obtained in the same way as for turn-on, with the exception that peak current for fall time, t f , is substituted for t r :I P = Q g / t f = 80 nC/ 80 ns ≈ 1.0 A In addition to the dynamic current required to turn off or onthe MOSFET, various application-related switching scenarios must be considered. These scenarios are presented in Figure 7. In order to withstand high dV/dt spikes, a low resistive path between gate and source is implemented during the OFF-state.Figure 7. OFF-State Driver RequirementDriver Requirement:Low Resistive Gate-Source Path DuringOFF-StateFlyback spike charges low-side gate via C rss charge current I rss up to 2.0 A. Causes increased uncon-trolled turn-on of low-sideMOSFET.C issC iss C rss C rssV BATDriver Requirement: Low Resistive Gate-Source Path During OFF-State. High Peak Sink Current CapabilityFlyback spike pulls down high-side source V GS .Delays turn-off of high-side MOSFET.C issC issC rssC rssV BATDriver Requirement:High Peak Sink CurrentCapabilityFlyback spike charges low-side gate via C rss charge current I rss up to 2.0 A.Delays turn-off of low-sideMOSFET.C issC issC rss C rssV BATDriver Requirement:Low Resistive Gate-Source Path DuringOFF-StateC issC issC rssC rssV BATFlyback spike pulls down high-side source V GS .Causes increased uncon-trolled turn-on of high-sideOFFOFFOFFOFFGATE_LSI LOADL1I LOAD L1I LOAD L1I LOAD L1I rssV GATEV GATE -V DRNGATE_HSGATE_LSGATE_HS GATE_HS GATE_LSGATE_HSGATE_LSFUNCTIONAL DEVICE OPERATION OPERATIONAL MODESLOW-DROP LINEAR REGULATORThe low-drop linear regulator is supplied by V CC2. If V CC2 exceeds 15.0 V, the output is limited to 14.5 V (typical).The low-drop linear regulator provides the 5.0 V for the logic section of the driver, the V gs_ls buffered at LR_OUT, and the +14.5 V for the charge pump, which generates theCP_OUT The low-drop linear regulator provides 4.0 mA average current per driver stage.In case of the full bridge, that means approximately16 mA —8.0 mA for the high side and 8.0 mA for the low side.Note: The average current required to switch a gate with a frequency of 100 kHz is:I CP = Q g * f PWM = 80 nC * 100 kHz = 8.0 mAIn a full-bridge application only one high side and one low side switches on or off at the same time.CHARGE PUMPThe charge pump generates the high-side driver supply voltage (CP_OUT), buffered at C CP_OUT. Figure 8 shows the charge pump basic circuit without load.Figure 8. Charge Pump Basic CircuitWhen the oscillator is in low state [(1) in Figure 8], C CP is charged through D2 until its voltage reaches V CC - V D2. When the oscillator is in high state (2), C CP is discharged though D1 in C CP_OUT, and final voltage of the charge pump, V CP_OUT, is V cc+ V LR_OUT - 2V D. The frequency of the 33883 oscillator is about 330 kHz.EXTERNAL CAPACITORS CHOICEExternal capacitors on the charge pump and on the linear regulator are necessary to supply high peak current absorbed during switching.Figure 9 represents a simplified circuitry of the high-side gate driver. Transistors Tosc1 and Tosc2 are the oscillator-switching MOSFETs. When Tosc1 is on, the oscillator is at low level. When Tosc2 is on, the oscillator is at high level. The capacitor C CP_OUT provides peak current to the high-sideFUNCTIONAL DEVICE OPERATIONOPERATIONAL MODESC CPC CP choice depends on power MOSFET characteristics and the working switching frequency. Figure 10 contains two diagrams that depict the influence of C CP value on V CP_OUT average voltage level. The diagrams represent two different frequencies for two power MOSFETs, MTP60N06HD and MPT36N06V.Figure 10. V CP_OUT Versus C CPThe smaller the C CP value is, the smaller the V CP_OUT value is. Moreover, for the same C CP value, when the switching frequency increases, the average V CP_OUT level decreases. For most of the applications, a typical value of 33 nF is recommended.C CP_OUTFigure 11 depicts the simplified C CP_OUT current and voltage waveforms. f PWM is the working switching frequency.CP_OUTWaveformsAs shown above, at high-side MOSFET turn-on V CP_OUTvoltage decreases. This decrease can be calculatedaccording to the C CP_OUT value as follows:Where Q g is power MOSFET gate charge.C LR_OUTC LR_OUT provides peak current needed by the low-sideMOSFET turn-on. V LR_OUT decrease is as follows:TYPICAL VALUES OF CAPACITORSIn most working cases the following typical values arerecommended for a well-performing charge pump:C CP = 33 nF, C CP_OUT = 470 nF, and C LR_OUT = 470 nFThese values give a typical 100 mV voltage ripple onV CP_OUT and V LR_OUT with Q g = 50 nC.g∆V CP_OUT =C CP_OUTQ g∆V LR_OUT =C LR_OUTQ gFUNCTIONAL DEVICE OPERATIONPROTECTION AND DIAGNOSTIC FEATURESPROTECTION AND DIAGNOSTIC FEATURESGATE PROTECTIONThe low-side driver is supplied from the built-in low-drop regulator. The high-side driver is supplied from the internal charge pump buffered at CP_OUT.The low-side gate is protected by the internal linear regulator, which ensures that V GATE_LS does not exceed the maximum V GS. Especially when working with the charge pump, the voltage at CP_OUT can be up to 65 V. The high-side gate is clamped internally in order to avoid a V GS exceeding 18 V.Gate protection does not include a fly-back voltage clamp that protects the driver and the external MOSFET from a fly-back voltage that can occur when driving inductive load. This fly-back voltage can reach high negative voltage values and needs to be clamped externally, as shown in Figure 12.Figure 12. Gate Protection and Flyback Voltage Clamp LOAD DUMP AND REVERSE BATTERYV CC and V CC2 can sustain load a dump pulse of 40 V and double battery of 24 V. Protection against reverse polarity is ensured by the external power MOSFET with the free-wheeling diodes forming a conducting pass from ground to V CC. Additional protection is not provided within the circuit. To protect the circuit an external diode can be put on the battery line. It is not recommended putting the diode on the ground line.TEMPERATURE PROTECTIONThere is temperature shutdown protection per each half-bridge. Temperature shutdown protects the circuitry against temperature damage by switching off the output drivers. Its typical value is 175°C with an hysteresis of 15°C.DV/DT AT V CCV CC voltage must be higher than (SRC_HS voltage minus a diode drop voltage) to avoid perturbation of the high-side driver.In some applications a large dV /d t at terminal C2 owing to sudden changes at V CC can cause large peak currents flowing through terminal C1, as shown in Figure 13.For positive transitions at terminal C2, the absolute value of the minimum peak current, I C1min, is specified at 2.0 A for a t C1min duration of 600 ns.For negative transitions at terminal C2, the maximum peak current, I C1max, is specified at 2.0 A for a t C1max duration of 600 ns. Current sourced by terminal C1 during a large dV /d t will result in a negative voltage at terminal C1 (Figure 13). The minimum peak voltage V C1min is specified at -1.5 V for a duration of t C1max = 600 ns. A series resistor with the charge pump capacitor (Ccp) capacitor can be added in order to limit the surge current.Output DriverOUTOutput Driver OUTINL1M2GATE_LSSRC_HSGATE_HSInductiveFlyback VoltageClampIND c l M1VCCCP_OUTLR_OUTV GS < 14 VUnder AllConditionsFUNCTIONAL DEVICE OPERATIONPROTECTION AND DIAGNOSTIC FEATURESFigure 13. Limits of C1 Current and Voltage with Large Values of dV/dtIn the case of rapidly changing V CC voltages, the large dV/dt may result in perturbations of the high-side driver, thereby forcing the driver into an OFF state. The addition ofcapacitors C3 and C4, as shown in Figure 14, reduces the dV/dt of the source line, consequently reducing driverperturbation. Typical values for R3 / R 4 and C3 / C 4 are 10 Ω and 10 nF, respectively.DV/DT AT V CC2When the external high-side MOSFET is on, in case of rapid negative change of V CC2 the voltage (V GATE_HS -V SRC_HS ) can be higher than the specified 18 V. In this case a resistance in the SRC line is necessary to limit the current to 5.0 mA max. It will protect the internal zener placed between GATE_HS and SRC terminals.In case of high current (SRC_HS >100 mA) and high voltage (>20 V) between GATE_HSX and SRC_HS an external zener of 18 V is needed as shown in Figure 14.t C1maxt C1minV CCI (C1+C2)I C1maxI C1minV (LR_OUT)0 VV (C1)0 AV C1minTYPICAL APPLICATIONSTYPICAL APPLICATIONSFigure 14. Application Schematic with External Protection CircuitIN_LS2IN_HS2IN_LS1IN_HS1V BAT G_ENC1C2C CPC LR_OUT C CP_OUT MCUVCC2VCC V BOOST33883M1M2M3M4R1R2470nF 470nF 50Ω50Ω50Ω50Ω33nFDC MotorR310Ω10nFC310nFC410ΩR4IN_LS2IN_HS2IN_LS1IN_HS1G_EN C1C2VCC2VCC GNDGATE_LS2SRC_HS2GATE_HS2GATE_LS1SRC_HS1GATE_HS1LR_OUT CP_OUT 18 V18 V。

ZC829, ZDC833, ZMV829, ZMDC830, ZV831 Series Device DescriptionA range of silicon varactor diodes for use in frequency control and filtering.Featuring closely controlled CV characteristics and high Q.Low reverse current ensures very low phase noise performance.Available in single or dual common cathode format in a wide rage of miniature surface mount packages.Features·Close tolerance C-V characteristics ·High tuning ratio ·Low I R (typically 200pA)·Excellent phase noise performance ·High Q·Range of miniature surface mount packagesApplications·VCXO and TCXO·Wireless communications ·Pagers ·Mobile radio*Where steeper CV slopes are required there is the 12V hyperabrupt range.ZC930, ZMV930, ZV930, ZV931 Series 830 seriesISSUE 6 - JANUARY 20021SILICON 28V HYPERABRUPT VARACTOR DIODES830 seriesISSUE 6 - JANUARY 20022PARTCapacitance (pF)V R =2V,f=1MHzMin Q V R =3V f=50MHzCapacitance RatioC 2/C 20at f=1MHzMIN.NOM.MAX.MIN.MAX.829A 7.388.29.02250 4.3 5.8829B 7.798.28.61250 4.3 5.8830A 9.010.011.0300 4.5 6.0830B 9.510.010.5300 4.5 6.0831A 13.515.016.5300 4.5 6.0831B 14.2515.015.75300 4.5 6.0832A 19.822.024.2200 5.0 6.5832B 20.922.023.1200 5.0 6.5833A 29.733.036.3200 5.0 6.5833B 31.3533.034.65200 5.0 6.5834A 42.347.051.7200 5.0 6.5834B 44.6547.049.35200 5.0 6.5835A 61.268.074.8100 5.0 6.5835B 64.668.071.4100 5.0 6.5836A 90.0100.0110.0100 5.0 6.5836B95.0100.0105.0100 5.06.5TUNING CHARACTERISTICS at Tamb = 25°CPARAMETER SYMBOLMAX UNIT Forward currentI F 200mA Power dissipation at T amb =25ЊC SOT23P tot 330mW Power dissipation at T amb =25ЊC SOD323P tot 330mW Power dissipation at T amb =25ЊC SOD523P tot250mW Operating and storage temperature range-55to +150ЊCABSOLUTE MAXIMUM RATINGSPARAMETERCONDITIONS MIN.TYP.MAX.UNIT Reverse breakdown voltage I R =10uA 25V Reverse voltage leakageV R =20V 0.220nA Temperature coefficient of capacitanceV R =3V,f =1MHz300400ppCm/ЊCELECTRICAL CHARACTERISTICS at Tamb = 25°C830 seriesTYPICAL CHARACTERISTICSISSUE 6 - JANUARY 20023830 seriesISSUE 6 - JANUARY 20024O R D E R C O D E S A N D P A R T M A R K I N GR E E L C O D ER E E L S I Z ET A P E W I D T HQ U A N T I T Y P E R R E E LT A7i n c h (180m m )8m m3000T C13i n c h (330m m )8m m 10000T A P E A N D R E E L I N F O R M A T I O NT h e o r d e r c o d e s a r e s h o w n a s T A w h i c h i s f o r 7i n c h r e e l s .F o r 13i n c h r e e l s s u b s t i t u t e T C i n p l a c e o f T A i n t h e o r d e r c o d e .ISSUE 6 - JANUARY 20025830 seriesSOT23 PACKAGE DIMENSIONSSOD323 PACKAGE DIMENSIONSZetex plcFields New Road ChaddertonOldham, OL9 8NP United KingdomTelephone (44) 161 622 4422Fax: (44) 161 622 4420Zetex GmbHStreitfeldstraße 19D-81673 München GermanyTelefon: (49) 89 45 49 49 0Fax: (49) 89 45 49 49 49Zetex Inc700 Veterans Memorial Hwy Hauppauge, NY11788USATelephone: (631) 360 2222Fax: (631) 360 8222Zetex (Asia) Ltd3701-04Metroplaza, Tower 1Hing Fong Road Kwai Fong Hong KongTelephone: (852) 26100 611Fax: (852) 24250 494These offices are supported by agents and distributors in major countries world-wide.This publication is issued to provide outline information only which (unless agreed by the Company in writing)may not be used,applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned.The Company reserves the right to alter without notice the specification,design,price or conditions of supply of any product or service.For the latest product information,log on to©Zetex plc 2001830 series6ISSUE 6 - JANUARY 2002DIM MILLIMETRES MIN.MAX A ᎏ0.800A10.0000.100A20.6000.800b10.1600.300c 0.0800.220D 0.7000.900E 1.500 1.700E1 1.100 1.300L 0.2000.400L10.1700.230⍜1Њ4Њ10ЊSOD523 PACKAGE DIMENSIONSSOD323 PACKAGE DIMENSIONS。

TDA4605脚号引脚代码引脚功能参数：R+lR- 备注1，该集成块为双列8 脚封装2.电源：6脚为+12.00V3.主要用途：开关电源控制/Jw动电路4.此数据在长虹2138FD型彩电上测得，仅供参考5.内部框图见图387I NF 反馈电压输入0.59/0.592 I 初级电流取样13.00/6.32 '3 V IN 初级电流监测输入6.71/6.024 GND 地0/05 OUT 脉冲输出1 ．12/1．126 Vcc 电源（范围为7.25-16V) 16.02/5.337 SOFT 软启动和积分电路音频输入11.48/7.208 FT 振荡器反馈输入7.83/6.50TDA4605开关电源集成电路TDA4605是飞利浦公司在TDA4601基础上改进开发的一种驱动场效应管的开关稳压控制集成电路。

1．内电路方框图TDA4605集成电路内含启动脉冲发生器、参考电压发生器、误差放大器、恒流源与电流控制输出器，以及各种电压检测器，过流、过压、欠压等保护电路。

该电路采用逻辑运算控制器，根据采样输入电压高低与负载轻重自动调整输出脉冲的占空比。

具有突发脉冲工作方式，还具有控制环开路或短路的保护功能和市电过低就关闭电源的特性，其内电路方框图如图所示。

2.引脚功能及数据TDA4605集成电路通常与场效应开关管配套构成工作频率为500 kHz的开关电源，故开关电源的效率较高。

TDA4605(k Q集成电路采用8脚封装，其集成电路的引脚功能及数据见表所列。

TDA4605-3集成电路内含稳压取样电压处理电路，欠压保护检测电路、激励脉冲输出电路、软启动控制电路等。

该IC采用8脚封装方式，其集成电路的引脚功能及数据见表所列。

TB1240N2.21 1.该集成块为双列33脚封装2.电源：3脚、17 脚、28脚、32脚为+9.10V, 6脚、16 脚为+5.00V3.振荡／时钟：11 脚、10脚、11脚4.主要用途：中频／彩色／扫描信号处理电路5.内部框图见图3671 AFT OUT 频率控制输出2 AUDIO DEEM 音频信号输出4.203 IF Vcc 电源9.104 SIF IN 伴音中频输入5.005 IF GND 地06 IF IN 图像中频输入1.987 IF IN 图像中频输入1.988 RF AGC OUT 射频AGC电压输出4.389 IF AGC FILTER 中频AGC信号滤波4.2010 APC FILTER 自动色相位控制信号滤波2.3811 XTAL 副载波外接晶体振荡器(4.43MHz)12 Y/C GND 地013 MODE SW 模式开关014 R IN 红基色字符输入2.6115 G IN 绿基色字符输入2.6116 B IN 蓝基色字符输入2.6117 红绿蓝Vcc 电源9.1018 R OUT 红基色输出2.8019 G OUT 绿基色输出2.8020 B OUT 蓝基色输出2.8021 ABL 自动亮度控制6.02、22 V SAW 场锯齿波形成4.1023 V NIB 场锯齿波反馈信号输入4.9124 V DRIVER OUT 场激励信号输出1.3025 V AGC 场自动增益控制信号滤波1.8026 SCL 12C总线串行时钟线4.10－27 SDA 12C总线串行数据线J 4.2028 H Vcc 电源8.7829 ID/CW OUT 识别了色副载波输出3.7130 H BLANK IN 行扫描字符消隐输入1.4231 SYNC OUT 同步脉冲信号输出4.6832 H DRIVER OUT 行激励输出1.8033 GND 地0TDA9332H 脚号引脚代码引脚功能参数：静动v 备注1.该集成块为四一列扁平44脚封装2.电源：39脚为+8.00V3.振荡／时钟：10 一脚、20脚、21脚4.主要用途：视一频信号三基色处理＿电路5.此数据在长虹DT2000彩电上测一得，仅供参考6.内部框图见图一427 户1 V- 场驱动反相输出2.25/2.302 V十场驱动同相输出2.26/2.313 E/W OUT E/W校正脉冲输出3.36/3.264 EHT EHT高压检测信号输入1.54/1.455 NC 未用0.07/0.066 GND 地0/07 DIGSUP 数据电路退藕5.00/5.008 H OUT 行激励脉冲输出0.67/6.679 SAND OUT 沙堡脉冲输出0.78/0.7810 SCL 时钟线3.04/3.10（不定值）11 SDA 数据线2.90/3.00（不定值）12 H SEL 未用4.16/4.9513 H FBP IN 行逆程脉冲输入0.60/0.5714 DPC 动态相位校正脉冲输入3.56/3.2015 V SAW 场锯齿波形成电容0/0.0316 Im 场锯齿波发生器基准电流3.89/3.8917 Vcc 行启动电源输入8.08/8.0518 BANDGAP 稳压电源信号滤波电容4.75/4.7519 GND 地0/020 XTAL 外接晶体振荡器1.22/1.0521 XTAL 外接晶体振荡器1.05/1.0722 L PST-UP 未用0.04/0.0423 V SYNC IN 场扫描同步脉冲信号输入0.02/0.0424 H SYNC IN 行扫描同步脉冲信号输入0.99/0.4025 DAC OUT 未用0.87/0.33、26 R-Y IN 红基色色差输入3.58/3.6027 B-Y IN 蓝基色色差输入3.60/3.5128 YIN 亮度信号输入3.40/3.4629 FBCSO 地0.05/0.0430 RIN1 红基色输入2.58/2.5831 GINl 绿基色输入2.58/2.5832 BIN1 蓝基色输入2.58/2.5833 Ys IN 快速消隐脉冲信号输入1.98/0.0434 PWL 白峰值限制退祸0.18/0.1435 RIN2 红基色输入3.55/3.5436 GIN2 绿基色输入3.54/3.5437 BIN2 蓝基色输入3.54/3.5438 Ys IN 快速消隐脉冲／混合信号输入/00 同上39 Vcc 电源8.00/8.0040 R OUT 红基色输出2.50/2.5041 G OUT 绿基色输出2.48/2.5342 B OUT 蓝基色输出2.51/2.5643 ABL 自动束流限制2.47/2.4644 BLACK 黑电流信号输入6.95/6.95TDA9332H It总线撞制的TV显示处理集成电路TDA9332H是飞利浦公司为高档彩电设计的显示处理集成电路，应用于各种新型大屏幕彩色电视机1．功能特点(1)具有nJV输入端和带快速消隐的RGB信号输入端，不仅将OSDII'ext输入端与其他视频信号输入端分开，而且既有快速消隐功能又可混合插入；同时内设RGB控制处理器，能实施连续阴极校正(CCC),白点和黑电平偏移调整；可提供黑电流稳定的BGR 输出。

八重洲2R说明书本翻译说明书从第十一页开始，前一部分的关于本机器的各部件的安装和说明不在此翻译范围内。

注意事项：不许将此说明书做商业用途。

不许公开此说明书（因为一方涉及到厂商的版权问题，另一方面本人水平有限）BG7IUT 翻译2003年10月18日调频：开机，旋转DIAL键可以按事先设定好的步进来调整当前操作波段的频率，顺时针方向可以使频率向高的方向步进，逆时针方向可以使频率向低的方向步进。

按F/W键，用顶部旋纽调1MHz频。

扫描：在VFO模式下，按住BAND 键一秒并用顶部旋纽进行向上或向下扫描。

当接收到一个足够强的信号时，扫描会停止在这个频点上，扫描停止保持的时间是依照你设定的“resume”条件来确定的。

（菜单#31）。

按PTT键退出扫描。

发射：VX-2R只能在144MHz和430MHz发射，发射时，仅仅需要按住PTT键就可以了。

在发射频率范围上，可以选择两种功率。

改变发射功率时，只需按H（高）/L（低）键就可以进行转换。

在高功率发射时，液晶上显示满格发射讯号；在低功率发射时，液晶上只显示两格发射讯号。

在FNB-82Li电池（3.7V）工作下，144MHz高功率时1.5W输出，低功率时0.1W输出；430MHz高功率时1.0W 输出，低功率时0.1W输出。

在外接电源（6.0V）工作下，144MHz 高功率时3W输出，低功率时0.3W输出；430MHz高功率时2.0W 输出，低功率时0.3W输出。

锁键：为了防止意外的频率误调整，面板和DIAL旋钮可以被锁定。

激活锁定功能如下：按住H/L键一秒进入设定模式用顶部旋纽DIAL键选择菜单#25（LOCK）按H/L键进行入设定，然后用顶部旋纽DIAL键选择：KEY（锁定按键），DIAL （锁定旋纽），K+D（锁定按键和旋纽），PTT（锁定发射键），K+P （锁定按键和发射键），D+P（锁定旋纽和发射键），ALL（锁定所有键）。

完成设定后，按PTT键保存新设置并退回正常操作模式。

ad829各部分作用AD829是一款高性能、低噪音全差分放大器，常被用于音频放大、传感器信号放大等应用。

它是ADI（Analog Devices Inc.）公司生产的集成电路，具有许多特性和功能，包括低噪音、高增益、高输入阻抗等。

下面将详细介绍AD829的各个部分的作用及其特点。

1.输入级AD829的输入级是一个全差分放大器，有两个输入引脚：正相位输入（IN+)和反相位输入（IN-）。

它的主要作用是将输入信号转换为差分信号，为后续的放大提供基础。

输入级具有高输入阻抗和低噪音的特点，可以有效地提取输入信号，并最小化干扰。

2.增益控制电路AD829内置了一个可调增益电路，可以通过控制输入级的输入电流来调节放大倍数。

增益控制电路通常由一个电阻网络组成，通过改变阻值来调节增益。

这种可调增益的特性使得AD829非常适用于各种应用场景，可以根据需要灵活地调节放大倍数。

3.差分放大级差分放大级是AD829的核心部分，它负责放大输入信号。

该级别具有高增益和低失真的特点，能够有效地放大差分信号，并保持高信噪比。

差分放大级一般采用双极性晶体管、场效应管等器件搭配，以实现理想的放大效果。

4.输出级AD829的输出级负责将放大后的信号输出到外部负载。

输出级通常采用共射/共漏极放大电路，以提供较大的输出功率，并保持较低的失真。

输出级还可通过调节基极电阻或负载电阻等参数，来适应不同的负载特性。

5.电源管理电路AD829的电源管理电路用于提供稳定可靠的电源供电。

它负责电源滤波、稳压和保护等功能，确保芯片的正常工作。

电源管理电路还可以通过调整偏置电压等参数，来优化整个电路的性能。

6.温度补偿电路AD829内置了温度补偿电路，用于自动调节放大器的增益、输入阻抗和输出阻抗等参数，以保持稳定的性能。

温度补偿电路能够有效地抵消由于温度变化引起的偏移和漂移，提高放大器的稳定性和可靠性。

7.输入和输出保护电路AD829的输入和输出保护电路能够保护芯片免受静电放电、过电压和过电流等损害。

常用开关电源芯片大全第1章DC-DC电源转换器/基准电压源1.1 DC-DC电源转换器1.低噪声电荷泵DC-DC电源转换器AAT3113/AAT31142.低功耗开关型DC-DC电源转换器ADP30003.高效3A开关稳压器AP15014.高效率无电感DC-DC电源转换器FAN56605.小功率极性反转电源转换器ICL76606.高效率DC-DC电源转换控制器IRU30377.高性能降压式DC-DC电源转换器ISL64208.单片降压式开关稳压器L49609.大功率开关稳压器L4970A10.1.5A降压式开关稳压器L497111.2A高效率单片开关稳压器L497812.1A高效率升压/降压式DC-DC电源转换器L597013.1.5A降压式DC-DC电源转换器LM157214.高效率1A降压单片开关稳压器LM1575/LM2575/LM2575HV15.3A降压单片开关稳压器LM2576/LM2576HV16.可调升压开关稳压器LM257717.3A降压开关稳压器LM259618.高效率5A开关稳压器LM267819.升压式DC-DC电源转换器LM2703/LM270420.电流模式升压式电源转换器LM273321.低噪声升压式电源转换器LM275022.小型75V降压式稳压器LM500723.低功耗升/降压式DC-DC电源转换器LT107324.升压式DC-DC电源转换器LT161525.隔离式开关稳压器LT172526.低功耗升压电荷泵LT175127.大电流高频降压式DC-DC电源转换器LT176528.大电流升压转换器LT193529.高效升压式电荷泵LT193730.高压输入降压式电源转换器LT195631.1.5A升压式电源转换器LT196132.高压升/降压式电源转换器LT343333.单片3A升压式DC-DC电源转换器LT343634.通用升压式DC-DC电源转换器LT346035.高效率低功耗升压式电源转换器LT346436.1.1A升压式DC-DC电源转换器LT346737.大电流高效率升压式DC-DC电源转换器LT378238.微型低功耗电源转换器LTC175439.1.5A单片同步降压式稳压器LTC187540.低噪声高效率降压式电荷泵LTC191141.低噪声电荷泵LTC3200/LTC3200-542.无电感的降压式DC-DC电源转换器LTC325143.双输出/低噪声/降压式电荷泵LTC325244.同步整流/升压式DC-DC电源转换器LTC340145.低功耗同步整流升压式DC-DC电源转换器LTC340246.同步整流降压式DC-DC电源转换器LTC340547.双路同步降压式DC-DC电源转换器LTC340748.高效率同步降压式DC-DC电源转换器LTC341649.微型2A升压式DC-DC电源转换器LTC342650.2A两相电流升压式DC-DC电源转换器LTC342851.单电感升/降压式DC-DC电源转换器LTC344052.大电流升/降压式DC-DC电源转换器LTC344253.1.4A同步升压式DC-DC电源转换器LTC345854.直流同步降压式DC-DC电源转换器LTC370355.双输出降压式同步DC-DC电源转换控制器LTC373656.降压式同步DC-DC电源转换控制器LTC377057.双2相DC-DC电源同步控制器LTC380258.高性能升压式DC-DC电源转换器MAX1513/MAX151459.精简型升压式DC-DC电源转换器MAX1522/MAX1523/MAX152460.高效率40V升压式DC-DC电源转换器MAX1553/MAX155461.高效率升压式LED电压调节器MAX1561/MAX159962.高效率5路输出DC-DC电源转换器MAX156563.双输出升压式DC-DC电源转换器MAX1582/MAX1582Y64.驱动白光LED的升压式DC-DC电源转换器MAX158365.高效率升压式DC-DC电源转换器MAX1642/MAX164366.2A降压式开关稳压器MAX164467.高效率升压式DC-DC电源转换器MAX1674/MAX1675/MAX167668.高效率双输出DC-DC电源转换器MAX167769.低噪声1A降压式DC-DC电源转换器MAX1684/MAX168570.高效率升压式DC-DC电源转换器MAX169871.高效率双输出降压式DC-DC电源转换器MAX171572.小体积升压式DC-DC电源转换器MAX1722/MAX1723/MAX172473.输出电流为50mA的降压式电荷泵MAX173074.升/降压式电荷泵MAX175975.高效率多路输出DC-DC电源转换器MAX180076.3A同步整流降压式稳压型MAX1830/MAX183177.双输出开关式LCD电源控制器MAX187878.电流模式升压式DC-DC电源转换器MAX189679.具有复位功能的升压式DC-DC电源转换器MAX194780.高效率PWM降压式稳压器MAX1992/MAX199381.大电流输出升压式DC-DC电源转换器MAX61882.低功耗升压或降压式DC-DC电源转换器MAX62983.PWM升压式DC-DC电源转换器MAX668/MAX66984.大电流PWM降压式开关稳压器MAX724/MAX72685.高效率升压式DC-DC电源转换器MAX756/MAX75786.高效率大电流DC-DC电源转换器MAX761/MAX76287.隔离式DC-DC电源转换器MAX8515/MAX8515A88.高性能24V升压式DC-DC电源转换器MAX872789.升/降压式DC-DC电源转换器MC33063A/MC34063A90.5A升压/降压/反向DC-DC电源转换器MC33167/MC3416791.低噪声无电感电荷泵MCP1252/MCP125392.高频脉宽调制降压稳压器MIC220393.大功率DC-DC升压电源转换器MIC229594.单片微型高压开关稳压器NCP1030/NCP103195.低功耗升压式DC-DC电源转换器NCP1400A96.高压DC-DC电源转换器NCP140397.单片微功率高频升压式DC-DC电源转换器NCP141098.同步整流PFM步进式DC-DC电源转换器NCP142199.高效率大电流开关电压调整器NCP1442/NCP1443/NCP1444/NCP1445100.新型双模式开关稳压器NCP1501101.高效率大电流输出DC-DC电源转换器NCP1550102.同步降压式DC-DC电源转换器NCP1570103.高效率升压式DC-DC电源转换器NCP5008/NCP5009 104.大电流高速稳压器RT9173/RT9173A105.高效率升压式DC-DC电源转换器RT9262/RT9262A106.升压式DC-DC电源转换器SP6644/SP6645107.低功耗升压式DC-DC电源转换器SP6691108.新型高效率DC-DC电源转换器TPS54350109.无电感降压式电荷泵TPS6050x110.高效率升压式电源转换器TPS6101x111.28V恒流白色LED驱动器TPS61042112.具有LDO输出的升压式DC-DC电源转换器TPS6112x 113.低噪声同步降压式DC-DC电源转换器TPS6200x114.三路高效率大功率DC-DC电源转换器TPS75003115.高效率DC-DC电源转换器UCC39421/UCC39422116.PWM控制升压式DC-DC电源转换器XC6371117.白光LED驱动专用DC-DC电源转换器XC9116118.500mA同步整流降压式DC-DC电源转换器XC9215/XC9216/XC9217119.稳压输出电荷泵XC9801/XC9802120.高效率升压式电源转换器ZXLB16001.2 线性/低压差稳压器121.具有可关断功能的多端稳压器BAXXX122.高压线性稳压器HIP5600123.多路输出稳压器KA7630/KA7631124.三端低压差稳压器LM2937125.可调输出低压差稳压器LM2991126.三端可调稳压器LM117/LM317127.低压降CMOS500mA线性稳压器LP38691/LP38693128.输入电压从12V到450V的可调线性稳压器LR8129.300mA非常低压降稳压器（VLDO）LTC3025130.大电流低压差线性稳压器LX8610131.200mA负输出低压差线性稳压器MAX1735132.150mA低压差线性稳压器MAX8875133.带开关控制的低压差稳压器MC33375134.带有线性调节器的稳压器MC33998135.1.0A低压差固定及可调正稳压器NCP1117136.低静态电流低压差稳压器NCP562/NCP563137.具有使能控制功能的多端稳压器PQxx138.五端可调稳压器SI-3025B/SI-3157B139.400mA低压差线性稳压器SPX2975140.五端线性稳压器STR20xx141.五端线性稳压器STR90xx142.具有复位信号输出的双路输出稳压器TDA8133143.具有复位信号输出的双路输出稳压器TDA8138/TDA8138A144.带线性稳压器的升压式电源转换器TPS6110x145.低功耗50mA低压降线性稳压器TPS760xx146.高输入电压低压差线性稳压器XC6202147.高速低压差线性稳压器XC6204148.高速低压差线性稳压器XC6209F149.双路高速低压差线性稳压器XC64011.3 基准电压源150.新型XFET基准电压源ADR290/ADR291/ADR292/ADR293151.低功耗低压差大输出电流基准电压源MAX610x152.低功耗1.2V基准电压源MAX6120153.2.5V精密基准电压源MC1403154.2.5V/4.096V基准电压源MCP1525/MCP1541155.低功耗精密低压降基准电压源REF30xx/REF31xx156.精密基准电压源TL431/KA431/TLV431A第2章AC-DC转换器及控制器1.厚膜开关电源控制器DP104C2.厚膜开关电源控制器DP308P3.DPA-Switch系列高电压功率转换控制器DPA423/DPA424/DPA425/DPA4264.电流型开关电源控制器FA13842/FA13843/FA13844/FA138455.开关电源控制器FA5310/FA53116.PWM开关电源控制器FAN75567.绿色环保的PWM开关电源控制器FAN76018.FPS型开关电源控制器FS6M07652R9.开关电源功率转换器FS6Sxx10.降压型单片AC-DC转换器HV-2405E11.新型反激准谐振变换控制器ICE1QS0112.PWM电源功率转换器KA1M088013.开关电源功率转换器KA2S0680/KA2S088014.电流型开关电源控制器KA38xx15.FPS型开关电源功率转换器KA5H0165R16.FPS型开关电源功率转换器KA5Qxx17.FPS型开关电源功率转换器KA5Sxx18.电流型高速PWM控制器L499019.具有待机功能的PWM初级控制器L599120.低功耗离线式开关电源控制器L659021.LINK SWITCH TN系列电源功率转换器LNK304/LNK305/LNK30622.LINK SWITCH系列电源功率转换器LNK500/LNK501/LNK52023.离线式开关电源控制器M51995A24.PWM电源控制器M62281P/M62281FP25.高频率电流模式PWM控制器MAX5021/MAX502226.新型PWM开关电源控制器MC4460427.电流模式开关电源控制器MC4460528.低功耗开关电源控制器MC4460829.具有PFC功能的PWM电源控制器ML482430.液晶显示器背光灯电源控制器ML487631.离线式电流模式控制器NCP120032.电流模式脉宽调制控制器NCP120533.准谐振式PWM控制器NCP120734.低成本离线式开关电源控制电路NCP121535.低待机能耗开关电源PWM控制器NCP123036.STR系列自动电压切换控制开关STR8xxxx37.大功率厚膜开关电源功率转换器STR-F665438.大功率厚膜开关电源功率转换器STR-G865639.开关电源功率转换器STR-M6511/STR-M652940.离线式开关电源功率转换器STR-S5703/STR-S5707/STR-S570841.离线式开关电源功率转换器STR-S6401/STR-S6401F/STR-S6411/STR-S6411F 442.开关电源功率转换器STR-S651343.离线式开关电源功率转换器TC33369～TC3337444.高性能PFC与PWM组合控制集成电路TDA16846/TDA1684745.新型开关电源控制器TDA1685046.“绿色”电源控制器TEA150447.第二代“绿色”电源控制器TEA150748.新型低功耗“绿色”电源控制器TEA153349.开关电源控制器TL494/KA7500/MB375950.Tiny SwitchⅠ系列功率转换器TNY253、TNY254、TNY25551.Tiny SwitchⅡ系列功率转换器TNY264P～TNY268G52.TOP Switch（Ⅱ）系列离线式功率转换器TOP209～TOP22753.TOP Switch-FX系列功率转换器TOP232/TOP233/TOP23454.TOP Switch-GX系列功率转换器TOP242～TOP25055.开关电源控制器UCX84X56.离线式开关电源功率转换器VIPer12AS/VIPer12ADIP57.新一代高度集成离线式开关电源功率转换器VIPer53第3章功率因数校正控制/节能灯电源控制器1.电子镇流器专用驱动电路BL83012.零电压开关功率因数控制器FAN48223.功率因数校正控制器FAN75274.高电压型EL背光驱动器HV8265.EL场致发光背光驱动器IMP525/IMP5606.高电压型EL背光驱动器/反相器IMP8037.电子镇流器自振荡半桥驱动器IR21568.单片荧光灯镇流器IR21579.调光电子镇流器自振荡半桥驱动器IR215910.卤素灯电子变压器智能控制电路IR216111.具有功率因数校正电路的镇流器电路IR216612.单片荧光灯镇流器IR216713.自适应电子镇流器控制器IR252014.电子镇流器专用控制器KA754115.功率因数校正控制器L656116.过渡模式功率因数校正控制器L656217.集成背景光控制器MAX8709/MAX8709A18.功率因数校正控制器MC33262/MC3426219.固定频率电流模式功率因数校正控制器NCP165320.EL场致发光灯高压驱动器SP440321.功率因数校正控制器TDA4862/TDA486322.有源功率因数校正控制器UC385423.高频自振荡节能灯驱动器电路VK05CFL24.大功率高频自振荡节能灯驱动器电路VK06TL第4章充电控制器1.多功能锂电池线性充电控制器AAT36802.可编程快速电池充电控制器BQ20003.可进行充电速率补偿的锂电池充电管理器BQ20574.锂电池充电管理电路BQ2400x5.单片锂电池线性充电控制器BQ2401xB接口单节锂电池充电控制器BQ2402x7.2A同步开关模式锂电池充电控制器BQ241008.集成PWM开关控制器的快速充电管理器BQ29549.具有电池电量计量功能的充电控制器DS277010.锂电池充电控制器FAN7563/FAN756411.2A线性锂/锂聚合物电池充电控制器ISL629212.锂电池充电控制器LA5621M/LA5621V13.1.5A通用充电控制器LT157114.2A恒流/恒压电池充电控制器LT176915.线性锂电池充电控制器LTC173216.带热调节功能的1A线性锂电池充电控制器LTC173317.线性锂电池充电控制器LTC173418.新型开关电源充电控制器LTC198019.开关模式锂电池充电控制器LTC400220.4A锂电池充电器LTC400621.多用途恒压/恒流充电控制器LTC400822.4.2V锂离子/锂聚合物电池充电控制器LTC405223.可由USB端口供电的锂电池充电控制器LTC405324.小型150mA锂电池充电控制器LTC405425.线性锂电池充电控制器LTC405826.单节锂电池线性充电控制器LTC405927.独立线性锂电池充电控制器LTC406128.镍镉/镍氢电池充电控制器M62256FP29.大电流锂/镍镉/镍氢电池充电控制器MAX150130.锂电池线性充电控制器MAX150731.双输入单节锂电池充电控制器MAX1551/MAX155532.单节锂电池充电控制器MAX167933.小体积锂电池充电控制器MAX1736B接口单节锂电池充电控制器MAX181135.多节锂电池充电控制器MAX187336.双路输入锂电池充电控制器MAX187437.单节锂电池线性充电控制器MAX189838.低成本/多种电池充电控制器MAX190839.开关模式单节锂电池充电控制器MAX1925/MAX192640.快速镍镉/镍氢充电控制器MAX2003A/MAX200341.可编程快速充电控制器MAX712/MAX71342.开关式锂电池充电控制器MAX74543.多功能低成本充电控制器MAX846A44.具有温度调节功能的单节锂电池充电控制器MAX8600/MAX860145.锂电池充电控制器MCP73826/MCP73827/MCP7382846.高精度恒压/恒流充电器控制器MCP73841/MCP73842/MCP73843/MCP73844 647.锂电池充电控制器MCP73861/MCP7386248.单节锂电池充电控制器MIC7905049.单节锂电池充电控制器NCP180050.高精度线性锂电池充电控制器VM7205。

RT8290A®©Copyright 2018 Richtek Technology Corporation. All rights reserved.is a registered trademark of Richtek Technology Corporation.Design ToolsGeneral DescriptionThe RT8290A is a high efficiency synchronous step-down DC/DC converter that can deliver up to 3A output current from 4.5V to 23V input supply. The RT8290A's current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. Cycle-by-cycle current limit provides protection against shorted outputs and soft-start eliminates input current surge during start-up. The RT8290A also provides output under voltage protection and thermal shutdown protection. The low current (<3μA)shutdown mode provides output disconnection, enabling easy power management in battery-powered systems. The RT8290A is awailable in an SOP-8 (Exposed Pad)package.3A, 23V, 340kHz Synchronous Step-Down ConverterFeatures●4.5V to 23V Input Voltage Range●1.5% High Accuracy Feedback Voltage ●3A Output Current●Integrated N-MOSFET Switches ●Current Mode Control●Fixed Frequency Operation : 340kHz ●Output Adjustable from 0.925V to 20V ●Up to 95% Efficiency●Programmable Soft-Start●Stable with Low-ESR Ceramic Output Capacitors ●Cycle-by-Cycle Over Current Protection ●Input Under Voltage Lockout ●Output Under Voltage Protection ●Thermal Shutdown Protection ●PSM / PWM Auto-Switched●Thermally Enhanced SOP-8 (Exposed Pad) Package ●RoHS Compliant and Halogen FreeApplications●Industrial and Commercial Low Power Systems ●Computer Peripherals ●LCD Monitors and TVs●Green Electronics/Appliances●Point of Load Regulation of High-Performance DSPs,FPGAs and ASICs.Ordering InformationNote :Richtek products are :❝RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.❝Suitable for use in SnPb or Pb-free soldering processes.G : Green (Halogen Free and Pb Free)Simplified Application CircuitOUTVRT8290A©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Marking InformationRT8290AGSP : Product NumberYMDNN : Date CodeFunctional Pin DescriptionPin Configurations(TOP VIEW)SOP-8 (Exposed Pad)SS BOOT VIN GNDSW FBEN COMPRT8290A©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Function Block DiagramAbsolute Maximum Ratings (Note 1)●Supply Voltage, V IN ------------------------------------------------------------------------------------------−0.3V to 25V●Switching Voltage, SW -------------------------------------------------------------------------------------−0.3V to (V IN + 0.3V)●SW (AC) 30ns-------------------------------------------------------------------------------------------------−5V to 30V●BOOT Voltage -------------------------------------------------------------------------------------------------(V SW − 0.3V) to (V SW + 6V)●The Other Pins ------------------------------------------------------------------------------------------------−0.3V to 6V ●Power Dissipation, P D @ T A = 25°CSOP-8 (Exposed Pad)--------------------------------------------------------------------------------------1.333W ●Package Thermal Resistance (Note 2)SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------75°C/W SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------15°C/W ●Junction T emperature ----------------------------------------------------------------------------------------150°C ●Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------260°C●Storage T emperature Range -------------------------------------------------------------------------------−65°C to 150°C ●ESD Susceptibility (Note 3)HBM (Human Body Model)---------------------------------------------------------------------------------2kV MM (Machine Model)----------------------------------------------------------------------------------------200VRecommended Operating Conditions (Note 4)●Supply Voltage, V IN ------------------------------------------------------------------------------------------4.5V to 23V ●Enable Voltage, V EN -----------------------------------------------------------------------------------------0V to 5.5V●Junction T emperature Range -------------------------------------------------------------------------------−40°C to 125°C ●Ambient T emperature Range -------------------------------------------------------------------------------−40°C to 85°CRT8290A©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.Note 2. θJA is measured at T A = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC ismeasured at the exposed pad of the package.Note 3. Devices are ESD sensitive. Handling precaution is recommended.Note 4. The device is not guaranteed to function outside its operating conditions.Electrical Characteristics(V = 12V, T = 25°C unless otherwise specified)RT8290A©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Typical Application CircuitOUT VTable 1. Recommended Component SelectionRT8290A©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Typical Operating CharacteristicsReference Voltage vs. Temperature0.9100.9150.9200.9250.9300.9350.940-50-25255075100125Temperature (°C)R e f e r e n c e V o l t a g e (V)Reference Voltage vs. Input Voltage0.9200.9220.9240.9260.9280.9300.9324681012141618202224Input Voltage (V)R e f e r e n c e V o l t a g e (V )Efficiency vs. Output Current01020304050607080901000.010.1110Output Current (A)E f f i c i e n c y (%)Output Voltage vs. Output Current3.203.223.243.263.283.303.323.343.363.383.400.00.30.60.91.21.51.82.12.42.73.0Output current (A)O u t p u t V o l t a g e (V)Frequency vs. Input Voltage3003053103153203253303353403453504681012141618202224Input Voltage (V)F r e q u e n c y (k H z )Frequency vs. Temperature300305310315320325330335340345350-50-25255075100125Temperature (°C)F r e q u e n c y (k H z )RT8290A©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Current Limit vs. Temperature3.03.54.04.55.05.56.06.57.0-50-25255075100125Temprature (°C)C u r r e n t L i m i t (A)Time (5ms/Div)Power On from VIN I L (2A/Div)V IN = 12V, V OUT = 3.3V, I OUT = 3AV IN (5V/Div)V OUT (2V/Div)Power Off from VINTime (5ms/Div)I L (2A/Div)V IN (5V/Div)V OUT (2V/Div)V IN = 12V, V OUT = 3.3V, I OUT = 3ASwitching WaveformTime (1μs/Div)V OUT (10mV/Div)V SW (10V/Div)V IN = 12V, V OUT = 3.3V, I OUT = 3AI L (2A/Div)Load Transient ResponseTime (100μs/Div)I OUT (2A/Div)V OUT(100mV/Div)V IN = 12V, V OUT = 3.3V, I OUT = 0.3A to 3ALoad Transient ResponseTime (100μs/Div)I OUT (2A/Div)V OUT(100mV/Div)V IN = 12V, V OUT = 3.3V, I OUT = 1.5A to 3ART8290A©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Power On from ENTime (10ms/Div)V IN = 12V, V OUT = 3.3V, I OUT = 3AI OUT (2A/Div)V EN (2V/Div)V OUT (2V/Div)Power Off from ENTime (10ms/Div)I OUT (2A/Div)V EN (2V/Div)V OUT (2V/Div)V IN = 12V, V OUT = 3.3V, I OUT = 3ART8290A©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Application InformationThe RT8290A is a synchronous high voltage buck converter that can support the input voltage range from 4.5V to 23V and the output current can be up to 3A.Output Voltage SettingThe resistive voltage divider allows the FB pin to sense the output voltage as shown in Figure 1.Figure 1. Output Voltage SettingThe output voltage is set by an external resistive voltage divider according to the following equation :⎛⎫+ ⎪⎝⎭OUT FB R1V = V 1R2where V FB is the feedback reference voltage (0.925V typ.).External Bootstrap DiodeConnect a 10nF low ESR ceramic capacitor between the BOOT pin and SW pin. This capacitor provides the gate driver voltage for the high side MOSFET.It is recommended to add an external bootstrap diode between an external 5V and the BOOT pin for efficiencyimprovement when input voltage is lower than 5.5V or duty ratio is higher than 65%. The bootstrap diode can be a low cost one such as 1N4148 or BAT54.The external 5V can be a 5V fixed input from system or a 5V output of the RT8290A. Note that the external boot voltage must be lower than 5.5V.Figure 2. External Bootstrap DiodeOUT OUT L IN V V I =1f L V ⎡⎤⎡⎤Δ×−⎢⎥⎢⎥×⎣⎦⎣⎦Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. High frequency with small ripple current can achieve highest efficiency operation. However, it requires a large inductor to achieve this goal.For the ripple current selection, the value of ΔI L = 0.2375(I MAX ) will be a reasonable starting point. The largest ripple current occurs at the highest V IN . To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation :OUT OUT L(MAX)IN(MAX)V V L =1f I V ⎡⎤⎡⎤×−⎢⎥⎢×Δ⎣⎦⎣⎦Inductor Core SelectionThe inductor type must be selected once the value for L is known. Generally speaking, high efficiency converters can not afford the core loss found in low cost powdered iron cores. So, the more expensive ferrite or mollypermalloy cores will be a better choice.The selected inductance rather than the core size for a fixed inductor value is the key for actual core loss. As the inductance increases, core losses decrease. Unfortunately,increase of the inductance requires more turns of wire and therefore the copper losses will increase.Ferrite designs are preferred at high switching frequency due to the characteristics of very low core losses. So,design goals can focus on the reduction of copper loss and the saturation prevention.Soft-StartThe RT8290A contains an external soft-start clamp that gradually raises the output voltage. The soft-start timing can be programmed by the external capacitor betweenSS pin and GND. The chip provides a 6μA charge current for the external capacitor. If a 0.1μF capacitor is used to set the soft-start, the period will be 15.5ms (typ.).Inductor SelectionThe inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔI L increases with higher V IN and decreases with higher inductance.RT8290A©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Ferrite core material saturates “hard ”, which means that inductance collapses abruptly when the peak design current is exceeded. The previous situation results in an abrupt increase in inductor ripple current and consequent output voltage ripple.Do not allow the core to saturate!Different core materials and shapes will change the size/current and price/current relationship of an inductor.T oroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate energy. However, they are usually more expensive than the similar powdered iron inductors. The rule for inductor choice mainly depends on the price vs. size requirement and any radiated field/EMI requirements.C IN and C OUT SelectionThe input capacitance, C IN, is needed to filter the trapezoidal current at the source of the high side MOSFET .To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by :This formula has a maximum at V IN = 2V OUT , whereI RMS = I OUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief.Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design.For the input capacitor, a 10μF x 2 low ESR ceramic capacitor is recommended. For the recommended capacitor, please refer to table 3 for more detail.The selection of C OUT is determined by the required ESR to minimize voltage ripple.Moreover, the amount of bulk capacitance is also a key for C OUT selection to ensure that the control loop is stable.Loop stability can be checked by viewing the load transient response as described in a later section.The output ripple, ΔV OUT, is determined by :RMS OUT(MAX)I = I OUT L OUT 1V I ESR 8fC ⎡⎤Δ≤Δ+⎢⎥⎣⎦The output ripple will be highest at the maximum input voltage since ΔI L increases with input voltage. Multiplecapacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. Dry tantalum,special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages.Special polymer capacitors offer very low ESR value.However, it provides lower capacitance density than other types. Although Tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies.Aluminum electrolytic capacitors have significantly higher ESR. However, it can be used in cost-sensitive applications for ripple current rating and long term reliability considerations. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing.Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, V IN . At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at V IN large enough to damage the part.Checking Transient ResponseThe regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V OUT immediately shifts by an amount equal to ΔI LOAD (ESR) and C OUT also begins to be charged or discharged to generate a feedback error signal for the regulator to return V OUT to its steady-state value. During this recovery time, V OUT can be monitored for overshoot or ringing that would indicate a stability problem.RT8290A11DS8290A-03 March 2018©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Thermal ConsiderationsFor continuous operation, do not exceed the maximum operation junction temperature 125°C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient.The maximum power dissipation can be calculated by following formula :P D(MAX) = (T J(MAX) − T A ) / θJAwhere T J(MAX) is the maximum operation junction temperature, T A is the ambient temperature and the θJA is the junction to ambient thermal resistance.For recommended operating conditions specification, the maximum junction temperature is 125°C. The junction to ambient thermal resistance θJA is layout dependent. For SOP-8 (Exposed Pad) package, the thermal resistance θJA is 75°C/W on the standard JEDEC 51-7 four-layers thermal test board. The maximum power dissipation at T A = 25°C can be calculated by following formula :P D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for SOP-8 (Exposed Pad) packageThe maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA . The derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.Layout ConsiderationsFollow the PCB layout guidelines for optimal performance of the RT8290A.❝Keep the traces of the main current paths as short and wide as possible.❝Put the input capacitor as close as possible to the device pins (VIN and GND).❝SW node is with high frequency voltage swing and should be kept in a small area. Keep sensitive components away from the SW node to prevent stray capacitive noise pick-up.❝Place the feedback components as close to the FB pin and COMP pin as possible.❝The GND pin and Exposed Pad should be connected to a strong ground plane for heat sinking and noise protection.Figure 3. Derating Curve of Maximum Power DissipationInput capacitor must be placed Figure 4. PCB Layout Guide0.00.20.40.60.81.01.21.41.6255075100125Ambient Temperature (°C)M a x i m u m P o w e r D i s s i p a t i o n (W )RT8290A12DS8290A-03 March 2018 ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Table 3. Suggested Capacitors for Cand CRT8290A13DS8290A-03 March 2018Richtek Technology Corporation14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C.Tel: (8863)5526789Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers shouldobtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.Outline DimensionBFHMI(Bottom of Package)8-Lead SOP (Exposed Pad) Plastic Package。