BackLED L en 2010-12-15

译文原文题目: LED Backlight Driving Systemfor Large-scale LCD Panels译文题目：LED背光驱动系统的大型液晶面板学院：电子信息学院专业班级：测控技术与仪器2009级2班学生姓名：余勇学号：40903050230LED Backlight Driving System for Large-Scale LCD PanelsHuang-Jen Chiu, Member, IEEE, and Shih-Jen Cheng Abstract：This paper presents an LED backlight driving system for large-scale liquid crystal display panels. High efficiency, high power factor, circuit simplicity, and low cost can be achieved by using a single-stage charge-pump asymmetrical half-bridge converter. To regulate the LED current and brightness for the LED backlight system, some current sharing methods are presented and compared. The requirements for the current sharing and luminance balance among paralleled LED arrays can be satisfied while current ripple is eliminated significantly. Because of the addition of bypass diodes, an alternative current path can be offered when a single LED fails. The LED array will not be extinguished. Reliability of the LED backlight system can thus be improved effectively.Keywords:light-emitting diode (LED) backlight, power factor, single-stage charge-pump asymmetrical half-bridge .I.INTRODUCTIONConventionally, multiple cold cathode fluorescent lamps (CCFLs) are required to provide sufficient backlighting for large-scale liquid crystal display (LCD) panels [1]–[6]. Growing concerns about environmental issues will exhibit the use of CCFLs that contain poisonous mercury, Owing to the improvement in long operative life, wider operation temperature range, and the simplicity of driver circuit, working with low and safe voltages, LED has gradually substituted CCFL as backlight [7]–[9]. As shown in Fig. 1,a typical LED backlight driving system is composed of a power factor corrector (PFC) and a dc/dc converter. The PFC circuit is added to achieve a sinusoidal source current, and the post stage dc/dc converter is used to regulate the current flow through the LED arrays with the current-limit resistors. The two-stage cascade configuration causes high circuit complexity and lower conversion efficiency as a result of twice the power conversion and resistive losses [10]–[13]. In theliterature [14], [15], a family of single-stage converter circuits that employs a charging capacitor to implement the power factor correction was presented. This type of circuit is sometimes referred to as the ―charge-pump converter.‖ The circuit simplicity and the high conversion efficiency are more attractive for low-power ac/dc applications. However, the output voltage ripple at twice the line frequency of the single-stage converter is poor. With only a small change in the forward bias voltage of the LEDs, the corresponding forward bias current increases by orders of magnitude. The variation in LED current would seriously affect the longevity of the LED backlight [16]–[19]. To regulate the LED current for the LED backlight system, some dimming control methods are presented and compared in this paper. The requirements for the current sharing and luminance balance among paralleled LED arrays can be satisfied while the current ripple is eliminated significantly. Furthermore, bypass diodes are added to offer an alternative current path when a single LED fails. Reliability can thus be improved effectively. The operation principles and design considerations for the studied LED backlight driving system are analyzed and discussed in the next sections.Fig. 1. Typical LED backlight driving system.II.DESCRIPTION OF OPERATION PRINCIPLESFig. 2 shows the studied single-stage LED backlight driving system with dimming control. The presented driving system consists of a charge-pump PFC cell integrated with an asymmetrical half-bridge (AHB) dc/dc cell. The charge-pump PFCcell is composed of resonant inductor Lr, charge-pump capacitors Cr1 and Cr2, input diodes Di1, and Di2, and clamping diodes Dc1 and Dc2. The power MOSFETs Q1 and Q2 operate with asymmetrical duty ratios δ and 1 − δ, which require short and well-defined dead time between the conduction intervals. D1, D2 and Cp1, Cp2 are the body diodes and the parasitic capacitors of power MOSFETs, respectively. The capacitor Cbus is used as the dc bus capacitor between the chargepump PFC cell and the poststage AHB dc/dc cell. The transformer leakage inductor Ll resonates with the parasitic capacitors Cp1 and Cp2 during dead-time intervals to achieve zero-voltage switching (ZVS) for the power MOSFETs. The blocking capacitor Cb is used to assure that the power sent into the transformer primary winding is a pure ac type. A dc voltage is supplied to the LED arrays through the secondary rectifier and filter circuit that are composed of D3, D4, Lo, and Co. The dimming circuits are connected in series with the corresponding LED arrays to regulate the LED current. Based on the symbols and signal polarities shown in Fig. 2, the theoretical waveforms of the single-stage ac/dc converter are shown in Fig. 3.Fig. 2Single-stage LED backlight driving system.Fig. 3. Theoretical waveforms of the single-stage ac/dc converter.There are 14 switching modes within an operating cycle. Referring to the equivalent circuits in Fig. 4, the operating principle of the single-stage ac/dc converter can be explained in detail.Fig. 4. Equivalent circuits for different switching modes.• Mode 1 (t0–t1): At t0, the input diode Di1 conducts and the voltage across the charge-pump capacitors Cr1 and Cr2 is clamped to the rectified input voltage |Vin|. During this mode, the lower switch Q2 is on. Cr1 is charged and Cr2 is discharged by the resonant inductor current ILr.• Mode 2 (t1–t2): At t1, the lower switch Q2 is turned off. The parasitic capacitor Cp1 is discharged and the parasitic capacitor Cp2 is charged by the leakage inductor current ILl. The voltage Vds1 across the upper switch Q1 decreases linearly and the voltage Vds2 across the lower switch Q2 increases linearly. When the voltage Vds2 is equal to the blocking capacitor voltage Vb at t2, the transformer winding voltagedecreases to zero and both secondary rectifier diodes D3 and D4 are on.• Mode 3 (t2–t3): During this time interval, the transformer winding voltage is clamped to zero, owing to the rectifier diodes D3 and D4 conduction. The parasitic capacitors Cp1 and Cp2 resonate with the transformer leakage inductor Ll. When the voltage Vds2 increases to the dc bus voltage Vbus at t3, the body diode D1 conducts and the ZVS of the upper switch Q1 can be achieved.• Mode 4 (t3–t4): During this time interval, the body diode D1 conducts and the voltage Vds2 is clamped to the dc bus voltage Vbus. The leakage inductor current ILl is forced to change its direction by the voltage difference of the dc bus voltage and the blocking capacitor voltage (Vbus − Vb).• Mode 5 (t4–t5): At t4, the current ILl changes its direction and the upper switch Q1 is turned on with ZVS. The secondary diode D4 is reverse-biased. The output inductor current flows through the rectifier diode D3.• Mode 6 (t5–t6): At t5, the charge-pump capacitor voltage VCr1 increases to the rectified input voltage |Vin| and the charge-pump capacitor voltage VCr2 decreases to zero. The clamping diode Dc2 conducts and the input diode Di1 is off. During this time interval, the dc bus voltage Vbus forces the resonant inductor current ILr to change its direction.• Mode 7 (t6–t7): When the resonant inductor current ILr changes its direction at t6, the charge-pump capacitor Cr2 is charged and its voltage VCr2 increases. Mode 8 (t7–t8): At t7, the voltage across the charge pump capacitors Cr1 and Cr2 is equal to the dc bus voltage Vbus and the input diode Di2 conducts. In this time interval, the capacitor voltage (VCr1 + VCr2) is clamped to the dc bus voltage Vbus due to the diode Di2 conduction. The capacitor Cr1 is discharged and the capacitor Cr2 is charged by the resonant inductor current ILr.• Mode 9 (t8–t9): The upper switch Q1 is turned off at t8. The parasitic capacitor Cp1 is charged and the parasitic capacitor Cp2 is discharged by the leakage inductor current ILl. The voltage Vds1 across the upper switch Q1 increases linearly and the voltage Vds2 across the lower switch Q2 decreases linearly. When the voltage Vds2 isequal to the blocking capacitor voltage Vb at t9, the transformer winding voltage decreases to zero and both secondary rectifier diodes D3 and D4 are on.• Mode 10 (t9–t10): During this time interval, the transformer winding voltage is clamped to zero due to the rectifier diodes D3 and D4 conduction. The parasitic capacitors Cp1 and Cp2 resonate with the trans-former leakage inductor Ll. When the voltage Vds2 decreases to zero at t10, the body diode D2 conducts and the ZVS of the lower switch Q2 can be achieved.• Mode 11 (t10–t11): During this time interval, the body diode D2 conducts and the voltage Vds2 is clamped to zero. The leakage inductor current ILl is forced to change its direction by the blocking capacitor voltage Vb.• Mode 12 (t11–t12): At t11, the current ILl changes its direction and the lower switch Q2 is turned on with ZVS. The secondary diode D3 is reverse-biased. The output inductor current flows through the rectifier diode D4.• Mode 13 (t12–t13): At t12, the charge-pump capacitor voltage VCr2 increases to the dc bus voltage Vbus and the charge-pump capacitor voltage VCr1 decreases to zero. The clamping diode Dc1 conducts and the input diode Di2 is off. The dc bus voltage Vbus forces the resonant inductor current ILr to change its direction.• Mode 14 (t13–t14): When the resonant inductor current ILr changes its direction at t13, the charge-pump capacitor Cr2 is discharged and its voltage VCr2 decreases. At t14,the capacitor voltage VCr2 decreases to rectified input voltage |Vin| and the input diodeDi1 conducts. The circuit will then proceed back to mode 1 after completing one operating cycle Ts. Thus, the capacitor voltage VCr1(t0) is zero and the capacitor voltage VCr2(t0) is the rectified input voltage |Vin|.III.DESIGN CONSIDERATIONS FOR THE LED BACKLIGHTDRIVING SYSTEMCurrent Sharing Among Parallel-Connected LED Arrays As shown in Fig.5(a), backlight LEDs of a large-scale LCD panel are usually connected in series andparallel. Variation in current/voltage characteristics of the backlight LEDs, as shown in Fig5(b), will cause luminance difference [16].（a）(b)Fig. 5. (a) LED backlight configuration. (b) Variation in LED current/voltagecharacteristics.The same amount of brightness provided by each LED array must be ensured so that the LCD panel has uniform backlight. In this paper, we introduce the following three dimming control methods for current sharing and luminance balance among the parallel-connected LED arrays in the LED back-light driving system: 1) the transconductance-amplifier (TA) dimming, 2) the current-mirror (CM) dimming, and 3) the burst-mode (BM) dimming. The operation principles and the advantages/drawbacks of these methods will be presented as follows.1) TA Dimming: The dimming circuit for LED current regulation is composed of a transconductance amplifier as shown in Fig. 6(a). The small-signal equivalent circuit shown in Fig. 6(b) is a series –series feedback configuration [20]. The feedback factor β and the closed -loop transfer function Agf can be derived as follows:d le d fb R I V ==β (1) d d g fe g fe d led gf R R A h A h V I A 1)(1≈+== (2)where hfe is the common –emitter current gain of the dimming transistor Qd, and Ag is the open-loop transconductance gain of the operational amplifier (OPA). Based on (2), the LED current can be regulated by the dimming voltage Vd asd dled R V I =. (3)(a)(b)Fig6(a) TA dimming circuit. (b) Small-signal equivalent circuit.For a given dimming resistor Rd, the current sharing among paralleled LED arrays can be achieved with the same dimming voltage Vd, and the current ripple at twice the line frequency caused by the single-stage ac/dc converter can also be eliminated. However, the conduction losses of the dimming transistors under dimming operation are very significant such that the thermal problem for the backlight system will be difficult to solve.2) CM Dimming: The dimming circuit is composed of a current mirror as shown in Fig7. The LED current can be regulated by the dimming voltage Vd asd BE dref ref ledN led led R V V I I N I I I -=≈++===β/)1(1121 (4)Fig7. CM dimming circuit.Therefore, the current sharing and ripple reduction can also be achieved. The CM dimming circuit is much simpler than the TA dimming circuit because the OPAs are not required. The conduction losses, however, and the resulting thermal problem of the dimming transistors in the CM circuit are still significant under dimming operation.3) BM Dimming: To achieve the dimming feature for LCD television, the backlight LED current can be controlled with a BM dimming circuit as shown in Fig. 8(a). The operating frequency of the dimming transistor Qd must be higher than 70 Hz that are perceivable to the human eye. Considering the switching loss for the dimming transistors, the BM frequency is usually designed at 400 Hz in practicalapplication. Because of the variations in current/voltage characteristics shown in Fig. 5(b), different LED array currents under the same supply voltage Vo will cause luminance difference. The pulsewidth of the gating signal for the dimming transistors will be varied to achieve the same LED average current Iled(av) as shown in Fig. 8(b). The current sharing and luminance balance can be achieved by using the BM dimming method. The dimming transistors are operated as low-frequency switches for the BM dimming method, thus the conduction losses can be significantly reduced. The thermal problem on the dimming transistors for the TA dimming or CM dimming methods will be improved.(a)(b)Fig. 8. (a) BM dimming circuit. (b) Theoretical waveforms.B. LED Bypass DesignFor an LED backlight system shown in Fig. 5(a), any LED failure will result in the extinguishment of the corresponding LED array. This problem can be partially solved by an LED lattice placement [21]. However, it makes the LED connection more complex and reduces reliability of the backlight system. In this paper, we present a bypass design for LED failure. As shown in Fig. 9(a), the backlight LED is parallel connected with a Zener diode. Under normal operation, the voltage across the backlight LED does not reach the breakdown voltage of the Zener diode and the current flows through the LED. When an LED fails, the LED current can flow through the parallel connected Zener diode and the LED array will not be extinguished. The reliability of the LED backlight system can be improved by the bypass design. A circuit variation for LED bypass design is shown in Fig. 9(b). If a backlight LED fails and the voltage across the Zener diode reach its breakdown voltage, the silicon controlled rectifier will be triggered to prevent the LED array from extinguishment.(a)(b)Fig. 9. Bypass design for backlight LED failure.C. Charge-Pump PFC DesignDuring the time interval from t0 to t5, the energy from the ac line input is transferred into the single-stage ac/dc converter. The capacitor voltage VCr1 is charged from zero to the rectified input voltage |Vin|. Therefore, the average rectified input current |Iin|av can be expressed as follows:in r s s av in V C f T Q I 1=∆= (5)where ΔQ is the charge variation of Cr1. From (5), we can see that the average rectified input current is proportional to the rectified input voltage. Thus, high power factor can be achieved. Based on the power balance between the input and output of the ac/dc converter, the following equation has to be satisfied: in in av in V V P I 202η= (6)where Po and η are the output power and overall efficiency of the converter. From (5) and (6), the design equations for the charge-pump capacitor Cr1 and the resonant inductor Lr can be derived as follows:2012in s r V f P C η= (7)0228P f V L s in r ∏=η (8)D. ZVS Design as shown in Fig. 4, the current (ILr + ILl) starts to flow through the body diode D1 at t3. As long as the upper switch Q1 is turned on before the inductor current ILl changes its direction at t4, ZVS can be assured. Thus, the ZVS condition of the upper switch Q1 is2212102)(21)(21bus p p Lr p s l V C C t I I n n L +≥⎥⎥⎦⎤⎢⎢⎣⎡+ （9）where np and ns2 are the turn number of the transformer primary and secondary lower windings. At t10, the current (ILr + ILl) starts to flow through the body diode D2. As long as the lower switch Q2 is turned on before the inductor current ILl changes its direction at t11, ZVS can be assured. Thus, the ZVS condition of the lower switch Q2 is 221201)(21)(21bus P P s Lr p s l V C C t I I n n L +≥⎥⎥⎦⎤⎢⎢⎣⎡+ (10)where ns1 are the turn number of the transformer secondary upper winding. The ZVS conditions depend on the resonant inductance current ILr that is related with the input voltage. At the zero crossing of input voltage, the resonant inductance current ILr will be ignorable. Considering the ZVS condition during an entire line period, the transformer leakage inductance Ll could be determined by using2021211),min()(⎥⎦⎤⎢⎣⎡+≥I n n V n C C L s s bus p P p (11) In practical design, an external inductor Le is usually needed to be added in series connection with Ll to satisfy the ZVS condition [22], [23].IV.SIMULATION AND EXPERIMENTAL VERIFICATIONSTo verify the feasibility of the presented single-stage chargepump LED backlight driving system, a laboratory prototype was implemented and tested with the following specifications:• input voltage: 80–130 Vac (nominal voltage 110 Vac);• switching frequency: 75 kHz;• output voltage: 56 V–65 Vdc adjustable (nominal voltage 60 Vdc);• output current: 1.4 A.Fig10 shows a schematic diagram of the laboratory prototype for the presented single-stage ac/dc converter. In laboratory experiments, a DSP chip TMS320LF2407A is used to implement the digital controller. Digital control brings the advantages of programmability, immunity to noise, and high reliability. However, the proposed scheme can also be implemented by using the cost-effective commercial pulsewidth modulation controllers. With complicated analog controls, the system usually requires more engineering time. The output voltage of the single-stage ac/dc converter is fed back to regulate the duty ratios of the power switches Q1 and Q2. The LUMILEDS emitter type high-power LED was used in this paper. This diode is a 1-W high-luminance LED with a nominal voltage of 3.42 V at a rated current of 350 mA. As shown in Fig. 10, the prototype is designed to supply four paralleled LED arrays with a maximum output current of 1.4 A. Fig. 11 shows the simulation and measured waveforms of the input voltage Vin and current Iin. The input current Iin has a near sinusoidal waveform and in phase with the input voltage Vin. Power factor can be measured by using an electronic load operated in constant current (CC) mode. Power factor variations under different output currents are depicted in Fig. 12. High power factor can be achieved under dimming operation. Fig. 13 shows the simulation and experimental waveforms for the drain–source voltage and gate–source voltage of the power MOSFETs to illustrate the ZVS features. The efficiency characteristics ofthe presented ac/dc converter can also be tested by using an electronic load operated in CC mode. The efficiency variations under different output currents are shown in Fig. 14. High efficiency can be achieved because of single-stage power conversion with soft-switching features.Fig. 10. Schematic diagram of the laboratory prototype.(a)(b)Fig. 11. (a) Simulation and (b) measured waveforms of the input voltage and current.Fig. 12. Power factor variations under different output currents.(a) (b)(c) (d)Fig. 13. (a) Simulation and (b) measured ZVS waveforms for MOSFET Q1. (c) Simulation and (d) measured ZVS waveforms for MOSFET Q2.Fig. 14. Efficiency variations for the presented ac/dc converter.V.CONCLUSIONThe advantages of LED backlighting over conventional CCFLs are numerous: fast response, broader color spectrum, longer life span, and no mercury. However, CCFLs still have cost advantages. For an LED backlighting, luminous efficacy and thermal management are the most important issues that are needed to be solved before commercialization. However, rapid advances in material and manufacturing technologies will enable significant developments in high-luminance LEDs for backlighting applications. In this paper, we presented an LED backlight driving system for the large-scale LCD panels. A single-stage charge-pump AHB converter is studied to achieve high power factor input and high conversion efficiency with a simple circuit configuration. Operation principles and design considerations for the single-stage ac/dc converter areAnalyzed and discussed in detail. Three dimming control methods, namely: 1) TA dimming, 2) CM dimming, and 3) BM dimming are then implemented to regulate the LED current and brightness for the LED backlight system. Current sharing and efficiency characteristics using these three dimming methods are presented and compared. Finally, a laboratory proto type of the presented LED backlight drivingsystem is built and tested. The simulation and experimental waveforms are shown to verify the feasibility of the proposed method. The results are satisfactory.VI.REFERENCES[1] C. H. Lin, ―Digital-dimming controller with current spikes elimination technique for LCD backlight electronic ballast,‖ IEEE Trans. Ind. Electron., vol. 53, no. 6, pp. 1881–1888, Dec. 2006.[2] S. J. Choi, K. C. Lee, and B. H. Cho, ―Design of fluorescen t lamp ballast with PFC using a power piezoelectric transformer,‖ IEEE Trans. Ind. Electron., vol. 52, no. 6, pp. 1573–1581, Dec. 2005.[3] S. K. Kim, H. S. Han, Y. J. Woo, and G. H. Cho,―Detection and regulation of CCFL current and open-lamp voltage while keeping floating condition of the lamp,‖ IEEE Trans. Ind. Electron., vol. 53, no. 2, pp. 707–709,Apr. 2006.[4] C. G. Kim, K. C. Lee, and B. H. Cho, ―Modeling of CCFL using lamp delay and stability analysis of backlight inverter for large size LCD TV,‖ in Proc. IEEE APEC, 2005, vol. 3, pp. 1751–1757.[5] C. C. Chen, C. Y. Wu, and T. F. Wu, ―LED back-light driving system for LCD panels,‖ in Proc. IEEE APEC, 2006, pp. 381–385.[6] C. C. Chen, C. Y. Wu, and T. F. Wu, ―Fast transition current-type burst mode dimming control for the LED back-light driving system of LCD TV,‖ in Proc. IEEE PESC, 2006, pp. 1–7.[7] S. Y. Lee, J. W. Kwon, H. S. Kim, M. S. Choi, and K. S. Byun, ―New design and application of high efficiency LED driving system for RGBLED backlight in LCD display,‖ in Proc. IEEE PESC, 2006, pp. 1–5.[8] M. Rico-Secades, A. J. Calleja, J. Ribas, E. L. Corominas, J. M. Alonso, J. Cardesin, and J. Garcia-Garcia, ―Evaluation of a low-cost permanent emergencylighting system based on high-efficiency LEDs,‖ IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 1386–1390, Sep./Oct. 2005.[9] H. Sugiura, S. Kagawa, H. Kaneko, M. Ozawa, H. Tanizoe, T. Kimura, and H. Ueno, ―Wide color gamut displays using LED backlight—Signal processing circuits, color calibration system and multi-primaries,‖ in Proc. IEEE ICIP, 2005, vol. 2, pp. 9–12.[10] G. Moschopoulos and P. Jain, ―Single-phase single-stage power-factorcorrected converter topologies,‖ IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 23–35, Feb. 2005.[11] C. S. Lin and C. L. Chen, ―A novel single-stage push–pull electronic ballast with high input power factor,‖ IEEE Trans. Ind. Electron., vol. 48, no. 4, pp. 770–776, Aug. 2001.[12] W. Guo and P. K. Jain, ―A power-factor-corrected AC–AC inverter topology using a unified controller for high-frequency power distribution architecture,‖ IEEE Trans. Ind. Electron., vol. 51, no. 4, pp. 874–883,Aug. 2004.LED背光驱动系统的大型液晶面板Huang-Jen Chiu, Member, IEEE, and Shih-Jen Cheng 摘要：本文介绍了一种LED背光驱动系统的大型液晶显示板。

User manual Rev. 1.3 (17/04/2018) CompactPCI Serial power supplyCompactPCI Serial power supply (for illustration only)CompactPCI Serial is a new standard that supports the fast serial protocols PCI Express, Serial ATA, USB and Ethernet. The payload power is +12 V. For wake-up events an additional +5 V Stdby voltage is defined. The Schroff pluggable CompactPCI Serial power supply is developed in accordance to the power definition within the CompactPCI Serial specification PICMG CPCI-S.0.The power supply is a 3 U, 8 HP unit and fits into a 3 U subrack slot by using the off-set card guides. The mains voltage is fed through the connector on the back. Pentair offers the mating power backplanes as well as CompactPCI Serial backplanes with the mating connector installed.Main featuresTotal power Input voltage Output voltage 1 Output voltage 2∙Active power factor correction ∙Wide range input∙Active current share – single wire ∙Remote sensing∙N+1 redundancy∙PS present∙Power fail ∙PS_ON∙Enable∙Temperature monitoring∙I2C interface∙Hot pluggable∙UL, cUL and DEMKO∙CE compliant ENVIRONMENTAL SPECIFICATIONS∙Humidity: Up to 95% non-condensing∙Storage temperature: -40︒ to +85︒C∙Temperature coefficient: ±0.01% / ︒C∙Ambient operating temperature: -40 to +70︒C continuous duty, full rating.∙Cooling: forced air cooling requiredSAFETY APPROVALS∙UL:∙CUL:∙DEMKO: 60950-1:2005 (2nd Edition); Am 1:2009 60950-1:2005 (2nd Edition); Am 1:2009EN 60950-1:2006, EN 60950-1:2006/A11:2009 EN 60950-1:2006/A1:2010EN 60950-1:2006/A12:2011ELECTRICAL SPECIFICATIONSInput specifications Main output specificationsInput range FrequencyEMI filterInrush current Input current Isolation EfficiencyActive PFC Switching frequency Leakage 90-264 V AC50-60 HzEN55022 Class B, FCC Part15<32 A @ 230 V AC1.3 A @ 264 V AC(1,45 A@230)4242 V DC (input to output)>90% @ 230 V AC0.99134 KHz<300 uADC outputLine RegulationLoad RegulationRipple and NoiseTransientResponseMaximum continuousoutput power 300 W withminimum 10 CFM fancooling required.±2 %±2 %1 % Pk to Pk2 % maximum deviation;returns to initial conditionin 1 msec max.Output specifications∙Long term stability 0.01 % after 20 minute warm-up∙Hold-up time 20 msec minimum∙OVP Set at 115 % to 135 %. Latching method. AC must be recycled torestart the unit∙Short-circuit protection The units will withstand a continuous short without damage. It willautomatically return to regulation upon removal of the short ∙Overload protection The overload protection feature will reduce the output voltage to asafe dissipation level when the output power rating exceeds 110 %of maximum rated power. The unit will automatically return toregulation upon removal of the overload∙ORing FET ORing FET provided for redundant operation∙Active current share (S2) 12V output will current share within 5% when interconnected by a single wire∙Passive current share 5 VSBY droop type∙Remote sensing(R2/E3)on 12V output only∙PS_ON (F3) Digital Input: A logic low enables the Main output of the supply. Alow shall not source more than 1 mA of current ∙Enable (R6) Digital Input. When driven high, main output is disabled. WhenLow, power supply main output state is as controlled by PS_ON ∙FAL/PWR_FAIL (U2) Digital output, Open Collector, driven high when outputs are inregulation. It will go low a minimum of 1 mS prior to output goingout of regulation∙DEG (U5) Open Collector, temperature warning signal default setting at 85︒Cwill change signal state from Hi to Low or Low to Hi (signal andtemperature preferences programmable at factory) ∙PS Present (H3) Digital Output. Pulled low via 100 Ohm resistor∙Thermal Protection The power supply has a built in thermal sensor to protect againstabnormal temperature conditions∙I²C/PMBUS Monitors temperature, output voltage, and output current,connects to a serial NVRAM which is programmed with serialnumber. PMBUS Standard to allow monitoring of overall operationof power supply∙LED Indicators The power supply will have two LED’s providing the power supplystatus:Status IndicationAll outputs are operating within spec Steady GreenStandby (PSON disabled) Blinking GreenVoltage or Temperature warning Blinking YellowVoltage or Temperature fault Steady YellowPSKILL and/or power supply off NO LED’s OVERALL MECHANICAL DIMENSIONSNot including face plate and connector6.40”L x 3.94”H x 1.47”W162.5mm x 100mm x 37.34mmIncluding face plate and connector:6.67”L x 5.06”H x 1.59”W169.4mm x 128.5mm x 40.3mmNOTES∙ Specifications subject to change without notice. ∙ All dimensions in inches/mm ∙ Weight: Approx. 1.6lbs (0.68Kg)VOLTAGE/CURRENT RATING CHARTItem number AssignmentVoltages Minimum Maximum 11098-538V25 VSB0 A2.5 ACONNECTORInput/Output……………….FCI Connector 51939-667PinoutP1P2 P3 P4 P5U1U2H3U4U5U6P6 P7 P8 P9L I N EN E U T R A LG N DN UN UNUFAL / PWR_FAILPS PRESENTCOMDEG5V STBYC O MC O M+12V O U T+12V O U TT1 T2G3T4T5T6NU NUCOMA05V STBY5V STBYS1S2F3 S4 S5S6NU12V CSPSON A1SCLCOMR1R2E3R4R5R6NU-VS+VSA2SDAENABLEWarranty conditionsDurationThis product has a warranty of 2 years. The warranty begins on the day of deliveryCover of defectsWithin the warranty period Schroff will repair free of charge any faulty functioning of the product resulting from faulty design or defective material. All other claims under the warranty are excluded, in particular consequential damage.Warranty exclusionThe warranty does not cover damage or functional defects caused by non-adherence to the Company´s operating instructions or such caused by dropping, knocking, contamination or other untoward handling. The warranty is invalidated if the product is opened by unauthorized personnel, tampered with or the serial number on the product has been changed or rendered illegible. Claims under warrantyThis product has been carefully checked. If you have a valid claim, please return the product to SCHROFF. In order to make a claim under the warranty, ensure that the following is carried out:∙Include a detailed description of the fault.∙The product should be returned in the originalcarton or similar packaging, insured and postpaid.。

Back end of lineThe back end of line(BEOL)is the second portion of IC fabrication where the individual devices(transistors,ca-pacitors,resistors,etc.)get interconnected with wiring on the wafer.[1]BEOL generally begins when thefirst layer of metal is deposited on the wafer.BEOL includes contacts,insulating layers(dielectrics),metal levels,and bonding sites for chip-to-package connections.After the last FEOL step,there is a wafer with isolated transistors(without any wires).In BEOL part of fabri-cation stage contacts(pads),interconnect wires,vias and dielectric structures are formed.For modern IC process, more than10metal layers can be added in the BEOL.The process used to form DRAM capacitors creates a rough and hilly surface,which makes it difficult to add metal interconnect layers and still maintain good yield. In1998,state-of-the-art DRAM processes had4metal layers,while state-of-the-art logic processes had7metal layers.[2]As of2002,5or6layers of metal interconnect are common.[3]As of2009,typical DRAM devices(1Gbit)use3lay-ers of metal interconnect,tungsten on thefirst layer and aluminum on the higher layers.[4][5]As of2011,many gate arrays are available with a3-layer interconnect.[6]Many power ICs and analog ICs use a3-layer interconnect.[7]The top-most layers of a chip have the thickest and widest and most widely-separated metal layers,which make the wires on those layers have the least resistance and small-est RC time delay,so they are used for power distri-bution and clock distribution.The bottom-most metal layers of the chip,closest to the transistors,have thin, narrow,tightly-packed wires,used only for local inter-connect.Adding layers can potentially improve perfor-mance,but adding layers also reduces yield and increases manufacturing cost.[8]All the chips decoded by the Visual6502project have only one or two metal layers,including the RCA1802,the 6800,the6502,the8086,the6809,the68000,etc.[9]Chips with a single metal layer typically use the polysili-con layer to“jump across”when one signal needs to cross another signal--such as the RCA CDP1802[10]and the 4004,giving effectively2layers of interconnections.[11]Many microprocessors were designed with two metal in-terconnect layers,both of them aluminum,including the 1987CVAX and the1989Rigel.Many high-performance microprocessors were designed with3metal interconnect layers,all of them aluminum. Those included several processors using the CMOS-3 process,including the1992Alpha21064;and proces-sors using the CMOS-6process,including the1996 StrongARM.The AMD Athlon Thunderbird has6interconnect layers, the AMD Athlon Palomino has7interconnect layers,the AMD Athlon Thoroughbred A has8interconnect layers, and the AMD Athlon Thoroughbred B has9interconnect layers.[12]The Intel Xeon Dunnington has nine copper in-terconnect layers.[13]Steps of the BEOL:1.Silicidation of source and drain regions and thepolysilicon region.2.Adding a dielectric(first,lower layer is Pre-Metaldielectric,PMD-to isolate metal from silicon andpolysilicon),CMP processing it3.Make holes in PMD,make a contacts in them.4.Add metal layer15.Add a second dielectric(this time it is Intra-Metaldielectric)6.Make vias through dielectric to connect lower metalwith higher metal.Viasfilled by Metal CVD pro-cess.Repeat steps4-6to get all metal layers.7.Addfinal passivation layer to protect the microchip Before1998,practically all chips used aluminum for the metal interconnection layers.[14]The four metals with the highest electrical conductivity are silver with the highest conductivity,then copper,then gold,then aluminum.As of2011,many commercial processes support2or3 metal layers;the most layers supported on a commercial process is11layers,and12layers are expected to be sup-ported soon.[15]After BEOL there is a“back-end process”(also called post-fab),which is done not in the cleanroom,often by a different company.It includes wafer test,wafer back-grinding,die separation,die tests,IC packaging andfinal test.123SEE ALSO 1References[1]Karen A.Reinhardt and Werner Kern(2008).Handbookof Silicon Wafer Cleaning Technology(2nd ed.).WilliamAndrew.p.202.ISBN978-0-8155-1554-8.[2]Yong-Bin Kim and Tom W.Chen.“Assessing MergedDRAM/Logic Technology”.1998.[3]M.Rencz.“Introduction to the IC technology”.2002.[4]Bruce Jacob,Spencer Ng,David Wang.“Memory sys-tems:cache,DRAM,disk”.2007.Section8.10.2.“Comparison of DRAM-optimized process versus a logic-optimized process”.Page376.[5]Young Choi.“Battle commences in50nm DRAM arena”.2009.[6]Epson Gate Arrays[7]Petrov group.“Intersil--power management strategy”.2010.[8]Paul DeMone.“The Incredible Shrinking CPU”2004.[9]The Visual6502project F.A.Q.[10]“Inside the RCA CDP1802”.[11]“Oral History of Federico Faggin”.[12]Frank Völkel.“New CPUs,Old Boards:Athlon XP2800+Starting From KT333”.2002.[13][14]“Copper Interconnect Architecture”[15]“IC Knowledge Cost and Price Model Supported ProcessList”2Further reading•Silicon VLSI Technology:Fundamentals,Practice,and Modeling.Prentice Hall2000,ISBN0-13-085037-3Chapter11“Back End Technology”pages681-786•“CMOS:Circuit Design,Layout,and Simulation”Wiley-IEEE,2010.ISBN978-0-470-88132-3.pages177-179(Chapter7.2CMOS Process Inte-gration);pages199-208(7.2.2Backend-of-the-lineIntegration)3See also•Front end of line•Integrated circuit3 4Text and image sources,contributors,and licenses4.1Text•Back end of line Source:/wiki/Back_end_of_line?oldid=589876375Contributors:Kaeslin,DavidCary,Retired username,SmackBot,Shihhsin hu,Nixeagle,A5b,Dicklyon,MarshBot,Bissinger,Edo248,Helpful Pixie Bot,BattyBot and Anonymous: 74.2Images•File:Question_book-new.svg Source:https:///wikipedia/en/9/99/Question_book-new.svg License:Cc-by-sa-3.0 Contributors:Created from scratch in Adobe Illustrator.Based on Image:Question book.png created by User:Equazcion Original artist:Tkgd20074.3Content license•Creative Commons Attribution-Share Alike3.0。

Compact barcode reader.•Simple configuration with WebLink. •5 megapixel sensor available.•Smallest in class.•IP40.•Single snap-in RJ50 connector and cable.•RS-232, Ethernet via USB.MicroHAWK V320-FOptics OptionsDirect Wiring OptionsAppearanceTypeModelDiffuser Kit – Peel and Stick Accessory. Exterior to unit.V330-AF1Polarizer Kit – Peel and Stick Accessory. Exterior to unit.V330-AF2AppearanceTypeLengthModelRJ50 to RS-232 and External PowerStraight2 Meters V320-WRX-2MRJ50 to RS-232 and External Power Right Angle2 Meters V320-WRXLR-2MPower Supply for V320-WRX-2M and V320-WRXLR-2M 2 Meters 97-9000006-01RJ50 to Flying Leads Straight3 Meters V320-W8-3MRJ50 to Flying Leads Right Angle to the Right *3 Meters V320-W8LR-3MV320-FWiring Options using V420-F Accessories*Right angle cables.AppearanceCategoryLengthModelAdapter V/F320-F to all V420-F Cable Accessories RJ50 to DB-151 Meter V320-WR-1MAdapter V/F320-F to all V420-F Cable Accessories Right Angle to the Right *RJ50 to DB-151 MeterV320-WRLR-1MUSB Breakout Cable 1 Meter V420-WUB-1MCable - USB Breakout With External Power Input 1 Meter V420-WUX-1M Power Supply2 Meters97-9000006-01Kit – Cable and Power Supply V420-AC1Cable – RS-232 Breakout (DB-15) and External Power Input 1 Meter V420-WRX-1M Power Supply2 Meters97-9000006-01Kit – Cable and Power Supply V420-AC0Cable – USB, IO, and Power Breakout 1 Meter V420-WU8X-1M Power Supply2 Meters97-000011-02Kit – Cable and Power Supply V420-AC2Cable – RS-232, USB, IO, and Power Breakout 1 Meter V420-WRU8X-1MPower Supply 2 Meters 97-000011-02Right angle to the rightV320-FV320-F Model Number StructureUse this legend when defining product part numbers. Please note that not all combinations of parameters are valid. For instance, fixed focus distance of 50 mm is not available with Narrow Lens. When ordering, use valid model numbers from the tables in the Ordering Information section only.V320-F [XXX][Y][ZZZ]-NN [P]Example Part Number:•V320-F050W03M-NNX: Fixed Focus at 50 mm, Wide Lens, 0.3 MP Monochrome, No Light, High Speed, X-ModeV320-F Valid Product MatrixV320-F Ordering InformationCategories:1.Fixed Focus Camerasa) V320 Monochrome and Color Fixed Focus Camera with Standard Lens b) V320 Monochrome and Color Fixed Focus Camera with Narrow Lens1a) V320 Mono and Color Camera with Standard Lens: Valid Combinations V320-F [XXX][Y][ZZZ]-NN [P]Key Classification Code MeaningXXXFocus Distance (mm)050Fixed Focus at 50 mm 064Fixed Focus at 64 mm 081Fixed Focus at 81 mm 102Fixed Focus at 102 mm 133Fixed Focus at 133 mm 190Fixed Focus at 190 mm 300Fixed Focus at 300 mmYLensW Wide Field of View - 5.2 mm Focal Length Lens M Medium Field of View – 7.7 mm Focal Length Lens NNarrow Field of View – 16 mm Focal Length Lens ZZZSensor03M 752 x 480 (0.3 MP) Pixel, Mono Sensor, Global Shutter 12M 1280 x 960 (1.2 MP) Pixel, Mono Sensor, Global Shutter 50C2592 x 1944 (5 MP) Pixel, Color Sensor, Rolling Shutter L Light Type N No Outer Light C Light Color N No Outer LightPSoftware LicenseP High Speed, Plus Mode XHigh Speed, X-ModeModelCategory Focus Type Sensor Lens Focus Distance (mm)Light License V320-FMonochromeFixed Focus 03M, 12M W, M 50, 64, 81, 102, 133, 190, 300None P, X Color Fixed Focus 50C W, M 50, 64, 81, 102, 133, 190, 300None P, X MonochromeFixed Focus 03M, 12M N 64, 81, 102, 133, 190, 300None P, X ColorFixed Focus50CN64, 81, 102, 133, 190, 300NoneP, XKey Classification Code MeaningXXXFocus Distance (mm)050Fixed Focus at 50 mm 064Fixed Focus at 64 mm 081Fixed Focus at 81 mm 102Fixed Focus at 102 mm 133Fixed Focus at 133 mm 190Fixed Focus at 190 mm 300Fixed Focus at 300 mmY Lens W Wide Field of View - 5.2 mm Focal Length Lens M Medium Field of View – 7.7 mm Focal Length Lens ZZZSensor03M 752 x 480 (0.3 MP) Pixel, Mono Sensor, Global Shutter 12M 1280 x 960 (1.2 MP) Pixel, Mono Sensor, Global Shutter 50C2592 x 1944 (5 MP) Pixel, Color Sensor, Rolling Shutter PSoftware LicenseP High Speed, Plus Mode XHigh Speed, X-ModeV320-F1b) V320 Mono and Color Camera with Narrow Lens: Valid CombinationsNote: 50 mm Fixed Focus option is not available with Narrow Lens.V320-F[XXX]N[ZZZ]-NN[P]Key Classification Code MeaningXXX Focus Distance (mm)064Fixed Focus at 64 mm081Fixed Focus at 81 mm102Fixed Focus at 102 mm133Fixed Focus at 133 mm190Fixed Focus at 190 mm300Fixed Focus at 300 mmZZZ Sensor03M752 x 480 (0.3 MP) Pixel, Mono Sensor, Global Shutter12M1280 x 960 (1.2 MP) Pixel, Mono Sensor, Global Shutter50C2592 x 1944 (5 MP) Pixel, Color Sensor, Rolling Shutter P Software License P High Speed, Plus ModeX High Speed, X-ModeV320-FRead RangesFixed Focus Field of View (mm) - Wide LensFixed Focus Field of View (mm) - Medium LensFixed Focus Field of View (mm) - Narrow Lens0.3 MP1.2 MP5 MPDistance (mm)Width Height Width Height Width Height 50493253395038646239664963478176498161785810295601017596721331217812997124921901711091821361741303002661702832132712024003532253762823592680.3 MP1.2 MP5 MPDistance (mm)Width Height Width Height Width Height 5034223627352664432745344332815334564254401026642705267501338454906786641901197612695121903001851181961471881404002451562601952491860.3 MP1.2 MP5 MPDistance (mm)Width Height Width Height Width Height 501510161216126419122115201581241525192418102301932243022133382440303929190543457435441300835389678563400111711188811384Read range specifications are subject to change.V320-FRatings and Specifications*1.These symbologies are supported based on Omron’s read capability validation standard. Omron recommends that validation be performed for each application.*2.Unless otherwise specified, reading performance is defined with center of field of view, angle R=∞.*3.*4.In an electrically noisy environment, use only the V430-F in combination with a noise filter cable (V430-W □F-□M) to ensure proper operation.V320-FV320-F □□□□03M-□□□V320-F □□□□12M-□□□V320-F □□□□50C-□□□Symbologies *11D SymbologiesCode 39, Code 128, BC412, Interleaved 2 of 5, UPC/EAN, Codabar, Code 93, Pharmacode, PLANET, Postnet, Japanese Post, Australian Post, Royal Mail, Intelligent Mail, KIX 2D Symbologies Data Matrix (ECC 0-200), QR Code, Micro QR Code, Aztec Code, DotCode Stacked SymbologiesPDF417, MicroPDF417, GS1 Databar (Composite and Stacked)Reading Performance *2Number of Reading Digits No Upper Limit (depending on bar width and reading distance)Aiming Light Two Blue LEDsIllumination Inner LEDs: Four White and Four Red (Wavelength: 625 nm)Outer LEDs:NoneOuter LEDs:NoneOuter LEDs:NoneReading Distance /Field of View Refer to Read Ranges section for detail.Pitch Angle (α) *3±30°Skew Angle (β) *3±30°Tilt Angle (γ) *3±180°Image CaptureFocus Fixed Focus (Wide = 5.2 mm, Medium = 7.7 mm, Narrow = 16 mm)Resolution752 (H) x 480 (V)1280 (H) x 960 (V)2592 (H) x 1944 (V)Color / Monochrome Monochrome CMOS Monochrome CMOS Color CMOS ShutterGlobal Shutter Global Shutter Rolling Shutter Frames per Second 60 fps42 fps5 fpsExposure50 to 100,000 μs Image Logging FTPTriggerExternal Trigger (Edge or Level), Communication Trigger (Ethernet, RS-232C)I/O Specifications Input Signals TriggerInput:5-28Vrated(0.16mA@5VDC);Default:3.3Vrated(********)Output Signals One Signal (Strobe): 5 V TTL-compatible, can sink 10 mA and source 10 mA Communication ConnectivityUSB 2.0 Full-Speed (Ethernet over USB and HID), RS-232Ethernet Specifications100BASE-TX / 10BASE-T Indicator LEDs PASS (Green), PWR (Green)Power Supply Voltage 5 VDC +/- 5%Current Consumption450 mA at 5 VDC (max.)Environmental Immunity *4Ambient Temperature RangeOperating: 0 to 40° C Storage: -50 to 75° C (No Icing or Condensation)Ambient Humidity RangeOperating and Storage: 5% to 95% (Non-Condensing)Ambient Atmosphere No Corrosive GasesVibration Resistance (Destructive)Oscillation Frequency: 10 to 150 Hz, Half Amplitude: 0.35 mm, Vibration Direction: X/Y/Z, Sweep Time: 8 minute/count, Sweep Count: 10 timesShock Resistance (Destructive)Impact Force: 150 m/s2, Test Direction: 6 directions, three times each (up/down, front/back, left/right)Degree of ProtectionIEC 60529 IP40Weight Main Body Only 59 gPackaging Weight Approx. 166 g (including packing)Dimensions Main Body Dimensions 52 (W) × 39 (D) × 24 (H) mm Packaging Dimensions 170 (W) × 117 (D) × 86 (H) mm AccessoriesReadMeFirst, CE Compliance Sheet LED Safety StandardIEC 62471-1: 2006 Risk-Exempt Group Safety StandardsEN 55024:2010, EN 55032:2015 + AC:2016FCC Part 15, Subpart B (Class B) UL60950-1BISRCM, KC, EAC and BSMI Pending Materials CaseAluminum Diecast, Alumite (Black)Reading Window Acrylic SoftwareWebLinkV320-F Dimensions (Unit: mm)V320-FDiffuser Kit – Peel and Stick Accessory. Exterior to unit. V330-AF1Polarizer Kit – Peel and Stick Accessory. Exterior to unit. V330-AF2V320-F RJ50 to RS-232 and External Power, Straight – 2 MetersV320-WRX-2MRJ50 to RS-232 and External Power, Right Angle – 2 MetersV320-WRXLR-2MPower Supply for V320-WRX-2M and V320-WRXLR-2M – 2 Meters97-9000006-01V320-FRJ50 to Flying Leads, Straight – 3 MetersV320-W8-3MRJ50 to Flying Leads, Right Angle to the Right– 3 MetersV320-W8LR-3MRight angle to the rightAdapter V/F320-F to all V420-F Cable Accessories, RJ50 to DB-15 – 1 Meter V320-WR-1MV320-F 11Adapter V/F320-F to all V420-F Cable Accessories, Right Angle to the Right, RJ50 to DB-15 – 1 MeterV320-WRLR-1MRight angle to the rightUSB Breakout Cable – 1 MeterV420-WUB-1MKit – USB Breakout Cable with External Power Input (1 Meter) and Power Supply (2 Meters)V420-AC1V320-F 12Kit – RS-232 Breakout Cable (DB-15) with External Power Input (1 Meter) and Power Supply (2 Meters)V420-AC0Kit – USB, IO, and Power Breakout Cable (1 Meters) and Power Supply (2 Meters)V420-AC2V320-F 13Related Manuals Man.No.Model Manual 84-9007234-02V320-F, V330-F, V420-F, V430-F MicroHAWK V320-F / V330-F / V420-F / V430-F User ManualCable – RS-232, USB, IO, and Power Breakout – 1 MeterV420-WRU8X-1MTerms and Conditions AgreementRead and understand this catalog.Please read and understand this catalog before purchasing the products. Please consult your OMRON representative if you have any questions or comments.Warranties.(a) Exclusive Warranty. Omron’s exclusive warranty is that the Products will be free from defects in materials and workmanshipfor a period of twelve months from the date of sale by Omron (or such other period expressed in writingby Omron). Omron disclaims all other warranties, express or implied.(b) Limitations. OMRON MAKES NO WARRANTY OR REPRESENTATION, EXPRESS OR IMPLIED, ABOUTNON-INFRINGEMENT, MERCHANT ABILITY OR FITNESS FOR A P ARTICULAR PURPOSE OF THEPRODUCTS. BUYER ACKNOWLEDGES THAT IT ALONE HAS DETERMINED THAT THE PRODUCTS WILLSUIT ABL Y MEET THE REQUIREMENTS OF THEIR INTENDED USE.Omron further disclaims all warranties and responsibility of any type for claims or expenses based on infringement by the Products or otherwise of any intellectual property right. (c) Buyer Remedy. Omron’s sole obligation hereunder shall be, at Omron’s election, to (i) replace (in the form originally shipped with Buyer responsible for labor charges for removal or replacement thereof) thenon-complying Product, (ii) repair the non-complying Product, or (iii) repay or credit Buyer an amount equal to the purchase price of the non-complying Product; provided that in no event shall Omron be responsible for warranty, repair, indemnity or any other claims or expenses regarding the Products unless Omron’s analysis confirms that the Products were properly handled, stored, installed and maintained and not subject to contamination, abuse, misuse or inappropriate modification. Return of any Products by Buyer must be approved in writing by Omron before shipment. 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Buyer shall take application responsibility in all cases.NEVER USE THE PRODUCT FOR AN APPLICA TION INVOLVING SERIOUS RISK TO LIFE OR PROPERTY OR IN LARGE QUANTITIES WITHOUT ENSURING THAT THE SYSTEM AS A WHOLE HAS BEEN DESIGNED TO ADDRESS THE RISKS, AND THA T THE OMRON PRODUCT(S) IS PROPERL Y RATED AND INSTALLED FOR THE INTENDED USE WITHIN THE OVERALL EQUIPMENT OR SYSTEM.Programmable Products.Omron Companies shall not be responsible for the user’s programming of a programmable Product, or any consequence thereof.Performance Data.Data presented in Omron Company websites, catalogs and other materials is provided as a guide for the user in determining suitability and does not constitute a warranty. It may represent the result of Omron’s test conditions, and the user must correlate it to actual application requirements. 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No. SP113A-EN-09190919 © OMRON Corporation 2019 All Rights Reserved.OMRON Corporation Industrial Automation CompanyOMRON ELECTRONICS LLC 2895 Greenspoint Parkway, Suite 200 Hoffman Estates, IL 60169 U.S.A.Tel: (1) 847-843-7900/Fax: (1) 847-843-7787Regional HeadquartersOMRON EUROPE B.V.Wegalaan 67-69, 2132 JD HoofddorpThe NetherlandsTel: (31)2356-81-300/Fax: (31)2356-81-388Contact: Kyoto, JAPAN OMRON ASIA PACIFIC PTE. LTD.No. 438A Alexandra Road # 05-05/08 (Lobby 2),Alexandra Technopark,Singapore 119967Tel: (65) 6835-3011/Fax: (65) 6835-2711OMRON (CHINA) CO., LTD.Room 2211, Bank of China Tower, 200 Yin Cheng Zhong Road, PuDong New Area, Shanghai, 200120, China Tel: (86) 21-5037-2222/Fax: (86) 21-5037-2200· EtherNet/IP TM is a trademark of ODVA.· QR code is the registered trademark of DENSO WAVE.· Other company names and product names in this document are the trademarks or registered trademarks of their respective companies. · The product photographs and figures that are used in this catalog may vary somewhat from the actual products.Note: Do not use this document to operate the Unit.。

CUSTOMER APPROVAL SHEETCompany NameMODELA070FW03 VDCUSTOMERAPPROVEDTitle : Name :□ APPROVAL FOR SPECIFICATIONS ONLY (Spec. Ver. )□ APPROVAL FOR SPECIFICATIONS AND ES SAMPLE (Spec. Ver. ) □ APPROVAL FOR SPECIFICATIONS AND CS SAMPLE (Spec. Ver. ) □CUSTOMER REMARK :AUO PM : Orion PengP/N : 97.07A04.D00Comment :1 Li-Hsin Rd. 2. Science-Based Industrial ParkHsinchu 300, Taiwan, R.O.C.Tel: +886-3-500-8899 Fax: +886-3-577-2730Doc. version : 0.0 Total pages : 28A UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Product Specification7.0" COLOR TFT-LCD MODULEModel Name ：A070FW03 VDPlanned Lifetime: From 2009/Dec To2011/DecPhase-out Control:From 2011/Jul To 2011/DecEOL Schedule:2011/Jul< >Preliminary Specification < >Final SpecificationNote: The content of this specification is subject to change.© 2009 AU Optronics All Rights Reserved, Do Not Copy.A UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Page:1/28Record of RevisionVersion Revise Date Page Content0.0 2009/03/10All First DraftA UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Page:2/28ContentsA. General Information.....................................................................................................................................3B.Outline Dimension (4)1. TFT-LCD Module – Front View....................................................................................................................42. TFT-LCD Module – Rear View....................................................................................................................5 C.Electrical Specifications .............................................................................................................................6 1. TFT LCD Panel Pin Assignment .................................................................................................................6 2. Backlight Pin Assignment............................................................................................................................7 3. Absolute Maximum Ratings.........................................................................................................................7 3. Electrical DC Characteristics.......................................................................................................................8 4. Electrical AC Characteristics.....................................................................................................................10 6. Power On/Off Characteristics....................................................................................................................17 D. Optical Specification .................................................................................................................................18 E. Reliability Test Items .................................................................................................................................21 F.Packing and Marking.................................................................................................................................24 1. Packing Form............................................................................................................................................24 2. Module/Panel Label Information ...............................................................................................................25 3. Carton Label Information...........................................................................................................................25 G.Precautions (26)A UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Page:3/28A. General InformationThis product is for portable DVD and digital photo frame application. NO. ItemUnit Specification Remark1 Screen Sizeinch 7.0(Diagonal)2 Display Resolution dot480RGB(W)×234(H)3 Overall Dimensionmm 164.9 (W)×100(H)×5.7(D) Note 1 4 Active Area mm154.08(W)×86.58(H) 5 Pixel Pitchmm 0.107(W)×0.370(H)6 Color Configuration --R. G. B. Stripe Note 2 7 NTSC Ratio% 48%8 Display Mode -- Normally White 9Panel surface Treatment -- Anti-Glare, 3H10 Weight g TBD 11 LCD Module Power ConsumptionW 2.212 Viewing direction6 o’clock (gray inversion)Note 1: Not include blacklight cable and FPC. Refer next page to get further information. Note 2: Below figure shows dot stripe arrangement.( 1………………………..234)A UOCo n fi de n ti a lF or Pr om aPage:4/28ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMSWITHOUT PERMISSION FROM AU OPTRONICS CORP.B. Outline Dimension (D00)1. TFT-LCD Module – Front ViewA UOPage:5/28ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMSWITHOUT PERMISSION FROM AU OPTRONICS CORP.2. TFT-LCD Module – Rear ViewA UPage:6/28C. Electrical Specifications1. TFT LCD Panel Pin AssignmentPin no Symbol I/O DescriptionRemark1 GND - Ground for logic circuit2 V CC I Supply voltage of logic control circuit for scan driver3 V GL I Negative power for scan driver4 V GH IPositive power for scan driver5 STVR I/O Vertical start pulse Note 16 STVL I/O Vertical start pulse Note 17 CKV I Shift clock input for scan driver 8 U/D I UP/DOWN scan control input Note 1,29 OEV I Output enable input for scan driver 10 VCOM I Common electrode driving signal 11 VCOM I Common electrode driving signal12 L/R I LEFT/RIGHT scan control input Note 1,213 MOD I Sequential sampling and simultaneous sampling setting14 OEH IOutput enable input for data driver15 STHL I/O Start pulse for horizontal scan lineNote 1 16 STHR I/O Start pulse for horizontal scan lineNote 1 17 CPH3 I Sampling and shifting clock pulse for data driver18 CPH2 I Sampling and shifting clock pulse for data driver19 CPH1 I Sampling and shifting clock pulse for data driver20 V CC I Supply voltage of logic control circuit for data driver21 GND - Ground for logic circuit22 VRIAlternated video signal input(Red) 23 VGI Alternated video signal input(Green) 24VBI Alternated video signal input(Blue)25 AV DD I Supply voltage for analog circuit 26AV SS-Ground for analog circuitA UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Page:7/28I: Input pin; P: Power pin; G: Ground pin; C: capacitor pinRefer to figure as below:Pin26 Pin12. Backlight Pin AssignmentRecommended connector : E&T H201K-P020N-02BPin no Symbol I/O Description Remark1 VLEDPLED power supply2GNDLEDP LED ground3. Absolute Maximum RatingsItemSymbol Condition Min. Max. Unit RemarkV CCGND=0-0.3 7 V AV DD AGND=0-0.3 7VV GH -0.3 18 V V GL GND=0-15 0.3 V Power voltageV GH －V GL-33VV i-0.3 AV DD +0.3 VNote 3 V I-0.3 V CC +0.3 V Note 4 Input signal voltageVCOM-2.9 7.5 VNote 1: Functional operation should be restricted under ambient temperature (25℃).Note 2: Maximum ratings are those values beyond which damages to the device may occur. Functionaloperation should be restricted to the limits in the Electrical Characteristics chapter.Note 3: VR, VG, VB.Note 4: STHL, STHR, OEH, LRC, CPH1~CPH3, STVD, STVU, OEV, CKV, UDC, MODA UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Page:8/283. Electrical DC Characteristicsa. Typical Operation Condition (AGND =GND = 0V)ItemSymbol Min. Typ. Max. Unit Remark V CC3 3.3 5.5 VDigital powerAV DD4.5 55.5 V Analog PowerV GH 14.3 15 15.7 V Positive power supply for gate driver Power VoltageVGL-10.5 -10 -9.5 V Negative power supply for gate driverV iA 0.4 - AV DD -0.4V Refer to Horizontal timing V iAC - 4- V AC component Video signal amplitude(VR,VG,VB) V iDC -AV DD /2 -VDC componentH LevelVIH 0.8xVCC - VCC VInputSignal Voltage L Level VIL GND - 0.2xVC VNote 1. V CAC 3.5 5.6 6.5 VAC component Gamma referencevoltageV CDC1.41.72.0VDC component Note 1: STHL, STHR, OEH, LRC, CPH1~CPH3, STVD, STVU, OEV, CKV, UDC, MOD.Note2: Must follow power On/Off Sequence.Note 3: If input signal amplitude is 3.3V, recommend value for Vcc is 3.3VIf input signal amplitude is 5V, recommend value for Vcc is 5Vb. Current Consumption (AGND=GND=0V)ParameterSymbol ConditionMin. Typ. Max. Unit RemarkInput current for V GH I GH V GH =15V- 0.12 1.0 m A Input current for V Gl I GL V Gl =-10V- 0.15 1.0 mA Input current for Vcc I CC DV CC =3.3- 2 6.0 mA Input current for Avdd I DDAV DD =5V-5.330mAA UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Page:9/28c. Backlight Driving ConditionsThe backlight (LED module, Note 1) is suggested to drive by constant current with typical value.ParameterSymbol Min. Typ. Max. Unit Remark LED light bar CurrentI L-- 200 -- mABL Power ConsumptionP BL --2.1 --WNote 1 LED Life TimeL L 10,000 ---- Hr Note 2, 3Note 1: The LED driving condition is defined for LED module (24 LED). The voltage range will be 8.7 to 11.6V based on suggested driving current set as 200mA .Note 2: Define “LED Lifetime”: brightness is decreased to 50% of the initial value. LED Lifetime isrestricted under normal condition, ambient temperature = 25℃ and LED lightbar current =200mA .Note 3: If it uses larger LED lightbar voltage more than 200mA , it maybe decreases the LED lifetime.A UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2Page:10/284. Electrical AC Characteristicsa. Signal AC CharacteristicsParameterSymbol Min. Typ. Max. Unit. Remark Clock cycle time t CPH100 103 107 ns CPH1 CPH pulse duty t CWH 405060%CPH1CPH pulse delay t C12 30 t CPH /3 t CPH /2 ns CPH1STH setup time t SUH 20 - - ns STHR,STHL STH hold time t HDH 20- - ns STHR,STHL STH pulse width t STH 1 t CPH STHR,STHL STH period t H 61.8 63.7 66.1 μs STHR,STHL OEH pulse width t OEH 1 - - t CPH OEH (Note 1)Sample and hold disable timet DIS1 1 - - t CPH Note 2 OEV pulse width t OEV 2.0 3.4 6.5 μs OEV CKV pulse width t CKV 1.0 3.1 4.68 μs CKV Clean enable timet DIS2 1.0- 1 t OEVμs Note 3 Horizontal display start t SH 1t CPH Horizontal display timing ranget DH 480t CPH STV setup time t SUV 400 -- ns STVU, STVD STV hold time t HDV 400 -- ns STVU, STVD STV pulse width t STV - -1t H STVU, STVDVertical display start t SV 3t H Vertical display timing ranget DV 234 t HVCOM rising time t rCOM - 5 μs VCOM falling time t fCOM- 5 μs VCOM delay time t DCOM 2 - - μs TFT charging time t ch 55 - - μs Output time delay t del 3 - - μs Setup time of analog VR/VG/VBt asu 60 - - ns Hold time of analog VR/VG/VBt ahd 40 - - ns Frame rate5060-HzNote 1: The maximum pulse width of OEH should refer to the minimum of tDIS1 and the hsyncback porch.Note 2: t DIS1 is time difference between OEH and STHL.Note 3: t DIS2 is time difference between OEV and CKVA UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Sampling clock timingVersion:0.0Page: 15/28ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.Vertical timing (From up to down)a lUs e On ly / 2010/1/5Version:0.0Page: 16/28ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.Page: 17/28 6. Power On/Off CharacteristicsPower OnPage:18/28D. Optical SpecificationAll optical specification is measured under typical condition (Note 1, 2)Item Symbol Condition Min. Typ. Max. Unit Remark Response TimeRise FallTr Tfθ=0°-- --12 1824 36ms ms Note 3 Contrast ratioCRAt optimizedviewing angle 300 400 -- Note 4TopBottom LeftViewing AngleRight 30 50 50 5040 65 65 65 -- -- -- -- deg. Note 5Brightness Y Lθ=0° 320 400 -- cd/m 2 Note 6 X θ=0° 0.25 0.30 0.35 ChromaticityWhiteY θ=0° 0.27 0.32 0.37 UniformityΔY L%7075 -- %Note 7Note 1: Ambient temperature =25℃, and LED lightbar current I L = 200 mA . To be measured in the dark room.Note 2: To be measured on the center area of panel with a viewing cone of 1° by Topcon luminance meterBM-5A, after 15 minutes operation.Note 3: Definition of response time:The output signals of photo detector are measured when the input signals are changed from“black” to “white”(falling time) and from “white” to “black”(rising time), respectively.The response time is defined as the time interval between the 10% and 90% of amplitudes.Refer to figure as below.A UOCo n fi de n ti a lF or Pr om 1/5Note 4.Definition of contrast ratio:Contrast ratio is calculated with the following formula.statusBlack"" at is LCD when output detector Photo statusWhite"" at is LCD when output detector Photo (CR) ratio Contrast =Note 5. Definition of viewing angle, θ, Refer to figure as below.Note 6. Measured at the center area of the panel when all the input terminals of LCD panel areelectrically opened.Note 7: Luminance Uniformity of these 9 points is defined as below:A UOCo n fi de n ti a lF or Pr om a t eI nt er nA UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Page:21/28E. Reliability Test ItemsNo. Test itemsConditions Remark1 High Temperature Storage240Hrs2 Low Temperature Storage Ta= -2240Hrs3 High Ttemperature Operation Tp240Hrs4 Low Temperature Operation Ta= -1 240Hrs5 High Temperature & High HumidityTp= 580% RH 240Hrs Operation6 Heat Shock -20d/1hr~70d/1hr judge 50cyclesNon-operation7 Electrostatic DischargeContact = ± 4 kV, class B Air = ± 8 kV, class BNote 4 8Image Sticking25, 4hrsNote 5Frequency range : 10~55HzStoke: 1.5mmSweep: 10 Hz ~55 Hz 2 hours for each direction of X,Y,Z9Vibration4 hours for Y directionNon-operationJIS C7021, A-10condition A : 15 minutes10 Mechanical Shock100G . 6ms, ±X,±Y,±Z3 times for each directionNon-operation JIS C7021,A-7condition C 11 Vibration (With Carton)Random vibration:0.015G 2/Hz from 5~200Hz–6dB/Octave from 200~500Hz IEC 68-3412 Drop (With Carton)Height: 60cm1 corner, 3 edges, 6 surfaces13 Pressure5kg, 5sec Note 6Note 1: Ta: Ambient Temperature. Tp: Panel Surface TemperatureNote 2: In the standard conditions, there is not display function NG issue occurred. All the cosmeticspecification is judged before the reliability stress.Note 3: All the cosmetic specification is judged before the reliability stress.Note 4 : All test techniques follow IEC6100-4-2 standard.A UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Page:22/28Contact Discharge ：330Ω, 150pF, 1sec, 8 point, 25times/pointgray pattern. After 20 minutes, the mura is less than JND 2.5Note 6: The panel is tested as figure. The jig is ψ10 mm made by Cu with rubber and the loadingspeed is 3mm/min on position 1~5. After the condition, no glass crack will be found and panelfunction check is OK.( no guarantee LC mura 、LC bubble)A UOCo n fi de n ti a lF or Pr om a t eI nt eUs eOn l y / 201Page:23/28A UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5Page:24/28F. Packing and Marking1. Packing FormA UOCo n fi de n ti a lF or Pn l y2. Module/Panel Label InformationThe module/panel (collectively called as the “Product”) will be attached with a label of Shipping Numberwhich represents the identification of the Product at a specific location. Refer to the Product outline drawing for detailed location and size of the label. The label is composed of a 22-digit serial number and printed with code128 with the following definition:Example:501M06ZL06123456781Z05: Product Manufacturing Week Code: WK50 Product Version: Version 1 Product Manufactuing Factory: M063. Carton Label InformationThe packing carton will be attached with a carton label where packing Q’ty, AUO Model Name, AUO PartNumber, Customer Part Number (Optional) and a series of Carton Number in 13 or 14 digits are printed. TheCarton Number is apparing in the following format:Refer to the drawing of packing format for the location and size of the carton label.A UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5G. Precautions1. Do not twist or bend the module and prevent the unsuitable external force for display module during assembly.2. Adopt measures for good heat radiation. Be sure to use the module with in the specified temperature.3. Avoid dust or oil mist during assembly.4. Follow the correct power sequence while operating. Do not apply the invalid signal, otherwise, it will cause improper shut down and damage the module.5. Less EMI: it will be more safety and less noise.6. Please operate module in suitable temperature. The response time & brightness will drift by different temperature.7. Avoid to display the fixed pattern (exclude the white pattern) in a long period, otherwise, it will cause image sticking.8. Be sure to turn off the power when connecting or disconnecting the circuit. 9. Polarizer scratches easily, please handle it carefully. 10. Display surface never likes dirt or stains.11. A dewdrop may lead to destruction. Please wipe off any moisture before using module.12. Sudden temperature changes cause condensation, and it will cause polarizer damaged.13. High temperature and humidity may degrade performance. Please do not expose the module to the direct sunlight and so on.14. Acetic acid or chlorine compounds are not friends with TFT display module.15. Static electricity will damage the module, please do not touch the module without any groundeddevice.16. Do not disassemble and reassemble the module by self.17. Be careful do not touch the rear side directly.18. No strong vibration or shock. It will cause module broken.19. Storage the modules in suitable environment with regular packing.20. Be careful of injury from a broken display module.21. Please avoid the pressure adding to the surface (front or rear side) of modules, because it will causethe display non-uniformity or other function issue.A UOCo n fi de n ti a lF or Pr om a t eI nt er na l Us eOn l y / 2010/1/5。

Doc. Number: 400048330Tentative SpecificationPreliminary SpecificationApproval Specification MODEL NO.: N173HGESUFFIX: L11Approved By Checked By Prepared By2010-12-20 13:36:34 CSTh2010-12-2009:43:49 CSTa2010-12-1510:40:49 CSTCONTENTS1. GENERAL DESCRIPTION (4)1.1 OVERVIEW (4)1.2 GENERAL SPECIFICATI0NS (4)2. MECHANICAL SPECIFICATIONS (4)2.1 CONNECTOR TYPE (4)3. ABSOLUTE MAXIMUM RATINGS (5)3.1 ABSOLUTE RATINGS OF ENVIRONMENT (5)3.2 ELECTRICAL ABSOLUTE RATINGS (5)3.2.1 TFT LCD MODULE (5)4. ELECTRICAL SPECIFICATIONS (6)4.1 FUNCTION BLOCK DIAGRAM (6)4.2. INTERFACE CONNECTIONS (7)4.3 ELECTRICAL CHARACTERISTICS (9)4.3.1 LCD ELETRONICS SPECIFICATION (9)4.3.2 LED CONVERTER SPECIFICATION (11)4.3.3 BACKLIGHT UNIT (13)4.4 LVDS INPUT SIGNAL TIMING SPECIFICATIONS (14)4.4.1 LVDS DC SPECIFICATIONS (14)4.4.2 LVDS DATA FORMAT (14)4.4.3 COLOR DATA INPUT ASSIGNMENT (15)4.5 DISPLAY TIMING SPECIFICATIONS (16)4.6 POWER ON/OFF SEQUENCE (17)5. OPTICAL CHARACTERISTICS (18)5.1 TEST CONDITIONS (18)5.2 OPTICAL SPECIFICATIONS (18)6. RELIABILITY TEST ITEM (21)7. PACKING (22)7.1 MODULE LABEL (22)7.2 CARTON................................................................................................! C7.3 PALLET (24)8. PRECAUTIONS (25)8.1 HANDLING PRECAUTIONS (25)8.2 STORAGE PRECAUTIONS (25)8.3 OPERATION PRECAUTIONS (25)Appendix. EDID DATA STRUCTURE (26)Appendix. OUTLINE DRAWING (28)REVISION HISTORYDescriptionVersion Date Page0.0 June.20, 2010 All Spec Ver.0.0 was first issued.1.0 Oct.20.2010 All Spec Ver.1.0 was first issued.Ver.2.0 was first issued.2.0 Dec.3.2010 AllSpec1. GENERAL DESCRIPTION 1.1 OVERVIEWN173HGE-L11 is a 17.3” TFT Liquid Crystal Display module with LED Backlight unit and 40 pins LVDS interface. This module supports 1920 x 1080 FHD model and can display 262,144 colors. The optimum viewing angle is at 6 o’clock direction.1.2 GENERAL SPECIFICATI0NSItem Specification Unit Note Screen Size 17.3” diagonal Driver Element a-si TFT active matrix - - Pixel Number 1920 x R.G.B. x 1080 pixel - Pixel Pitch 0.1989 (H) x 0.1989 (V) mm - Pixel Arrangement RGB vertical stripe - - Display Colors 262,144 color - Transmissive Mode Normally white - - Surface Treatment Hard coating (3H), Anti-Glare - - Luminance, White 300 Cd/m2 Power Consumption Total (11.1W) (Max.) @ cell (3)W (Max.), BL (8.1)W (Max.) (1) Note (1) The specified power consumption (with converter efficiency) is under the conditions at VCCS = 3.3 V, fv = 60 Hz, LED_VCCS = Typ, fPWM = 200 Hz, Duty=100% and Ta = 25 ± 2 ºC, whereas mosaic pattern is displayed.2. MECHANICAL SPECIFICATIONSItem Min. Typ. Max. Unit NoteHorizontal (H) 397.6 398.1 398.6 mmVertical (V) 232.3 232.8 233.3 mmModule Size Thickness (T) - 5.7 6.0 mm (1) Horizontal 385.88 386.18 386.48 mmBezel AreaVertical 218.55 218.85 219.15 mm Horizontal - 381.888 - mmActive AreaVertical - 214.812 - mm Weight - 585 600 g Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.2.1 CONNECTOR TYPEPlease refer Appendix Outline Drawing for detail design.Connector Part No.: Starconn 111A40-0000RA-G3, Tyco# 5-2069716-3, or equivalent User’s connector Part No: Starconn 111B40-0000RA-G3, Tyco#5-2069715-3, or equivalentPin1Pin403. ABSOLUTE MAXIMUM RATINGS3.1 ABSOLUTE RATINGS OF ENVIRONMENTValueItem SymbolMin. Max.Unit NoteStorage TemperatureT ST -20 +60 ºC (1) Operating Ambient Temperature T OP 0+50 ºC (1), (2)Note (1) (a) 90 %RH Max. (Ta <= 40 ºC).(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).(c) No condensation.Note (2) The temperature of panel surface should be 0 ºC min. and 60 ºC max.3.2 ELECTRICAL ABSOLUTE RATINGS3.2.1 TFT LCD MODULEValueItem Symbol Min. Max.Unit NotePower Supply Voltage VCCS -0.3 +4.0 VLogic Input Voltage V IN -0.3 VCCS+0.3 V (1)Converter Input VoltageLED_VCCS -0.3 25 V (1) Converter Control Signal Voltage LED_PWM, -0.3 6 V (1) Converter Control Signal VoltageLED_EN-0.3 6 V (1)Note (1) Stresses beyond those listed in above “ELECTRICAL ABSOLUTE RATINGS” may causepermanent damage to the device. Normal operation should be restricted to the conditions described in “ELECTRICAL CHARACTERISTICS”.4. ELECTRICAL SPECIFICATIONS 4.1 FUNCTION BLOCK DIAGRAM4.2. INTERFACE CONNECTIONSPIN ASSIGNMENTPin Symbol Description Remark1 NC No Connection (Reserve)2 VCCS Power Supply (3.3V typ.)3 VCCS Power Supply (3.3V typ.)4 VEDID DDC 3.3V powerSelfTestPanel5 BISTDDCclock6 CLKEDIDdata7 DATAEDIDDDC8 RXO0- LVDS Differential Data Input (Odd)R0-R5, G09 RXO0+ LVDS Differential Data Input (Odd)Ground10 VSS11 RXO1- LVDS Differential Data Input (Odd)G1~G5, B0, B112 RXO1+ LVDS Differential Data Input (Odd)Ground13 VSS14 RXO2- LVDS Differential Data Input (Odd)B2-B5,HS,VS, DE15 RXO2+ LVDS Differential Data Input (Odd)Ground16 VSS17 RXOC- LVDS Clock Data Input (Odd)LVDS CLK18 RXOC+ LVDS Clock Data Input (Odd)Ground19 VSS20 RXE0- LVDS Differential Data Input (Even)R0-R5, G021 RXE0+ LVDS Differential Data Input (Even)Ground22 VSS23 RXE1- LVDS Differential Data Input (Even)G1~G5, B0, B124 RXE1+ LVDS Differential Data Input (Even)Ground25 VSS26 RXE2- LVDS Differential Data Input (Even)B2-B5,HS,VS, DE27 RXE2+ LVDS Differential Data Input (Even)28 VSSGround29 RXEC- LVDS Clock Data Input (Even)LVDS CLK30 RXEC+ LVDS Clock Data Input (Even)LEDGround31 LED_GNDGroundLED32 LED_GNDGroundLED33 LED_GND34 NC No Connection (Reserve)35 LED_PWM PWM Control Signal of LED Converter36 LED_EN Enable Control Signal of LED Converter37 NC No Connection (Reserve)38 LED_VCCS LED Power Supply39 LED_VCCS LED Power Supply40 LED_VCCS LED Power SupplyNote (1) The first pixel is odd as shown in the following figure.4.3 ELECTRICAL CHARACTERISTICS4.3.1 LCD ELETRONICS SPECIFICATIONValueParameter Symbol Min. Typ. Max.Unit NotePower Supply Voltage VCCS3.03.33.6V(1)-Ripple Voltage V RP - 50 - mV(1)- Inrush Current I RUSH - - 1.5 A (1),(2)Mosaic - 440 - mA (3)a Power Supply CurrentBlack lcc- 540 640 mA(3)bNote (1) The ambient temperature is Ta = 25 ± 2 ºC. Note (2) I RUSH : the maximum current when VCCS is risingI IS : the maximum current of the first 100ms after power-onMeasurement Conditions: Shown as the following figure. Test pattern: black..SWVCCS+3.3VVCCS rising time is 0.5msNote (3) The specified power supply current is under the conditions at VCCS = 3.3 V, Ta = 25 ± 2 ºC, DCCurrent and f v = 60 Hz, whereas a power dissipation check pattern below is displayed.Active Areab. Black PatternActive Areaa. Mosaic Pattern4.3.2 LED CONVERTER SPECIFICATIONValueParameter Symbol Min. Typ. Max.Unit NoteConverter Input power supply voltage LED_Vccs 7.5 12.0 21.0 VConverter Inrush Current ILED RUSH- - 1.5 A (1) Backlight On3.0 - 3.6 VEN Control LevelBacklight Off0 - 0.5V PWM High Level3.0-3.6VPWM Control LevelPWM Low Level0 - 0.5 V 10 - 100 %PWM Control Duty Ratio5 - 100 % (2)PWM Control Permissive RippleVoltageV PWM_pp- - 100 mVPWM Control Frequencyf PWM 190 - 2K Hz (3) LED Power Current LED_VCCS =Typ.ILEDTBD625675mA(4)Note (1) I LED RUSH : the maximum current when LED_VCCS is rising, ILED IS : the maximum current of the first 100ms after power-on,Measurement Conditions: Shown as the following figure. LED_VCCS = Typ, Ta = 25 ± 2 ºC, f PWM = 200 Hz, Duty=100%.LED_VCCS(Typ)ILEDLED_VCCLED_PWM LED_ENNote (2) If the PWM control duty ratio is less than 10%, there is some possibility that acoustic noise orbacklight flash can be found. And it is also difficult to control the brightness linearity.Note (3)If PWM control frequency is applied in the range less than 1KHz, the “waterfall” phenomenon onthe screen may be found. To avoid the issue, it’s a suggestion that PWM control frequency should follow the criterion as below.PWM control frequency f PWM should be in the range≤∗+f N )33.0( f PWM f N ∗+≤)66.0(N : Integer )3(≥Nf : Frame rateNote (4) The specified LED power supply current is under the conditions at “LED_VCCS = Typ.”, Ta = 25± 2 ºC, f PWM = 200 Hz, Duty=100%.VLED rising time is 0.5ms4.3.3 BACKLIGHT UNITTa = 25 ± 2 ºCValueParameterSymbolMin. Typ. Max.Unit NoteLED Light Bar Power Supply VoltageV L 30.8 35.2 37.4 V LED Light Bar Power Supply CurrentI L 174.8 184 193.2 mA(1)(2)(Duty100%)Power Consumption P L 5.38 6.47 7.22 W (3) LED Life TimeL BL 15000 - - Hrs (4)Note (1) LED current is measured by utilizing a high frequency current meter as shown below :Note (2) For better LED light bar driving quality, it is recommended to utilize the adaptive boost converter with current balancing function to drive LED light-bar.Note (3) P L = I L ×V L (Without LED converter transfer efficiency)Note (4) The lifetime of LED is defined as the time when it continues to operate under the conditions at Ta = 25 ±2 o C and I L = 23 mA(Per EA) until the brightness becomes 50% of its original value.V I ChannelsRxin0Rxin1 Rxin2 CLK+4.4 LVDS INPUT SIGNAL TIMING SPECIFICATIONS 4.4.1 LVDS DC SPECIFICATIONSValueParameter Symbol Min. Typ. Max.Unit NoteLVDS Differential Input High Threshold V TH(LVDS)- -+100 mV(1),V CM=1.2VLVDS Differential Input Low Threshold V TL(LVDS) -100 - - mV(1)V CM =1.2V LVDS Common Mode Voltage V CM 1.125 - 1.375 V (1) LVDS Differential Input Voltage |V ID | 100 - 600 mV (1) LVDS Terminating ResistorR T - 100 - Ohm -Note (1) The parameters of LVDS signals are defined as the following figures.4.4.2 LVDS DATA FORMAT0V V CM|Single Ended0V|V TH(LVDS)V TL(LVDS)Differential4.4.3 COLOR DATA INPUT ASSIGNMENTThe brightness of each primary color (red, green and blue) is based on the 6-bit gray scale data inputfor the color. The higher the binary input the brighter the color. The table below provides the assignmentof color versus data input.Data SignalRed Green Blue ColorR5 R4 R3 R2R1R0G5G4G3G2G1G0B5 B4 B3 B2B1B0Basic Colors BlackRedGreenBlueCyanMagentaYellowWhite111111111111111111111111111111111111111111111111111111111111111111111111Gray Scale Of Red Red(0)/DarkRed(1)Red(2)::Red(61)Red(62)Red(63)::111::111::111::1111::111::11::::::::::::::::::::::::Gray Scale Of Green Green(0)/DarkGreen(1)Green(2)::Green(61)Green(62)Green(63)::::::::::::::111::111::111::1111::111::11::::::::::::Gray Scale Of Blue Blue(0)/DarkBlue(1)Blue(2)::Blue(61)Blue(62)Blue(63)::::::::::::::::::::::::::111::111::111::1111::111::11Note (1) 0: Low Level Voltage, 1: High Level Voltage4.5 DISPLAY TIMING SPECIFICATIONSThe input signal timing specifications are shown as the following table and timing diagram . Signal Item SymbolMin. Typ. Max. Unit NoteDCLK Frequency 1/Tc 65.9 69.3372.8 MHz - Vertical Total Time TV 10901111 1388 TH-Vertical Active Display PeriodTVD 108010801080 TH - Vertical Active Blanking PeriodTVB TV-TVD 31 TV-TVD TH - Horizontal Total Time TH 200020802600 Tc - Horizontal Active Display Period THD 192019201920Tc-DEHorizontal Active Blanking PeriodTHBTH-THD160TH-THDTc -Note (1) Because this module is operated by DE only mode, Hsync and Vsync are ignored.INPUT SIGNAL TIMING DIAGRAMDCLKDEDEDATA4.6 POWER ON/OFF SEQUENCEThe power sequence specifications are shown as the following table and diagram . ValueSymbolMin. Typ. Max.Unit Notet1 0.5 - 10 ms t2 0 - 50 ms t3 0 - 50 ms t4 500 - - ms t5 200 - - ms t6 200 - - ms t7 0.5 - 10 mst A 0.5 - 10 ms t B 0 10 ms t C 10 - - ms t D 10 - - ms t E 10 - - ms t F 10 - - msNote (1) Please don’t plug or unplug the interface cable when system is turned on. Note (2) Please avoid floating state of the interface signal during signal invalid period.Note (3) It is recommended that the backlight power must be turned on after the power supply for LCD and theinterface signal is valid.- Power Supplyfor LCD, VCCS- Interface Signal (LVDS Signal of Transmitter), V IPower On Power Off- Power Supply forLED Converter, LED_VCCS - LED ConverterDimming Signal, LED_PWM- LED Converter Enable Signal, LED_EN5. OPTICAL CHARACTERISTICS 5.1 TEST CONDITIONSItem Symbol Value UnitAmbient Temperature Ta 25±2 oC Ambient Humidity Ha 50±10 %RH Supply Voltage V CC 3.3 V Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS" LED Light Bar Input Current I L 184 mA The measurement methods of optical characteristics are shown in Section 5.2. The following items should be measured under the test conditions described in Section 5.1 and stable environment shown in Note (5).5.2 OPTICAL SPECIFICATIONSItem Symbol Condition Min. Typ. Max. Unit NoteContrast Ratio CR 500 650 - -(2),(5) ,(7)T R - 2 8 msResponse Time T F - 6 12 ms(3) ,(7)Average Luminance of White L AVE 255 300 - cd/m 2(4),(6) ,(7)Rx 0.640 - RedRy 0.333 - Gx 0.313 -GreenGy 0.613 - Bx 0.154 -BlueBy 0.060 -Wx 0.313 -Color Chromaticity WhiteWyθx =0°, θY =0° Viewing Normal AngleTyp – 0.030.329 Typ +0.03 - (1) ,(7)θx +60 70 Horizontalθx - 60 70 - θY +50 60 - Viewing Angle VerticalθY -CR ≥1050 60 - Deg.(1),(5) ,(7) White Variation of 5 Points δW 5pθx =0°, θY =0° 80 - - % (5),(6) ,(7)Note (1) Definition of Viewing Angle (θx, θy):Note (2) Definition of Contrast Ratio (CR):The contrast ratio can be calculated by the following expression. Contrast Ratio (CR) = L63 / L0 L63: Luminance of gray level 63 L 0: Luminance of gray level 0 CR = CR (1)CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (6).Note (3) Definition of Response Time (T R , T F ):Note (4) Definition of Average Luminance of White (L AVE ):Measure the luminance of gray level 63 at 5 pointsL AVE = [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5L (x) is corresponding to the luminance of the point X at Figure in Note (6)100% 90%10% 0%OpticalNote (5)Measurement Setup:The LCD module should be stabilized at given temperature for 20 minutes to avoid abrupt temperature change during measuring. In order to stabilize the luminance, the measurement should be executed after lighting Backlight for 20 minutes in a windless room.Note (6) Definition of White Variation (δW):Measure the luminance of gray level 63 at 5 points δW 5p = {Minimum [L (1) ~ L (5)] / Maximum [L (1) ~ L (5)]}*100%areaNote (7) The listed optical specifications refer to the initial value of manufacture, but the condition ofthe specifications after long-term operation will not be warranted.: Test Point X=1 to 136. RELIABILITY TEST ITEMTest Item Test Condition Note High Temperature Storage Test 60ºC, 240 hoursLow Temperature Storage Test -20ºC, 240 hoursThermal Shock Storage Test -20ºC, 0.5hour¡60¢J, 0.5hour; 100cycles, 1hour/cycleHigh Temperature Operation Test 50ºC, 240 hoursLow Temperature Operation Test 0ºC, 240 hoursHigh Temperature & High Humidity Operation Test 50ºC, RH 80%, 240hours(1) (2)ESD Test (Operation) 150pF, 330£[, 1sec/cycleCondition 1 : Contact Discharge, 8KVCondition 2 : Air Discharge, 15KV(1)Shock (Non-Operating) 220G, 2ms, half sine wave,1 time for each direction of±X,±Y,±Z(1)(3)Vibration (Non-Operating) 1.5G / 10-500 Hz, Sine wave, 30 min/cycle, 1cycle for eachX, Y, Z(1)(3)Note (1) criteria : Normal display image with no obvious non-uniformity and no line defect.Note (2) Evaluation should be tested after storage at room temperature for more than two hourNote (3) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that the module would not be twisted or bent by the fixture.7. PACKING7.1 MODULE LABELThe barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.(a) Model Name: N173HGE-L11(b) Revision: Rev. XX, for example: C1, C2 …etc. (c)Serial ID includes the information as below:(a) Manufactured Date: Year: 0~9, for 2010~2019Month: 1~9, A~C, for Jan. ~ Dec.Day: 1~9, A~Y , for 1st to 31st , exclude I , O and U(b) Revision Code: cover all the change(c) Serial No.: Manufacturing sequence of product (d) Product Line: 1 -> Line1, 2 -> Line 2, …etc.Product Line Year, Month, DateCMO Internal Use Revision CMO Internal Use Serial No.N173HGE-L11Rev. XXxxxx7.2 CARTONFigure. 7-2 Packing Method7.3 PALLETFigure. 7-3 Packing Method8. PRECAUTIONS8.1 HANDLING PRECAUTIONS(1) The module should be assembled into the system firmly by using every mounting hole. Be carefulnot to twist or bend the module.(2) While assembling or installing modules, it can only be in the clean area. The dust and oil may causeelectrical short or damage the polarizer.(3) Use fingerstalls or soft gloves in order to keep display clean during the incoming inspection andassembly process.(4) Do not press or scratch the surface harder than a HB pencil lead on the panel because the polarizeris very soft and easily scratched.(5) If the surface of the polarizer is dirty, please clean it by some absorbent cotton or soft cloth. Do notuse Ketone type materials (ex. Acetone), Ethyl alcohol, Toluene, Ethyl acid or Methyl chloride. It might permanently damage the polarizer due to chemical reaction.(6) Wipe off water droplets or oil immediately. Staining and discoloration may occur if they left on panelfor a long time.(7) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. Incase of contacting with hands, legs or clothes, it must be washed away thoroughly with soap.(8) Protect the module from static electricity, it may cause damage to the C-MOS Gate Array IC.(9) Do not disassemble the module.(10) Do not pull or fold the LED wire.(11) Pins of I/F connector should not be touched directly with bare hands.8.2 STORAGE PRECAUTIONS(1) High temperature or humidity may reduce the performance of module. Please store LCD modulewithin the specified storage conditions.(2) It is dangerous that moisture come into or contacted the LCD module, because the moisture maydamage LCD module when it is operating.(3) It may reduce the display quality if the ambient temperature is lower than 10 ºC. For example, theresponse time will become slowly, and the starting voltage of LED will be higher than the room temperature.8.3 OPERATION PRECAUTIONS(1) Do not pull the I/F connector in or out while the module is operating.(2) Always follow the correct power on/off sequence when LCD module is connecting and operating.This can prevent the CMOS LSI chips from damage during latch-up.(3) The startup voltage of Backlight is approximately 1000 Volts. It may cause electrical shock whileassembling with converter. Do not disassemble the module or insert anything into the Backlight unit.Appendix. EDID DATA STRUCTUREThe EDID (Extended Display Identification Data) data formats are to support displays as defined in the VESA Plug & Display and FPDI standards.Byte # (decimal) Byte #(hex)Field Name and CommentsValue(hex)Value(binary)0 0 Header 00 000000001 1 Header FF 111111112 2 Header FF 111111113 3 Header FF 111111114 4 Header FF 111111115 5 Header FF 111111116 6 Header FF 111111117 7 Header 00 000000008 8 EISA ID manufacturer name (“CMO”) 0D 000011019 9 EISA ID manufacturer name (Compressed ASCII) AF 1010111110 0A ID product code (N173HGE-L11) 20 0010000011 0B ID product code (hex LSB first; N173HGE-L11) 17 0001011112 0C ID S/N (fixed “0”) 00 0000000013 0D ID S/N (fixed “0”) 00 0000000014 0E ID S/N (fixed “0”) 00 0000000015 0F ID S/N (fixed “0”) 00 0000000016 10 Week of manufacture (fixed week code) 02 0000001017 11 Year of manufacture (fixed year code) 15 0001010118 12 EDID structure version # (“1”) 01 0000000119 13 EDID revision # (“3”) 03 0000001120 14 Video I/P definition (“digital”) 80 1000000021 15 Max H image size (“38.189cm”) 26 0010011022 16 Max V image size (“21.481cm”) 15 0001010123 17 Display Gamma (Gamma = ”2.2”) 78 0111100024 18 Feature support (“Active off, RGB Color”) 0A 0000101025 19 Rx1, Rx0, Ry1, Ry0, Gx1, Gx0, Gy1, Gy0 D8 1101100026 1A Bx1, Bx0, By1, By0, Wx1, Wx0, Wy1, Wy0 95 1001010127 1B Rx=0.640 A3 1010001128 1C Ry=0.333 55 0101010129 1D Gx=0.303 4D 0100110130 1E Gy=0.613 9D 1001110131 1F Bx=0.154 27 0010011132 20 By=0.060 0F 0000111133 21 Wx=0.313 50 0101000034 22 Wy=0.329 54 0101010035 23 Established timings 1 00 0000000036 24 Established timings 2 00 0000000037 25 Manufacturer’s reserved timings 00 0000000038 26 Standard timing ID # 1 01 0000000139 27 Standard timing ID # 1 01 0000000140 28 Standard timing ID # 2 01 0000000141 29 Standard timing ID # 2 01 0000000142 2A Standard timing ID # 3 01 0000000143 2B Standard timing ID # 3 01 0000000144 2C Standard timing ID # 4 01 0000000145 2D Standard timing ID # 4 01 0000000146 2E Standard timing ID # 5 01 0000000147 2F Standard timing ID # 5 01 0000000148 30 Standard timing ID # 6 01 0000000149 31 Standard timing ID # 6 01 0000000150 32 Standard timing ID # 7 01 0000000151 33 Standard timing ID # 7 01 0000000152 34 Standard timing ID # 8 01 0000000153 35 Standard timing ID # 8 01 000000015436 Detailed timing description # 1 Pixel clock (“138.7MHz”, According toVESA CVT Rev1.1)2E 0010111055 37 # 1 Pixel clock (hex LSB first) 36 0011011056 38 # 1 H active (“1920”) 80 1000000057 39 # 1 H blank (“160”) A0 1010000058 3A # 1 H active : H blank (“1920 : 160”) 70 0111000059 3B # 1 V active (”1080”) 38 0011100060 3C # 1 V blank (”31”) 1F 0001111161 3D # 1 V active : V blank (”1080 : 31”) 40 0100000062 3E # 1 H sync offset (”48”) 30 0011000063 3F # 1 H sync pulse width ("32”) 20 0010000064 40 # 1 V sync offset : V sync pulse width (”3 : 5”) 35 001101016541 # 1 H sync offset : H sync pulse width : V sync offset : V sync width(”48 : 32 : 3 : 5”)00 0000000066 42 # 1 H image size (”382 mm”) 7E 0111111067 43 # 1 V image size (”215 mm”) D7 1101011168 44 # 1 H image size : V image size (”382 : 215”) 10 0001000069 45 # 1 H boarder (”0”) 00 0000000070 46 # 1 V boarder (”0”) 00 000000007147 # 1 Non-interlaced, Normal, no stereo, Separate sync, H/V polNegatives18 0001100072 48 Detailed timing description # 2 00 0000000073 49 # 2 Flag 00 0000000074 4A # 2 Reserved 00 00000000754B # 2 FE (hex) defines ASCII string (Model Name “N173HGE-L11”,ASCII)FE 1111111076 4C # 2 Flag 00 0000000077 4D # 2 1st character of name (“N”) 4E 0100111078 4E # 2 2nd character of name (“1”) 31 0011000179 4F # 2 3rd character of name (“7”) 37 0011011180 50 # 2 4th character of name (“3”) 33 0011001181 51 # 2 5th character of name (“H”) 48 0100100082 52 # 2 6th character of name (“G”) 47 0100011183 53 # 2 7th character of name (“E”) 45 0100010184 54 # 2 8th character of name (“-”) 2D 0010110185 55 # 2 9th character of name (“L”) 4C 0100110086 56 # 2 9th character of name (“1”) 31 0011000187 57 # 2 9th character of name (“1”) 31 0011000188 58 # 2 New line character indicates end of ASCII string 0A 0000101089 59 # 2 Padding with “Blank” character 20 0010000090 5A Detailed timing description # 3 00 0000000091 5B # 3 Flag 00 0000000092 5C # 3 Reserved 00 0000000093 5D # 3 FE (hex) defines ASCII string (Vendor “CMO”, ASCII) FE 1111111094 5E # 3 Flag 00 0000000095 5F # 3 1st character of string (“C”) 43 0100001196 60 # 3 2nd character of string (“M”) 4D 0100110197 61 # 3 3rd character of string (“O”) 4F 0100111198 62 # 3 New line character indicates end of ASCII string 0A 0000101099 63 # 3 Padding with “Blank” character 20 00100000 100 64 # 3 Padding with “Blank” character 20 00100000 101 65 # 3 Padding with “Blank” character 20 00100000 102 66 # 3 Padding with “Blank” character 20 00100000 103 67 # 3 Padding with “Blank” character 20 00100000 104 68 # 3 Padding with “Blank” character 20 00100000 105 69 # 3 Padding with “Blank” character 20 00100000 106 6A # 3 Padding with “Blank” character 20 00100000 107 6B # 3 Padding with “Blank” character 20 00100000 108 6C Detailed timing description # 4 00 00000000 109 6D # 4 Flag 00 00000000 110 6E # 4 Reserved 00 000000001116F # 4 FE (hex) defines ASCII string (Model Name“N173HGE-L11”,ASCII)FE 11111110112 70 # 4 Flag 00 00000000 113 71 # 4 1st character of name (“N”) 4E 01001110 114 72 # 4 2nd character of name (“1”) 31 00110001 115 73 # 4 3rd character of name (“7”) 37 00110111 116 74 # 4 4th character of name (“3”) 33 00110011 117 75 # 4 5th character of name (“H”) 48 01001000 118 76 # 4 6th character of name (“G”) 47 01000111 119 77 # 4 7th character of name (“E”) 45 01000101 120 78 # 4 8th character of name (“-”) 2D 00101101 121 79 # 4 9th character of name (“L”) 4C 01001100 122 7A # 4 9th character of name (“1”) 31 00110001 123 7B # 4 9th character of name (“1”) 31 00110001 124 7C # 4 New line character indicates end of ASCII string 0A 00001010 125 7D # 4 Padding with “Blank” character 20 00100000 126 7E Extension flag 00 00000000 127 7F Checksum 6E 01101110Appendix. OUTLINE DRAWING。