OX8541中文资料

四川理工学院课程设计书学院计算机学院专业物联网工程20121班课程无线传感器网络题目现代小区智能电表课程设计教师符长友学生胥玉环刘依粒胡伟杰宋治桦设计时间：2014年7月5日至2017年7月11日前言近年来，在低碳经济、绿色节能及可持续发展思想的推动下，如何进一步提高电网效率，积极应对环境挑战，提高供电可靠性和电能质量，完善电力用户服务，适应更加开放的能源及电力市场化环境需要，对未来电网的发展提出了更高的要求。

智能电网的概念应运而生并成为全球电力行业共同研究和探讨的热点，支撑中国乃至全球智能电网的将是通信技术、信息处理技术和控制技术。

智能电表作为智能电网建设的重要基础装备，加快智能电表产业链整合，促进其产业化，对于电网实现信息化、自动化和互动化具有支撑作用。

基于以上分析，本文研究旨在基于AT89C51单片机的智能电表的设计。

本次设计基于单片机AT89C51是以微处理器或微控制器芯片为核心的可以存储大量的测量信息并具有对测量结果进行实时分析、综合和做出各种判断能力的仪器。

一般具有自动测量功能，强大的数据处理能力，进行自动调零和单位换算功能，能进行简单的故障提示，具有操作面板和显示器，有简单的报警功能。

本文主要包括以下三个方面的工作：(1)智能电表的设计背景、优点及发展现状本文首先分析智能电表的设计背景，其次讨论智能电表的优点及相关的应用。

(2)智能电表的硬件和软件实现分析智能电表应该具备的功能，给出该仪表的总体设计框图；详细讨论了该电路的核心芯片选取、数据采集电路的设计、通信电路及输入输出系统的实现并给出了核心芯片．AT89C51的详细参数；使用结构化程序设计手段，利用单片机C语言程序实现按键的扫描并处理程序、数据的采集及后续的算法程序、红外或RS485通信方式的自动抄表程序、CPU卡的读写操作程序以及段式LCD的显示驱动程序。

(3)设计的结论分析、不足及未来的展望阐述了设计的测试结果并对结论进行了分析，给出了设计中的不足之处，并提出了将来的修改意见及改进之处，对智能电表的未来进行展望。

External—Free ReleaseOxford Semiconductor, Inc.1900 McCarthy Boulevard, Suite 210 © Oxford Semiconductor, Inc. 2007F EATURES• Four 16C950 High performance UART channels • 8-bit Pass-through Local Bus (PCI Bridge )• IEEE1284 Compliant SPP/EPP/ECP parallel port (with external transceiver)• Efficient 32-bit, 33 MHz, multi-function target-only PCIcontroller, fully compliant to PCI Local Bus Specification 3.0 and PCI Power Management Specification 1.1 • Software compatible with OXmPCI954• UARTs fully software compatible with 16C550-type devices • UART operation up to 60 MHz via external clock source. Up to 20 MHz with the crystal oscillator• Baud rates up to 60 Mbps in external 1x clock mode and 15 Mbps in asynchronous mode• 128-byte deep FIFO per transmitter and receiver • Flexible clock prescaler, from 1 to 31.875• Automated in-band flow control using programmable Xon/Xoff in both directions•Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR#• Programmable RS485 turnaround delay• Arbitrary trigger levels for receiver and transmitter FIFO interrupts and automatic in-band and out-of-band flow control• Infra-red (IrDA) receiver and transmitter operation • 9-bit data framing, as well as 5, 6, 7, and 8 bits • Detection of bad data in the receiver FIFO• Global Interrupt Status and readable FIFO levels to facilitate implementation of efficient device drivers.• Local registers to provide status/control of device functions • 11 multi-purpose I/O pins, which can be configured as input interrupt pins or ‘wake-up’• Auto-detection of a wide range of optional MICROWIRE TM compatible EEPROMs, to re-configure device parameters • Function access , to pre-configure each function prior to handover to generic device drivers • Operation via I/O or memory mapping• 3.3 V or 5 V operation (PCI Universal Voltage)• Extended operating temperature range: -40° C to 85° C •176-pin LQFP packageD ESCRIPTIONThe OXuPCI954 is a single chip solution for PCI-based serial and parallel expansion add-in cards. It is a dual function PCI device, where function 0 offers four ultra-high performance OX16C950 UARTs, and function 1 is configurable either as an 8-bit local bus or a bi-directional parallel port.Each UART channel in the OXuPCI954 is the fastest available PC-compatible UART, offering data rates up to 15 Mbps and 128-byte deep transmitter and receiver FIFOs. The deep FIFOs reduce CPU overhead and allow utilization of higher data rates. Each UART channel is software compatible with the widely used industry-standard 16C550 devices (and compatibles), as well as the OX16C95x family of high performance UARTs. In addition to increased performance and FIFO size, the UARTs also provide the full set of OX16C95x enhanced features including automated in-band flow control, readable FIFO levels, etc.To enhance device driver efficiency and reduce interrupt latency, internal UARTs have multi-port features such as shadowed FIFO fill levels, a global interrupt source register and Good-Data Status, readable in four adjacent DWORD registers visible to logical functions in I/O space and memory space.Expansion of serial ports beyond four channels is possible using the 8-bit pass-through Local Bus function. This provides a general address/data bus and interrupt capability to a discrete UART part, such as the Oxford SemiconductorOX16C954. Other controllers could be used to provide capabilities beyond additional UART ports. The addressable space provided by the Local Bus can be increased up to 256 bytes, and divided into four chip-select regions. This flexible expansion scheme caters for cards with up to 20 serial ports using external 16C950, 16C954 or compatible devices, or composite applications such as combined serial and parallel port expansion cards. Serial port cards with up to 20 ports (or with 4 serial ports and a parallel port) can be designed without redefining any device or timing parameters.The parallel port is an IEEE 1284 compliant SPP/EPP/ECP parallel port that fully supports the existing Centronics interface. The parallel port can be enabled in place of the local bus. A n external bus transceiver is required for 5V parallel port operation if device is 3.3V sourced.For full flexibility, all the default configuration register values can be overwritten using an optional M ICROWIRE compatibleserial EEPROM. This EEPROM can also be used to provide function access to pre-configure devices on the local bus/parallel port, prior to any PCI configuration accesses and before control is handed to (generic) device drivers.The OXuPCI954 can be used to replace the OXmPCI954 in a PCI application where quad UARTs and a local bus/parallel port functionality are required.OXuPCI954 DATA SHEETIntegrated High Performance Quad UARTs,8-bit Local Bus/Parallel Port,3.3 V and 5 V (Universal Voltage) PCI Interface .Improvements of the OXuPCI954 over Discrete SolutionsHigher degree of integrationThe OXuPCI954 device offers four internal 16C950 high-performance UARTs and an 8-bit local bus or abi-directional parallel port.Multi-function deviceThe OXuPCI954 is a multi-function device to enable users to load individual device drivers for the internal serial ports, drivers for the peripheral devices connected to the local bus or drivers for the internal parallel port.Quad Internal OX16C950 UARTsThe OXuPCI954 device contains four ultra-high performance UARTs, which can increase driver efficiency by using features such as the 128-byte deep transmitter and receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt and flow control trigger levels and readable FIFO levels. Data rates are up to 60 Mbps.Improved access timingAccess to the internal UARTs require zero or one PCI wait state. A PCI read transaction from an internal UART can complete within five PCI clock cycles and a write transaction to an internal UART can complete within four PCI clock cycles. Reduces interrupt latencyThe OXuPCI954 device offers shadowed FIFO levels and Interrupt status registers on the internal UARTs and the MIO pins. This reduces the device driver interrupt latency. Power managementThe OXuPCI954 device complies with the PCI Power Management Specification 1.1 and the Microsoft Communications Device-class Power Management Specification 2.0 (2000). Both functions offer the extended capabilities for Power Management. This achieves significant power savings by enabling device drivers to power down the PCI functions. For function 0, this is through switching off the channel clock, in power state D3. Wake-up (PME# generation) can be requested by either functions. For function 0, this is via the RI# inputs of the UARTs in the power-state D3 or any modem line and SIN inputs of the UARTs in power-state D2. For function 1, this is via the MIO[2] input.Optional EEPROMThe OXuPCI954 device can be reconfigured from an external EEPROM to the end-user’s requirements. However, this is not required in many applications as the default values are sufficient for typical applications. An overrun detection mechanism built into the EEPROM controller prevents the PCI system from ‘hanging’ due to an incorrectly programmed EEPROM.R EVISION H ISTORYRevision Modification May 2007 First publication.Sep 2007 Feature revision, including removal of D3coldT ABLE OF C ONTENTS1OXuPCI954 Device Modes (6)2Block Diagram (7)3Pin Information—176-Pin LQFP (8)3.1Mode ‘0’ Quad UARTs + 8-bit Local Bus (8)3.1.1Mode ‘1’ : Quad UARTs + Parallel Port (9)3.2Pin Descriptions (10)4Configuration and Operation (16)5PCI Target Controller (17)5.1Operation (17)5.2Configuration Space (17)5.2.1PCI Configuration Space Register Map (18)5.3Accessing Logical Functions (20)5.3.1PCI Access to Internal UARTs (21)5.3.2PCI Access to 8-bit Local Bus (22)5.3.3PCI Access to Parallel Port (22)5.4Accessing Local Configuration Registers (23)5.4.1Local Configuration and Control Register ‘LCC’ (Offset 0x00) (23)5.4.2Multi-purpose I/O Configuration Register ‘MIC’ (Offset 0x04) (24)5.4.3Local Bus Timing Parameter Register 1 ‘LT1’ (Offset 0x08) (26)5.4.4Local Bus Timing Parameter Register 2 ‘LT2’ (Offset 0x0C) (27)5.4.5UART Receiver FIFO Levels ‘URL’ (Offset 0x10) (28)5.4.6UART Transmitter FIFO Levels ‘UTL’ (Offset 0x14) (29)5.4.7UART Interrupt Source Register ‘UIS’ (Offset 0x18) (29)5.4.8Global Interrupt Status and Control Register ‘GIS’ (Offset 0x1C) (30)5.5PCI Interrupts (31)5.6Power Management (32)5.6.1Power Management of Function 0 (32)5.6.2Power Management of Function 1 (33)5.6.3Universal Voltage (34)5.7Unique Bar Option – for Function 0 (35)6Internal OX16C950 UARTs (36)6.1Operation – Mode Selection (36)6.1.1450 Mode (36)6.1.2550 Mode (36)6.1.3Extended 550 Mode (36)6.1.4750 Mode (36)6.1.5650 Mode (36)6.1.6950 Mode (37)6.2Register Description Tables (38)6.3UART Reset Configuration (41)6.3.1Hardware Reset (41)6.3.2Software Reset (41)6.4Transmitter and Receiver FIFOs (42)6.4.1FIFO Control Register ‘FCR’ (42)6.5Line Control and Status (43)6.5.1False Start Bit Detection (43)6.5.2Line Control Register ‘LCR’ (43)6.5.3Line Status Register ‘LSR’ (44)6.6Interrupts and Sleep Mode (45)6.6.1Interrupt Enable Register ‘IER’ (45)6.6.2Interrupt Status Register ‘ISR’ (46)6.6.3Interrupt Description (46)6.6.4Sleep Mode (47)6.7Modem Interface (47)6.7.1Modem Control Register ‘MCR’ (47)6.7.2Modem Status Register ‘MSR’ (48)6.8Other Standard Registers (48)6.8.1Divisor Latch Registers ‘DLL and DLM’ (48)6.8.2Scratch Pad Register ‘SPR’ (48)6.9Automatic Flow Control (49)6.9.1Enhanced Features Register ‘EFR’ (49)6.9.2Special Character Detection (50)6.9.3Automatic In-band Flow Control (50)6.9.4Automatic Out-of-band Flow Control (50)6.10Baud Rate Generation (51)6.10.1General Operation (51)6.10.2Clock Prescaler Register ‘CPR’ (51)6.10.3Times Clock Register ‘TCR’ (51)6.10.4External 1x Clock Mode (53)6.10.5Crystal Oscillator Circuit (53)6.11Additional Features (54)6.11.1Additional Status Register ‘ASR’ (54)6.11.2FIFO Fill Levels ‘TFL and RFL’ (54)6.11.3Additional Control Register ‘ACR’ (54)6.11.4Transmitter Trigger Level ‘TTL’ (55)6.11.5Receiver Interrupt. Trigger Level ‘RTL’ (55)6.11.6Flow Control Levels ‘FCL’ and ‘FCH’ (56)6.11.7Device Identification Registers (56)6.11.8Clock Select Register ‘CKS’ (56)6.11.9Nine-bit Mode Register ‘NMR’ (57)6.11.10Modem Disable Mask ‘MDM’ (57)6.11.11Readable FCR ‘RFC’ (58)6.11.12Good-data Status Register ‘GDS’ (58)6.11.13Port Index Register ‘PIX’ (58)6.11.14Clock Alteration Register ‘CKA’ (58)6.11.15RS485 Delay Enable ‘RS485_DLYEN’ (58)6.11.16RS485 Delay Count ‘RS485_DLYCNT’ (59)7Local bus (60)7.1Overview (60)7.2Operation (60)7.3Configuration and Programming (61)8Bidirectional Parallel Port (62)8.1Operation and Mode Selection (62)8.1.1SPP Mode (62)8.1.2PS2 Mode (62)8.1.3EPP Mode (62)8.1.4ECP Mode (62)8.2Parallel Port Interrupt (63)8.3Register Description (63)8.3.1Parallel Port Data Register ‘PDR’ (64)8.3.2ECP FIFO Address / RLE (64)8.3.3Device Status Register ‘DSR’ (64)8.3.4Device Control Register ‘DCR’ (64)8.3.5EPP Address register ‘EPPA’ (65)8.3.6EPP Data Registers ‘EPPD1-4’ (65)8.3.7ECP Data FIFO (65)8.3.8Test FIFO (65)8.3.9Configuration A Register (65)8.3.10Configuration B Register (65)8.3.11Extended Control Register ‘ECR’ (65)9Serial EEPROM (66)9.1Specification (66)9.1.1Zone 0: Header (67)9.1.2Zone 1: Local Configuration Registers (68)9.1.3Zone 2: Identification Registers (69)9.1.4Zone 3: PCI Configuration Registers (69)9.1.5Zone 4: Power Management DATA (and DATA_SCALE Zone) (70)9.1.6Zone 5: Function Access (70)10Operating Conditions (72)10.1DC Electrical Characteristics (72)11AC Electrical Characteristics (76)11.1PCI Bus Timings (76)11.2Local Bus (77)11.3Serial Ports (79)12Timing Waveforms (80)13Package Information (95)13.1176-Pin LQFP (95)14Ordering Information (96)1OX U PCI954D EVICE M ODESThe OXuPCI954 supports two modes of operation. These modes are summarized in the following table.Device Mode Mode Pin Selection Functionality0 MODE = 0 Function 0 : Quad UARTs Function 1 : 8-bit local bus1 MODE = 1 Function 0 : Quad UARTs Function 1 : Parallel Port* The OXuPCI954 is not pin-compatible with the OX16PCI954 or the OXmPCI954, but is the same in all other aspects.2B LOCK D IAGRAMFIFOSELMODEAD[31:0]C/BE[3:0]#PCI_CLKFRAME#DEVSEL#IRDY#TRDY#STOP#PARPERR#IDSELRST#INTA#PME#XTLIXTLOUART_Clk_Out Local_Bus ClkEE_DIEE_CSEE_CKEE_DOSOUT[3:0]SIN[3:0]RTS[3:0]DTR[3:0]CTS[3:0]DSR[3:0]DCD[3:0]RI[3:0]MIO[10:0]PD[7:0]ACK#PEBUSYSLCTERR#SLIN#INIT#AFD#STB#LBA[7:0]LBD[7:0]LBCS[3:0]LBWR#LBRD#LBRSTDATA_DIR OXuPCI954 Block DiagramOSCDIS XTLSEL3P IN I NFORMATION—176-P IN LQFP 3.1Mode ‘0’ Quad UARTs + 8-bit Local Bus7 NC. Do not connect these pins:23, 40, 41, 136, 137, 138, 1393.1.1Mode ‘1’ : Quad UARTs + Parallel Port15 NC. Do not connect these pins:23, 40, 41, 74, 112, 113, 114, 115, 116, 117, 124, 136, 137, 138, 1393.2Pin DescriptionsFor the actual pinouts of the OXuPCI954 device (for the various modes), refer to the Section 3, Pin Information. The I/O direction key table is on page 15.PCI Interface – All ModesPin Dir1Name Description149, 150, 151, 154, 155,157, 158, 160, 164, 165,167, 168, 169, 170, 171,174, 13, 14, 15, 17, 18, 20,24, 25, 27, 28, 31, 32, 33,34, 35, 39P_I/O AD[31:0] Multiplexed PCI Address/Data bus161, 175, 12, 26 P_I C/BE[3:0]# PCI Command/Byte enable146 P_I CLK PCI system clock (33MHz)176 P_IFRAME#CycleFrame5 P_ODEVSEL#DeviceSelect1 P_IIRDY#Initiatorready2 P_OTRDY#Targetready6 P_O STOP# Target Stop request10 P_I/OPAR Parity8 P_OSERR#Systemerror7 P_I/OPERR#Parityerror163 P_I IDSEL Initialization device select144 P_I RST# PCI system reset142 P_ODINTA# PCIinterrupt147 P_OD PME# Power management eventSerial Port Pins – All ModesPin Dir1Name Description50 I FIFOSEL FIFO select. For backward compatibility with 16C550,16C650 and 16C750 devices the UARTs’ FIFO depth is 16when FIFOSEL is low. The FIFO size is increased to 128when FIFOSEL is high. The unlatched state of this pin isreadable by software. The FIFO size may also be set to 128by setting FCR[5] when LCR[7] is set, or by putting thedevice into Enhanced mode.82, 81, 63, 62 O(h)SOUT[3:0]IrDA_Out[3:0] These four pins are present in all modes but they can serve one of two functions, as follows:UART serial data outputs.UART IrDA data output when MCR[6] of the corresponding channel is set in Enhanced mode.91, 73, 72, 55I(h) I(h) SIN[3:0]IrDA_In[3:0]These four pins are present in all modes but they can serveone of two functions, as follows:UART serial data inputs.UART IrDA data input when IrDA mode is enabled (seeabove).Serial Port Pins – All ModesPin Dir1Name Description89, 76, 71, 57 I(h) DCD[3:0]# Active-low modem data-carrier-detect input 84, 79, 65, 60O(h) O(h) O(h) DTR[3:0]#485_En[3:0]Tx_Clk_Out[3:0]These four pins are present in all modes but they can serveone of three functions, as follows:Active-low modem data-terminal-ready output. If automatedDTR# flow control is enabled, the DTR# pin is asserted anddeasserted if the receiver FIFO reaches or falls below theprogrammed thresholds, respectively.In RS485 half-duplex mode, the DTR# pin may beprogrammed to reflect the state of the transmitter empty bitto automatically control the direction of the RS485transceiver buffer (see register ACR[4:3]).Transmitter 1x clock (baud rate generator output). Forisochronous applications, the 1x (or Nx) transmitter clockmay be asserted on the DTR# pins (see register CKS[5:4]).83, 80, 64, 61 O(h) RTS[3:0]# Active-low modem request-to-send output. If automatedRTS# flow control is enabled, the RTS# pin is deassertedand reasserted whenever the receiver FIFO reaches or fallsbelow the programmed thresholds, respectively.85, 78, 67, 59 I(h) CTS[3:0]# Active-low modem clear-to-send input. If automated CTS#flow control is enabled, upon deassertion of the CTS# pin,the transmitter will complete the current character and enterthe idle mode until the CTS# pin is reasserted. Note: any in-band flow control characters are transmitted regardless ofthe state of the CTS# pin.86, 77, 66, 58I(h) I(h) DSR[3:0]#Rx_Clk_In[3:0]These four pins are present in all modes but they can serveone of two functions, as follows:Active-low modem data-set-ready input. If automated DSR#flow control is enabled, upon deassertion of the DSR# pin,the transmitter will complete the current character and enterthe idle mode until the DSR# pin is reasserted. Note: any in-band flow control characters are transmitted regardless ofthe state of the DSR# pin.External receiver clock for isochronous applications. TheRx_Clk_In is selected when CKS[1:0] = ‘01’.90, 75, 70, 56 I(h)I(h) RI[3:0]#Tx_Clk_In[3:0]Active-low modem Ring-Indicator inputExternal transmitter clock. This clock can be used by thetransmitter (and indirectly by the receiver) when CKS[6]=’1’.Clock Interface Pins – All ModesPin Dir 1 Name Description49 I/OXTLOCrystal oscillator output when OSCDIS = ‘0’.External clock source input when OSCDIS = ‘1’48 I XTLI Crystal oscillator input when OSCDIS = ‘0’, up to 20MHz.N/C when OSCDIS = ‘1’45 I OSCDIS Oscillator disable.When 0, the internal crystal oscillator is enabled and a crystal needs to be attached to XTLI/XTLO.XTLSEL must be set according to the crystal frequency that is used (up to 20Mhz).When 1, the internal crystal oscillator is disabled and an external oscillator source (up to 60MHz) can be input to XTLO. XTLI is N/C and XTLSEL must be 0130 I XTLSEL Defines the frequency of the crystal attached to XTLI/XTLO(when OSCDIS = ‘0’)0 = 1 MHz – 12 MHz 1 = 12 MHz – 20 MHz8-bit Local Bus – Mode 0Pin Dir 1 Name Description 111O UART_CLK_Out Buffered crystal output. This clock can drive external UARTsconnected to the local bus. Can be enabled / disabled by software.123 O(h) LBRST Local bus active-high reset. 124 O LBRST# Local bus active-low reset. 104 O LBDOUT Local bus data out enable. This pin can be used by externaltransceivers; it is high when LBD[7:0] are in output mode and low when they are in input mode.74 O LBCLK Buffered PCI clock. Can be enabled / disabled by software. 114, 115, 116, 117 O(h) O(h) LBCS[3:0]# LBDS[3:0]# Local bus active-low Chip-Select (Intel mode).Local bus active-low Data-Strobe (Motorola mode).112 O O LBWR# LBRDWR# Local bus active-low write-strobe (Intel mode).Local bus Read-not-Write control (Motorola mode).113 O Z LBRD# Hi-Z Local bus active-low read-strobe (Intel mode).Permanent high impedance (Motorola mode).105, 106, 108, 109 118, 119, 120, 122 O(h) LBA[7:0] Local bus address signals. 96, 97, 98, 99 100, 101, 102, 103I/O(h) LBD[7:0] Local bus data signals.Parallel Port – Mode 1Pin Dir 1 NameDescription123 I(h) I(h) ACK#INTR#Acknowledge (SPP mode). ACK# is asserted (low) by the peripheral to indicate that a successful data transfer has taken place.Identical function to ACK# (EPP mode).122 I(h) PEPaper Empty. Activated by printer when it runs out of paper. 120 I(h) I(h) BUSYWAIT#Busy (SPP mode). BUSY is asserted (high) by the peripheral when it is not ready to accept data.Wait (EPP mode). Handshake signal for interlocked IEEE 1284 compliant EPP cycles.109 OD(h) O(h) SLIN#ADDRSTB#Select (SPP mode). Asserted by host to select the peripheral.Address strobe (EPP mode) provides address read and write strobe.119 I(h) SLCT Peripheral selected. Asserted by peripheral when selected. 118 I(h) ERR#Error. Held low by the peripheral during an error condition. 108 OD(h) O(h) INIT#INIT#Initialize (SPP mode). Commands the peripheral to initialize.Initialize (EPP mode). Identical function to SPP mode. 106 OD(h) O(h) AFD#DATASTB# Auto Feed (SPP mode, open-drain).Data strobe (EPP mode) provides data read and write strobe.105 OD(h) O(h) STB#WRITE#Strobe (SPP mode). Used by peripheral to latch data currently available on PD[7:0].Write (EPP mode). Indicates a write cycle when low and a read cycle when high . 96, 97, 98, 99, 100, 101, 102, 103I/O(h) PD[7:0] Parallel data bus.104OPDOUTParallel port data out enable. This pin should be used by external transceivers for 5 V signaling; it is high when PD[7:0] are in output mode and low when they are in input mode.Multi-purpose and External Interrupt Pins – All ModesPin Dir1Name DescriptionMODE0 1135 --135I/O(h)OMIO0NCMulti-purpose I/O 0. Can drive high or low, or assert a PCIinterrupt.Output Driving ‘0’. Can be left as a No-connect.134 134 134134I/O(h)MIO1NCMulti-purpose I/O 1. Can drive high or low, or assert a PCIinterrupt (as long as LCC[6:5] = “00”).Output Driving ‘0’ (when LCC[6:5] ≠ ‘00’)Can be left as a No-Connect.133 133 133133I/O(h)IMIO2PME_InMulti-purpose I/O 2. When LCC[7] = 0, this pin can drive highor low, or assert a PCI interrupt.Input power management event. When LCC[7] is set thisinput pin can assert a function 1 PME#.93, 94, 95, 125, 126, 127, 128, 132 I/O(h) MIO[10:3] Multi-purpose I/O pins. Can drive high or low, or assert a PCIinterrupt.EEPROM Pins – All ModesPin Dir1Name Description53 OEE_CKEEPROMclock.52 O EE_CS EEPROM active-high Chip Select.54 IU(h) EE_DI EEPROM data in, with internal pull-up.When the serial EEPROM is connected, this pin should bepulled up using a 1-10k resistor. When the EEPROM is notused the internal pull-up is sufficient.Pin to be connected to the external EEPROM’s EE_DO pin(if used).51 O EE_DO EEPROM data out.Pin to be connected to the external EEPROM’s EE_DI pin(if used).Table 1: Pin DescriptionsI/O Direction Key P_I PCI input 3.3 V Only P_O PCI output / PCITristates 3.3 V Only P_I/O PCI bi-directional 3.3 V Only P_OD PCI open drain 3.3 V OnlyI Input LVTTL level I(h) Input LVTTL level, 5 V tolerant IU(h) Input with internal pull-up LVTTL level, 5 V tolerant I/O(h) Bi-Directional LVTTL level, 5 V tolerantO Output Standard Output O(h) Output 5 V tolerant (High Voltage BI-Direct in output mode) OD Open drain Standard Open-drain Output OD(h) Open drain 5 V tolerant (High Voltage BI-Direct in open-drain mode) NC No connectG Ground V VoltageMiscellaneous PinsPin Dir 1 NameDescription44 IMODEMode selector Pin0 : Function 0 : Quad UART. Function 1 : 8-bit local bus.1 : Function 0 : Quad UART. Function 1 : Parallel port.Power and GroundPinType Name Description19, 42, 47, 69, 88, 107, 131, 148VVDDPower Supply (3.3 V)11, 22, 36, 140, 156, 162, 173 V VIOPCI I/O Universal VoltageDefines the (clamping) voltage of the PCI I/O Buffers.To be connected to the VIO pin of the PCI connector. 3, 4, 9, 16, 21, 29, 30, 37, 38, 43, 46, 68, 87, 92, 110, 121, 129, 141, 143, 145, 152, 153, 159, 166, 172G GNDPower Supply Ground (0 V)4C ONFIGURATION AND O PERATIONThe OXuPCI954 is a multi-function, target-only PCI device, compliant with the PCI Local Bus Specification, Revision 3.0 and the PCI Power Management Specification, Revision 1.1.The OXuPCI954 affords maximum configuration flexibility by treating the internal UARTs, the local bus and the parallel port as separate logical functions. Each function has its own configuration space and is therefore recognized and configured by the PCI BIOS separately. The functions used are configured by the Mode Selection Pin as shown in Section 1 OXuPCI954 Device Modes.The OXuPCI954 is configured by system start-up software during the bootstrap process that follows bus reset. The system scans the bus and reads the vendor and device identification codes from any devices it finds. It then loads device-driver software according to this information and configures the I/O, memory and interrupt resources. Device drivers can then access the functions at the assigned addresses in the usual fashion, with the improved data throughput provided by PCI.Each function operates as though it was a separate device. However there are a set of Local Configuration Registers that can be used to enable signals and interrupts, configure timings, and improve the efficiency of multi-port drivers. This architecture enables separate drivers to be installed for each function. Generic port drivers can be hooked to use the functions individually, or more efficient multi-port drivers can hook both functions, accessing the Local Configuration Registers from either.All registers default after reset to suitable values for typical applications such a 4/8 port serial, or combo 4-port serial/1-port parallel add-in cards. However, all identification, control and timing registers can be redefined using an optional serial EEPROM.5PCI T ARGET C ONTROLLER5.1OperationThe OXuPCI954 responds to the following PCI transactions:-•Configuration access: The OXuPCI954 responds to type 0 configuration reads and writes if the IDSELsignal is asserted and the bus address is selecting theconfiguration registers for function 0 or 1. The devicewill respond to the configuration transaction by asserting DEVSEL#. Data transfer then follows. Anyother configuration transaction will be ignored by theOXuPCI954.•I/O reads/writes: The address is compared with the addresses reserved in the I/O Base Address Registers(BARs). If the address falls within one of the assignedranges, the device will respond to the I/O transactionby asserting DEVSEL#. Data transfer follows thisaddress phase. For the UARTs and 8-bit local buscontroller, only byte accesses are possible. For I/Oaccesses to these regions, the controller comparesAD[1:0] with the byte-enable signals as defined in thePCI specification. The access is always completed;however if the correct BE signal is not present thetransaction will have no effect.•Memory reads/writes: These are treated in the same way as I/O transactions, except that the memoryranges are used. Memory access to single-byte regions is always expanded to DWORDs in theOXuPCI954. In other words, OXuPCI954 reserves aDWORD per byte in single-byte regions. The deviceallows the user to define the active byte lane usingLCC[4:3] so that in Big-Endian systems the hardwarecan swap the byte lane automatically. For Memorymapped access in single-byte regions, the OXuPCI954 compares the asserted byte-enable withthe selected byte-lane in LCC[4:3] and completes theoperation if a match occurs, otherwise the access willcomplete normally on the PCI bus, but it will have noeffect on either the internal UARTs or the local buscontroller.•All other cycles (64-bit, special cycles, reserved encoding etc.) are ignored.The OXuPCI954 will complete all transactions as disconnect-with-data, i.e. the device will assert the STOP# signal alongside TRDY#, to ensure that the Bus Master does not continue with a burst access. The exception to this is Retry, which will be signaled in response to any access while the OXuPCI954 is reading from the serial EEPROM.The OXuPCI954 performs medium-speed address decoding as defined by the PCI specification. It asserts the DEVSEL# bus signal two clocks after FRAME# is first sampled low on all bus transaction frames which address the chip. The internal UARTs are accessed with zero wait states inserted. Fast back-to-back transactions are supported by the OXuPCI954 as a target, so a bus master can perform faster sequences of write transactions to the UARTs or local bus when an inter-frame turn-around cycle is not required.The device supports any combination of byte-enables to the PCI Configuration Registers and the Local Configuration Registers. If a byte-enable is not asserted, that byte is unaffected by a write operation and undefined data is returned upon a read.The OXuPCI954 performs parity generation and checking on all PCI bus transactions as defined by the standard. Note this is entirely unrelated to serial data parity which is handled within the UART functional modules themselves. If a parity error occurs during the PCI bus address phase, the device will report the error in the standard way by asserting the SERR# bus signal. However if that address/command combination is decoded as a valid access, it will still complete the transaction as though the parity check was correct.The OXuPCI954 does not support any kind of caching or data buffering in addition to that already provided within the UARTs by the transmit and receive data FIFOs. In general, registers in the UARTs and on the local bus can not be pre-fetched because there may be side-effects on read.5.2Configuration SpaceThe OXuPCI954 is a dual-function device, where each logical function has its own configuration space. All required fields in the standard header are implemented, plus the Power Management Extended Capability register set. The format of the configuration space is shown in the following tables.In general, writes to any registers that are not implemented are ignored, and all reads from unimplemented registers return 0.。

SGM8541 SGM8542 SGM85441.1MHz, 42µA, Rail-to-Rail I/O CMOS Operational AmplifierShengbang Microelectronics Co, LtdREV . BELECTRICAL CHARACTERISTICS : V S = +5V (At R L = 100kΩ connected to Vs/2,and V OUT= Vs/2, unless otherwise noted)Specifications subject to change without notice.PACKAGE/ORDERING INFORMATIONMODEL ORDERNUMBERPACKAGEDESCRIPTIONPACKAGEOPTIONMARKINGINFORMATIONSGM8541XN5/TR SOT23-5 Tape and Reel, 3000 8541 SGM8541SGM8541XS/TR SO-8 Tape and Reel, 2500 SGM8541XSSGM8542XS/TR SO-8 Tape and Reel, 2500 SGM8542XS SGM8542SGM8542XMS/TR MSOP-8 Tape and Reel, 3000 SGM8542XMSSGM8544XS/TR SO-16 Tape and Reel, 2500 SGM8544XS SGM8544SGM8544XTS TSSOP-16 Tape and Reel, 3000 SGM8544XTSABSOLUTE MAXIMUM RATINGS Supply Voltage, V+ to V- ........................................... 7.5 V Common-Mode Input Voltage...........................................(–V S )– 0.5 V to (+V S) +0.5V Storage Temperature Range.................. –65℃ to +150℃Junction Temperature ............................................... 150℃Operating Temperature Range ........... –55℃ to +150℃Package Thermal Resistance @ T A = 25℃SOT23-5, θJA.............................................................. 190/W℃SO-8, θJA......................................................................125/W℃MSOP-8, θJA.............................................................. 216/W℃SO-16, θJA..................................................................... 82/W℃TSSOP-16, θJA............................................................ 105/W℃Lead Temperature Range (Soldering 10 sec).....................................................260℃ESD Susceptibility HBM.. (4000V)MM (400V)NOTES1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTIONThis integrated circuit can be damaged by ESD. Shengbang Micro-electronics recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.TYPICAL PERFORMANCE CHARACTERISTICSAt T A = +25℃, V S = +5V , and R L = 100k Ω connected to Vs/2,unless otherwise noted.Small-Signal Step Response Large-Signal Step Response2µs/div 10µs/div20m V /d i v500m V /d i vG = +1C L = 100pF R L= 100K ΩG = +1C L = 100pF R L= 100K ΩTYPICAL PERFORMANCE CHARACTERISTICS At T A = +25℃, V S = +5V, and R L = 100kΩconnected to Vs/2,unless otherwise noted.TYPICAL PERFORMANCE CHARACTERISTICS At T A = +25℃, V S = +5V, and R L = 100kΩconnected to Vs/2,unless otherwise noted.Overload Recovery TimeTime(2µs/div)Vs = 5VG = -5V IN= 500mV 2.5V0V500mV0VAPPLICATION NOTESDriving Capacitive LoadsThe SGM854X can directly drive 250pF in unity-gain without oscillation. The unity-gain follower (buffer) is the most sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers and this results in ringing or even oscillation. Applications that require greater capacitive drive capability should use an isolation resistor between the output and the capacitive load like the circuit in Figure 1. The isolation resistor R ISO and the load capacitor C L form a zero to increase stability. The bigger the R ISO resistor value, the more stable V OUT will be. Note that this method results in a loss of gain accuracy because R ISO forms a voltage divider with the R LOAD.V IN V OUTFigure 1. Indirectly Driving Heavy Capacitive LoadAn improvement circuit is shown in Figure 2, It provides DC accuracy as well as AC stability. R F provides the DC accuracy by connecting the inverting signal with the output, C F and R Iso serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier’s inverting input, thereby preserving phase margin in the overall feedback loop.V IN V OUTFigure 2. Indirectly Driving Heavy Capacitive Load with DC AccuracyFor no-buffer configuration, there are two others ways to increase the phase margin: (a) by increasing the amplifier’s gain or (b) by placing a capacitor in parallel with the feedback resistor to counteract the parasitic capacitance associated with inverting node. Power-Supply Bypassing and Layout The SGM854X family operates from either a single +2.5V to +5.5V supply or dual ±1.25V to ±2.75V supplies. For single-supply operation, bypass the power supply V DD with a 0.1µF ceramic capacitor which should be placed close to the V DD pin. For dual-supply operation, both the V DD and the V SS supplies should be bypassed to ground with separate 0.1µF ceramic capacitors. 2.2µF tantalum capacitor can be added for better performance.VnVpV SSV SS(GND)Figure 3. Amplifier with Bypass CapacitorsTypical Application Circuits Differential AmplifierThe circuit shown in Figure 4 performs the difference function. If the resistors ratios are equal ( R4 / R3 = R2 / R1 ), thenV OUT = ( Vp – Vn ) × R2 / R1 + Vref.Vn VpOUT Figure 4. Differential AmplifierInstrumentation AmplifierThe circuit in Figure 5 performs the same function as that in Figure 4 but with the high input impedance.Vn VpV OUT Figure 5. Instrumentation AmplifierLow Pass Active FilterThe low pass filter shown in Figure 6 has a DC gain of ( - R2 / R1 ) and the –3dB corner frequency is 1/2πR2C. Make sure the filter is within the bandwidth of the amplifier. The Large values of feedback resistors can couple with parasitic capacitance and cause undesired effects such as ringing or oscillation in high-speed amplifiers. Keep resistors value as low as possible and consistent with output loading consideration.V INV OUT Figure 6. Low Pass Active FilterPACKAGE OUTLINE DIMENSIONS SOT23-5PACKAGE OUTLINE DIMENSIONS SO-8PACKAGE OUTLINE DIMENSIONS MSOP-8PACKAGE OUTLINE DIMENSIONS SO-16PACKAGE OUTLINE DIMENSIONS TSSOP-16REVISION HISTORYLocation Page 11/06— Data Sheet changed from REV.A to REV.BChanges to ABSOLUTE MAXIMUM ATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 3Shengbang Microelectronics Co, LtdUnit 3, ChuangYe PlazaNo.5, TaiHu Northern Street, YingBin Road Centralized Industrial ParkHarbin Development ZoneHarbin, HeiLongJiang 150078P.R. ChinaTel.: 86-451-84348461Fax: 86-451-84308461。

五、用户必读1、故障代码含义速查表是按代码值从小到大排序，卡中出码顺序由电脑主板上BIOS确定;2、四位代码中分为两组两位代码。

前两位（千位和百位）为一组；后两位（十位和个位）为另一组。

您分别查看这两组代码的含义说明既不仅知道被测计算机故障自检不能通过的部件（由千位和百位显示）；并且知道计算机故障自检到最后所通过的部件（由十位和个位显示）;3、未定义的代码表中未能列出;4、对于不同BIOS（常用的AMI、Award、Phoenix）同一代码所代表的意义则不同，因此应弄清您所检测的电脑是属于哪一种类型的BIOS,您可查阅您的电脑使用手册，或从电脑主板上的BIOS芯片上直接查看，也可以在启动的屏幕中直接看到;5、有少数电脑主板的PCI槽只送出一部分代码，但ISA槽则有完整自检代码输出。

且目前已发现有极个别原装机电脑主板的ISA槽无代码输出，而PCI槽则有完整代码输出，故建议您在查看代码不成功时，将本双槽卡换到另一种插槽试一下。

另外，同一块电脑主板的不同PCI槽，有的槽有完整代码送出，如DELL810台式电脑主板上只有靠近CPU的一个PCI槽有完整代码显示，一直变化到“00”或“FF”，而其它PCI槽走到“38”后则不继续变化;6、复位信号所需时间ISA与PCI不一定同步，故有可能ISA开始出代码，但PCI的复位灯还未熄，故PCI 代码停在起始代码上;7、由于电脑主板品种和结构的多样性及BIOS POST 代码不断更新，令紧接在代码后面的查找故障部件和围的准确性受到影响，故《代码含义速查表》中说明的故障部件和围只能作为参考;六、指示灯功能速查表+5V、+12V、OSC和FRAME、CLK、RUN、-5V和+3V3、-12V、BIOS和IRDY、RST灯名信号名称说明CLK 总线时钟不论ISA或PCI只要电脑（无CPU等）接通电源就应常亮，否则CLK信号坏。

BIOS 基本输入输出电脑主板运行时对BIOS有读操作时就闪亮。

玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理。

8-位微控制器Publication Release Date: March 25, 2008目录-1 概述.............................................................................................................................................42 特性.............................................................................................................................................43 产品型号信息...............................................................................................................................5 3.1无铅(RoHS) 产品型号信息表列 (5)4 管脚配置......................................................................................................................................5 5 管脚描述......................................................................................................................................6 6功能描述......................................................................................................................................7 6.1 I/O 端口...........................................................................................................................7 6.2 串行 I/O...........................................................................................................................7 6.3 定时器.............................................................................................................................7 6.4 中断.................................................................................................................................7 6.5 数据指针..........................................................................................................................7 6.6CPU 架构........................................................................................................................7 6.6.1 ALU...................................................................................................................................7 6.6.2 累加器(ACC).....................................................................................................................8 6.6.3 B 寄存器............................................................................................................................8 6.6.4 程序状态字寄存器(PSW)...................................................................................................8 6.6.5 片内便签RAM....................................................................................................................8 6.6.6 堆栈指针............................................................................................................................8 7 内存组织......................................................................................................................................9 7.1 程序内存..........................................................................................................................9 7.2 数据存储器......................................................................................................................9 7.3 寄存器的映射..................................................................................................................9 7.4 工作寄存器....................................................................................................................11 7.5 位寻址区........................................................................................................................11 7.6堆栈 (11)8 特殊功能寄存器.........................................................................................................................13 9 指令...........................................................................................................................................34 9.1 指令时序........................................................................................................................42 10电源管理 (45)10.1 空闲模式........................................................................................................................45 10.2掉电模式 (45)11 复位条件 (47)11.1复位源 (47)11.1.1外部复位 (47)11.1.2上电复位 (POR) (47)11.1.3欠压复位(BOR) (47)11.1.4看门狗定时器复位 (47)11.2复位状态 (47)12INTERRUPTS (50)12.1中断源 (50)12.2中断优先级 (51)12.3中断响应时间 (52)13可编程定时器/计数器 (54)13.1定时器/计数器0&1 (54)13.2时基选择 (54)13.2.1模式0 (54)13.2.2模式1 (55)13.2.3模式2 (55)13.2.4模式3 (56)14数据存储器 (56)15看门狗定时器 (58)15.1看门狗控制 (59)15.2看门狗时钟控制 (59)16串行 (UART) (60)16.1模式 0 (60)16.2模式1 (61)16.3模式 2 (62)16.4模式 3 (63)16.5帧错误检测 (64)16.6多机通信 (64)17脉宽调制(PWM) (66)18模拟比较器 (68)18.1模拟比较器中断 (68)19时控访问保护 (70)20I/O端口配置 (72)20.1准双向端口模式配置 (72)20.2开漏端口模式配置 (73)21振荡器 (74)21.1片内RC振荡器选项 (74)21.2外部时钟输入选项 (74)22电源监视功能 (75)22.1欠压检测 (75)22.2ICP(在电路编程) FLASH 编程 (76)23配置位 (77)23.1CONFIG0 (77)23.2CONFIG1 (78)24电气特性 (79)24.1极限参数 (79)24.2DC 电气特性 (80)24.3模拟比较器电气特性 (82)24.4AC 电气特性 (83)24.5外部时钟特性 (83)24.6RC OSC 和 AC 规格 (83)25典型应用电路 (85)26封装尺寸 (86)26.120-pin SOP (86)26.220-pin DIP (87)27版本历史 (88)华邦电子（上海）集成电路有限公司（8位单片机）uC微控制器产品部上海市长宁区延安西路2299号27楼（邮编200336）电话：************传真：************Publication Release Date: March 25, 20081 概述W79E4051/2051系列是一个快速51微控制器，它有可以在系统编程的(ICP)应用程序Flash EPROM，可以使用烧写器在系统中编程。

Copyright © 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package DrawingPins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)JM38510/07801BJAACTIVE CDIP J 241TBD Call TI Level-NC-NC-NC SN54LS181J ACTIVE CDIP J 241TBD Call TI Level-NC-NC-NC SN54S181J ACTIVE CDIP J 241TBD Call TI Level-NC-NC-NC SN74LS181N ACTIVE PDIP N 2415Pb-Free (RoHS)CU NIPDAU Level-NC-NC-NC SN74LS181N3OBSOLETE PDIP N 24TBD Call TI Call TISN74LS181NE4ACTIVE PDIP N 2415Pb-Free (RoHS)CU NIPDAU Level-NC-NC-NC SN74S181J OBSOLETE CDIP J 24TBD Call TI Call TI SN74S181N OBSOLETE PDIP N 24TBD Call TI Call TI SN74S181N3OBSOLETE PDIP N 24TBD Call TI Call TISNJ54LS181FK ACTIVE LCCC FK 281TBD Call TI Level-NC-NC-NC SNJ54LS181J ACTIVE CDIP J 241TBD Call TI Level-NC-NC-NC SNJ54LS181W ACTIVE CFP W 241TBD Call TI Level-NC-NC-NC SNJ54S181FK ACTIVE LCCC FK 281TBD Call TI Level-NC-NC-NC SNJ54S181J ACTIVE CDIP J 241TBD Call TI Level-NC-NC-NC SNJ54S181JT OBSOLETE CDIP JT 24TBD Call TI Level-NC-NC-NC SNJ54S181WACTIVECFPW241TBDCall TILevel-NC-NC-NC(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TIdoes not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS)or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM17-Oct-2005Addendum-Page 1元器件交易网元器件交易网IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. 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Rev.3.2_00STEP-DOWN, 600 kHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLERS-8540/8541 SeriesSeiko Instruments Inc. 1The S-8540/8541 Series is a family of CMOS step-down switching regulator controllers with PWM control (S-8540 Series) and PWM/PFM switchover control (S-8541 Series). These devices consist of a reference voltage source, oscillation circuit, an error amplifier, phase compensation circuit, PWM control circuit, current limit circuit. A high efficiency and large current switching regulator is realized with the help of small external components due to the high oscillation frequency, 300 kHz and 600 kHz.The S-8540 Series provides low-ripple voltage, high efficiency, and excellent transient characteristics which come from the PMW control circuit capable of varying the duty ratio linearly from 0 to 100%, the optimized error amplifier, and the phase compensation circuit. The S-8541 Series operates under PWM control when the duty ratio is 29% or higher and operates under PFM control when the duty ratio is less than 29% to ensure high efficiency over all load range.These controllers serve as ideal main power supply units for portable devices due to the high oscillation frequencies together with the small 8-Pin MSOP package.Features• Oscillation frequency600 kHz (A, B types) 300 kHz (C, D types)• Output voltage1.5 to 6.0 V, selectable in 0.1V steps (A, C types) • Output voltage precision±2.0%• Feed back type for output voltage (FB) • External components:a transistor, a coil, a diode, and capacitors • Built-in PWM/PFM switchover control circuit (S-8541 series) Duty ratio: 29% (PFM control)29 to 100% (PWM control)• Current limit circuit Current is set by an external resistor R SENSE . • Soft-startTime is set by a capacitor C SS and a resistor R SS . • Shutdown function• Small package 8-Pin MSOP • Lead-free productsApplications• Power supplies for PDAs, electric organizers, and portable devices.• Power supplies for audio equipment such as portable CD players and headphone stereos. • Main or sub Power supplies for notebook computers and peripheral equipment.PackagePackage Name Drawing CodePackage Tape Reel8-Pin MSOP FN008-AFN008-A FN008-ASTEP-DOWN, 600 kHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLERS-8540/8541 Series Rev.3.2_00Block Diagrams1. A, C types (fixed output voltage)S SFigure 12. B, D types (feed back)S SFigure 22 Seiko Instruments Inc.STEP-DOWN, 600 kHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLER Rev.3.2_00 S-8540/8541 SeriesSeiko Instruments Inc. 3Product Name Structure• The control types, product types, and output voltage for the S-8540/8541 series can be selected at theuser’s request. Please refer to the “1. Product name ” for the definition of the product name and “2. Product Name List ” for the full product names. 1. Product nameS -854X X XX FN - XXX T2 GProduct typeA: Fixed output voltage, fosc = 600 kHz B: Feed back type, fosc = 600kHz C: Fixed output voltage, fosc = 300 kHz D: Feed back type, fosc = 300 kHz Output voltage *3 15 to 60(e.g. When the output voltage is 1.5 V, it is expressed as 15.) Control system0: PWM control1: PWM/PFM switching controlFN: 8-Pin MSOPProduct code *2IC direction in tape specifications*1*1. Refer to the taping specifications at the end of this book. *2. Refer to the “2. Product name list ”. *3. 00: Feed back typeSTEP-DOWN, 600 kHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLERS-8540/8541 SeriesRev.3.2_00 4 Seiko Instruments Inc.2.Product name list2.1 A, B types (oscillation frequency: 600 kHz)Table 1Output Voltage (V)S-8540XXXFN SeriesS-8541XXXFN Series1.5 S-8540A15FN-IAAT2G − 1.6 −S-8541A16FN-IGBT2G 1.8 S-8540A18FN-IADT2G S-8541A18FN-IGDT2G 2.5 S-8540A25FN-IAKT2G S-8541A25FN-IGKT2G 3.3 S-8540A33FN-IAST2G S-8541A33FN-IGST2G 5.0 S-8540A50FN-IBBT2G −Feed back (1.5 to 6.0) S-8540B00FN-IMAT2G S-8541B00FN-IMDT2G Remark Please consult the SII marketing department for products with an output voltageother than those specified above. 2.2 C,D types (oscillation frequency: 300 kHz)Table 2Output Voltage (V) S-8540XXXFN Series S-8541XXXFN Series1.8 S-8540C18FN-ICDT2G S-8541C18FN-IIDT2G2.5 S-8540C25FN-ICKT2G S-8541C25FN-IIKT2G3.2 −S-8541C32FN-IIRT2G 3.3 S-8540C33FN-ICST2G S-8541C33FN-IIST2GFeed back (1.5 to 6.0) S-8540D00FN-IMBT2G S-8541D00FN-IMET2G Remark Please consult the SII marketing department for products with an output voltageother than those specified above.STEP-DOWN, 600 kHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLER Rev.3.2_00 S-8540/8541 SeriesSeiko Instruments Inc. 5Pin Configuration8-Pin MSOP TOP viewFigure 3The NC pin can be connected to VIN and VSS.STEP-DOWN, 600 kHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLERS-8540/8541 SeriesRev.3.2_006 Seiko Instruments Inc.Absolute Maximum RatingsTable 4*2. When mounted on board [Mounted board] (1) Board size : 114.3 mm × 76.2 mm × t1.6 mm (2) Board name : JEDEC STANDARD51-7Caution The absolute maximum ratings are rated values exceeding which the product could sufferphysical damage. These values must therefore not be exceeded under any conditions.(1) When mounted on board(2) When not mounted on board 050 100 150 400 200 0 P o w e r d i s s i p a t i o n P D (m W )Ambient temperature Ta (°C)500300 100 600 050 100 150 2001000P o w e r d i s s i p a t i o n P D (m W )Ambient temperature Ta (°C)25015050300350Figure 4 Power Dissipation of PackageSTEP-DOWN, 600 kHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLER Rev.3.2_00 S-8540/8541 SeriesSeiko Instruments Inc.7Electrical Characteristics1. S-8540/8541 Series A, C typesTable 5Coil (L) :Sumida Corporation. CDRH6D28-100 Diode (SD) :Matsushita Electric Inducstrial Co., Ltd. MA2Q737 (Schottky diode) Output capacitor (C OUT ) :Nichicon Corporation F93 (16 V, 47 μF, tantalum) Input capacitor (C IN ) :Nichicon Corporation F93 (16 V, 47 μF, tantalum)Transistor (P SW ):Toshiba Corporation 2SA1213 Base resistor (R b ) :100 m ΩBase capacitor (C b ) :2200pF C VL :1.0 μFC SS :0.047 μFR SS :220 k ΩR SENSE :100 m Ω Condition: Recommended parts are used unless otherwise specified.V IN =V OUT (S) ×1.5 V, I OUT = 120 mA (When V OUT (S) ≤ 1.6 V, then V IN = 2.5 V) *1. V OUT (S) : Specified output voltage value, V OUT (E) : Actual output voltage value *2. Applied to the S-8541 series onlyCaution 1. Line regulation and load regulation may change greatly due to GND wiring when V IN is high.2. In the S-8540 series (PWM control), a state in which the duty ratio 0% continues for severalclocks may occur when the input voltage is high and the output current is low. In this case, the operation changes to the pseudo PFM mode, but the ripple voltage hardly increases.STEP-DOWN, 600 kHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLERS-8540/8541 SeriesRev.3.2_008 Seiko Instruments Inc.2. S-8540/8541 Series B, D typesTable 6Coil (L) :Sumida Corporation CDRH6D28-100Diode (SD) :Matsushita Electric Inducstrial Co., Ltd. MA2Q737 (Schottky diode) Output capacitor (C OUT ) :Nichicon Corporation F93 (16 V, 47 μF, tantalum) Input capacitor (C IN ) :Nichicon Corporation F93 (16 V, 47 μF, tantalum)Transistor (P SW ):Toshiba Corporation 2SA1213 Base resistor (R b ) :100 m ΩBase capacitor (C b ) :2200pF C VL :1.0 μFC SS :0.047 μFR SS :220 k ΩR SENSE :100 m Ω R A :200 k Ω R B :100 k ΩC FB :50pF Condition: Connect recommended parts unless otherwise specified. V IN =4.5 V, I OUT =120 mA *1. V OUT (S) : Specified output voltage value, V OUT (E) : Actual output voltage value*2. The typical value (specified output voltage value) is V OUT (S) = 1 + R A /R B = 3.0 V. See “Output Voltage adjustment”. *3. S-8541 series onlyCaution 1. Line regulation and load regulation may change greatly due to GND wiring when V IN is high.2. In the S-8540 series (PWM control), a state in which the duty ratio 0% continues for severalclocks may occur when the input voltage is high and the output current is low. In this case, the operation changes to the pseudo PFM mode, but the ripple voltage hardly increases.STEP-DOWN, 600 kHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLER Rev.3.2_00 S-8540/8541 SeriesSeiko Instruments Inc.9Measurement Circuits1.VLFigure 52.VVLFigure 63.Figure 74.V VLFigure 8STEP-DOWN, 600 kHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLERS-8540/8541 Series Rev.3.2_00Operation1. Switching control method1. 1 PWM control (S-8540 Series)The S-8540 series consists of pulse width modulation (PWM) DC/DC converters. In conventional pulse frequency modulation (PFM) DC/DC converters, pulses are skipped when they operate at low output load current, causing the variation in the ripple frequency and the increase in the ripple voltage of the output voltage both of which constitute inherent drawbacks to those converters.In the S-8540 series the pulse width varies in the range from 0 to 100% according to the load current, yet ripple voltage produced by the switching can easily be removed by a filter since the switching frequency is always constant. These converters thus provide a low-ripple voltage over wide range of input voltage and load current. And it will be skippped to be low current consumption when the pulse width is 0% or it is no load, input current voltage is high.1. 2 PWM/PFM switchover control (S-8541 Series)The S-8541 series is a DC-DC converter that automatically switches between a pulse width modulation method (PWM) and a pulse frequency modulation method (PFM), depending on the load current, and features low current consumption.The S-8541 series operates under PWM control with the pulse width duty changing from 29 to 100% when the output load current is high. On the other hand, when the output current is low, the S-8541 series operates under PFM control with the pulse width duty fixed at 29%, and pulses are skipped according to the load current. The oscillation circuit thus oscillates intermittently so that the resultant lower self current consumption prevents a reduction in the efficiency when the load current is low. The switching point from PWM control to PFM control depends on the external devices (coil, diode, etc.), input voltage, and output voltage. This series is an especially efficient DC-DC converter at an output current of around 100 μA.10 Seiko Instruments Inc.2. Soft-start functionThe S-8540/8541 series has a built-in soft-start circuit. This circuit enables the output voltage to risegradually over the specified soft-start time to suppress the overshooting of the output voltage and the rush current from the power source when the power is switched on or the power-off pin is set to "H" The soft-start function of this IC, however, can not suppress rush current to the load completely (Refer to Figure 9) . The rush current is affected by the input voltage and the load. Please evaluate the rush current under the actual test condition.time (1 ms/div)VS-8540A33FN (V IN = V ON / OFF = 0 → 5 V)Figure 9 Waveforms of output voltage and rush current at soft-startThe soft-start function of the IC is achieved by raising internal reference voltage gradually, which is caused by the raising of shutdown pin voltage through RC components (R SS and C SS ) connected to shutdown pin. A soft-start time (t SS ) is changed by R SS , C SS and the input voltage V ON/OFF to R SS . t SS is calculated from the following formula:t SS [ms]=R [k Ω] × C [μF] × In (V [V] / (V [V]− 1.8)) e.g. When R SS = 220 k Ω, C SS = 0.047 μF, V ON/OFF = 2.7 V , then t SS = 11.4 ms.3. ON/OFF pin (shutdown pin)This pin deactivates or activates the step-down operation.When the OFFON pin is set to "L", the V IN voltage appears through the EXT pin, prodding the /switching transistor to go off. All the internal circuits stop working, and substantial savings in current consumption are thus achieved.The OFFON pin is configured as shown in Figure 10. Since pull-up or pull-down is not performed /internally, please avoid operating the pin in a floating state. Also, try to refrain from applying a voltage of 0.3 to 1.8 V to the pin, lest the current consumption increase. When this OFFON pin is not used,/leave it coupled to the VIN pin.Figure 104. Current limit circuitThe S-8540/8541 series contains a current limit circuit.The current limit circuit is designed to prevent thermal destruction of external transistors due to overloador magnetic saturation of the coil.The current limit circuit can be enabled by inserting a SENSE resistor (R SENSE ) between the external coil and the output pin VOUT, and connecting the node for the SENSE resistor and the coil to the SENSE pin.A current limit comparator in the IC is used to check whether the voltage between the SENSE pin and VOUT pin reaches the current limit detection voltage (V SENSE = 125 mV (typ.) ). The current flowing through the external transistor is limited by turning it off during the left time of the oscillation period after detection. The transistor is turned on again at the next clock and current limit detection resumes. If the overcurrent state still persists, the current limit circuit operates again, and the process is repeated. If the overcurrent state is eliminated, the normal operation resumes. Slight overshoot occurs in the output voltage when the overcurrent state is eliminated.Current limit setting value (I Limit ) is calculated by the following formula:I Limit =RsensemV)125 ( Vsense =If the change with time of the current flowing through the sense resistor is higher than the response speed of the current limit comparator in the IC, the actual current limit value becomes higher than the I Limit (current limit setting value) calculated by the above formula. When the voltage difference between VIN pin and VOUT pin is large, the actual current limit value increases since the change with time of the current flowing through the sense resistor becomes large. 4. 1 V IN vs. I peak in the overcurrent stateV IN vs. I peak0.00.51.01.52.0 2.53.0 2.54.05.5 7.0 8.5 10.0V IN (V)I p e a k (A )(IC: S-8540A33FN, coil: CDRH6D28-100, R S ENSE : 100 m Ω)1.25 AFigure 11 l peak change by input voltageWhen the output voltage is approximate 1.0 V or less, the load short-circuit protection does not work,since the current limit circuit does not operate.When the current limit circuit is not used, remove the SENSE resistor and connect the SENSE pin to the VSS or VOUT pin.5. 100% duty cycleThe S-8540/8541 series operates up to the maximum duty cycle of 100%. The switching transistor iskept on continuously to supply current to the load, when the input voltage falls below the preset output voltage value. The output voltage in this case is equal to the subtraction of lowering causes by DC resistance of the coil and on resistance of the switching FET from the input voltage.Even when the duty cycle is 100%, the current limit circuit works when overcurrent flows.Selection of Series Products and Associated External Components1. Selecting a productThe S-8540/8541 series is classified into eight types according to the way of control (PWM andPWM/PFM switching), the oscillation frequencies, and output voltage settings (fixed and feed back).Please select the type that suits your needs best by taking the advantage described below into account.1. 1 Control method:Two different control methods are available: PWM control (S-8540 series) and PWM/PFM switchingcontrol (S-8541 series).1. 2 Oscillation frequencies:The oscillation frequencies are selectable in 600 kHz (A and B types) or 300 kHz (C and D types).Because of their high oscillation frequency, the products in the A and B types allow the use of smallsize inductors since the peak current decreases when the same load current flows. In addition, theycan also be used with small output capacitors. These outstanding features make the A and B typesideal for downsized devices.On the other hand, the C and D types, having lower oscillation frequency, are characterized by smallself-consumption current and excellent efficiency under light load.1. 3 Output voltage setting:Two different types are available: fixed output (A and C types) and feed back type (B and D types).Table 8 provides a rough guide for selecting a product depending on the requirements of theapplication. Choose the product that has the best score ({).Table 8S-8541 S-8540A B C D A B C DThe set output voltage is fixed (1.5 to 6.0 V)Set an output voltage freely (1.5 to 6.0 V)The efficiency at light load (less than 10 mA) is{{{{important.The efficiency at 100 mA or more is important. {{{{Low-ripple voltage is important. {{{{Use of small external parts is Important. ~~~~Remark : Indispensable condition{ : Superiority of requirement~ : Particularly superiority of requirement2. InductorThe inductance value (L) greatly affects the maximum output current (I OUT ) and the efficiency (η).The peak current (I PK ) increases by decreasing L and the stability of the circuit improves and I OUT increases. If L is made even smaller, the efficiency falls causing a decline in the current drive capacity for the switching transistor, and I OUT decreases.The loss of I PK by the switching transistor decreases by increasing L and the efficiency becomes maximum at a certain L value. Increasing L further decreases the efficiency due to the loss of coil DC resistance. I OUT also decreases.When the inductance is large in an S-8540/8541 series product, the output voltage may grow unstable in some cases, depending on the conditions of the input voltage, output voltage, and the load current. Perform sufficient evaluation under the actual condition and decide an optimum inductance. The recommended inductances are 10 μH for A, B types and 22 μH for C, D types.When choosing an inductor, attention to its allowable current should be paid since the current over the allowable value will cause magnetic saturation in the inductor, leading to a marked decline in efficiency. An inductor should therefore be selected so as not I PK to surpass its allowable current. The peak current (I PK ) is represented by the following equation in non-continuous operation mode:INOSC OUT IN OUT OUT PK V L f 2)V (V V I I ×××−×+=Where f OSC is the oscillation frequency.3. DiodeThe diode to be externally coupled to the IC should be a type that meets the following conditions: • The forward voltage is low (Schottky barrier diode recommended). • The switching speed is high (50 ns max.).• The reverse direction voltage is higher than V IN . • The current rating is larger than I PK .4. Capacitors4. 1 Capacitors (C IN , C OUT )The capacitor inserted in the input side (C IN ) serves to reduce the power impedance and to averagethe input current for better efficiency. The C IN value should be selected according to the impedance of the power supply. It should be 47 to 100 μF, although the actual value depends on the impedance of the power source used and load current value.For the output side capacitor (C OUT ), select a large capacitance with low ESR (Equivalent Series Resistance) to smoothen the ripple voltage. When the input voltage is extremely high or the load current is extremely large, the output voltage may become unstable. In this case the unstable area will become narrow by selecting a large capacitance for an output side capacitor. A tantalum electrolytic capacitor is recommended since the unstable area widens when a capacitor with a large ESR, such as an aluminum electrolytic capacitor, or a capacitor with a small ESR, such as a ceramic capacitor, is chosen. The range of the capacitance should generally be 47 to 100 μF.4. 2 Internal power source stabilization capacitor (C VL )The main circuits of the IC work on an internal power source connected to the CVREF pin. The C VL is a bypass capacitor for stabilizing the internal Power source. C VL should be a 1 μF ceramic capacitor and wired in a short distance and at a low impedance.5. External transistorThe S-8540/8541 series can work with an enhancement (Pch) MOS FET or a bipolar (PNP) transistor as an external transistor.5. 1 Enhancement (Pch)MOS FETThe EXT pin can directly drive the Pch MOS FET with a gate capacity of approximate 1200 pF.When a Pch MOS FET is chosen, efficiency will be 2 to 3 % higher than that achieved by a PNP bipolar transistor since the MOS FET switching speed is faster than that of the bipolar transistor and power loss due to the base current is avoided.The important parameters in selecting a Pch MOS FET are the threshold voltage, breakdown voltage between gate and source, breakdown voltage between drain and source, total gate capacity, on-resistance, and the current ratings.The EXT pin swings from voltage V IN to V SS. When the input voltage is low, a MOS FET with a low threshold voltage has to be used so that the MOS FET will turn on as required. When, conversely, the input voltage is high, select a MOS FET whose gate-source breakdown voltage is higher than the input voltage by at least several volts.Immediately after the power is turned on, or the power is turned off (that is, when the step-down operation is terminated), the input voltage is applied across the drain and the source of the MOS FET.The transistor therefore needs to have drain-source breakdown voltage that is also several volts higher than the input voltage.The total gate capacity and the on-resistance affect the efficiency.The power loss for charging and discharging the gate capacity by switching operation will affect the efficiency at low load current region more when the total gate capacity becomes larger and the input voltage becomes higher. If the efficiency at low load is a matter of concern, select a MOS FET with a small total gate capacity.In regions where the load current is high, the efficiency is affected by power loss caused by the on-resistance of the MOS FET. If the efficiency under heavy load is particularly important in the application, choose a MOS FET having on-resistance as low as possible.As for the current rating, select a MOS FET whose maximum continuous drain current rating is higher than I PK.5. 2 Bipolar (PNP) transistorFigure 12 shows a circuit diagram using Toshiba Corporation 2SA1213-Y for the bipolar transistor(PNP). Using a bipolar transistor, the driving capacity for increasing the output current is determined by the h FE value and the R b value.2SA1213-YFigure 12The R b value is given by the following equation:EXTLIN I 0.4I 0.7V R bb −−=Calculate the necessary base current Ib using the h FE value of the bipolar transistor from the relation, I b = I PK /h FE , and select a smaller value for R b which is calculated from the above equation.A small R b value will certainly contribute to increase the output current, but it will also decrease the efficiency. Determine the optimum value through experiment since the base current flows as pulses and voltage drop may takes place due to the wiring resistance and so on.In addition, if speed-up capacitor C b is inserted in parallel with resistance R b , as shown in Figure 12, the switching loss will be reduced, leading to a higher efficiency. by using the following equation :0.7f R 21C OSC b b ×××≤πSelect a C b value after performing sufficient evaluation since the optimum C b value differs depending upon the characteristics of the bipolar transistor.Standard Circuits1. Fixed output voltage (Pch MOS FET)V INFigure 132. Feed back type (Pch MOS FET)V INOne pointFigure 14Caution The above connection diagram and constant will not guarantees successful operation.Perform through evaluation using the actual application to set the constant.Precautionsy Install the external capacitors, diode, coil, and other peripheral components as close to the IC as possible, and make a one-point grounding.When the input voltage is 9 to 10 V, V OUT may vary largely according to the grounding method.When it is difficult to make one-point grounding, use two grounds: one for V IN, C IN, and SD GND, and the other for V OUT, V CVREF, and IC GND.y Characteristics ripple voltage and spike noise occur in IC containing switching regulators. Moreover rush current flows at the time of a power supply injection. Because these largely depend on the inductor, the capacitor and impedance of power supply used, fully check them using an actually mounted model.y If the input voltage is high and output current is low, pulses with a low duty ratio may appear, and then the 0% duty ratio continues for several clocks. In this case the operation changes to the pseudo pulse frequency modulation (PFM) mode, but the ripple voltage hardly increases.y If the input power supply voltage is lower than 1.0 V, the IC operation is unstable and the external switch may be turned on.If input power supply voltage is 10.0 V or higher, the circuit operation is unstable and the IC may be damaged.The input voltage must be in the standard range (2.5 to 10.0 V).y The current limit circuit of the IC limits current by detecting a voltage difference of external resistor R SENSE.In choosing the components, make sure that overcurrent will not surpass the allowable dissipation of the switching transistor and the inductor.y Make sure that dissipation of the switching transistor will not surpass the allowable power dissipation of the package (especially at high temperature).y Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.y Seiko Instruments Inc. shall bear no responsibility for any patent infringement by a product that includes an IC manufactured by Seiko Instruments Inc. in relation to the method of using the IC in that product, the product specifications, or the destination country.Application Circuits1. External adjustment of output voltageThe output voltage can be adjusted or changed in the output voltage setting range (1.5 to 6.0 V) by adding external resistors (R A, R B) and a capacitor (C FB) in the S-8540/8541B00AFN and S-8540/8541D00AFN, as shown in Figure 15. Temperature gradient can be given by inserting a thermistor in series to R A and R B.V INTOne pointFigure 15Caution The above connection diagram and constant will not guarantees successful operation.Perform through evaluation using the actual application to set the constant.R A , R B must be R A + R B ≤ 2 M Ω and the ratio of R A to R B should be set so that the FB pin is 1.0 V. Add acapacitor (C FB ) in parallel to R A to prevent unstable operation like output oscillation.Set the C FB so that f = 1/(2 × πC FB × R A ) is 0.1 to 20 kHz (normally 10 kHz).e.g. When V OUT = 3.0 V, R A = 200 k Ω, R B = 100 k Ω, then C FB = 100 pF.The precision of output voltage (V OUT ) determined by R A , R B is affected by the precision of the voltage at the FB pin (1 V ± 2.0%), the precision of R A and R B , current input to the FB pin, and IC power supply voltage V DD .Suppose that the FB pin input current is 0 nA, and that the maximum absolute values of the external resistors R A and R B are R A max. and R B max, and the minimum absolute values of the external resistors R A and R B are R A min. and R B min., and that the output voltage shift due to the V DD voltage dependency is ΔV, the minimum value V OUT min. and maximum value V OUT max. of the output voltage V OUT variation is calculated by the following formula:V OUT min. = (1 +max.R min.R B A ) × 0.98 − ΔV [V ]V OUT max. = (1 +R max.R min.A B ) × 1.02 + ΔV [V ]The precision of the output voltage V OUT cannot be made lower than the precision of the IC output voltage without adjustment of external resistors R A and R B . The lower the R A /R B , the less it is affected by the absolute value precision of the external resistors R A and R B . The lower the R A and R B , the less it is affected by the FB pin input current.To suppress the influence of FB pin input current on the variation of output voltage V OUT , the external resistor R B value must be made sufficiently lower than the input impedance of the FB pin, 1 V/50 nA = 20 M Ω max.Waste current flows through external resistors R A and R B . When it is not a negligible value with respect to load current in actual use, the efficiency decreases. The R A and R B values of the external resistors must therefore be made sufficiently high.Evaluation of the influence of the noise is needed in the actual condition If the R A and R B values of resistors are high (1 M Ω or higher) since they are susceptible to external noise.The output voltage V OUT precision and the waste current are in a trade-off relation. They must be considered according to application requests.。

Precision Mixed Signal Copyright © 2004 by Silicon Laboratories6.15.2004C8051F00525 MIPS, 32 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCUAnalog Peripherals12-Bit ADC-±1 LSB INL; no missing codes-Programmable throughput up to 100 ksps-8 external inputs; programmable as single-ended or differential -Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5-Data-dependent windowed interrupt generator -Built-in temperature sensor (±3 °C)Two 12-Bit DACs-Voltage output-10 µsec settling timeTwo Comparators-16 programmable hysteresis values-Configurable to generate interrupts or resetInternal Voltage ReferenceV DD Monitor/Brown-out DetectorOn-Chip JTAG Debug-On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit emulation-Supports breakpoints, single stepping, watchpoints, inspect/modify memory, and registers-Superior performance to emulation systems using ICE-chips, target pods, and sockets-Fully compliant with IEEE 1149.1 specificationHigh-Speed 8051 µC Core-Pipelined instruction architecture; executes 70% of Instructions in 1 or 2 system clocks-Up to 25 MIPS throughput with 25 MHz clock-Expanded interrupt handler; up to 21 interrupt sourcesMemory-2304 bytes data RAM-32 kB Flash; in-system programmable in 512-byte sectors (512 bytes are reserved)Digital Peripherals-32 port I/O; all are 5 V tolerant-Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports available concurrently-Programmable 16-bit counter/timer array with five capture/compare modules- 4 general-purpose 16-bit counter/timers-Dedicated watchdog timer; bidirectional reset Clock Sources-Internal programmable oscillator: 2–16 MHz -External oscillator: Crystal, RC, C, or Clock -Can switch between clock sources on-the-fly Supply Voltage: 2.7 to 3.6 V-Typical operating current: 12.5 mA at 25 MHz -Multiple power saving sleep and shutdown modes64-Pin TQFPTemperature Range: –40 to +85 °C元器件交易网Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 6.15.2004Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders25 MIPS, 32 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCUSelected Electrical Specifications(T A = –40 to +85 C°, V DD = 2.7 V unless otherwise specified)Package InformationC8051F005DK Development Kit元器件交易网。

Pentium® 4 Processor Software Evaluation Guide forXMPEG* 4.5 with DivX* 5.02/performance November 2002Rev. 1.0.Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.Intel may make changes to specifications and product descriptions at any time, without notice.Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.The Intel® Pentium® 4 processor may contain design defects or errors known as errata. Current characterized errata are available on request.Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor at 3.06 GHz or higher, a chipset and BIOS that utilize this technology, and an operating system that includes optimizations for this technology. Look for systems with the Intel® Pentium® 4 Processor with HT Technology logo which your system vendor has verified utilize Hyper-Threading Technology. See /info/hyperthreading for information.MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s Website at .Copyright ©2002 Intel Corporation.* Other names and brands may be claimed as the property of others.About this DocumentThis document is a guide measuring performance of the Intel® Pentium® 4 processor on application software. The primary audience for this document includes individuals, publications, OEMs and technical analysts whose goal is to test or evaluate the performance benefits and features of the Pentium 4 processor. If there are questions that are not answered here on software application performance evaluation of the Pentium 4 processor, please contact your Intel representative.Each software application test measures different aspects of processor and/or system performance. While no single numerical measurement can completely describe the performance of a complex device like a microprocessor or a personal computer, application tests can be useful tools for comparing different components and systems. The following results and procedures give a glimpse of the performance of certain software applications, however your own usage of each application may vary from what is shown here. The only totally accurate way to measure the performance of your system, is to test the actual software applications you use, in the way you use them, on your computer system. Test results published by Intel are measured on specific systems or components using specific hardware and software configurations, and any differences between those configurations (including software) and your configuration may make those results inapplicable to your component or system.Software application tests are, at most, only one kind of information that you may use during the purchasing process. To get a true picture of the performance of a component or system you are considering purchasing, you must consult other sources of information (such as performance information on the exact system you are considering purchasing). If you have any questions about the performance of any Intel microprocessor, please view the detailed performance briefs and reports published by Intel or call Intel at (US) 1-800-628-8686 or 916-356-3104..Chapter 1Pentium® 4 Processor Performance on XMPEG* 4.5 with DivX* 5.021.0 DescriptionXMPEG* is a multipurpose video encoding application, which takes MPEG-1 and MPEG-2 streams, or DVD-IFO video format and converts them to AVI or bbMPeg Encoder format, changing video parameters, frame rate and audio frequency.One of the most popular uses for uses for XMPEG is to convert un-encrypted DVD VOB files to either MPEG-1 (compatible with Panasonic/LSX Encoders) or to an AVI file (compatible with most codecs1). XMPEG is a very widely-used tool by those users who want to do more with their DVDs, than just play them.It tries to achieve the maximum possible quality while minimizing the conversion impact and provides a straightforward approach to the MPEG1/2 to MPEG/AVI conversion. XMPEG uses 'plug-ins' to support output formats making the program more flexible by allowing for a wide variety of output options. In this test case the output format is DivX* v5.02.DivX is a new format for digital video, much like MP3 is a format for digital music. The DivX codec is based on the MPEG-4 compression standard and can reduce an MPEG-2 video (the same format used for DVD) to ten percent of its original size. The DivX technology provides excellent compression and the resulting visual quality is virtually indistinguishable from a DVD.For more information on XMPEG, go to /xmpeg_index.aspFor more information on DivX 5.02 go to Description1.1 TestWorkloadThe workload takes a one minute non-encrypted MPEG-2 movie file and transcodes it to a DivX MPEG-4 compressed movie file.1.2 ResultsThe XMPEG software with DivX 5.02 encoding test shows excellent performance for the Pentium® 4 processor by using a real-world MPEG-4 encoder to assess the CPU power available to perform software-based video compression. This application benefits from enhanced SSE2 technology implementation, rapid execution engine, high memory bandwidth with the 400 MHz or 533 MHz micro-architecture system bus, and balanced platform design. Furthermore, this workload consists of two threads that each uses roughly half of the computing power. Since the workload uses a functional decomposition model, with the XMPEG engine and the DivX codec running in parallel, the threads rarely compete for the execution resources. As a consequence, the threads increase the processor resource utilization and improve the overall transcode time significantly. The Intel Pentium 4 Processor with HT Technology 3.06 GHz offers 8 times the performance gain while transcoding an MPEG-2 video file to the DivX format compared to the Pentium III processor 500 MHz. The frames per second (fps) value in the chart below is the rate at which the system is transcoding a sample video.1 Codec is an abbreviation for compression - decompression.Note: The above results are in frames per second. For configuration see Table 1.0 and for detailed procedure see Chapter 2.1.3 BenefitsVideo encoding professionals and enthusiasts interested in transcoding from an MPEG-2 to a DivX format can save a significant amount of time by using a PC based on an Intel® Pentium® 4 Processor with HT Technology 3.06 GHz, relative to a PC based on a Pentium III processor 500 MHz. In the example above, the Intel Pentium 4 Processor with HT Technology 3.06 GHz can transcode 102 frames per second while the Intel Pentium III processor 500 MHz can transcode only 12.7 frames per second and the Pentium 4 processor 2A GHz can transcode 54.2 frames per second. Consider an example in which a video encoding professional transcodes a 90-minute video clip in NTSC format from MPEG-2 to the DivX format. The 90-minute clip contains 161838 frames (= 90 x 60 x 29.97). To complete transcoding the MPEG-2 video clip, the Pentium III processor 500 MHz needs 3 hours 32 minutes, the Pentium 4 processor 2A GHz needs 50 minutes, and the Intel Pentium 4 Processor with HT Technology 3.06 GHz needs only about 26 minutes, i.e. it takes only about half an hour to transcode the video clip in this example compared to almost half a work day on a Pentium III processor 500 MHz. Thus, a PC based on an Intel Pentium 4 Processor with HT Technology 3.06 GHz saves the video encoding professional a significant amount of time and offers the highest performance available today.Chapter 2System Configuration and Setup2.0 CurrentReferenceConfigurationThis section describes the configuration used for the Pentium® 4 processor desktop performance evaluation as reported in this document. Note that the configuration is subject to change, and any changes may be reflected in the later versions of this document. Table 1 shows the hardware and software configuration used for this performance evaluation.Operating System Windows* XP Professional Edition (Build 2600, FAT32 partition,32-bit File System with “System Restore” DISABLED) Motherboard or System (1) Intel® SE2 440BX with Pentium® III processor 500 MHzSE440BX2 P17 BIOS(2) Intel D850EMV2 with Pentium 4 processor 2A GHzMV85010A.86A.0025.P10 BIOS(3) Intel D850EMV2 with Pentium 4 Processor 3.06 GHzsupporting HT Technology MV85010A.86A.0036.P14 BIOS Memory Size (1) 1x128MB Crucial* (Micron*) PC100 CL2 SDRAM(2) 2x128MB Non-ECC RDRAM Samsung* PC800-40(3) 2x128MB Non-ECC RDRAM Corsair* PC1066-32Graphic Adapter (2D/3D) (1) nVidia* GeForce 3* AGP with 64MB(2,3) Leadtek WinFast A250 Ultra TD (nVidia GeForce 4 Ti 4600) 4x AGP graphicsChipset Inf File (1) N/A(2,3) Intel® Chipset Software Installation Utility v 4.00.1009 Hard Disk (1) IBM* DTLA-307030 30GB ATA-100(2,3) IBM 120GXP 80 GB IC35L080AVVA07-0 ATA-100 Hard Disk Driver (1) N/A(2,3) Intel® Application Accelerator v 2.2.2128Graphics Driver (1) nVidia Detonator 3 reference driver 21.81(2,3) nVidia Detonator 4 reference driver 28.32 Resolution /Colors 1024 x 768 @ 32-bit colorDirectX Support Default MS DirectX 8.1 from Windows XPTable 2.0 Current Reference Configurations:Note: All equipment is publicly available unless it is stated otherwise.The sources for obtaining all the latest driver versions, software, BIOS, etc. are as follows:•The nVidia* graphics reference driver Detonator 4 can be downloaded from/view.asp?PAGE=windows2000.•The latest BIOS for Intel motherboards can be downloaded from/support/motherboards/desktop/•The latest Intel® Application Accelerator can be downloaded from/support/chipsets/iaa/2.1 Run Procedure Common to All Standard Benchmarks and TestsThis section outlines the run procedure recommended for all benchmarks:•Always start with a clean, formatted hard disk.•Install Windows*XP from the original operating system CD.•Immediately after installing the Windows*XP operating system, install the latest INF files to allow the operating system to recognize the chipset and all the components on the motherboard. This step iscritical to ensure that AGP4X and fast writes are enabled and functional. The INF file can bedownloaded from /design/software/drivers/platform/inf.htm. For further details, please visit /support/chipsets/storagedrivers/ultraATA/.•One can use several publicly available utility based on CPUID/RDTSC instructions to check to make sure that APG4X and fast writes are enabled. Example, WCPUID utility available at http://www.h-.•Install the Intel® Application Accelerator by downloading from:/support/chipsets/iaa/•Download and Install the nVidia graphics reference driver from:/•Make sure the system has at least a 10GB hard drive with 250MB free space.•In the Control Panel, set the display to 1024x768 resolution and 32-bit color mode at 75Hz refresh rate.•In the Control Panel, double click on Display, click on the Settings tab, click the Advanced button, click the GeForce3 tab, click the Additional Properties button, click the OpenGL settings tab and change the Vertical Sync setting to “Always Off.” This prevents the graphics card from having to wait for thevertical refresh of the monitor.•Turning off Visual Effects: Right click on My Computer on your desktop, click on the Advanced Tab and click on the Settings button in the performance section, Click the Visual Effects Tab, choose Custom and uncheck all the boxes. Click OK. Having visual effects on is known to decrease performance across all platforms.•Disable System Restore: Right click on My Computer on your desktop, click on the System Restore Tab, check the box called Turn off System Restore. Click ok. The System Restore captures the state of the system at any given time and stores the information on the hard disk. Having System Restore On,increases the run to run variation on most benchmarks.•Disable Windows Update: Right click on My Computer on your desktop, click on the Automatic Updates Tab, click the option to “Turn off automatic updating, I want to update my computer manually.”Click OK. It is important to turn this option off because the window may come to the foreground duringa benchmark run which may cause the benchmark to fail.•In the Control Panel, double click on Display, click on the Settings tab, click the Screen Saver tab, select (None) in the Screen Saver option. Click on the Power button, click on the Power Schemes tab, and change the power schemes to “Always On,” change the Turn off monitor option to Never. Click on theHibernate Tab, and uncheck the Enable hibernation box. Click Ok. It is important that screen savers and hibernate do not occur during a benchmark run because they may cause benchmarks to fail.•Install the required benchmark from its CD according to the directions provided by the benchmark vendor (or let the “Auto run” feature start the installation program automatically). Be sure to copy the files to the hard drive by checking the box that says “Copy support files to hard drive” when prompted.After the benchmark installation is complete and the system is ready for evaluation, use the Shut Down command on the Start menu to Shut Down and Restart the systemChapter 3Procedure for Evaluating Pentium® 4 Processor PerformanceThe following is a procedure for evaluating Pentium 4 processor performance using XMPEG* software with DivX* 5.02 for transcoding an MPEG-2 stream into the DivX format.Run this test on a Pentium 4 processor system running Windows XP.3.0 Installing XMPEG4.5 and DivX5.02:1Before proceeding, follow the steps outlined in section 2.1, “Run Procedure Common to All Standard Benchmarks and Tests”.2Download and install DivX 5.02 from /.3Reboot your system.4Download the file Xmpeg.4.5.exe from /xmpeg_index.asp and save it to your desktop.5Double Click on the Xmpeg.4.5.exe icon on your desktop.6Extract the contents to folder called XMPEG on your desktop.7Double Click on the XMPEG folder on your desktop.8Double Click on the XMPEG.exe icon910Click on the green box with the arrow in the Welcome dialog.1112Click on File -> Open Media13In the File Name box of the Open window, type in the location of your MPEG-2 test file.14Click Open.15You will be asked to perform a “performance & quality” benchmark.1617Click OK.18The program will remain unresponsive until the test is complete.19You should see your video when the preliminary test is complete.20Exit the XMPEG* program.21Reboot your system.3.1 Running XMPEG4.5 with DivX*5.02:22Double Click on the XMPEG folder on your desktop.23Double Click on the XMPEG.exe icon2425Click on File -> Open Media26In the File Name box of the Open window, type in the location of your MPEG-2 test file. 27Click Open.28Click on Options-> Output Format Options2930You will see the “AVI Plugin” dialog.31Click on the video codec selection box and select DivX Pro 5.02 Codec.3233The DivX* Codec properties box will come up. Click on the Advanced Parameters tab. 34In the Performance/quality selection box, make sure the “Fastest” setting is selected.3536Click OK.37Click on the green arrow box in the “AVI Plugin” dialog.38Click on Options-> Output Project Options (Export Movie Settings)3940In the “Options” window click on the Audio tab.41Click Don’t process audio.42Click on the Post Processing tab.43Click on YV12 in the Format selection area.4445Click OK.46Click on Options-> Output Project Options (Export Movie Settings)4748Click on the General tab.49Click on the Overlay (Automatic for YUV2 or YV12) box in the “Miscellaneous” section. Make sure this box is unchecked.5051Click OK.52Click on Run -> Start Conversion5354Read the fps value in the bottom left corner until the processing progress bar goes to 100%.5556Write down the last fps value you see when the progress bar goes to 100%57This is your XMPEG*/DivX* frame rate in frames per second transcoding from MPEG-2 to MPEG-4.58 A higher frame rate means better performance.To test again, delete the output file c:\Output Video File.avi, reboot your system, and repeat the procedure from step 22 onwards.GERMANY, Intel GmbHDornacher Strasse 185622 Feldkirchen/ MuenchenTel: +49 89/99143-0HONG KONG, Intel Semiconductor Ltd.32/F Two Pacific Place, 88 Queensway, CentralTel: +852 2844-4555CANADA, Intel Semiconductor of Canada, Ltd.190 Attwell Drive, Suite 500Rexdale, Ontario M9W 6H8Tel: +416 675-2438BRAZIL, Intel Semicondutores do BrasilCentro Empresarial Nações Unidas - Edifício Torre Oeste Av. das Nações Unidas, 12.901 - 18o. andar - Brooklin Novo 04578.000 São Paulo - S.P. – BrasilTel: +55-11-5505-2296。

ELECTRONIC GIANT EG8542芯片用户手册通用型CMOS轨到轨运放芯片通用型CMOS轨到轨运放芯片版本变更记录通用型CMOS轨到轨运放芯片目录1. 特点 (4)2. 描述 (4)3. 应用领域 (4)4. 引脚 (5)4.1. 引脚定义 (5)4.2. 引脚描述 (5)5. 结构框图 (6)6. 电气特性 (7)6.1 极限参数 (7)6.2 典型参数 (7)7. 应用设计 (9)7.1陷波滤波器 (9)7.2比较器功能 (10)7.3光电二极管应用 (11)8. 封装尺寸 (12)8.1 SOP8封装尺寸 (12)通用型CMOS轨到轨运放芯片EG8542芯片用户手册V1.01. 特点⏹单电源供电：2.7 V至5.5 V⏹低电源电流：每个放大器45 uA⏹低输入电流：4 pA⏹宽带宽：1 MHz⏹单位增益稳定⏹轨到轨输入和输出2. 描述EG8542是一款低工作电流、单电源供电、1 MHz带宽及轨到轨输入与输出的双路运放。

轨到轨输入与输出便于设计人员在单电源系统中实现ASIC缓冲。

EG8542经过优化设计,可以在较低电源电压时保持高增益,因而能够用于有源滤波器和增益级。

EG8542具有极低的输入偏置电流,可用于积分器、光电二极管放大器、压电传感器以及其它具有较高源阻抗的应用。

每路放大器的电源电流仅为45uA,非常适合电池供电应用。

EG8542的额定温度范围为-40℃至+125℃扩展工业温度范围。

EG8542提供8引脚SOIC表面贴装封装。

3. 应用领域⏹ASIC输入或输出放大器⏹压电传感器放大器⏹移动通信⏹便携式系统⏹传感器接口⏹医疗仪器⏹音频输出通用型CMOS轨到轨运放芯片4. 引脚4.1. 引脚定义图4-1. EG8542管脚定义4.2. 引脚描述通用型CMOS 轨到轨运放芯片5. 结构框图GND图5-1. EG8542结构框图通用型CMOS轨到轨运放芯片6. 电气特性6.1 极限参数注：超出所列的极限参数可能导致芯片内部永久性损坏，在极限的条件长时间运行会影响芯片的可靠性。