verilog- HDL实现流水灯
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用verilog实现流水灯
module flow_deng(
input wire pin_clk_in,
input wire pin_rest_n ,
input wire [1:0] pin_ctrl,
output reg [7:0] pin_led_out
);
wire clk ;
reg [31: 0] counter32;
//fen ping
always @ (posedge pin_clk_in or negedge pin_rest_n) begin
if(pin_rest_n==1'b0) begin
counter32 <= 32'b0;
end
else begin
counter32 <= counter32+1'b1;
end
end
assign clk = counter32[3] ; //16 fen pin
reg [4:0] state;
parameter [4:0] IDLE =5'b0_0001;
parameter [4:0] RIGHT =5'b0_0010;
parameter [4:0] LEFT =5'b0_0100;
parameter [4:0] DOUB_LEFT =5'b0_1000;
parameter [4:0] ERROR =5'b1_0000;
reg [4:0] cur_sta;
always @ (posedge clk or negedge pin_rest_n) begin
if(pin_rest_n==1'b0) begin
state <= IDLE ;
end
else begin
case (state)
IDLE : begin
if (pin_ctrl==2'b00) begin
state <= LEFT ;
end
else if (pin_ctrl==2'b01) begin state <= RIGHT ;
end
else if (pin_ctrl==2'b10) begin
state <= DOUB_LEFT ;
end
else begin
state <= ERROR ;
end
end
LEFT : begin
if (pin_ctrl==2'b00) begin
state <= LEFT ;
end
else if (pin_ctrl==2'b01) begin
state <= RIGHT ;
end
else if (pin_ctrl==2'b10) begin
state <= DOUB_LEFT ;
end
else begin
state <= ERROR ;
end
end
RIGHT : begin
if (pin_ctrl==2'b00) begin
state <= LEFT ;
end
else if (pin_ctrl==2'b01) begin
state <= RIGHT ;
end
else if (pin_ctrl==2'b10) begin
state <= DOUB_LEFT ;
end
else begin
state <= ERROR ;
end
end
DOUB_LEFT : begin
if (pin_ctrl==2'b00) begin
state <= LEFT ;
end else if (pin_ctrl==2'b01) begin
state <= RIGHT ;
end
else if (pin_ctrl==2'b10) begin
state <= DOUB_LEFT ;
end
else begin
state <= ERROR ;
end
end
ERROR : begin
if (pin_ctrl==2'b00) begin
state <= LEFT ;
end
else if (pin_ctrl==2'b01) begin
state <= RIGHT ;
end
else if (pin_ctrl==2'b10) begin
state <= DOUB_LEFT ;
end
else begin
state <= ERROR ;
end
end
default: state <= IDLE ;
endcase
end
end
always @ (posedge clk or negedge pin_rest_n) begin
if (pin_rest_n == 1'b0) begin
pin_led_out[7:0]<=8'b0000_0000 ;
end
else begin
case (state)
IDLE : begin
pin_led_out [7:0] <=8'b0000_0000 ;
end
LEFT : begin
if
((pin_led_out[0]+pin_led_out[1]+pin_led_out[2]+pin_led_out[3]+pin_led_out[4]+pin_led_out[5]+pin_led_out[6]+pin_led_out[7])!=8'd1 ) begin
pin_led_out[7:0] <= 8'b0000_0001;
end
else begin
pin_led_out[7:1] <= pin_led_out[6:0];
pin_led_out[0] <= pin_led_out[7];
end
end
RIGHT : begin
if((pin_led_out[0]+pin_led_out[1]+pin_led_out[2]+pin_led_out[3]+pin_led_out[4]+pin_led_out[5]+pin_led_out[6]+pin_led_out[7])!=8'd1 ) begin
