2SB649L-B-AB3-R中文资料

UNISONIC TECHNOLOGIES CO., LTD2SD669/ANPN SILICON TRANSISTORBIPOLAR POWER GENERAL PURPOSE TRANSISTORAPPLICATIONS* Low frequency power amplifier complementary pair with UTC 2SB649/A*Pb-free plating product number: 2SD669L/2SD669ALORDERING INFORMATIONOrder Number Pin AssignmentNormal Lead Free Plating Package1 2 3 Packing 2SD669-x-AA3-R 2SD669L-x-AA3-R SOT-223 B C E Tape Reel2SD669-x-AB3-R 2SD669L-x-AB3-R SOT-89 B C E Tape Reel 2SD669-x-T60-K 2SD669L-x-T60-K TO-126 E C B Bulk 2SD669-x-T6C-R 2SD669L-x-T6C-R TO-126C E C B Bulk 2SD669-x-T92-B 2SD669L-x-T92-B TO-92 E C B Tape Box 2SD669-x-T92-K 2SD669L-x-T92-K TO-92 E C B Bulk 2SD669-x-T9N-B 2SD669L-x-T9N-B TO-92NL E C B Tape Box 2SD669-x-T9N-K 2SD669L-x-T9N-K TO-92NL E C B Bulk 2SD669-x-T9N-R 2SD669L-x-T9N-R TO-92NL E C B Tape Reel 2SD669-x-TM3-T 2SD669L-x-TM3-T TO-251 E C B Tube 2SD669-x-TN3-R 2SD669L-x-TN3-R TO-252 B C E Tape Reel 2SD669-x-TN3-T 2SD669L-x-TN3-T TO-252 B C ETubeORDERING INFORMATION(Cont.)Order Number Pin AssignmentNormalLead Free Plating Package1 2 3 Packing 2SD669A-x-AA3-R 2SD669AL-x-AA3-R SOT-223 B C E Tape Reel2SD669A-x-AB3-R 2SD669AL-x-AB3-R SOT-89 B C E Tape Reel 2SD669A-x-T60-K 2SD669AL-x-T60-K TO-126 E C B Bulk 2SD669A-x-T6C-R 2SD669AL-x-T6C-R TO-126C E C B Bulk 2SD669A-x-T92-B 2SD669AL-x-T92-B TO-92 E C B Tape Box 2SD669A-x-T92-K 2SD669AL-x-T92-K TO-92 E C B Bulk 2SD669A-x-T9N-B 2SD669AL-x-T9N-B TO-92NL E C B Tape Box 2SD669A-x-T9N-K 2SD669AL-x-T9N-K TO-92NL E C B Bulk 2SD669A-x-T9N-R 2SD669AL-x-T9N-R TO-92NL E C B Tape Reel 2SD669A-x-TM3-T 2SD669AL-x-TM3-T TO-251 E C B Tube 2SD669A-x-TN3-R 2SD669AL-x-TN3-R TO-252 B C E Tape Reel 2SD669A-x-TN3-T 2SD669AL-x-TN3-T TO-252 B C E TubeABSOLUTE MAXIMUM RATING (Ta=25℃, unless otherwise specified)PARAMETER SYMBOL RATINGS UNITCollector-Base Voltage V CBO 180 V2SD669 120Collector-Emitter Voltage 2SD669A V CEO 160VEmitter-Base Voltage V EBO 5 V Collector Current I C 1.5 A Collector Peak Current l C(PEAK) 3 A Collector Power Dissipation SOT-223 0.5 WCollector Power Dissipation TO-126 P D1 W Junction Temperature T J +150Storage Temperature T STG -40 ~ +150Note Absolute maximum ratings are those values beyond which the device could be permanently damaged.Absolute maximum ratings are stress ratings only and functional device operation is not implied.ELECTRICAL CHARACTERISTICS (Ta=25℃, unless otherwise specified)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITCollector to Base Breakdown Voltage BV CBO I C =1mA, I E =0 180 V 2SD669 120Collector to Emitter Breakdown Voltage 2SD669A BV CEO I C =10mA, R BE =∞ 160 VEmitter to Base Breakdown Voltage BV EBO I E =1mA, I C =0 5 V Collector Cut-off Current I CBO V CB =160V, I E =0 10 µAh FE1 V CE =5V, I C =150mA (Note) 60 320DC Current Gainh FE2 V CE =5V, I C =500mA (Note)30 Collector-Emitter Saturation Voltage V CE(SAT)I C =600mA, I B =50mA (Note) 1 V Base-Emitter Voltage V BE V CE =5V, I C =150mA (Note) 1.5 V Current Gain Bandwidth Product f T V CE =5V, I C =150mA (Note) 140 MHz Output Capacitance C ob V CB =10V, I E =0, f=1MHz 14 pF Note: Pulse test.CLASSIFICATION OF h FE1RANK B C DRANGE 60-120 100-200 160-320TYPICAL CHARACTERISTICS1501001502002503001310301003001,0003,000Collector C urrent, I C (mA)D C C u r r e n t T r a n s f e r R a t i o , h F EDC Current Transfer Ratio vs. Collector CurrentCollector to Emitter Saturation Voltagevs. Collector Current 1310301003001,000Collector C urrent, I C (mA)0.20.40.60.81.01.2C o l l e c t o r t o e m i t t e r s a t u r a ti o n v o l t a g e , V C E (S A T ) (V)1310301003001,00000.20.40.60.81.01.2Collector C urrent, I C (mA)Base to Emitter Saturation Voltagevs. Collector Current B a s e t o E m i t t e r S a t u r a t i o nV o l t a g e , V B E (S A T ) (V )10301003001,000Collector Current,I C (mA)04080120160200240G a i n B a n d w i d t h P r o d u c t , f T (M H z )Gain Bandwidth Product vs. Collector Current151********225102050100200Collector to Base Voltage, V CB (V)Collector Output Capacitance vs. Collector to Base VoltageC o l l e c t o r O u t p u t C a p a c i t a n c e ,C o b (p F )Area of Safe OperationCollector to Emitter Voltage, V CE (V)131010030030C o l l e c t o r C u r r e n t , I C (A )TYPICAL CHARACTERISTICS(Cont.)Base to Emitter Voltage , V BE (V)0.20.40.60.8 1.0125102050100200500Typical Transfer CharacteristicsC o l l e c t o r C u r r e n t , I C (m A )。

BL24C02AT24C0224C022K串行EEPROMBL24C02/BL24C04/BL24C08/BL24C16 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Two-wire Serial EEPROMFeaturesTwo-wire Serial InterfaceV CC = 1.8V to 5.5VBi-directional Data Transfer ProtocolInternally OrganizedBL24C02, 256 X 8 (2K bits)BL24C04, 512 X 8 (4K bits)BL24C08, 1024 X 8 (8K bits)BL24C16, 2048 X 8 (16K bits)1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write ModesSelf-timed Write Cycle (5 ms max)1 Million Write Cycles guaranteed Data Retention > 100 Years Operating Temperature: -40℃ to +85℃8-lead PDIP, 8-lead SOP and 8-lead TSSOP PackagesDescriptionBL24C02/BL24C04/BL24C08/BL24C16 provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The BL24C02/BL24C04/BL24C08/BL24C16 is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial interface.Pin DescriptionsBlock DiagramDEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the BL24C02. Eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).The BL24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground.The BL24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bussystem. The A0 and A1 pins are no connects and can be connected to ground.The BL24C16 does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects and can be connected to ground.SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices.SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.WRITE PROTECT (WP): The BL24C02/BL24C04/BL24C08/BL24C16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following Table 2.Part of the Array ProtectedWP Pin Status:BL24C02 BL 24C04 BL 24C08 BL 24C16At V CC Full (2K)ArrayFull (4K)ArrayFull (8K)ArrayFull (16K) ArrayAt GND Normal Read/Write OperationsMemory OrganizationBL24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing.BL24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing.BL24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing.BL24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16Krequires an 11-bit data word address for random word addressing.Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see to Figure 2 on page 4).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 on page 4).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received eachword. This happens during the ninth clock cycle. STANDBY MODE: The K24C02/K24C04/K24C08/K24C16 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operationsMEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1. Clock up to 9 cycles.2. Look for SDA high in each cycle while SCL is high.3. Create a start condition.Device AddressingThe 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 on page 7).The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hardwired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. TheA0 pin is no connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 5 on page 7).PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 6 on page 7).The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted tothe EEPROM, the data word address will "roll over" and previous datawill be overwritten.ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 7 on page 8).Read OperationsRANDOM READ: A random read requires a "dummy" bytewrite sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 8).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9 on page 8).Electrical CharacteristicsAC Electrical CharacteristicsBus TimingWrite Cycle TimingPackage Information8-lead PDIP Outline DimensionsMILLIMETER SYMBOLMIN NOM MAX A 3.60 3.80 4.00 A2 3.10 3.30 3.50 b 0.44 - 0.53B1 1.52BSCc 0.25 - 0.31c1 0.24 0.25 0.26 D 9.05 9.25 9.45E1 6.15 6.35 6.55 e 2.54BSCeA 7.62BSCL 3.00 - -MILLIMETER MIN NOM MAX A - - 1.77A1 0.08 0.18 0.28b 0.44 - 0.53c 0.21 - 0.26D 4.70 4.90 5.10E 5.80 6.00 6.20 E1 3.70 3.90 4.10 e 1.27BSCΘ 0 - 8°SYMBOL MILLIMETER MIN NOM MAXA - - 1.20A1 0.05 - 0.15 A2 0.90 1.00 1.05 A3 0.34 0.44 0.54b 0.20 - 0.28b1 0.20 0.22 0.24c 0.10 - 0.19c1 0.10 0.13 0.15D 2.83 2.93 3.03E 6.20 6.40 6.60 E1 4.30 4.40 4.50 e 0.65BSC L 0.45 0.60 0.75 L1 1.00REF L2 0.25BSC R 0.09 - - R1 0.09 - -S 0.20 - - Θ1 0° - 8° Θ2 10° 12° 14° Θ3 10° 12° 14°。

第一学期期中考试初一英语试卷本试卷分第Ⅰ卷客观题（59分）和第Ⅱ卷主观题（71分）两部分，满分130分，考试时间l00分钟。

注意：请同学们将第Ⅰ卷答案填涂在答题卡上，将第Ⅱ卷答案填在答案卷上。

第Ⅰ卷客观题（三大题，共59分）一、听力选择（共20分）A. 听对话回答问题本部分共有10道小题，每小题你将听到一段对话，每段对话听两遍。

听完后，请你从题中所给的A、B、C三个选项中选出最佳选项。

( ) 1. What’s Linda’s favourite sport?A. B. C.( ) 2. What’s the weather like today?A. B. C.( ) 3. What is Jim’s uncle?A. B. C.( ) 4. How does the girl’s brother go to school?A. B. C.( ) 5. What’s her telephone nu mber?A. 84351978B. 84561968C. 83561958 ( ) 6. What’s the girl’s name?A. She’s Jill.B. She’s Sally.C. She’s Millie.( ) 7. Can Sandy make a model plane?A. No, she can’t.B. Yes, she can.C. I don’t know.( ) 8. What’s Sim on doing now?A. He is doing his homework.B. He is reading in his room.C. He is watching TV.( ) 9. Where is Mary at the moment?A. In the classroom.B.In the teachers’ office.C.At home. ( ) 10. How many apples are there on the table?A. 12.B. 22.C. 10.B. 听对话和短文回答问题你将听到一段对话和两篇短文，各听两遍。

BDTIC /ATMELTwo-wire SerialEEPROM256K (32,768 x 8)25279C–SEEPR–3/09AT24C256BFigure 1-1.Block Diagram 1.Absolute Maximum Ratings*Operating Temperature .....................................− 55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature ........................................− 65°C to +150°C Voltage on Any Pinwith Respect to Ground .......................................− 1.0V to +7.0V Maximum Operating Voltage..........................................6.25V DC Output Current........................................................5.0 mA35279C–SEEPR–3/09AT24C256B2.Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices.When the pins are hardwired, as many as eight 256K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 9.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capaci-tive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhib-ited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.3.Memory OrganizationAT24C256B, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64bytes each. Random word addressing requires a 15-bit data word address.Note:1.This parameter is characterized and is not 100% tested.Table 3-1.Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, SCL)6pFV IN = 0V45279C–SEEPR–3/09AT24C256BNotes:1.V IL min and V IH max are reference only and are not tested.Table 3-2.DC CharacteristicsApplicable over recommended operating range from: T AI = − 40°C to +85°C, V CC = +1.8V to +5.5V (unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.85.5V I CC1Supply Current V CC = 5.0V READ at 400 kHz 1.0 2.0mA I CC2Supply Current V CC = 5.0V WRITE at 400 kHz 2.0 3.0mA I SB1Standby Current (1.8V option)V CC = 1.8V V IN = V CC or V SS1.0µA V CC = 5.5V 6.0µA I LI Input Leakage Current V CC = 5.0V V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage Current V CC = 5.0V V OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)− 0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low LevelV CC = 1.8VI OL = 0.15 mA0.2V55279C–SEEPR–3/09AT24C256BNotes:1.This parameter is ensured by characterization and is not 100% tested.2.AC measurement conditions:R L (connects to V CC ): 1.3 k Ω (2.5V, 5.5V), 10 k Ω (1.8V)Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall times: ≤ 50 nsInput and output timing reference voltages: 0.5 V CCTable 3-3.AC Characteristics (Industrial Temperature)Applicable over recommended operating range from T AI = − 40°C to +85°C, V CC = +1.8V to +5.5V, CL = 100 pF (unless oth-erwise noted). Test conditions are listed in Note 2.Symbol Parameter1.8-volt2.5, 5.0-volt Units MinMax MinMax f SCL Clock Frequency, SCL 4001000kHz t LOW Clock Pulse Width Low 1.30.4µs t HIGH Clock Pulse Width High 0.60.4µs t i Noise Suppression Time (1)10050ns t AA Clock Low to Data Out Valid 0.050.90.050.55µs t BUF Time the bus must be free before a new transmission can start (1) 1.30.5µs t HD.STA Start Hold Time 0.60.25µs t SU.STA Start Set-up Time 0.60.25µs t HD.DAT Data In Hold Time 00µs t SU.DAT Data In Set-up Time 100100ns t R Inputs Rise Time (1)0.30.3µs t F Inputs Fall Time (1)300100ns t SU.STO Stop Set-up Time 0.60.25µs t DH Data Out Hold Time 5050ns t WRWrite Cycle Time 55ms Endurance (1)25°C, Page Mode, 3.3V1,000,000Write Cycles65279C–SEEPR–3/09AT24C256B4.Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4-1).Data changes during SCL high periods will indicate a start or stop condition as defined below.Figure 4-1.Data ValiditySTART CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 4-2).Figure 4-2.Start and Stop DefinitionSTOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-ure 4-2).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word.STANDBY MODE: The AT24C256B features a low-power standby mode that is enabled uponpower-up and after the receipt of the stop bit and the completion of any internal operations.75279C–SEEPR–3/09AT24C256BSOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9cycles, (c) create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps have been completed.Figure 4-3.Software ResetFigure 4-4.Bus TimingFigure 4-5.Write Cycle TimingNote:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.85279C–SEEPR–3/09AT24C256BFigure 4-6.Output Acknowledge95279C–SEEPR–3/09AT24C256B5.Device AddressingThe 256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5-1). The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all two-wire EEPROM devices.Figure 5-1.Device AddressThe next three bits are the A2, A1, A0 device address bits to allow as many as eight devices onthe same bus. These bits must compare to their corresponding hardwired input pins. The A2,A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/write operation select bit. A read operation is ini-tiated if this bit is high, and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made,the device will return to a standby state.DATA SECURITY: The AT24C256B has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at V CC.105279C–SEEPR–3/09AT24C256B6.Write OperationsBYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a microcontroller, must then terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6-1).Figure 6-1.Byte WriteNote:* = DON’T CARE bitPAGE WRITE: The 256K EEPROM is capable of 64-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must termi-nate the page write sequence with a stop condition (see Figure 6-2).Figure 6-2.Page WriteNote:* = DON’T CARE bitThe data word address lower six bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the fol-lowing byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond witha “0”, allowing the read or write sequence to continue.115279C–SEEPR–3/09AT24C256B7.Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations:current address read, random address read, and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over”during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 7-1).Figure 7-1.Current Address ReadRANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 7-2).Figure 7-2.Random ReadNote:*= DON’T CARE bit125279C–SEEPR–3/09AT24C256BSEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 7-3).Figure 7-3.Sequential Read135279C–SEEPR–3/09AT24C256B8.AT24C256B Ordering CodesNotes:1.“-B” denotes bulk.2.“-T” denotes tape and reel. SOIC = 4K per reel. TSSOP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K per reel.3.Available in tape & reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Pleasecontact Serial Interface Marketing.Ordering CodeVoltage Package Operation RangeAT24C256B-PU (Bulk Form Only)AT24C256BN-SH-B (1) (NiPdAu Lead Finish)AT24C256BN-SH-T (2) (NiPdAu Lead Finish)AT24C256BW-SH-B (1) (NiPdAu Lead Finish)AT24C256BW-SH-T (2) (NiPdAu Lead Finish)AT24C256B-TH-B (1) (NiPdAu Lead Finish)AT24C256B-TH-T (2) (NiPdAu Lead Finish)AT24C256BY7-YH-T (2) (NiPdAu Lead Finish)AT24C256BU2-UU-T (2) 1.81.81.81.81.81.81.81.81.88P38S18S18S28S28A28A28Y78U2-1Lead-free/Halogen-free Industrial Temperature (−40°C to 85°C)AT24C256B-W-11 1.8Die SaleIndustrial Temperature (−40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)8S28-lead, 0.200” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)8U2-18-ball, die Ball Grid Array Package (dBGA2)8A28-lead, 4.40 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y78-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)Options−1.8Low-voltage (1.8V to 5.5V)145279C–SEEPR–3/09AT24C256B9.Part Marking Scheme 8-PDIP8-SOICTOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L U Y W W 9: 2009 3: 2013:: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 E B 152 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom MarkTOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L H Y W W 9: 2009 3: 2013:: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 E B 152 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom Mark155279C–SEEPR–3/09AT24C256B8-TSSOP8-Ultra Thin SAPTOP MARKPin 1 Indicator (Dot)Y = SEAL YEAR WW = SEAL WEEK |6: 2006 0: 2010 02 = Week 2 |---|---|---|---| 7: 2007 1: 2011 04 = Week 4 * H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 E B 1 50 = Week 50 |---|---|---|---|---| 52 = Week 52BOTTOM MARKXX = Country of Origin |---|---|---|---|---|---|---| X X|---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 IndicatorTOP MARKSeal Year| Seal Week Y = SEAL YEARWW = SEAL WEEK | | |6: 2006 0: 2010 02 = Week 2 |---|---|---|---|---|---|---|---| 7: 2007 1: 2011 04 = Week 4 A T M L H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 E B 150 = Week 50 |---|---|---|---|---|---|---|---| 52 = Week 52Lot Number|---|---|---|---|---|---|---|---| * |Pin 1 Indicator (Dot)165279C–SEEPR–3/09AT24C256BdBGA2TOP MARKLINE 1-------> 2EBU LINE 2-------> YMTC|<-- Pin 1 This CornerY = ONE DIGIT YEAR CODE 4: 2004 7: 20075: 2005 8: 20086: 2006 9: 2009M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY " " """"""" J = OCTOBER K = NOVEMBER L = DECEMBERTC = TRACE CODE175279C–SEEPR–3/09AT24C256B10.Packaging Information 8P3 – PDIP185279C–SEEPR–3/09AT24C256B8S1 – JEDEC SOIC195279C–SEEPR–3/09AT24C256B205279C–SEEPR–3/09AT24C256B8U2-1 – dBGA2215279C–SEEPR–3/09AT24C256B8A2 – TSSOP225279C–SEEPR–3/09AT24C256B8Y7 – SAP235279C–SEEPR–3/09AT24C256BRevision HistoryDoc. Rev.Date Comments5279C 3/2009Changed the Vcc to 5.5V in the test condition for Isb15279B 3/2008Format changes to document5279A1/2008AT24C256B product with date code 2008 work week 14 (814) or later supports 5Vcc operation Initial document release。

UNISONIC TECHNOLOGIES CO., LTD2SB649/APNP SILICON TRANSISTORBIPOLAR POWER GENERAL PURPOSE TRANSISTORAPPLICATIONS* Low frequency power amplifier complementary pair with UTC 2SB669/A*Pb-free plating product number: 2SB649L/2SB649ALORDERING INFORMATIONOrder Number Pin AssignmentNormal Lead Free Plating Package1 2 3 Packing 2SB649-x-AB3-R 2SB649L-x-AB3-R SOT-89 B C E Tape Reel2SB649-x-T6C-K 2SB649L-x-T6C-K TO-126C E C B Bulk 2SB649-x-T60-K 2SB649L-x-T60-K TO-126 E C B Bulk 2SB649-x-T92-B 2SB649L-x-T92-B TO-92 E C B Tape Box 2SB649-x-T92-K 2SB649L-x-T92-K TO-92 E C B Bulk 2SB649-x-TN3-R 2SB649L-x-TN3-R TO-252 B C E Tape Reel 2SB649-x-TN3-T 2SB649L-x-TN3-T TO-252 B C E Tube 2SB649A-x-AB3-R 2SB649AL-x-AB3-R SOT-89 B C E Tape Reel 2SB649A-x-T6C-K 2SB649AL-x-T6C-K TO-126C E C B Bulk 2SB649A-x-T60-K 2SB649AL-x-T60-K TO-126 E C B Bulk 2SB649A-x-T92-B 2SB649AL-x-T92-B TO-92 E C B Tape Box 2SB649A-x-T92-K 2SB649AL-x-T92-K TO-92 E C B Bulk 2SB649A-x-TN3-R 2SB649AL-x-TN3-R TO-252 B C E Tape Reel 2SB649A-x-TN3-T 2SB649AL-x-TN3-T TO-252 B C ETubeABSOLUTE MAXIMUM RATINGS (Ta=25℃, unless otherwise specified)PARAMETER SYMBOL RATING UNITCollector-Base Voltage V CBO -180 V2SB649-120Collector-Emitter Voltage 2SB649A V CEO -160VEmitter-Base Voltage V EBO -5 V Collector Current I C -1.5 A Collector Peak Current l C(PEAK)-3 ATO-126/TO-126C 1.4 W TO-92 1 WSOT-89 500 mW Collector Power Dissipation TO-252 P D2 WJunction Temperature T J +150 °C Storage Temperature T STG -40 ~ +150 °C Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.Absolute maximum ratings are stress ratings only and functional device operation is not implied.ELECTRICAL CHARACTERISTICS (Ta=25℃, unless otherwise specified)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITCollector to Base Breakdown Voltage BV CBO I C =-1mA, I E =0 -180 V 2SB649 -120Collector to Emitter Breakdown Voltage 2SB649A BV CEO I C =-10mA, R BE =∞-160 V Emitter to Base Breakdown Voltage BV EBO I E =-1mA, I C =0 -5 V Collector Cut-off Current I CBO V CB =-160V, I E =0 -10µAh FE1 V CE =-5V, I C =-150mA (note) 60 3202SB649 h FE2 V CE =-5V, I C =-500mA (note) 30h FE1 V CE =-5V, I C =-150mA (note) 60 200DC Current Gain2SB649A h FE2 V CE =-5V, I C =-500mA (note) 30Collector-Emitter Saturation Voltage V CE(SAT)Ic=-600mA, I B =-50mA -1 V Base-Emitter Voltage V BE V CE =-5V, I C =-150mA -1.5V Current Gain Bandwidth Product f T V CE =-5V,I C =-150mA 140 MHz Output Capacitance Cob V CB =-10V, I E =0, f=1MHz 27 pF Note: Pulse test.CLASSIFICATION OF h FERANK B C D RANGE 60-120 100-200 160-320TYPICAL CHARACTERISTICS=2WC oll ec to rCu r r e nt ,I C(A)C o l l e c t o r C u r r e n t , I C (m A )1310301003001,00000.20.40.60.81.01.2Collector Current, I C (mA)Base to Emitter Saturation Voltagevs. Collector Current B a s e t o E m i t t e r S a t u r a t i o n V o l t a g e , V B E (S A T ) (V )10301003001,000Collector Current, I C (mA)04080120160200240G a i n B a n d w i d t h P r o d u c t , f T (M H z )Gain Bandwidth Product vs. Collector Current V Ta=25TYPICAL CHARACTERISTICS(Cont.)-1-10-30-100-325102050100200Collector to Base Voltage, V CB (V)Collector Output Capacitance vs. Collector to Base VoltageC o l l e c t o r Ou tp ut C a p ac i t an ce ,C o b (p F )C o l l e c t o r C u r r e n t , I C (A )。

三氧化二锑母粒
HX-Sb
一、产品特点
由于三氧化二锑粒径细微，粘度大，粉尘漂浮严重，对生产区域带来极大的污染和浪费，苏州市海翔塑业有限公司应客户之所求，采用先进的设备，完全密闭的生产工艺，及其合理的配方和技术，使之加工成系列三氧化二锑母粒HX-Sb，且含量超过90%以上，可等量替代粉体三氧化二锑，阻燃效果不降低，与各类热塑性树脂相溶性好。

本系列母粒还完全避免了操作工人因接触三氧化二锑粉尘过敏而导致皮肤奇痒的问题，符合欧盟的ROHS环保要求。

与树脂均匀混合后便可直接挤出或注塑加工，简单易使用。

二、具体使用建议
本系列三氧化二锑母粒HX-Sb在任意需要阻燃的橡胶、塑料中使用，且与粉状三氧化二锑等量替换，不改变阻燃效果。

一般建议按（3-6%）比例添加，即可达到UL-94V0级。

四、ROHS环保指标
五、友情提示
1.由于不同的产品，厚度、工艺等的差异，本母料的添加比例也不一样，因此，批量生产前须做好小试。

同时，要保持生产场所的通风良好。

2.以上实验测试典型数据仅供参考，不作为正式质保凭证。

3.三氧化二锑母粒也可根据客户不同要求定制相应配方方案，定制生产。

Micron Parallel NOR Flash Embedded Memory (P30-65nm)JS28F256P30B/TFx, RC28F256P30B/TFx, PC28F256P30B/TFx,RD48F4400P0VBQEx, RC48F4400P0VB0Ex,PC48F4400P0VB0Ex, PF48F4000P0ZB/TQExFeatures•High performance–100ns initial access for Easy BGA–110ns initial access for TSOP–25ns 16-word asychronous page read mode–52 MHz (Easy BGA) with zero WAIT states and 17ns clock-to-data output synchronous burstread mode–4-, 8-, 16-, and continuous word options for burst mode–Buffered enhanced factory programming (BEFP) at 2 MB/s (TYP) using a 512-word buffer– 1.8V buffered programming at 1.14 MB/s (TYP) using a 512-word buffer•Architecture–MLC: highest density at lowest cost–Asymmetrically blocked architecture–Four 32KB parameter blocks: top or bottom con-figuration–128KB main blocks–Blank check to verify an erased block•Voltage and power–V CC (core) voltage: 1.7V to 2.0V–V CCQ (I/O) voltage: 1.7V to 3.6V–Standy current: 65µA (TYP) for 256Mb–52 MHz continuous synchronous read current: 21mA (TYP), 24mA (MAX)•Security–One-time programmable register: 64 OTP bits, programmed with unique information from Mi-cron; 2112 OTP bits available for customer pro-gramming–Absolute write protection: V PP = V SS–Power-transition erase/program lockout–Individual zero-latency block locking–Individual block lock-down–Password access•Software–25μs (TYP) program suspend–25μs (TYP) erase suspend–Flash Data Integrator optimized–Basic command set and extended function Inter-face (EFI) command set compatible–Common flash interface•Density and Packaging–56-lead TSOP package (256Mb only)–64-ball Easy BGA package (256Mb, 512Mb)–QUAD+ and SCSP packages (256Mb, 512Mb)–16-bit wide data bus•Quality and reliabilty–JESD47 compliant–Operating temperature: –40°C to +85°C–Minimum 100,000 ERASE cycles per block–65nm process technologyStatus RegisterRead Status RegisterTo read the status register, issue the READ STATUS REGISTER command at any address.Status register information is available at the address that the READ STATUS REGISTER,WORD PROGRAM, or BLOCK ERASE command is issued to. Status register data is auto-matically made available following a word program, block erase, or block lock com-mand sequence. Reads from the device after any of these command sequences will out-put the devices status until another valid command is written (e.g. READ ARRAY com-mand).The status register is read using single asynchronous mode or synchronous burst modereads. Status register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. Inasynchronous mode, the falling edge of OE# or CE# (whichever occurs first) updatesand latches the status register contents. However, when reading the status register insynchronous burst mode, CE# or ADV# must be toggled to update status data.The device write status bit (SR7) provides the overall status of the device. SR[6:1]present status and error information about the PROGRAM, ERASE, SUSPEND, V PP, andBLOCK LOCK operations.Note: Reading the status register is a nonarray READ operation. When the operation oc-curs in asynchronous page mode, only the first data is valid and all subsequent data areundefined. When the operation occurs in synchronous burst mode, the same data wordrequested will be output on successive clock edges until the burst length requirementsare satisfied.Table 16: Status Register DescriptionNotes: 1.Default value = 0x80.2.Always clear the status register prior to resuming ERASE operations. This eliminates sta-tus register ambiguity when issuing commands during ERASE SUSPEND. If a commandsequence error occurs during an ERASE SUSPEND, the status register contains the com-mand sequence error status (SR[7,5,4] set). When the ERASE operation resumes and fin-ishes, possible errors during the operation cannot be detected via the status register be-cause it contains the previous error status.3.When bits 5:4 indicate a PROGRAM/ERASE operation error, either a CLEAR STATUS REG-ISTER 50h) or a RESET command must be issued with a 15µs delay.Clear Status RegisterThe CLEAR STATUS REGISTER command clears the status register. It functions inde-pendently of V PP. The device sets and clears SR[7,6,2], but it sets bits SR[5:3,1] withoutclearing them. The status register should be cleared before starting a command se-quence to avoid any ambiguity. A device reset also clears the status register.Configuration RegisterRead Configuration RegisterThe read configuration register (RCR) is a 16-bit read/write register used to select busread mode (synchronous or asynchronous) and to configure device synchronous burstread characteristics. To modify RCR settings, use the CONFIGURE READ CONFIGURA-TION REGISTER command. RCR contents can be examined using the READ DEVICEIDENTIFIER command and then reading from offset 0x05. On power-up or exit from re-set, the RCR defaults to asynchronous mode. RCR bits are described in more detail be-low.Note: Reading the configuration register is a nonarray READ operation. When the oper-ation occurs in asynchronous page mode, only the first data is valid, and all subsequentdata are undefined. When the operation occurs in synchronous burst mode, the sameword of data requested will be output on successive clock edges until the burst lengthrequirements are satisfied.Table 17: Read Configuration RegisterRead ModeThe read mode (RM) bit selects synchronous burst mode or asynchronous page modeoperation for the device. When the RM bit is set, asynchronous page mode is selected(default). When RM is cleared, synchronous burst mode is selected.Latency CountThe latency count (LC) bits tell the device how many clock cycles must elapse from therising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until thefirst valid data word is driven to DQ[15:0]. The input clock frequency is used to deter-mine this value. The First Access Latency Count figure shows the data output latency fordifferent LC settings.Figure 13: First Access Latency CountCLK [C]Address [A]ADV# [V]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]Note: 1.First Access Latency Count Calculation:•1 / CLK frequency = CLK period (ns)•n x (CLK period) ≥t AVQV (ns) – t CHQV (ns)•Latency Count = n。

第一册仪表常用数据手册第一章常用计量单位和单位换算1m=100cm=1000mm=106μm 1mm=0.03937in=39.37mils(密耳)1in=25.4mm 1m2=10000cm21t=1000kg=106g 1工程大气压（at）=1公斤力/厘米24 密度单位和单位换算密度：单位体积某物质的质量。

公式ρ=mvρ-物质的密度 m-物质的质量 v-质量为m的物质的体积单位为kg/m3 ,根据需要也可用g/m3表示1kg/m3=0.001g/cm3 1g/cm3=1000kg/m35浓度单位和单位换算气体浓度的表示方法：有摩尔分数、体积分数、质量浓度、质量分数、物质的量浓度、质量摩尔浓度等。

在线分析其体重浓度的表示方法有以下四种。

摩尔分数：组分B的物质的量与混合气体中各组分物质的量的总和之比。

常用单位%mol。

体积分数：组分B的体积V B与混合气体中各组分体积的总和之比。

常用单位%mol。

质量浓度：组分气体B的质量m与混合气体的体积V之比。

常用单位有kg/m3,g/m3,mg/m3质量分数：组分气体B的质量mb与气体中各组分的质量总和之比。

气体浓度单位换算绝对含量-mg/m3体积百万分含量—ppmVol 质量百万分含量—ppmWt6湿度单位和单位换算湿度：把气体中水蒸汽的含量定义为湿度。

露点：在一个大气压下，水蒸气量达到饱和时的温度称为露点温度，简称露点。

用℃表示。

霜点：当水蒸汽的湿度低于0℃时，水蒸气在一个平面上结成霜的温度第二章图形符号第三章防火、防爆、防毒、外壳防护等级1中国对爆炸性危险场所的划分爆炸性气体按其危险程度的大小划分为0、1、2三个级别；爆炸性粉尘危险场所划分为10、11两个级别国家对爆炸性危险场所的划分2中国电气防爆标志的构成分为五个部分A 防爆总标志EX 表示该设备为防爆电气设备B 防爆型式表明该设备采用何种措施进行防爆仪表防爆型式选择如下0区—只能选ia型和专为0区设计的S型1区—可选除n型以外的其他型式，但s型是指专为1区设计的s型2区—所有防爆型式均可选用C 防爆设备类别分为两大类Ⅰ为煤矿井下用电气设备，Ⅱ为工厂用电气设备D 防爆级别分为A、B、C三级，说明Ⅱ类电气设备防爆能力的强弱E 温度组别分为T1~T6六组，说明该设备的最高表明温度允许值在IEC标准和国际中，使用IP代码表示外壳的防护等级。

Table 2: MCP Part Number InformationNote: 1.The last digit is assigned randomly to cover packaging media, features, or other specific configuration infor-mation. Sample part number: RC48F4400P0VB0E*Table 3: Discrete and MCP Part CombinationsSignal DescriptionsTable 7: TSOP and Easy BGA Signal DescriptionsTable 7: TSOP and Easy BGA Signal Descriptions (Continued)Table 8: QUAD+ SCSP Signal DescriptionsTable 8: QUAD+ SCSP Signal Descriptions (Continued)One-Time Programmable RegistersRead OTP RegistersThe device contains 17 OTP registers that can be used to implement system security measures and/or device identification. Each OTP register can be individually locked.The first 128-bit OTP register is comprised of two 64-bit (8-word) segments. The lower 64-bit segment is preprogrammed at the Micron factory with a unique 64-bit number.The upper 64-bit segment, as well as the other sixteen 128-bit OTP registers, are ers can program them as needed. Once programmed, users can also lock the OTP register(s) to prevent additional bit programming (see the OTP Register Map figure be-low).The OTP registers contain OTP bits; when programmed, PR bits cannot be erased. Each OTP register can be accessed multiple times to program individual bits, as long as the register remains unlocked.Each OTP register has an associated lock register bit. When a lock register bit is pro-grammed, the associated OTP register can only be read; it can no longer be program-med. Additionally, because the lock register bits themselves are OTP , when program-med, they cannot be erased. Therefore, when an OTP register is locked, it cannot be un-locked.The OTP registers can be read from an OTP-RA address. To read the OTP register, a READ DEVICE IDENTIFIER command is issued at an OTP-RA address to place the de-vice in the read device identifier state. Next, a READ operation is performed using the address offset corresponding to the register to be read. The Device Identifier Informa-tion table shows the address offsets of the OTP registers and lock registers. PR data is read 16 bits at a time.256Mb and 512Mb (256Mb/256Mb), P30-65nm One-Time Programmable Registers。