© 2007 Xilinx, Inc. All Rights Reserved
Course Outline
Day 2
The course consists of the following modules:
• EDK Overview Lab 1: Simple Hardware Design • Hardware Design • Hardware Design Using EDK Lab 2: Adding IP to a Hardware Design • System Debug Lab 3: Writing Basic Software Applications Lab 4: HW/SW System Debug
Course Objectives
After completing this course, you will be able to:
• Describe general FPGA architectures • Understand the ISE processes as they relate to the FPGA Design Flow steps • Create and debug HDL designs • Configure FPGAs and verify hardware operation
• Perform an on-chip hardware/software co-verification
– Debug using the GNU Debugger and Chipscope-Pro
© 2007 Xilinx, Inc. All Rights Reserved
Course Outline
Xilinx FPGA Fundamental ISE And EDK