CDLL5534C中文资料
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常见的文件后缀名ACA Microsoft的代理使用的角色文档acf系统管理配置acm音频压缩管理驱动程序,为Windows系统提供各种声音格式的编码和解码功能aif声音文件,支持压缩,可以使用Windows Media Player和QuickTime Player播放AIF音频文件,使用Windows Media Player播放AIFC音频文件,使用Windows Media Player播放AIFF音频文件,使用Windows Media Player播放ani动画光标文件扩展名,例如动画沙漏。
ans ASCII字符图形动画文件arc一种较早的压缩文件,可以使用WinZip,WinRAR,PKARC等软件打开arj压缩文件。
可以使用WinZip,WinRAR,PKARC等软件打开asf微软的媒体播放器支持的视频流,可以使用Windows Media Player播放asp微软的视频流文件,可以使用Windows Media Player打开asp微软提出的Active Server Page,是服务器端脚本,常用于大型网站开发,支持数据库连接,类似PHP。
可以使用Visual InterDev编写,是目前的大热门asx Windows Media 媒体文件的快捷方式au是Internet中常用的声音文件格式,多由Sun工作站创建,可使用软件Waveform Hold and Modify 播放。
Netscape Navigator中的LiveAudio也可以播放.au文件avi一种使用Microsoft RIFF规范的Windows多媒体文件格式,用于存储声音和移动的图片bak备份文件,一般是被自动或是通过命令创建的辅助文件,它包含某个文件的最近一个版本,并且具有于该文件相同的文件名bas Basic 语言源程序文件,可编译成可执行文件,目前使用Basic开发系统的是Visual Basicbat批处理文件,在MS-DOS中,.bat文件是可执行文件,有一系列命令构成,其中可以包含对其他程序的调用bbs电子告示板系统文章信息文件bfc Windows的公文包文件bin二进制文件,其用途依系统或应用而定bmp Bitmap位图文件,这是微软公司开发Paint的自身格式,可以被多种Windows和Windows NT平台及许多应用程序支持,支持32位颜色,用于为Windows界面创建图标的资源文件格式。
system32下系统文件解释大全C:\WINDOWS\system32:12520437.cpx ...代码页转换表.12520850.cpx ... 代码页转换表.6to4svc.dll ....在IP4网络上提供IPv6 连接的服务aaaamon.dll ....Aaaa Monitor Dllacledit.dll ....访问控制列表编辑器ac3filter.cpl ..ac3filter 控制面板扩展属于我所安装用于看电影的AC3Filter 编解码器.ahui.exe .......应用程序兼容用户界面ALSNDMGR.CPL ...Realtek AC97 音频控制面板我用RTLCPL.EXE (Realtek 音频控制面板) 作为代替.amcompat.tlb ...ansi.sys .......apcups.dll .....APC 智能提供程序APPEND.EXE .....(Append). 允许应用程序在当前文件夹中打开指定目录中的数据文件. 此工具源于MS-DOS 5.0.asctrls.ocx ....Active Setup 控件AT.EXE .........(AT). 用于设置在指定时间和日期执行任务. 需要运行计划任务服务.atkctrs.dll ....Windows NT AppleTalk 性能计数器dllATMADM.EXE .....(ATM). ATM 呼叫管理器.auditusr.exe ... 设置每用户审核策略atmfd.dll ......Windows NT OpenType/Type 1 字体驱动atmlib.dll .....Windows NT OpenType/Type 1 API 库.atmpvcno.dll ...Atm Epvc Install DLLatrace.dll .....Async Trace DLLATTRIB.EXE .....(文件属性). 显示或更改文件属性(只读, 存档, 隐藏, 或系统).AUTOCONV.EXE ...(自动转换). 用于将FAT 分区格式转为NTFS.autodisc.dll ...Windows AutoDiscovery API , 自动收取邮件AUTOFMT.EXE ...(自动格式化). 用于转换文件系统的工具.AUTOLFN.EXE ....长文件名转换工具. 用于DOS模式下. 能够自动将长文件名转换为8.3 格式.-------------------------------------------------------batt.dll .......电池类安装程序如果你使用笔记本的话, 那么设备管理器会需要这个文件来访问你的电池属性.-------------------------------------------------------bidispl.dll ....Bidispl DLLbios1.rom ......bios4.rom ......bitsprx2.dll ...后台智能传输服务代理bitsprx3.dll ... 后台智能传输服务2.0 代理blastcln.exe ...Blaster/Nachi 移除工具BOOTOK.EXE .....(启动确认). 在一次成功地登录系统之后, ―上次正确的配置‖ 会用它保存配置参数.BOOTVRFY.EXE ...(启动验证). ―上次正确的配置‖ 会用它验证一个引导选择.browsewm.dll ...BrowseWM Playerbthci.dll ......蓝牙类别安装程序bthprops.cpl ...蓝牙控制面板小程序(无线公司)bthserv.dll ....蓝牙支持服务btpanui.dll ....蓝牙PAN 用户界面-------------------------------------------------------capesnpn.dll ...Microsoft 证书模板管理扩展ccfgnt.dll .....Internet 配置库certmgr.dll ....证书管理工具certmgr.msc .... <-- 证书管理控制台.cdosys.dll .....Microsoft CDO for Windows Librarycdfview.dll ....频道定义文件文件查看器cewmdm.dll .....Windows CE WMDM 服务提供程序CHARMAP.EXE ....(字符映射表). 用于显示某个字体所能显示的所有字符.-------------------------------------------------------以下文件没有用批处理文件删除. 需要手动删除它们:cdplayer.exe.manifestlogonui.exe.manifestncpa.cpl.manifestnwc.cpl.manifestsapi.cpl.manifestWindowsLogon.manifest-------------------------------------------------------ChCfg.exe ......?? (我拿它没办法.) .......用于更换系统代码页的工具cmos.ram .......CHKNTFS.EXE ....(NTFS 驱动器检查工具). 用于检查NTFS 分区的完整性.ckcnv.exe ......Cookie 转换工具cnvfat.dll .....FAT 文件系统转换工具DLLcomcat.dll .....Microsoft C 运行时库文件comctl32.ocx ...Windows 通用控件ActiveX 控件DLLCOMP.EXE .......(比较). 用于比较两个文件之间的差别.compatUI.dll patUI Modulecompobj.dll ....OLE 2.1 16/32 互用性-------------------------------------------------------compstui.dll ...通用属性表用户界面DLL没有这个文件的话, 你可能无法访问打印机属性或是打印机参数.-------------------------------------------------------CONFIG.TMP .....confmsp.dll ....Microsoft IP 会议媒体服务提供程序CONIME.EXE .....(输入法控制台). 这个输入法控制台用于转换字符.console.dll ....控制面板控制台小程序control.exe ....Windows 控制面板(这个不是实际上的控制面板.)CONVERT.EXE ....(转换). 用于将分区格式从FAT 转为NTFS 以及从NTFSv4 转为NTFSv5.corpol.dll .....Microsoft COM 运行时执行引擎country.sys ....cryptdlg.dll ...Microsoft 通用证书对话框cryptext.dll ...加密外壳扩展cryptnet.dll ...加密网络相关APICSCRIPT.EXE ....(基于命令行的脚本宿主). 能让你通过命令行运行VBScript 和JScript 脚本.ctfmon.exe ....CTF 加载器(在你安装手写识别, 语音识别, 输入法编辑器之后, 就会在任务栏上显示一个语言栏. 还有, 如果你添加了第二种语言或是键盘布局, 也会导致显示语言栏的.)ctl3d32.dll ....Ctl3D 3D Windows 控件ctl3dv2.dll ....Ctl3D 3D Windows NT(WOW) 控件Dcache.bin .....dbgeng.dll .....符号调试引擎DEBUG.EXE ......(调试程序). 命令行下的调试工具.DEFRAG.EXE .....(磁盘碎片整理). 用于整理磁盘碎片的命令行工具.desktop.ini ....DFRGFAT.EXE ....(FAT 碎片整理工具). 用于整理FAT 分区上的磁盘碎片.dgnet.dll ......Dgnet Moduledgrpsetu.dll ...Digi RealPort® 驱动升级dgsetup.dll ....DGSETUP DLLdhcpmon.dll ....DHCP Monitor Dlldhcpsapi.dll ...DHCP Server API Stub DLLDIANTZ.EXE .....(Cab 打包程序). 用于将文件打包为.cab 文件.digest.dll .....Digest SSPI 认证包DLLHOST.EXE ....(COM+ 服务器进程). COM+ 进程管理器.DLLHST3G.EXE ...(COM 代替品). 一个COM+ 进程组件.dmconfig.dll ...逻辑磁盘管理器配置库DOSKEY.EXE .....(DOS 键盘). MS-DOS 5.0 键盘输入历史记录器,能提供宏.DOSX.EXE .......(DOS 扩展器). 一个DOS 虚拟机(VDM), 提供标准模式.DRW ATSON.EXE ...(Dr. Watson).16位的程序错误监测和记录工具.DRWTSN32.EXE ...(Dr. Watson 32). 32位的程序错误监测和记录工具.dsauth.dll .....用于服务的DS 认证 .......edit.hlp .......EDLIN.EXE ......(编辑行). 基于DOS 的编辑器.emptyregdb.dat ..encdec.dll .....XDSCodec & Encypter/Decrypter 标识滤镜EqnClass.Dll ...Equinox 多端口串行协同安装程序esent97.dll ....Microsoft(R) Windows NT(TM) 服务器数据库存储引擎esentprf.dll ... 服务器数据库存储性能库esentprf.hxx ...esentprf.ini ...esentutl.exe ... 服务器数据库存储工具EUDCEDIT.EXE ...(私有字符编辑器). 一个造字程序, 可让你创建大约6400 个私有字符. EXE2BIN.EXE ....(Exe to Bin). 基于DOS, 用于将.exe 文件转为.bin 文件. EXPAND.EXE .....(Expand). 用于展开Cab 压缩包中的某些文件.expsrv.dll .....Visual Basic 运行时文件extmgr.dll .....扩展管理器EXTRAC32.EXE ...(CAB 文件提取工具). 用于解压缩Cab 压缩包exts.dll .......调试器扩展FASTOPEN.EXE ...(快速打开). 一个DOS 工具, 用于改善系统性能, 加速访问经常用到的文件.fc.exe .........文件比较工具fe客户端.dll ...Windows NT 文件加..密客户端接口find.exe .......查找字符串(Grep) 的工具findstr.exe .... 查找字符串(QGrep) 的工具FIXMAPI.EXE ....(MAPI 修复工具). 探测并解决(MAPI) 文件出现的问题.fldrclnr.dll ...桌面清理向导fltlib.dll .....筛选库fltMc.exe ......筛选管理器控制程序fontsub.dll ....字体设置DLLFORCEDOS.EXE ...(强制DOS). 强制在Windows XP 下将包含OS/2 和DOS 代码的程序运行在DOS 模式下. .....Disk Format Utility格式化命令fsmgmt.msc .....Microsoft 通用控制台文档(共享文件夹)fsquirt.exe ....(属于蓝牙)fsusd.dll ......摄像头设备DLLFSUTIL.EXE .....(FSUtil). 一个卷管理工具. 重分析点管理和稀疏文件控制FTP.EXE ........(FTP). 命令行模式下的FTP 工具.ftsrch.dll .....Microsoft® 文本搜索g711codc.ax ....Intel G711 CODECgcdef.dll ......游戏控制器的默认表GDI.EXE ........(物理设备接口). 一个核心系统组件, 可以提供Win16 图形设备接口API l库, 以实现向后兼容.gpkrsrc.dll ....Gemplus 加.密服务提供程序资源文件 ...代码页工具 ...h323.tsp .......h323msp.dll ....Microsoft H.323 媒体服务提供程序hccoin.dll B 协同安装程序HELP.EXE .......(帮助). 显示Windows XP 命令的基本常规帮助信息.hidphone.tsp ...hlink.dll ......Microsoft 超链接库hnetmon.dll ....家庭网络监视DLLhnetwiz.dll ....网络安装向导homepage.inf ...hotplug.dll ....用于安全移除硬件, 比如, U 盘HSFCISP2.dll ...HSF 协同安装程序httpapi.dll ....HTTP 协议堆栈APIiccvid.dll .....(Cinepak® Codec) 用于显示'Cinepak' 格式的媒体文件. (非常古老的A.VI 编,解.码格式.)IE4UINIT.EXE ...(IE 安.装工具). IE 5.0 每用户安.装工具.iedkcs32.dll ...Microsoft Internet Explorer 定.制DLLieencode.dll ...Microsoft 字符编码iernonce.dll ...带用户界面的扩展RunOnce 处理库iesetup.dll ....IOD 版本映射ieuinit.inf ....IEXPRESS.EXE ...(自解压和自安装创建程序). 用于创建自解压包或是自.安.装程序包.ifmon.dll ......IF Monitor DLLigmpagnt.dll ...Microsoft IGMP subagentils.dll ........用户位置服务组件模块imeshare.dll ...Microsoft Office IME 共.享属性库inetmib1.dll ...Microsoft MIB-II subagentinitpki.dll ....Microsoft 受信赖的安装和设置input.dll ......(文本输入DLL). 语言和区域设置需要这个文件来显示相关对话框inseng.dll .....(安装引擎). Active Setup 安装引擎, 允许打开或执行cab 文件. 用于控制安装.instcat.sql ....用于安装编录intl.cpl .......区域和语言设置iologmsg.dll ...IO 日志DLLipconf.tsp .....iprop.dll ......OLE 属性集ir32_32.dll ....ir41_32.ax .....Intel Indeo® Video 4.5ir41_qc.dll ....Intel Indeo® 视频快速压缩编码器(文件版本: 4.30.62.2)ir41_qcx.dll ...Intel Indeo®视频快速压缩编码器(文件版本: 4.30.62.2)ir50_32.dll ....Intel Indeo® video 5.10 (文件版本: 5.2562.15.55)ir50_qc.dll ....Intel Indeo® 5.10视频快速压缩编码器(文件版本: 5.0.63.48 )ir50_qcx.dll ...Intel Indeo® 5.10 视频快速压缩编码器(文件版本: 5.0.63.48 )irclass.dll ....Infrared Class 协同安装程序isrdbg32.dll ...ISR 32 位调试引擎ivfsrc.ax ......Intel Indeo® 视频IVF 源滤镜5.10itircl.dll .....Microsoft® InfoTech IR Local DLLitss.dll .......Microsoft® InfoTech 存储系统库文件iyuv_32.dll ....Intel Indeo(R) Video YUV Codec (文件版本: 5.1.2600.2180)jet500.dll .....JET 引擎DLLjgaw400.dll ....JG 音频接口DLL (AOL 文件)jgdw400.dll ....JG ART DLL (AOL 文件)jgmd400.dll ....JG MIDI Player DLL (AOL 文件)jgpl400.dll ....JG ART Player DLL (AOL 文件)jgsd400.dll ....JG ART DLL (AOL 文件)jgsh400.dll ....JG 幻灯片播放器DLL (AOL 文件)jobexec.dll ....Active Setup 任务执行程序joy.cpl ........游戏控制器控制面板小程序jsproxy.dll ....JScript 代理自动配置kd1394.dll .....核心调试程序IEEE 1394 HW Extension DLL .......key01.sys ......keyboard.sys ...keymgr.dll .....存储的用户名和密码kmddsp.tsp .....KRNL386.EXE ....(Kernel 386). 包含了用于Win16 增强模式下的核心Kernel 例程.l3codecp.acm ...MPEG Audio Layer-3 Codec for MSACM (系统默认的MP3 解码器)LABEL.EXE ......(卷标). 用于显示, 编辑, 或更改驱动器的卷标.lanman.drv .....laprxy.dll .....Windows Media Logagent Proxylicmgr10.dll ...ActiveX 许可管理器LIGHTS.EXE .....(Lights). 在Win 9x 下通过监视COM 端口来提供对于调制解调器状态的设置.LNKSTUB.EXE ....(Win95-Winnt 迁移工具). 用于把Windows 95 升级至Windows. ....localui.dll ....本地监视用户界面DLLLOCATOR.EXE ....(Locator). 向Windows XP 的环境添加对于Remote Procedure Calls (RPCs) 的支持.loghours.dll ...计划对话框lpk.dll ........会话注销工具lusrmgr.msc ....lusrmgr.msc = 本地用户和用户组. 无法在Home 版XP上使用这个管理工具. 用于管理电脑上的用户帐号.MAKECAB.EXE ....(Cab 文件创建工具). 用于创建 .cab 压缩包文件.mapi32.dll .....Extended MAPI 1.0 for Windows NTmcastmib.dll ...Microsoft 多播子代理mcd32.dll ......OpenGL MCD 客户端DLLmcdsrv32.dll ...MCD 服务器mchgrcoi.dll ...中级更改器协同安装程序mciavi32.dll ... Windows MCI 视频驱动mciole16.dll ...MCIOLE16 - OLE Handler DLL for MCI Objectsmciole32.dll ...MCI OLE DLLmciwave.dll ....MCI 波形音频驱动mdhcp.dll ......Microsoft MDHCP 客户端COM 接口mdwmdmsp.dll ...用于MDM 驱动的WMDM 服务提供程序驱动MEM.EXE ........(Memory). 一个用于显示当前内存状态的命令行工具.mf3216.dll .....32 位至16 位元文件的转换DLLmfc40.dll ......MFCDLL 共.享库–零售版mfc40u.dll .....MFCDLL 共.享库–零售版mfcsubs.dll ....MSCTFIME.IME ...mgmtapi.dll ....Microsoft SNMP 管理器API (使用WinSNMP)mib.bin ........MIGPWD.EXE .....(迁移dll). 用于Windows 95 至Windows NT 的迁移工具.miglibnt.dll ...NT 迁移支持dllmlang.dat ......mll_hp.dll .....HP 媒体卷标库mll_mtf.dll ....MTF (Microsoft 磁带格式) 媒体卷标库mll_qic.dll ....QIC113媒体卷标库mmdrv.dll ......多媒体核心支持驱动mobsync.dll ....Microsoft 同步管理器MOBSYNC.EXE ....(脱机工作同步程序). 同步脱机网站. .......DOS 命令modex.dll ......ModeX 显示驱动 .......Dos 命令moricons.dll ...Windows NT 安装图标资源库MOUNTVOL.EXE ...(卷加载器). 创建, 列出以及修改你的存储卷加载点.mpg4ds32.ax ....(文件版本: 8.0.0.4487). Microsoft MPEG-4 视频解码器mplay32.exe ....Windows Media Player 5.1 (非常古老的媒体播放器.) MRINFO.EXE .....(多播信息). 用于查询多播路由器接口的命令行工具.msacm.dll ......Microsoft 音频压缩管理器msaatext.dll ... Active Accessibility 文本支持msadds32.ax ....(文件版本: 8.0.0.4487). Windows Media 音频解码器msafd.dll ......Microsoft Windows Sockets 2.0 服务提供程序msapsspc.dll ...32 位平台下的DPA 客户端msaudite.dll ...安全审核事件DLLmscat32.dll ....MSCAT32 Forwarder DLLMSCTFP.dll .....MSCTFP Server DLLmsdadiag.dll ...Microsoft Data Access –内建诊断msdart.dll .....Microsoft Data Access - OLE DB 例行运行时msdatsrc.tlb ...msdtcprf.ini ...msencode.dll ...Microsoft 字符编码器msieftp.dll ....Microsoft Internet Explorer FTP 文件夹外壳扩展msimsg.dll .....Windows® Installer 国际消息mslbui.dll .....msnsspc.dll ....MSN Internet Accessmsobjs.dll .....系统对象审核名称MsPMSNSv.dll ...Microsoft 媒体设备服务提供程序msr2c.dll ......Microsoft Forms DLLmsr2cenu.dll ...Microsoft Forms DLLmsratelc.dll ...Internet 分级和本地用户管理DLLmsrating.dll ...Internet 分级和本地用户管理DLLmsrclr40.dll ...Microsoft Jet公文包调解程序msrd2x40.dll ...Microsoft (R) Red ISAMmsrd3x40.dll ...Microsoft (R) Red ISAMmsrecr40.dll ...Microsoft Jet公文包调解程序资源库msrepl40.dll ...Microsoft 复制库msrle32.dll ....Microsoft RLE 压缩器msscds32.ax ....(文件版本: 8.0.0.4487). Microsoft 屏幕视频解压器msscript.ocx ...Microsoft (r) 脚本控件mssign32.dll ...Microsoft 受信赖签证APIsmssip32.dll ....MSSIP32 Forwarder DLLmstime.dll .....Microsoft (R) 用于HTML 的定时交互多媒体扩展msswch.dll .....(屏幕键盘). 用于msswchx.exe.msswchx.exe ....msswchx (属于屏幕键盘.)msutb.dll ......MSUTB 服务器DLL-------------------------------------------------------msvbvm50.dll ...Visual Basic 虚拟机(文件版本: 5.2.82.44)这是个老版本的VB 虚拟机. msvbvm60.dll (也是VB 虚拟机)文件版本: 6.0.96.90-------------------------------------------------------msvcirt.dll ....Windows NT IOStreams DLLmsvcp50.dll ....Microsoft (R) C++ 运行时库文件msvcrt20.dll ...Microsoft® C运行时库文件msvcrt40.dll ...VC 4.x CRT DLL (向后兼容msvcrt.dll)msvideo.dll ....Microsoft Video for Windows DLLmsxml.dll ......XML OM for Win32msxml2.dll .....XML OM for Win32msxml2r.dll ....XML2 资源文件msxmlr.dll .....XML 资源文件msyuv.dll ......Microsoft UYVY 视频解压器mtxoci.dll .....对于Oracle 的Microsoft 数据库支持DLLmydocs.dll .....我的文档文件夹用户界面ncxpnt.dll ork (不是Network) 安装向导支持DLLndptsp.tsp .....NET.EXE ........(Network). 用于管理, 配置和查看与网络相关的信息, 例如net use, net print, net user, 等等.net.hlp ........NET1.EXE .......(Network). 与NET.EXE 的功能相同.netapi.dll .....Microsoft 网络动态链接库neth.dll .......网络帮助消息DLLnetplwiz.dll ...映射网络驱动器向导netsetup.cpl ...网络安装向导控制面板小程序NETSETUP.EXE ...(网络安装向导). 通过软盘帮你配置电脑网络.netui0.dll .....NT LM UI Common Code - GUI Classes (文件版本: 5.1.2600.2180)netui1.dll .....NT LM UI Common Code - GUI Classes (文件版本: 5.1.2600.2180)netui2.dll .....NT LM UI Common Code - GUI Classes (文件版本: 5.1.2600.0) <-- 版本要比netui1.dll 老?netrap.dll .....网罗远程管理协议DLL-------------------------------------------------------所有的"noise", "wbcache" 和"wbdbase" 文件(不同语言下的文件) 都可被删除.(它们大都是索引服务用到的文件, 可通过nLite 删除)(下列文件列在了注册表中的这个位置:HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\ContentIndex\Language )noise.chs <<简体中文noise.cht <<繁体中文noise.datnoise.deu <<...注意: ...DEU = 这是德国的noise.engnoise.enu <<英文noise.esn < noise.fra < noise.ita < noise.nld < noise.sve < noise.thawbcache.deuwbcache.enu <<英文wbcache.esn < wbcache.fra < wbcache.ita < wbcache.nld < wbcache.sve <wbdbase.deuwbdbase.enu <<英文wbdbase.esn < wbdbase.fra < wbdbase.ita < wbdbase.nld < wbdbase.sve <-------------------------------------------------------npptools.dll ...NPP 工具助手DLLnscompat.tlb ...NSLOOKUP.EXE ...(域名服务器查寻). 用于显示DNS 服务器的诊断和统计信息.ntlsapi.dll ....Microsoft® 许可服务器接口DLLntdos404.sys ...ntdos411.sys ...ntdos412.sys ...ntdos804.sys ...ntimage.gif ....ntio404.sys ....ntio411.sys ....ntio412.sys ....ntio804.sys ....ntlanman.dll ...Microsoft® 局域网管理器ntlanui.dll ....ntlanui2.dll ...网络对象外壳用户界面NTSD.EXE .......(符号调试器). 系统出问题时, 这个疑难解答工具就会详细列出系统状态.ntsdexts.dll ... Windows 2000 下的符号调试工具nwprovau.dll ...用于NetWare 提供程序和认证的客户端服务NTVDM.EXE ......(NT DOS 虚拟机). 提供用于DOS 程序和Windows-on-Windows (WOW—支持Win16) 的虚拟机.ntvdmd.dll .....NTVDMD.DLLoakley.dll .....Oakley 键盘管理器objsel.dll .....对象挑选对话框occache.dll ....对象控件查看器OSUNINST.EXE ....(卸载工具). 用于卸载Windows XP, 并将其还原到升级前使用的Windows 操作系统. 可在安全模式下运行于命令行模式.-------------------------------------------------------oembios.bin ....oembios.dat ....oembios.sig ....删掉oembios.sig 的话, 可能会导致系统栏提示"还剩下X 天用于激活Windows". 这个可能会发生在OEM 版Windows 中. 如果出现了这种情况, 请将其放回.-------------------------------------------------------ole2.dll .......OLE 2.1 16/32相互操作库ole2disp.dll ...OLE 2.1 16/32相互操作库ole2nls.dll ....OLE 2.1 16/32相互操作库oleprn.dll .....Oleprn DLLp2p.dll ........点对点群p2pgasvc.dll ... 点对点群认证服务p2pgraph.dll ... 点对点图形p2pnetsh.dll ... 点对点NetSh 助手p2psvc.dll ..... 点对点服务PACKAGER.EXE ...(Object Packager). 用于在文档中创建嵌入数据的图标链接.panmap.dll .....PANOSE(tm) 字体映射器paqsp.dll ......PaqSP Modulepautoenr.dll ...自动注册DLLpcl.sep ........PENTNT.EXE .....(NT Pentium 测试工具). 一个用于检测你的系统是否有Pentium 浮点运算错误的命令行工具. (我还把在―性能‖ 中的快捷方式删掉了).pifmgr.dll .....Windows NT PIF 管理器图标资源库pjlmon.dll .....PJL 语言监视器plustab.dll ....效果控制面板扩展pmspl.dll ......Microsoft 局域网管理器2.1 网络动态polstore.dll …策略存储dllpowercfg.exe ...电源设置命令行工具pnrpnsp.dll ....PNRP 命名空间提供程序proctexe.ocx ...Intel 程序纹理prodspec.ini ...PROGMAN.EXE ....(程序管理器). 可用于替换Windows XP 资源管理器的外壳. 它的主界面基于Windows 3.x, Windows for Workgroups, 和Windows NT 3.51.pschdcnt.h .....pschdprf.dll ...Microsoft® Windows(TM) PSched 性能监视器pschdprf.ini ...pscript.sep ....psnppagn.dll ... NPPAgent对象的DCOM 代理pubprn.vbs .....proquota.exe ...ProQuota 能让你设置一个用户配置文件的最大大小.PROXYCFG.EXE ...(代理配置工具). 一个用于查看和更改你当前代理设置的命令行工具.qmgrprxy.dll ...后台智能传输服务代理qosname.dll ....Microsoft Windows GetQosByName 服务提供程序query.dll ......目录索引工具DLLrdpdd.dll ......RDP 显示驱动RECOVER.EXE ....(还原). 一个用于从有问题的驱动器中还原可读数据的命令行工具.REDIR.EXE ......(Redirector).Win16 网络重定向工具.remotesp.tsp...REG.EXE ........(注册表控制台). 一个用于查询和修改注册表的命令行工具.REGEDT32.EXE ...(注册表编辑器). 一个32 位的注册表工具, 可用于设置注册表中相关项值的安全权限. 在Windows XP 中, 原本带有更多功能的regedt32.exe 已被合并regedit.exe 中了. Regedt32.exe 现在只不过相当于一个快捷方式. 如果你运行regedt32.exe, 那么系统就会自动启动regedit.exeregsvc.dll .....远程注册表服务REGWIZ.EXE .....(注册向导). 令注册XP 的过程自动化.regwizc.dll .... 注册向导的相关模块rend.dll .......Microsoft 集合控件REPLACE.EXE ....(Replace). 用于替换文件的命令行工具.rnr20.dll ......Windows Socket2 命名空间DLLroutetab.dll ...Microsoft 路由表DLLrpcns4.dll .....Remote Procedure Call 命名服务客户端rsmps.dll ......RSM 代理存根rsaci.rat ...... <-- 属于msrating.dll. 你可在以下位置查看分级选项: Internet 选项-> 内容-> 分级审查-> 启用RTCSHARE.EXE ...(RTC 程序共享). 实时时钟组件.rtipxmib.dll ...Microsoft Router IPX MIB subagentRUNAS.EXE ......(运行方式). 这个工具可用一个新用户名和密码执行一个进程. 一般, 可用来在低权限用户登录的系统上以高权限的管理员身份来运行一个程序.safrdm.dll .....Microsoft 帮助中心桌面管理器safrslv.dll ....Microsoft 帮助中心会话处理程序S***EDUMP.EXE ...(转储). 当系统出现STOP 错误时, 可用于将内存中的内容转储为文件.sbe.dll ........DirectShow 流缓冲滤镜sbeio.dll ...... 流缓冲输入输出DLLSC.EXE .........( Windows NT 服务管理). 一个服务管理工具.scrobj.dll .....Windows (r) 脚本组件运行时scrrun.dll .....Microsoft (r) 脚本运行时SDBINST.EXE ....(Installer). AppFix 和AppHelp 安装程序.sendcmsg.dll ....发送控制台消息sdhcinst.dll ...Secure Digital Host 控制器类别控制器sdpblb.dll .....Microsoft Sdpblbsecupd.sig .....security.dll ...安全支持提供程序接口senscfg.dll ....SENS 安装设置工具serialui.dll ...串行端口属性页面setup.bmp ......SETUP.EXE ......(Setup). Windows 安装程序setupdll.dll ...Windows 2000 安装DLLSETVER.EXE .....(设置版本). 用于定义报告给某个应用程序关于DOS 的版本.sfc.exe ........(Windows 2000 系统文件检查工具). 用于验证XP 的文件是否存在以及是否正确.sfc_os.dll ...(Windows 文件保护). 用于保护Windows 的系统文件.sfmapi.dll .....Windows NT Macintosh 文件服务客户端SHARE.EXE ......(Share). 能让两个程序同时使用一个文件的DOS 工具.shellstyle.dll ..Windows 外壳样式资源DllSHMGRATE.EXE ... Windows XP 用户数据转移工具.SHRPUBW.EXE ....(共享文件夹创建工具). 用于在Windows XP 系统上创建共享文件夹.shscrap.dll ....外壳碎片对象句柄SHUTDOWN.EXE ...(远程关机工具). 允许关闭或重启本地或远程电脑.sigtab.dll .....文件完整性设置SIGVERIF.EXE ...(文件签名验证工具). 验证所选文件是否经过认证.simpdata.tlb ....sisbkup.dll ....单实例存储备份支持功能skdll.dll ......序列号SKEYS.EXE ......(序列号). 一个可提供支持序列号功能的系统服务.slayerxp.dll ...‖兼容性‖ 选项卡外壳扩展DLLsmbinst.exe ....系统管理BIOS 驱动安装程序softpub.dll ....Softpub Forwarder DLLSORT.EXE .......(Sort). 用于整理键盘输入并将结果写入一个文件或是显示在屏幕上.spmsg.dll ......Service Pack 消息spnike.dll .....用于Nike 设备的MDM 设备接口spnpinst.exe ...点对点定制安装SPRESTRT.EXE ...重启时还原注册表sprio600.dll ... Rio 600 的MDM 设备接口sprio800.dll ... Rio 800 的MDM 设备接口spxcoins.dll ...Specialix MPS NT 升级协同安装程序srvsvc.dll .....服务器服务DLLsti_ci.dll .....静止图像类别安装程序sti.dll ........ 静止图像设备客户端DLLstimon.exe ..... 静止图像设备监视器storage.dll ....OLE 2.1 16/32 相互操作库strmfilt.dll ...流滤镜库SUBST.EXE ......(虚拟). 可将一个路径虚拟为一个分区.svcpack.dll ....Windows 2000 Service Pack 安装程序SYNCAPP.EXE ....(同步). 公文包用于同步所含文件的工具.synceng.dll ....Windows 公文包引擎syncui.dll .....Windows 公文包资源文件SYSEDIT.EXE .....(系统编辑器). 一个用于打开编辑system.ini, win.ini, config.sys, 和autoexec.bat 的编辑器.sysinv.dll .....Windows 系统清单SYSKEY.EXE .....(Windows XP 帐户数据库管理器). 用于设置Windows XP 帐户数据库的安全特性.sysmon.ocx .....系统监视控件sysprint.sep ...sysprtj.sep ....SYSTRAY.EXE ....(系统栏). 系统栏提供程序. 它能控制任务栏和系统栏. 但是, 没它的话, 也没有什么不正常的地方.t2embed.dll ....t2embedtaskman.exe ....任务管理器(不是平时使用的那个. 平时那个是: "taskmgr.exe")tdc.ocx ........TDC ActiveX 控件TELNET.EXE .....(Telnet). 一个Telnet 客户端, 可用于访问远程Telnet 服务器系统.tftp.exe .......简单文件传输协议应用程序toolhelp.dll ...Windows 调试工具助手库traffic.dll ....Microsoft 网络交通控制1.0 DLL .......将文件夹列为树形结构tsbyuv.dll .....东芝视频解码器typelib.dll ....OLE 2.1 16/32 相互操作库ufat.dll .......FAT 工具DLLumandlg.dll ....UManDlg DLLunimdm.tsp .....unimdmat.dll ...通用调制解调器服务提供程序AT 微型驱动ureg.dll .......注册表工具DLLusbmon.dll .....标准动态打印端口监视器DLLUSER.EXE .......(Windows 用户界面核心组件). 用于保持Win16 的兼容性. 不是一个有效的Win32 应用程序.v7vga.rom .......vbajet32.dll ...Visual Basic 应用程序开发环境- Expression 服务加载器vcdex.dll ......32 位MSCDEX 虚拟设备驱动vdmredir.dll ...DOS 虚拟机网络接口库verifier.dll ...标准应用程序验证提供程序dllVERIFIER.EXE ...(驱动验证管理器). 可用它探测一个驱动的操作是否会导致系统冲突vfpodbc.dll ....vfpodbcvga256.dll .....256 色VGA\SVGA 显示驱动vga64k.dll .....32K/64K 色VGA\SVGA 显示驱动View Channels.scf ..(查看频道).vjoy.dll .......32 位手柄虚拟设备驱动(我没有手柄)w32topl.dll ....Windows NT Topology 维护工具wavemsp.dll ....Microsoft Wave MSPwdl.trm ........webvw.dll ......网页视图外壳扩展库WEXTRACT.EXE ...(Win32 Cab 自解压程序创建工具). 用于提取Cab 压缩包中的文件.wiasf.ax .......WIA 流快照滤镜wifeman.dll ....Windows WIFE 接口核心组件 ........用于保持兼容性win87em.dll ....winbrand.dll ...Windows Branding 资源WINCHAT.EXE ....简单的聊天工具winfax.dll .....Microsoft 传真API 支持DLL (我没有传真机.)winhelp.hlp ....WINHLP32.EXE ...(Windows 帮助). 用于打开帮助文件.WINMSD.EXE .....(Windows XP 诊断工具或是系统信息工具). Windows XP 诊断工具.winnls.dll .....Windows IME 接口核心组件winntbbu.dll ...Windows 安装画面DLLwinoldap.mod ...winshfhc.dll ...文件风险评估winsock.dll ....Windows Socket 16-Bit DLLwinstrm.dll ....Streams DLLwkssvc.dll .....Workstation 服务DLLwmidx.dll ......Windows Media 索引DLLwmiprop.dll ....WDM 动态属性页面协同安装程序wmv8ds32.ax ....(文件版本: 8.0.0.4000). Windows Media 视频解码器V8wmvds32.ax .....Windows Media 视频解码器WOWDEB.EXE .....(WOW 调试程序). WOW 调试程序. Win16 调试助手wowexec.exe ....Windows Win16 程序启动工具wowfax.dll .....Windows 3.1 兼容传真驱动DLLwowfaxui.dll ...Windows 3.1兼容传真驱动DLLWPABALN.EXE ....(Windows 产品激活). Windows 产品激活气球提示器.WRITE.EXE ......写字板, 支持纯文本和RTF 文档.有Word 就不用它了wscntfy.exe ....Windows 安全中心通知程序wscui.cpl ...... 安全中心控制面板小程序WSCRIPT.EXE ....(脚本宿主). 基于Windows 的脚本宿主.wshatm.dll .....Windows 套接层助手DLLwshbth.dll .....Windows套接层助手DLLwshcon.dll .....Microsoft (r) Windows 脚本控制器wshisn.dll .....NWLINK2套接层助手DLLwshnetbs.dll bios Windows套接层助手DLLwshom.ocx ......Windows 脚本宿主运行时库WshRm.dll ......用于PGM 的Windows套接层助手wsnmp32.dll ....Microsoft WinSNMP v2.0 Manager APIxactsrv.dll ....下级API 服务器DLLxcopy.exe ......加强版的复制命令xenroll.dll ....XEnrollxpob2res.dll ...Service Pack 2 OOB 消息350 个没有删除的System32 文件...以及原因............我为什么不删除这些文件是有很多重要原因的, 其中有许多文件要经常用到. 我会把为什么不想删除这些文件的原因列在下面.-------------------------------------------------NVDVD 需要以下文件acelpdec.ax 音频解码器以下是NVDVD 安装的文件:DolbyHph.dll .....杜比耳机引擎license.955200 ...... <-- 在我把这个看起来无害的文件删除之后,当我重启电脑时就会提示内存出错,还会在事件查看器中显示程序错误. 即使我将其放回system32 文件夹中, 错误仍然存在.msxml3a.dll ....XML 资源文件-------------------------------------------------Needed for Regeditaclui.dll .....Security Descriptor Editorclb.dll .....Column List Box-------------------------------------------------重启电脑需要以下文件AUTOCHK.EXE ..(自动检查磁盘). 如果存储卷被标记为杂乱的话(有坏簇, 错误区块, 或是有其它损坏), 那么在WinXP 启动期间就会自动运行这个程序.bootvid.dll .....VGA 启动驱动csseqchk.dll ....CSSeqChkdpcdll.dll ......Dpcdll Modulehal.dll ........(硬件抽象层). 隐藏Windows 应用程序处理硬件问题的复杂性.kdcom.dll .......内核调试程序硬件扩展DLLshgina.dll .....Windows 外壳用户登录<-- 这个文件用于从你的桌面上重启电脑.进一步讲, 一旦你将其删除或是将其从system32 文件夹中移走,那么即使你将其放回, 也照样无法从你的桌面重新启动.USERINIT.EXE ..(用户初始化). 在用户登录之后, 用于确定操作系统的环境.-------------------------------------------------安装Yahoo Messenger 需要以下文件***ICAP32.dll .....***I 捕获类当我安装Yahoo Messenger 时,弹出以下错误对话框:"无法启动这个程序, 因为没有找到***ICAP32.dll. 请安装此文件以解决这个问题."然而, 即使出现了这个消息, 也能成功安装Yahoo Messenger.-------------------------------------------------这些文件属于Windows Media Player 10avifil32.dll .....Microsoft ***I 文件支持库<-- Plus! MP3 Audio Converter LE 需要此文件blackbox.dll ..BlackBox DLLLOGAGENT.EXE ..(Windows Media Player 日志代理). 可记录Windows Media Player 出现的错误.MsPMSP.dll ....Microsoft Media 设备服务提供程序MSSCP.dll .....Windows Media 安全内容提供程序msvfw32.dll ...Microsoft Video for Windows DLLMSWMDM.dll ....Windows Media 设备管理器核心qasf.dll ......DirectShow ASF 支持wmadmod.dll ...Windows Media 音频解码器wmadmoe.dll ...Windows Media 音频编码器/转换器WMASF.DLL ......Windows Media ASF DLLWMDMLOG.dll ...Windows Media 设备管理器日志程序WMDMPS.dll ....Windows Media 设备管理器Proxy Stubwmnetmgr.dll ..Windows Media 网络插件管理器DLLWMP.DLL ........Windows Media Player 核心wmp.ocx ......Windows Media Playerwmpasf.dll ....Windows Media Filter Shimwmpcd.dll .....Windows Media Playerwmpcore.dll ...Windows Media Playerwmpdxm.dll ....Windows Media 6.4 Player ShimWMPLOC.DLL .....Windows Media Playerwmpshell.dll ..Windows Media Player 启动程序wmpui.dll .....Windows Media Playerwmsdmod.dll ...Windows Media 屏幕解码器WMVCORE.DLL ....Windows Media 回放/认证DLLwmvdmod.dll ...Windows Media 视频解码器-------------------------------------------------------NLS 文件= 多国语言资源文件. 字符集转换; 本地语言服务驱动(字体或字体映射). 就我的U.S.English (美国英文) 设置而言, 保留了以下NLS 文件:c_437.nlsc_932.nlsc_936.nls?简体中文代码页c_1250.nlsc_1251.nlsc_1252.nls?ANSI Latin 代码页c_1255.nlsc_20127.nlsc_28591.nlsc_28592.nlsC_28595.NLSc_28605.nlsctype.nlsl_intl.nlslocale.nlssortkey.nlssorttbls.nlsunicode.nls-------------------------------------------------.cab 文件夹cabview.dll ....Cab 文件查看器外壳扩展-------------------------------------------------我需要cards.dll 来玩纸牌游戏cards.dll ......纸牌游戏相关DLL-------------------------------------------------Windows Update 需要以下文件CDM.DLL ........Windows Update CDM StubDCIMAN32.DLL ...DCI 管理器dssenh.dll .....Microsoft Enhanced DSS 和Diffie-Hellman 加.密提供程序iuengine.dll ...Windows Update 控制引擎JSCRIPT.DLL ....Microsoft (r) JScriptlicdll.dll .....Licdll Modulepidgen.dll .....Pid3.0 生成器rasapi32.dll ....远程访问APIrasman.dll ......远程访问连接管理器wshext.dll .....Microsoft (r) Windows 脚本宿主外壳扩展WUAPI.DLL ......Windows Update 客户端APIwuauclt1.exe ...Windows Update 自动更新客户端WUAUCLT.EXE ....(Windows Update). 自动更新客户端wuaucpl.cpl ....自动更新控制面板WUAUENG1.DLL ...Windows Update 自动更新引擎WUCLTUI.DLL ....Windows Update 客户端用户界面插件wupdmgr.exe ....Windows Update 管理器WUWEB.DLL ......Windows Update 网络控件SDBINST.EXE ....(Installer). AppFix 和AppHelp 安装程序. sendcmsg.dll ....发送控制台消息。
Freescale Semiconductor Data Sheet: Technical DataContentsDocument Number: MPC5554Rev. 3.0, 11/2008This document provides electrical specifications, pin assignments, and package diagrams for the MPC5554 microcontroller device. For functional characteristics, refer to the MPC5553/MPC5554 Microcontroller Reference Manual .1OverviewThe MPC5554 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers built on the Power Architecture™ embedded technology. Thisfamily of parts has many new features coupled with high performance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement over the MPC500 family.The host processor core of this device complies with the Power Architecture embedded category that is 100% user-mode compatible (including floating point library) with the original Power PC™ user instruction set architecture (UISA). The embedded architectureenhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 43.1Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 43.2Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . 53.3Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.4EMI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 83.5ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 93.6VRC and POR Electrical Specifications . . . . . . . . . 93.7Power-Up/Down Sequencing. . . . . . . . . . . . . . . . . 103.8DC Electrical Specifications . . . . . . . . . . . . . . . . . 133.9Oscillator and FMPLL Electrical Characteristics . . 203.10eQADC Electrical Characteristics . . . . . . . . . . . . . 223.11H7Fa Flash Memory Electrical Characteristics . . . 233.12AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 243.13AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.1MPC5554 416 PBGA Pinout. . . . . . . . . . . . . . . . . 454.2MPC5554 416-Pin Package Dimensions . . . . . . . 485Revision History for the MPC5554 Data Sheet . . . . . . . 505.1Changes to Revision 2 in Revision 3. . . . . . . . . . . 50MPC5554Microcontroller Data Sheetby:Microcontroller DivisionOverviewThe MPC5500 family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565.The MPC5554 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB) unified cache. The next level in the hierarchy contains the 64-KB on-chip internal SRAM andtwo-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and data. The external bus interface is designed to support most of the standard memories used with the MPC5xx family.The complex input/output timer functions of the MPC5554 are performed by two enhanced time processor unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is programmed using a high-level programming language.The less complex timer functions of the MPC5554 are performed by the enhanced modular input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include edge-aligned and center-aligned PWM.Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and general-purpose input/output (GPIOs) signals.The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC). The 416 package has 40-channels.The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing.Ordering Information2Ordering InformationFigure 1. MPC5500 Family Part Number ExampleUnless noted in this data sheet, all specifications apply from T L to T H .Table 1. Orderable Part NumbersFreescale Part Number 1All devices are PPC5554, rather than MPC5554, until product qualifications are complete. Not all configurations are available in the PPC parts.Package DescriptionSpeed (MHz)Operating Temperature 22The lowest ambient operating temperature is referenced by T L ; the highest ambient operating temperature is referenced by T H.Nominal Max. 3 (f MAX )3Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and132 MHz parts allow for 128MHz system clock +2% FM.Min. (T L )Max.(T H )MPC5554MVR132MPC5554 416 package Lead-free (PbFree)132132 –40° C 125° C MPC5554MVR112112114MPC5554MVR808082MPC5554AVR132132132–55° C 125° C MPC5554MZP132MPC5554 416 packageLeaded (SnPb)132132 –40° C 125° C MPC5554MZP112112114MPC5554MZP808082MPC5554AZP132132132–55° C125° CM PC M 80R Qualification statusCore codeDevice numberTemperature range Package identifierOperating frequency (MHz)T ape and reel status Temperature Range M = –40° C to 125° C A = –55° C to 125° CPackage Identifier ZP = 416PBGA SnPb VR = 416PBGA Pb-freeOperating Frequency 80 = 80 MHz 112 = 112 MHz 132 = 132 MHzTape and Reel Status R2 = Tape and reel (blank) = T raysQualification Status P = Pre qualification M = Fully spec. qualified5554ZP Note: Not all options are available on all devices. Refer to Table 1.2Electrical Characteristics3Electrical CharacteristicsThis section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU.3.1Maximum RatingsTable2. Absolute Maximum Ratings1Spec Characteristic Symbol Min.Max.Unit1 1.5 V core supply voltage 2V DD–0.3 1.7V2Flash program/erase voltage V PP–0.3 6.5V 4Flash read voltage V FLASH–0.3 4.6V 5SRAM standby voltage V STBY–0.3 1.7V 6Clock synthesizer voltage V DDSYN–0.3 4.6V7 3.3 V I/O buffer voltage V DD33–0.3 4.6V8Voltage regulator control input voltage V RC33–0.3 4.6V 9Analog supply voltage (reference to V SSA)V DDA–0.3 5.5V 10I/O supply voltage (fast I/O pads) 3V DDE–0.3 4.6V 11I/O supply voltage (slow and medium I/O pads) 3V DDEH–0.3 6.5V12DC input voltage 4V DDEH powered I/O padsV DDE powered I/O pads V IN–1.0 5–1.0 56.5 64.6 7V13Analog reference high voltage (reference to V RL)V RH–0.3 5.5V 14V SS to V SSA differential voltage V SS – V SSA–0.10.1V 15V DD to V DDA differential voltage V DD – V DDA–V DDA V DD V 16V REF differential voltage V RH – V RL–0.3 5.5V 17V RH to V DDA differential voltage V RH – V DDA–5.5 5.5V 18V RL to V SSA differential voltage V RL – V SSA–0.30.3V 19V DDEH to V DDA differential voltage V DDEH – V DDA–V DDA V DDEH V 20V DDF to V DD differential voltage V DDF – V DD–0.30.3V 21 V RC33 to V DDSYN differential voltage spec has been moved to Table9 DC Electrical Specifications, Spec 43a.22V SSSYN to V SS differential voltage V SSSYN – V SS–0.10.1V 23V RCVSS to V SS differential voltage V RCVSS – V SS–0.10.1V 24Maximum DC digital input current 8(per pin, applies to all digital pins)4I MAXD–22mA25Maximum DC analog input current 9(per pin, applies to all analog pins)I MAXA–33mA26Maximum operating temperature range 10Die junction temperatureT J T L150.0o C 27Storage temperature range T STG–55.0150.0o CElectrical Characteristics3.2Thermal CharacteristicsThe shaded rows in the following table indicate information specific to a four-layer board.28Maximum solder temperature 11Lead free (Pb-free)Leaded (SnPb)T SDR ——260.0245.0oC29Moisture sensitivity level 12MSL—3Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond any of the listed maxima can affect device reliability or cause permanent damage to the device.21.5 V ± 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 o C.3All functional non-supply I/O pins are clamped to V SS and V DDE , or V DDEH .4AC signal overshoot and undershoot of up to ± 2.0 V of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration).5Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met. Keep the negative DC voltage greater than –0.6 V on eTPUB[15] and SINB during the internal power-on reset (POR) state.6Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDEH supplies, if themaximum injection current specification is met (2 mA for all pins) and V DDEH is within the operating voltage specifications.7Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDE supplies, if the maximum injection current specification is met (2 mA for all pins) and V DDE is within the operating voltage specifications.8T otal injection current for all pins (including both digital and analog) must not exceed 25 mA.9T otal injection current for all analog input pins must not exceed 15 mA.10Lifetime operation at these specification limits is not guaranteed.11Moisture sensitivity profile per IPC/JEDEC J-STD-020D.12Moisture sensitivity per JEDEC test method A112.Table 3. MPC5554 Thermal CharacteristicsSpec MPC5554 Thermal CharacteristicSymbol 416 PBGAUnit 1Junction to ambient 1, 2, natural convection (one-layer board)Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.2Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.R θJA 24°C/W 2Junction to ambient 1, 3, natural convection (four-layer board 2s2p)3Per JEDEC JESD51-6 with the board horizontal.R θJA 18°C/W 3Junction to ambient 1, 3 (@200 ft./min., one-layer board)R θJMA 19°C/W 4Junction to ambient 1, 3 (@200 ft./min., four-layer board 2s2p)R θJMA 15°C/W 5Junction to board 4 (four-layer board 2s2p)4Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.R θJB 9°C/W 6Junction to case 55Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.R θJC 5°C/W 7Junction to package top 6, natural convection6Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.ΨJT2°C/WTable 2. Absolute Maximum Ratings 1 (continued)Spec CharacteristicSymbol Min.Max.UnitElectrical Characteristics3.2.1General Notes for Specifications at Maximum Junction Temperature, can be obtained from the equation:An estimation of the device junction temperature, TJT J = T A + (RθJA× P D)where:T A = ambient temperature for the package (o C)RθJA = junction to ambient thermal resistance (o C/W)P D = power dissipation in the package (W)The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:•Construction of the application board (number of planes)•Effective size of the board which cools the component•Quality of the thermal and electrical connections to the planes•Power dissipated by adjacent componentsConnect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:•One oz. (35 micron nominal thickness) internal planes•Components are well separated•Overall power dissipation on the board is less than 0.02 W/cm2The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.Electrical CharacteristicsAt a known board temperature, the junction temperature is estimated using the following equation:T J = T B + (R θJB × P D )where:T J = junction temperature (o C)T B = board temperature at the package perimeter (o C/W)R θJB = junction-to-board thermal resistance (o C/W) per JESD51-8P D = power dissipation in the package (W)When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance:R θJA = R θJC + R θCA where:R θJA = junction-to-ambient thermal resistance (o C/W)R θJC = junction-to-case thermal resistance (o C/W)R θCA = case-to-ambient thermal resistance (o C/W)R θJC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, R θCA . For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required.A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models.To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (ΨJT ) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation:T J = T T + (ΨJT × P D )where:T T = thermocouple temperature on top of the package (o C)ΨJT = thermal characterization parameter (o C/W)P D = power dissipation in the package (W)Electrical CharacteristicsThe thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.References:Semiconductor Equipment and Materials International 3081 Zanker Rd.San Jose, CA., 95134(408) 943-6900MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956.JEDEC specifications are available on the web at .1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.2.G . Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applica-tions,” Electronic Packaging and Production, pp. 53–58, March 1998.3. B. Joiner and V . Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.3.3PackageThe MPC5554 is available in packaged form. Read the package options in Section 2, “Ordering Information.” Refer to Section 4, “Mechanicals,” for pinouts and package drawings.3.4EMI (Electromagnetic Interference) CharacteristicsTable 4. EMI Testing Specifications 1EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554 and applied to the MPC5500 family as generic EMI performance data. Spec CharacteristicMinimum Typical Maximum Unit 1Scan range 0.15—1000MHz 2Operating frequency ——f MAX MHz 3V DD operating voltages— 1.5—V 4V DDSYN , V RC33, V DD33, V FLASH , V DDE operating voltages — 3.3—V 5V PP , V DDEH , V DDA operating voltages — 5.0—V 6Maximum amplitude ——14 232 32Measured with the single-chip EMI program.3Measured with the expanded EMI program.dBuV7Operating temperature——25oCElectrical Characteristics3.5ESD (Electromagnetic Static Discharge) Characteristics3.6Voltage Regulator Controller (V RC ) andPower-On Reset (POR) Electrical SpecificationsThe following table lists the V RC and POR electrical specifications:Table 5. ESD Ratings 1, 21All ESD testing conforms to CDF-AEC-Q100 Stress T est Qualification for Automotive Grade Integrated Circuits.2Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature.Characteristic SymbolValue Unit ESD for human body model (HBM)2000V HBM circuit descriptionR11500ΩC100pFESD for field induced charge model (FDCM)500 (all pins)V 750 (corner pins)Number of pulses per pin:Positive pulses (HBM)Negative pulses (HBM)——11——Interval of pulses—1second Table 6. V RC and POR Electrical SpecificationsSpec CharacteristicSymbol Min.Max.Units 11.5 V(V DD ) POR 1Negated (ramp up)Asserted (ramp down)V POR151.11.1 1.351.35V23.3 V(V DDSYN ) POR 1Asserted (ramp up)Negated (ramp up)Asserted (ramp down)Negated (ramp down)V POR330.02.02.00.00.302.852.850.30V3RESET pin supply (V DDEH6) POR 1, 2Negated (ramp up)Asserted (ramp down) V POR5 2.02.0 2.852.85V 4V RC33 voltageBefore V RC allows the pass transistor to start turning onV TRANS_START 1.0 2.0V 5When V RC allows the passtransistor to completely turn on 3, 4V TRANS_ON 2.02.85V6When the voltage is greater than the voltage at which the V RC keeps the 1.5 V supply in regulation 5, 6V VRC33REG3.0—V – 55o C 711.0—mA Current can be sourced – 40oC 11.0—mA 7by V RCCTL at Tj:25o C I VRCCTL 89.0—mA 150o C7.5—mAElectrical Characteristics3.7Power-Up/Down SequencingPower sequencing between the 1.5 V power supply and V DDSYN or the RESET power supplies is required if using an external 1.5 V power supply with V RC33 tied to ground (GND). To avoid power-sequencing, V RC33 must be powered up within the specified operating range, even if the on-chip voltage regulator controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”Power sequencing requires that V DD33 must reach a certain voltage where the values are read as ones before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33.”Although power sequencing is not required between V RC33 and V DDSYN during power up, V RC33 must not lead V DDSYN by more than 600 mV or lag by more than 100 mV for the V RC stage turn-on to operate within specification. Higher spikes in the emitter current of the pass transistor occur if V RC33 leads or lags V DDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance.8Voltage differential during power up such that:V DD33 can lag V DDSYN or V DDEH6 before V DDSYN and V DDEH6 reach the V POR33 and V POR5 minimums respectively.V DD33_LAG— 1.0V 9Absolute value of slew rate on power supply pins ——50V/ms 10Required gain at Tj:I DD ÷ I VRCCTL (@ f sys = f MAX )6, 8, 9, 10– 55o C 7BET A 1170——– 40o C70——25o C8511——150o C10511500—1The internal POR signals are V POR15, V POR33, and V POR5RESET must remain asserted until the power supplies are within the operating conditions as specified in T able 9 DC Electrical internal POR asserts.2V IL_S (T able 9, Spec15) is guaranteed to scale with V DDEH6 down to V POR5.3Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.4It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.5At peak current for device.6Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal traces/routing from the V RCCTL package signal to the base of the external pass transistor and between the emitter of the pass transistor to the V DD package signals must have a maximum of 100 nH inductance and minimal resistance(less than 1 Ω). V RCCTL must have a nominal 1 μF phase compensation capacitor to ground. V DD must have a 20 μF (nominal) bulk capacitor (greater than 4 μF over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of eight 0.01 μF , two 0.1 μF , and one 1 μF capacitors around the package on the V DD supply signals.7Only available on devices that support -55o C.8I VRCCTL is measured at the following conditions: V DD = 1.35 V , V RC33 = 3.1 V , V VRCCTL = 2.2 V .9Refer to T able 1 for the maximum operating frequency.10Values are based on I DD from high-use applications as explained in the I DD Electrical Specification. 11BET A represents the worst-case external transistor. It is measured on a per-part basis and calculated as (I DD ÷ I VRCCTL ).Table 6. V RC and POR Electrical Specifications (continued)Spec CharacteristicSymbol Min.Max.UnitsFurthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase of the current consumed by V RC33. If V RC33 lags V DDSYN by more than 100 mV , the increase in current consumed can drop V DD low enough to assert the 1.5 V POR again. Oscillations are possible when the 1.5V POR asserts and stops the system clock, causing the voltage on V DD to rise until the 1.5V POR negates again. All oscillations stop when V RC33 is powered sufficiently.When powering down, V RC33 and V DDSYN have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, no delta between V RC33 and V DDSYN is required for the V RC to operate within specification.There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending on which supplies are powered.Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and pad_sh (slow type).The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins during power up.Before exiting the internal POR state, the pins go to a high-impedance state until POR negates. When the internal POR negates, the functional state of the signal during reset applies and the weak-pull devices (up or down) are enabled as defined in the device reference manual. If V DD is too low to correctly propagate the logic signals, the weak-pull devices can pull the signals to V DDE and V DDEH .To avoid this condition, minimize the ramp time of the V DD supply to a time period less than the time required to enable the external circuitry connected to the device outputs.Table 7. Pin Status for Fast Pads During the Power SequenceV DDE V DD33V DD POR Pin Status for Fast Pad Output Driverpad_fc (fast)Low ——Asserted Low V DDE Low Low Asserted High V DDE Low V DD Asserted HighV DDE V DD33Low Asserted High impedance (Hi-Z)V DDE V DD33V DD Asserted Hi-Z V DDEV DD33V DDNegatedFunctionalTable 8. Pin Status for Medium and Slow Pads During the Power SequenceV DDEH V DD POR Pin Status for Medium and Slow Pad Output Driverpad_mh (medium) pad_sh (slow)Low —Asserted LowV DDEH Low Asserted High impedance (Hi-Z)V DDEH V DD Asserted Hi-Z V DDEHV DDNegatedFunctional3.7.1Input Value of Pins During POR Dependent on V DD33When powering up the device, V DD33 must not lag the latest V DDSYN or RESET power pin (V DDEH6) by more than the V DD33 lag specification listed in Table6, spec 8. This avoids accidentally selecting the bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when POR negates. V DD33 can lag V DDSYN or the RESET power pin (V DDEH6), but cannot lag both by more than the V DD33 lag specification. This V DD33 lag specification applies during power up only. V DD33 has no lead or lag requirements when powering down.3.7.2Power-Up Sequence (V RC33 Grounded)The 1.5V V DD power supply must rise to 1.35V before the 3.3V V DDSYN power supply and the RESET power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5V power supply does not begin to operate below the specified operation range lower limit of 1.35V. Because the internal 1.5V POR is disabled, the internal 3.3V POR or the RESET power POR must hold the device in reset. Since they can negate as low as 2.0V, V DD must be within specification before the 3.3V POR and the RESET POR negate.V DDSYNV DD2.0 V1.35 VV DD must reach 1.35 V before V DDSYN and the RESET power reach 2.0 VFigure2. Power-Up Sequence (V RC33 Grounded)3.7.3Power-Down Sequence (V RC33 Grounded)The only requirement for the power-down sequence with V RC33 grounded is if V DD decreases to less than its operating range, V DDSYN or the RESET power must decrease to less than 2.0V before the V DD power increases to its operating range. This ensures that the digital 1.5V logic, which is reset only by an ORed POR and can cause the 1.5V supply to decrease less than its specification value, resets correctly. See Table6, footnote 1.。
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________________________________________________ 1Joseph E. Urban, Arizona State University, Department of Computer Science and Engineering, P.O. Box 875406, Tempe, Arizona, 85287-5406, joseph.urban@ 2Maria A. Reyes, Arizona State University, College of Engineering and Applied Sciences, Po Box 874521, Tempe, Arizona 852189-955, maria@ 3Mary R. Anderson-Rowland, Arizona State University, College of Engineering and Applied Sciences, P.O. Box 875506, Tempe, Arizona 85287-5506, mary.Anderson@MINORITY ENGINEERING PROGRAM COMPUTER BASICS WITH AVISIONJoseph E. Urban 1, Maria A. Reyes 2, and Mary R. Anderson-Rowland 3Abstract - Basic computer skills are necessary for success in an undergraduate engineering degree program. Students who lack basic computer skills are immediately at risk when entering the university campus. This paper describes a one semester, one unit course that provided basic computer skills to minority engineering students during the Fall semester of 2001. Computer applications and software development were the primary topics covered in the course that are discussed in this paper. In addition, there is a description of the manner in which the course was conducted. The paper concludes with an evaluation of the effort and future directions.Index Terms - Minority, Freshmen, Computer SkillsI NTRODUCTIONEntering engineering freshmen are assumed to have basic computer skills. These skills include, at a minimum, word processing, sending and receiving emails, using spreadsheets, and accessing and searching the Internet. Some entering freshmen, however, have had little or no experience with computers. Their home did not have a computer and access to a computer at their school may have been very limited. Many of these students are underrepresented minority students. This situation provided the basis for the development of a unique course for minority engineering students. The pilot course described here represents a work in progress that helped enough of the students that there is a basis to continue to improve the course.It is well known that, in general, enrollment, retention, and graduation rates for underrepresented minority engineering students are lower than for others in engineering, computer science, and construction management. For this reason the Office of Minority Engineering Programs (OMEP, which includes the Minority Engineering Program (MEP) and the outreach program Mathematics, Engineering, Science Achievement (MESA)) in the College of Engineering and Applied Sciences (CEAS) at Arizona State University (ASU) was reestablished in 1993to increase the enrollment, retention, and graduation of these underrepresented minority students. Undergraduate underrepresented minority enrollment has increased from 400 students in Fall 1992 to 752 students in Fall 2001 [1]. Retention has also increased during this time, largely due to a highly successful Minority Engineering Bridge Program conducted for two weeks during the summer before matriculation to the college [2] - [4]. These Bridge students were further supported with a two-unit Academic Success class during their first semester. This class included study skills, time management, and concept building for their mathematics class [5]. The underrepresented minority students in the CEAS were also supported through student chapters of the American Indian Science and Engineering Society (AISES), the National Society of Black Engineers (NSBE), and the Society of Hispanic Professional Engineers (SHPE). The students received additional support from a model collaboration within the minority engineering student societies (CEMS) and later expanded to CEMS/SWE with the addition of the student chapter of the Society of Women Engineers (SWE) [6]. However, one problem still persisted: many of these same students found that they were lacking in the basic computer skills expected of them in the Introduction to Engineering course, as well as introductory computer science courses.Therefore, during the Fall 2001 Semester an MEP Computer Basics pilot course was offered. Nineteen underrepresented students took this one-unit course conducted weekly. Most of the students were also in the two-unit Academic Success class. The students, taught by a Computer Science professor, learned computer basics, including the sending and receiving of email, word processing, spreadsheets, sending files, algorithm development, design reviews, group communication, and web page development. The students were also given a vision of advanced computer science courses and engineering and of computing careers.An evaluation of the course was conducted through a short evaluation done by each of five teams at the end of each class, as well as the end of semester student evaluations of the course and the instructor. This paper describes theclass, the students, the course activities, and an assessment of the short-term overall success of the effort.M INORITY E NGINEERING P ROGRAMSThe OMEP works actively to recruit, to retain, and to graduate historically underrepresented students in the college. This is done through targeted programs in the K-12 system and at the university level [7], [8]. The retention aspects of the program are delivered through the Minority Engineering Program (MEP), which has a dedicated program coordinator. Although the focus of the retention initiatives is centered on the disciplines in engineering, the MEP works with retention initiatives and programs campus wide.The student’s efforts to work across disciplines and collaborate with other culturally based organizations give them the opportunity to work with their peers. At ASU the result was the creation of culturally based coalitions. Some of these coalitions include the American Indian Council, El Concilio – a coalition of Hispanic student organizations, and the Black & African Coalition. The students’ efforts are significant because they are mirrored at the program/staff level. As a result, significant collaboration of programs that serve minority students occurs bringing continuity to the students.It is through a collaboration effort that the MEP works closely with other campus programs that serve minority students such as: Math/Science Honors Program, Hispanic Mother/Daughter Program, Native American Achievement Program, Phoenix Union High School District Partnership Program, and the American Indian Institute. In particular, the MEP office had a focus on the retention and success of the Native American students in the College. This was due in large part to the outreach efforts of the OMEP, which are channeled through the MESA Program. The ASU MESA Program works very closely with constituents on the Navajo Nation and the San Carlos Apache Indian Reservation. It was through the MESA Program and working with the other campus support programs that the CEAS began investigating the success of the Native American students in the College. It was a discovery process that was not very positive. Through a cohort investigation that was initiated by the Associate Dean of Student Affairs, it was found that the retention rate of the Native American students in the CEAS was significantly lower than the rate of other minority populations within the College.In the spring of 2000, the OMEP and the CEAS Associate Dean of Student Affairs called a meeting with other Native American support programs from across the campus. In attendance were representatives from the American Indian Institute, the Native American Achievement Program, the Math/Science Honors Program, the Assistant Dean of Student Life, who works with the student coalitions, and the Counselor to the ASU President on American Indian Affairs, Peterson Zah. It was throughthis dialogue that many issues surrounding student success and retention were discussed. Although the issues andconcerns of each participant were very serious, the positiveeffect of the collaboration should be mentioned and noted. One of the many issues discussed was a general reality that ahigh number of Native American students were c oming to the university with minimal exposure to technology. Even through the efforts in the MESA program to expose studentsto technology and related careers, in most cases the schoolsin their local areas either lacked connectivity or basic hardware. In other cases, where students had availability to technology, they lacked teachers with the skills to help them in their endeavors to learn about it. Some students were entering the university with the intention to purse degrees in the Science, Technology, Engineering, and Mathematics (STEM) areas, but were ill prepared in the skills to utilize technology as a tool. This was particularly disturbing in the areas of Computer Science and Computer Systems Engineering where the basic entry-level course expected students to have a general knowledge of computers and applications. The result was evident in the cohort study. Students were failing the entry-level courses of CSE 100 (Principals of Programming with C++) or CSE 110 (Principals of Programming with Java) and CSE 200 (Concepts of Computer Science) that has the equivalent of CSE 100 or CSE 110 as a prerequisite. The students were also reporting difficulty with ECE 100, (Introduction to Engineering Design) due to a lack of assumed computer skills. During the discussion, it became evident that assistance in the area of technology skill development would be of significance to some students in CEAS.The MEP had been offering a seminar course inAcademic Success – ASE 194. This two-credit coursecovered topics in study skills, personal development, academic culture issues and professional development. The course was targeted to historically underrepresented minority students who were in the CEAS [3]. It was proposed by the MEP and the Associate Dean of Student Affairs to add a one-credit option to the ASE 194 course that would focus entirely on preparing students in the use of technology.A C OMPUTERB ASICSC OURSEThe course, ASE 194 – MEP Computer Basics, was offered during the Fall 2001 semester as a one-unit class that met on Friday afternoons from 3:40 pm to 4:30 pm. The course was originally intended for entering computer science students who had little or no background using computer applications or developing computer programs. However, enrollment was open to non-computer science students who subsequently took advantage of the opportunity. The course was offered in a computer-mediated classroom, which meantthat lectures, in- class activities, and examinations could all be administered on comp uters.During course development prior to the start of the semester, the faculty member did some analysis of existing courses at other universities that are used by students to assimilate computing technology. In addition, he did a review of the comp uter applications that were expected of the students in the courses found in most freshman engineering programs.The weekly class meetings consisted of lectures, group quizzes, accessing computer applications, and group activities. The lectures covered hardware, software, and system topics with an emphasis on software development [9]. The primary goals of the course were twofold. Firstly, the students needed to achieve a familiarity with using the computer applications that would be expected in the freshman engineering courses. Secondly, the students were to get a vision of the type of activities that would be expected during the upper division courses in computer science and computer systems engineering and later in the computer industry.Initially, there were twenty-two students in the course, which consisted of sixteen freshmen, five sophomores, and one junior. One student, a nursing freshman, withdrew early on and never attended the course. Of the remaining twenty-one students, there were seven students who had no degree program preference; of which six students now are declared in engineering degree programs and the seventh student remains undecided. The degree programs of the twenty-one students after completion of the course are ten in the computing degree programs with four in computer science and six in computer systems engineering. The remaining nine students includes one student in social work, one student is not decided, and the rest are widely distributed over the College with two students in the civil engineering program and one student each in bioengineering, electrical engineering, industrial engineering, material science & engineering, and mechanical engineering.These student degree program demographics presented a challenge to maintain interest for the non-computing degree program students when covering the software development topics. Conversely, the computer science and computer systems engineering students needed motivation when covering applications. This balance was maintained for the most part by developing an understanding that each could help the other in the long run by working together.The computer applications covered during the semester included e-mail, word processing, web searching, and spreadsheets. The original plan included the use of databases, but that was not possible due to the time limitation of one hour per week. The software development aspects included discussion of software requirements through specification, design, coding, and testing. The emphasis was on algorithm development and design review. The course grade was composed of twenty-five percent each for homework, class participation, midterm examination, and final examination. An example of a homework assignment involved searching the web in a manner that was more complex than a simple search. In order to submit the assignment, each student just had to send an email message to the faculty member with the information requested below. The email message must be sent from a student email address so that a reply can be sent by email. Included in the body of the email message was to be an answer for each item below and the URLs that were used for determining each answer: expected high temperature in Centigrade on September 6, 2001 for Lafayette, LA; conversion of one US Dollar to Peruvian Nuevo Sols and then those converted Peruvian Nuevo Sols to Polish Zlotys and then those converted Polish Zlotys to US Dollars; birth date and birth place of the current US Secretary of State; between now and Thursday, September 6, 2001 at 5:00 pm the expected and actual arrival times for any US domestic flight that is not departing or arriving to Phoenix, AZ; and your favorite web site and why the web site is your favorite. With the exception of the favorite web site, each item required either multiple sites or multiple levels to search. The identification of the favorite web site was introduced for comparison purposes later in the semester.The midterm and final examinations were composed of problems that built on the in-class and homework activities. Both examinations required the use of computers in the classroom. The submission of a completed examination was much like the homework assignments as an e-mail message with attachments. This approach of electronic submission worked well for reinforcing the use of computers for course deliverables, date / time stamping of completed activities, and a means for delivering graded results. The current technology leaves much to be desired for marking up a document in the traditional sense of hand grading an assignment or examination. However, the students and faculty member worked well with this form of response. More importantly, a major problem occurred after the completion of the final examination. One of the students, through an accident, submitted the executable part of a browser as an attachment, which brought the e-mail system to such a degraded state that grading was impossible until the problem was corrected. An ftp drop box would be simple solution in order to avoid this type of accident in the future until another solution is found for the e-mail system.In order to get students to work together on various aspects of the course, there was a group quiz and assignment component that was added about midway through the course. The group activities did not count towards the final grade, however the students were promised an award for the group that scored the highest number of points.There were two group quizzes on algorithm development and one out-of-class group assignment. The assignment was a group effort in website development. This assignment involved the development of a website that instructs. The conceptual functionality the group selected for theassignment was to be described in a one-page typed double spaced written report by November 9, 2001. During the November 30, 2001 class, each group presented to the rest of the class a prototype of what the website would look like to the end user. The reports and prototypes were subject to approval and/or refinement. Group members were expected to perform at approximately an equal amount of effort. There were five groups with four members in four groups and three members in one group that were randomly determined in class. Each group had one or more students in the computer science or computer systems engineering degree programs.The three group activities were graded on a basis of one million points. This amount of points was interesting from the standpoint of understanding relative value. There was one group elated over earning 600,000 points on the first quiz until the group found out that was the lowest score. In searching for the group award, the faculty member sought a computer circuit board in order to retrieve chips for each member of the best group. During the search, a staff member pointed out another staff member who salvages computers for the College. This second staff member obtained defective parts for each student in the class. The result was that each m ember of the highest scoring group received a motherboard, in other words, most of the internals that form a complete PC. All the other students received central processing units. Although these “awards” were defective parts, the students viewed these items as display artifacts that could be kept throughout their careers.C OURSE E VALUATIONOn a weekly basis, there were small assessments that were made about the progress of the course. One student was selected from each team to answer three questions about the activities of the day: “What was the most important topic covered today?”, “What topic covered was the ‘muddiest’?”, and “About what topic would you like to know more?”, as well as the opportunity to provide “Other comments.” Typically, the muddiest topic was the one introduced at the end of a class period and to be later elaborated on in the next class. By collecting these evaluation each class period, the instructor was able to keep a pulse on the class, to answer questions, to elaborate on areas considered “muddy” by the students, and to discuss, as time allowed, topics about which the students wished to know more.The overall course evaluation was quite good. Nineteen of the 21 students completed a course evaluation. A five-point scale w as used to evaluate aspects of the course and the instructor. An A was “very good,” a B was “good,” a C was “fair,” a D was “poor,” and an E was “not applicable.” The mean ranking was 4.35 on the course. An average ranking of 4.57, the highest for the s even criteria on the course in general, was for “Testbook/ supplementary material in support of the course.” The “Definition and application of criteria for grading” received the next highest marks in the course category with an average of 4.44. The lowest evaluation of the seven criteria for the course was a 4.17 for “Value of assigned homework in support of the course topics.”The mean student ranking of the instructor was 4.47. Of the nine criteria for the instructor, the highest ranking of 4.89 was “The instructor exhibited enthusiasm for and interest in the subject.” Given the nature and purpose of this course, this is a very meaningful measure of the success of the course. “The instructor was well prepared” was also judged high with a mean rank of 4.67. Two other important aspects of this course, “The instructor’s approach stimulated student thinking” and “The instructor related course material to its application” were ranked at 4.56 and 4.50, respectively. The lowest average rank of 4.11 was for “The instructor or assistants were available for outside assistance.” The instructor keep posted office hours, but there was not an assistant for the course.The “Overall quality of the course and instruction” received an average rank of 4.39 and “How do you rate yourself as a student in this course?” received an average rank of 4.35. Only a few of the students responded to the number of hours per week that they studies for the course. All of the students reported attending at least 70% of the time and 75% of the students said that they attended over 90% of the time. The students’ estimate seemed to be accurate.A common comment from the student evaluations was that “the professor was a fun teacher, made class fun, and explained everything well.” A common complaint was that the class was taught late (3:40 to 4:30) on a Friday. Some students judged the class to be an easy class that taught some basics about computers; other students did not think that there was enough time to cover all o f the topics. These opposite reactions make sense when we recall that the students were a broad mix of degree programs and of basic computer abilities. Similarly, some students liked that the class projects “were not overwhelming,” while other students thought that there was too little time to learn too much and too much work was required for a one credit class. Several students expressed that they wished the course could have been longer because they wanted to learn more about the general topics in the course. The instructor was judged to be a good role model by the students. This matched the pleasure that the instructor had with this class. He thoroughly enjoyed working with the students.A SSESSMENTS A ND C ONCLUSIONSNear the end of the Spring 2002 semester, a follow-up survey that consisted of three questions was sent to the students from the Fall 2001 semester computer basics course. These questions were: “Which CSE course(s) wereyou enrolled in this semester?; How did ASE 194 - Computer Basi cs help you in your coursework this semester?; and What else should be covered that we did not cover in the course?”. There were eight students who responded to the follow-up survey. Only one of these eight students had enrolled in a CSE course. There was consistency that the computer basics course helped in terms of being able to use computer applications in courses, as well as understanding concepts of computing. Many of the students asked for shortcuts in using the word processing and spreadsheet applications. A more detailed analysis of the survey results will be used for enhancements to the next offering of the computer basics course. During the Spring 2002 semester, there was another set of eight students from the Fall 2001 semester computer basi cs course who enrolled in one on the next possible computer science courses mentioned earlier, CSE 110 or CSE 200. The grade distribution among these students was one grade of A, four grades of B, two withdrawals, and one grade of D. The two withdrawals appear to be consistent with concerns in the other courses. The one grade of D was unique in that the student was enrolled in a CSE course concurrently with the computer basics course, contrary to the advice of the MEP program. Those students who were not enrolled in a computer science course during the Spring 2002 semester will be tracked through the future semesters. The results of the follow-up survey and computer science course grade analysis will provide a foundation for enhancements to the computer basics course that is planned to be offered again during the Fall 2002 semester.S UMMARY A ND F UTURE D IRECTIONSThis paper described a computer basics course. In general, the course was considered to be a success. The true evaluation of this course will be measured as we do follow-up studies of these students to determine how they fare in subsequent courses that require basic computer skills. Future offerings of the course are expected to address non-standard computing devices, such as robots as a means to inspire the students to excel in the computing field.R EFERENCES[1] Office of Institutional Analysis, Arizona State UniversityEnro llment Summary, Fall Semester , 1992-2001, Tempe,Arizona.[2] Reyes, Maria A., Gotes, Maria Amparo, McNeill, Barry,Anderson-Rowland, Mary R., “MEP Summer Bridge Program: A Model Curriculum Project,” 1999 Proceedings, American Society for Engineering Education, Charlotte, North Carolina, June 1999, CD-ROM, 8 pages.[3] Reyes, Maria A., Anderson-Rowland, Mary R., andMcCartney, Mary Ann, “Learning from our MinorityEngineering Students: Improving Retention,” 2000Proceedings, American Society for Engineering Education,St. Louis, Missouri, June 2000, Session 2470, CD-ROM, 10pages.[4] Adair, Jennifer K,, Reyes, Maria A., Anderson-Rowland,Mary R., McNeill, Barry W., “An Education/BusinessPartnership: ASU’s Minority Engineering Program and theTempe Chamber of Commerce,” 2001 Proceeding, AmericanSociety for Engineering Education, Albuquerque, NewMexico, June 2001, CD-ROM, 9 pages.[5] Adair, Jennifer K., Reyes, Maria A., Anderson-Rowland,Mary R., Kouris, Demitris A., “Workshops vs. Tutoring:How ASU’s Minority Engineering Program is Changing theWay Engineering Students Learn, “ Frontiers in Education’01 Conference Proceedings, Reno, Nevada, October 2001,CD-ROM, pp. T4G-7 – T4G-11.[6] Reyes, Maria A., Anderson-Rowland, Mary R., Fletcher,Shawna L., and McCartney, Mary Ann, “ModelCollaboration within Minority Engineering StudentSocieties,” 2000 Proceedings, American Society forEngineering Education, St. Louis, Missouri, June 2000, CD-ROM, 8 pages.[7] Anderson-Rowland, Mary R., Blaisdell, Stephanie L.,Fletcher, Shawna, Fussell, Peggy A., Jordan, Cathryne,McCartney, Mary Ann, Reyes, Maria A., and White, Mary,“A Comprehensive Programmatic Approach to Recruitmentand Retention in the College of Engineering and AppliedSciences,” Frontiers in Education ’99 ConferenceProceedings, San Juan, Puerto Rico, November 1999, CD-ROM, pp. 12a7-6 – 12a7-13.[8] Anderson-Rowland, Mary R., Blaisdell, Stephanie L.,Fletcher, Shawna L., Fussell, Peggy A., McCartney, MaryAnn, Reyes, Maria A., and White, Mary Aleta, “ACollaborative Effort to Recruit and Retain UnderrepresentedEngineering Students,” Journal of Women and Minorities inScience and Engineering, vol.5, pp. 323-349, 1999.[9] Pfleeger, S. L., Software Engineering: Theory and Practice,Prentice-Hall, Inc., Upper Saddle River, NJ, 1998.。
Dll文件动态链接库文件,与系统的性命相关,但大部分网站中都没有详细的解释,总算被我大海捞针找到了,和大家分享一下吧。
System32每个DLL的作用aclui.dll .....Security Descriptor Editor,没有它,注册表编缉器会无法运行ACTIVEDS.DLL .....(ADs 路由层DLL). 没有它, 打开事件查看器会出错ADSLDPC.DLL ......ADs LDAP 提供程序C DLLADVAPI32.DLL .....(高级Windows 32 基本API)...这个avicap32.dll 用于将从数码摄像头捕获的视频另存为AVI 格式. 如果你正在录制视频或是正在视频聊天, 那么你将服务终止这个进程ADVPACK.DLL ......(Advpack Library). Windows 用它来验证 .inf 文件. 如果advpack.dll 不可用, windows 将无法正常工作. (没有它, 打开系统属性会出错.) ASYCFILT.DLL ....我所安装的一个程序StatBar, 需要这个文件ATL.DLL .......... Windows XP ATL模块(Unicode)AUTHZ.DLL ........认证框架BASESRV.DLL ......Windows NT BASE API Server DLL BATMETER.DLL .....(电池助手DLL). 打开电源选项需要这个文件bootvid.dll .....VGA 启动驱动BROWSELC.DLL .....外壳浏览器用户界面库browser.dll puter Browser Service DLLBROWSEUI.DLL ..... 外壳浏览器用户界面库browsewm.dll ...BrowseWM PlayerCABINET.DLL ......(Microsoft? Cab 文件API). 想要正常打开系统选项就要保留这个文件CALC.EXE .......(计算器). Windows 自带的计算器程序CFGMGR32.DLL ...配置管理转发器DLL,没有它,无法在资源管理器中对磁盘进行格式化clb.dll .....Column List Box,没有它,注册表编缉器会无法运行CMD.EXE ....(命令行).可提供Windows NT 下的命令行提示符(MS-DOS 外壳解释程序) comcat.dll .....Microsoft C 运行时库文件COMCTL32.DLL .....通用控件库COMDLG32.DLL .....通用对话框DLLconsole.dll ....控制面板控制台小程序control.exe ....Windows 控制面板(这个不是实际上的控制面板.) CONVERT.EXE ....(转换). 用于将分区格式从FAT 转为NTFS 以及从NTFSv4 转为NTFSv5 CREDUI.DLL .......授权证书管理程序用户界面crtdll.dll .....加密管理器CRYPT32.DLL ......32 位加密API CRYPTDLL.DLL .....加密管理程序CRYPTUI.DLL ......Microsoft 加密用户界面提供程序CSRSRV.DLL .......客户端服务器运行时进程CSRSS.EXE ........(客户端-服务器运行时服务器子系统). 用于维护Win32 系统环境控制台以及其它基本功能.desk.cpl ......显示属性deskmon.dll .... 高级显示监视器属性devenum.dll ....设备枚举devmgr.dll .....设备管理器MMC 管理工具diskcopy.dll ...Windows DiskCopy dmintf.dll ..... 磁盘管理DCOM 接口存根dmutil.dll ..... 逻辑磁盘管理器工具库DNSAPI.DLL .......DNS 客户端API DLLfmifs.dll ......FM IFS 工具DLL framebuf.dll ...帧缓冲显示驱动GDI32.DLL ........GDI 客户端DLL (含有XCMD设置字体的函数)hal.dll ........(硬件抽象层). 隐藏Windows 应用程序处理硬件问题的复杂性(启动之后可删除的文件)hccoin.dll B 协同安装程序hotplug.dll ....用于安全移除硬件, 比如, U 盘icaapi.dll ..... TermDD 设备驱动的DLL 接口ifsutil.dll ....IFS 工具DLL IMAGEHLP.DLL .....Windows NT 图像助手(IE显示图像需要)imm32.dll ........(Windows XP IMM32 API 客户端DLL). 用于正常打开系统属性inetmib1.dll ...Microsoft MIB-IIsubagentinput.dll ......(文本输入DLL). 语言和区域设置需要这个文件来显示相关对话框IPHLPAPI.DLL .....IP 助手APIiyuv_32.dll ....Intel Indeo(R) Video YUV Codec (文件版本: 5.1.2600.2180)kbdus.dll .....美国键盘布局kdcom.dll .......内核调试程序硬件扩展DLL(启动之后可删除的文件)KERBEROS.DLL .....Kerberos 安全包kernel32.dll .....Windows NT BASEAPI 客户端DLLLINKINFO.DLL .....Windows 卷目追踪lpk.dll ........会话注销工具LSASRV.DLL .......LSA 服务器DLLLSASS.EXE ........(LSA 安全服务). 本地安全认证服务器进程main.cpl ......鼠标MFC42.DLL ......MFCDLL 共享库mfc42u.dll .....MFCDLL 共享库MPR.DLL ..........多个提供程序路由DLLMPRAPI.DLL .......(Windows NT MP路由管理DLL)mprui.dll .......多个提供程序MSASN1.DLL .......ASN.1 运行时APImscat32.dll ....MSCAT32 Forwarder DLLmscms.dll ........(Microsoft 色彩匹配系统DLL). 这个模块中包含了一些用于校正图像色彩,以及用于色彩映射, 色彩管理的函数MSCTF.DLL ......MSCTF 服务器DLLmsftedit.dll ..RTF 文本编辑控件, v4.1MSGINA.DLL .......Windows NT 登录GINA DLLmsh263.drv ....Microsoft H.263 ICM 驱动msidntld.dll ...Microsoft 标识管理器MSIMG32.DLL ......GDIEXT 客户端DLLMSIMTF.DLL .....Active IMM 服务器DLLmsls31.dll .......(Microsoft 线性服务库文件). Internet Explorer 需要这个文件msports.dll ....端口类别安装程序MSPRIVS.DLL ......Microsoft 特权转换msrle32.dll ....Microsoft RLE 压缩器mssign32.dll ...Microsoft 受信赖签证APIsmssip32.dll ....MSSIP32 Forwarder DLLmsvcirt.dll ....Windows NT IOStreams DLLMSVCP60.DLL ......Microsoft (R) C 运行时库文件msvcrt40.dll ...VC 4.x CRT DLL (向后兼容msvcrt.dll)MSVCRT.DLL .......Windows NT CRT DLLmsvfw32.dll ...Microsoft Video for Windows DLLmsvidc32.dll ...Microsoft Video 1 压缩器mydocs.dll .....我的文档文件夹用户界面ncxpnt.dll ork (不是Network) 安装向导支持DLLNDDEAPI.DLL work DDE 共享管理APIsNET1.EXE .......(Network). 与NET.EXE 的功能相同(在使用net命令的时候需要调用net1,若不存在就无法完成操作)NET.EXE ........(Network). 用于管理, 配置和查看与网络相关的信息, 例如net use, net print, net user, 等等NETAPI32.DLL Win32 API DLLnetrap.dll .....网络远程管理协议DLL netui0.dll .....NT LM UI Common Code - GUI Classes (文件版本: 5.1.2600.2180)netui1.dll .....NT LM UI Common Code - GUI Classes (文件版本: 5.1.2600.2180)newdev.dll ....添加硬件设备库文件NOTEPAD.EXE ......(记事本). 文本编辑工具NTDLL.DLL ........NT Layer DLL NTDSAPI.DLL ......(NT5DS Library) Windows 的目录服务需要这个ntdsapi.dll 库文件. 目录服务可令Windows 能够更容易地定位设备以及网络上的资源ntlanman.dll ...Microsoft? 局域网管理器ntlsapi.dll ....Microsoft? 许可服务器接口DLLNTMARTA.DLL ......Windows NT MARTA 提供程序NTOSKRNL.EXE ..(操作系统内核).Windows XP 操作系统内核, 启动画面就在这个文件中ocmanage.dll ..可选组件管理库ODBC32.DLL .......Microsoft Data Access - ODBC 驱动管理器ODBCBCP.DLL ......(Microsoft BCP for ODBC). 没有这个文件的话, 当你打开电脑管理时会遇到一个错误. 但还是可以打开电脑管理. (我把电脑管理删掉了.)ODBCINT.DLL ......Microsoft Data Access - ODBC 资源OLE32.DLL ........Microsoft OLE for Windowsoleacc.dll .......(Active Accessibility 核心组件)OLEAUT32.DLL ..... Windows 要用它执行OLE (对象链接和嵌入) 操作. OLE 允许将程序创建的对象嵌入到另一个程序的文档或对象中. 例如. 将一个Excel 表格嵌入到Word 文档中. Windows 应用程序要经常用到OLE, 因此一般你是无法将其删除的OLECLI32.DLL ..... 对象链接和嵌入客户端库文件OLECNV32.DLL .....Microsoft OLE for Windowsoledlg.dll .......(Microsoft Windows(TM) OLE 2.0 用户接口支持)OLESVR32.DLL ..... 对象链接和嵌入服务器库OLETHK32.DLL .....Microsoft OLE for Windowsperfctrs.dll ...性能计数器powercfg.cpl ..电源选项POWRPROF.DLL .....(电源配置助手DLL). 如要正常打开设备管理器中的键盘属性, 需要保留这个文件PROFMAP.DLL erenv PSAPI.DLL ........进程状态助手pstorec.dll ..... 受保护存储的COM 接口pstorsvc.dll .... 受保护存储服务器REG.EXE ........(注册表控制台). 一个用于查询和修改注册表的命令行工具REGAPI.DLL .......注册表配置APIs REGSVR32.EXE ...(注册服务器). 用于注册组件, DLLriched20.dll ...RTF 编辑控件, v3.0 rnr20.dll ......Windows Socket2 命名空间DLLRPCRT4.DLL .......远程过程调用运行时RPCSS.DLL ........分布式COM 服务RSAENH.DLL .......Microsoft 增强加密提供程序rshx32.dll ....安全外壳扩展rtipxmib.dll ...Microsoft Router IPX MIB subagentRTUTILS.DLL ......路由工具RUNDLL32.EXE ...(Run DLL). 用于运行DLL 文件的命令行工具RUNONCE.EXE ....(Run Once). 用于将要执行的任务添加定义到RunOnce 注册表项中SAMLIB.DLL .......SAM 库DLLSAMSRV.DLL .......SAM 服务器DLLSCESRV.DLL .......Windows安全配置编辑器引擎SCHANNEL.DLL .....TLS / SSL 安全提供程序SECUR32.DLL ......安全支持提供程序接口security.dll ...安全支持提供程序接口services.exe .....(安全和控制程序). Windows XP 用它管理服务SETUP.EXE ......(Setup). Windows 安装程序SETUPAPI.DLL .....Windows SetupAPISFC.DLL ..........Windows 文件保护SFC_OS.DLL .......Windows 文件保护sfcfiles.dll .....Windows 2000 系统文件检查工具SHDOCVW.DLL ...... 外壳文档对象和控件库SHELL32.DLL ......Windows 外壳通用Dllshellstyle.dll ..Windows 外壳样式资源DllSHFOLDER.DLL .....(外壳文件夹服务). 若要正常打开系统属性, 需要保留此文件shgina.dll .....Windows 外壳用户登录<-- 这个文件用于从你的桌面上重启电脑. 进一步讲, 一旦你将其删除或是将其从system32 文件夹中移走, 那么即使你将其放回, 也照样无法从你的桌面重新启动shimgvw.dll ......(Windows 图片和传真查看器). 我要用它看电脑上的图片SHLWAPI.DLL ......外壳Light-weight 工具库sigtab.dll .....文件完整性设置(系统属性-->硬件-->驱动程序签名选项的对话框)SMSS.EXE .........(会话管理器). 是个会话管理器, 用于在启动期间创建Windows XP 环境snmpapi.dll ....SNMP 工具库softpub.dll ....Softpub Forwarder DLLsoftpub.dll ....Softpub Forwarder DLLSTOBJECT.DLL .....(Systray 外壳服务对象). stobject.dll 是个库文件, 包含了一些像是图标这样的资源streamci.dll ... 流设备类别安装程序SVCHOST.EXE ...... Win32 服务的常规宿主进程SXS.DLL ..........Fusion 2.5 sysdm.cpl .....系统属性SYSTRAY.EXE ....(系统栏). 系统栏提供程序. 它能控制任务栏和系统栏. 但是, 没它的话, 也没有什么不正常的地方TASKMGR.EXE ...(任务管理器). 平时使用的任务管理器themeui.dll ......Windows 主题API timedate.cpl ..时间和日期ufat.dll .......FAT 工具DLLULIB.DLL .......文件工具支持DLL umdmxfrm.dll .....Unimodem 转换模块umpnpmgr.dll .....用户模式即插即用服务untfs.dll ......NTFS 工具DLL ureg.dll .......注册表工具DLL urlmon.dll ....... Win32 OLE32 扩展usbui.dll B 用户界面Dlluser32.dll .......Windows XP 用户API 客户端DLLuserenv.dll ......用户环境USERINIT.EXE ..(用户初始化). 在用户登录之后, 用于确定操作系统的环境usp10.dll .....Uniscribe Unicode 脚本处理器UXTHEME.DLL ......Microsoft UxTheme LibraryVERSION.DLL ......版本检查和文件安装库vga64k.dll .....32K/64K 色VGA\SVGA 显示驱动vga.dll .....VGA 16 色显示驱动w32topl.dll ....Windows NT Topology 维护工具WDIGEST.DLL ......Microsoft 采集访问WIN32K.SYS .......多用户Win32 驱动WININET.DLL ......Internet 扩展winipsec.dll ....Windows IPSec SPD Client DLLWINLOGON.EXE .....Windows NT 登录应用程序WINMM.DLL ........MCI API DLL WINRNR.DLL .......LDAP RnR 提供程序DLLWINSPOOL.DRV ...Windows 缓冲池驱动WINSRV.DLL .......Windows Server DLLWINSTA.DLL .......工作站库文件WINTRUST.DLL .....Microsoft 受信赖证书APIsWLDAP32.DLL ......Win32 LDAP API DLLWMI.DLL ..........(WMI DC 和DP 功能). 若要正常打开电脑管理, 则需要保留此文件WS2_32.DLL .......Windows Socket 2.0 32 位DLLWS2HELP.DLL ......Windows Socket 2.0 助手wshnetbs.dll bios Windows套接层助手DLLWSOCK32.DLL ......(Windows 32 位套接层DLL). 某些涉及到网络的软件会需要它WTSAPI32.DLL .....Windows 终端服务器SDK APInetid.dll -----(系统属性-->计算机名) fontview.exe --字体查看器fontext.dll --与字体文件夹视图安装字体有关下面是一些有关修复Dll文件的操作:WindowsXP系统文件的备份。
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at /legal.htm .All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.IntroductionThe Spartan ™ and the Spartan-XL families are a high-vol-ume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates.These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume,approach and in many cases are equivalent to mask pro-grammed ASIC devices.The Spartan series is the result of more than 14 years of FPGA design experience and feedback from thousands of customers. By streamlining the Spartan series feature set,leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. The Spar-tan and Spartan-XL families in the Spartan series have ten members, as shown in T able 1.Spartan and Spartan-XL FeaturesNote: The Spartan series devices described in this data sheet include the 5V Spartan family and the 3.3V Spartan-XL family. See the separate data sheet for the 2.5V Spartan-II family.•First ASIC replacement FPGA for high-volume production with on-chip RAM•Density up to 1862 logic cells or 40,000 system gates •Streamlined feature set based on XC4000 architecture •System performance beyond 80MHz•Broad set of AllianceCORE ™ and LogiCORE ™ predefined solutions available •Unlimited reprogrammability •Low cost•System level features-Available in both 5V and 3.3V versions -On-chip SelectRAM ™ memory -Fully PCI compliant-Full readback capability for program verificationand internal node observability -Dedicated high-speed carry logic -Internal 3-state bus capability-Eight global low-skew clock or signal networks -IEEE 1149.1-compatible Boundary Scan logic -Low cost plastic packages available in all densities -Footprint compatibility in common packages•Fully supported by powerful Xilinx development system -Foundation Series: Integrated, shrink-wrapsoftware-Alliance Series: Dozens of PC and workstationthird party development systems supported-Fully automatic mapping, placement and routing Additional Spartan-XL Features• 3.3V supply for low power with 5V tolerant I/Os •Power down input •Higher performance •Faster carry logic•More flexible high-speed clock network•Latch capability in Configurable Logic Blocks •Input fast capture latch•Optional mux or 2-input function generator on outputs •12 mA or 24 mA output drive •5V and 3.3V PCI compliant •Enhanced Boundary Scan •Express Mode configuration •Chip scale packagingSpartan and Spartan-XL Families Field Programmable Gate ArraysDS060 (v1.6) September 19, 2001Product Specification T able 1: Spartan and Spartan-XL Field Programmable Gate Arrays1.Max values of Typical Gate Range include 20-30% of CLBs used as RAM.2DS060 (v1.6) September 19, 2001General OverviewSpartan series FPGAs are implemented with a regular, flex-ible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and sur-rounded by a perimeter of programmable Input/Output Blocks (IOBs), as seen in Figure 1. They have generous routing resources to accommodate the most complex inter-connect patterns.The devices are customized by loading configuration data into internal static memory cells. Re-programming is possi-ble an unlimited number of times. The values stored in thesememory cells determine the logic functions and intercon-nections implemented in the FPGA. The FPGA can either actively read its configuration data from an external serial PROM (Master Serial mode), or the configuration data can be written into the FPGA from an external device (Slave Serial mode).Spartan series FPGAs can be used where hardware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 50,000 systems per month.Figure 1: Basic FPGA Block DiagramSpartan series devices achieve high-performance, low-cost operation through the use of an advanced architecture and semiconductor technology. Spartan and Spartan-XL devices provide system clock rates exceeding 80MHz and internal performance in excess of150MHz. In contrast to other FPGA devices, the Spartan series offers the most cost-effective solution while maintaining leading-edge per-formance. In addition to the conventional benefit of high vol-ume programmable logic solutions, Spartan series FPGAs also offer on-chip edge-triggered single-port and dual-port RAM, clock enables on all flip-flops, fast carry logic, and many other features.The Spartan/XL families leverage the highly successful XC4000 architecture with many of that family’s features and benefits. T echnology advancements have been derived from the XC4000XLA process developments.Logic Functional DescriptionThe Spartan series uses a standard FPGA structure as shown in Figure1, page2. The FPGA consists of an array of configurable logic blocks (CLBs) placed in a matrix of routing channels. The input and output of signals is achieved through a set of input/output blocks (IOBs) forming a ring around the CLBs and routing channels.•CLBs provide the functional elements for implementing the user’s logic.•IOBs provide the interface between the package pins and internal signal lines.•Routing channels provide paths to interconnect the inputs and outputs of the CLBs and IOBs.The functionality of each circuit block is customized during configuration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA.Configurable Logic Blocks (CLBs)The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simpli-fied block diagram in Figure2. There are three look-up tables (LUT) which are used as logic function generators, two flip-flops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Description, page13.Function GeneratorsTwo 16x1 memory look-up tables (F-LUT and G-LUT) are used to implement 4-input function generators, each offer-ing unrestricted logic implementation of any Boolean func-tion of up to four independent input signals (F1 to F4 or G1 to G4). Using memory look-up tables the propagation delay is independent of the function implemented.A third 3-input function generator (H-LUT) can implement any Boolean function of its three inputs. Two of these inputs are controlled by programmable multiplexers (see box "A" of Figure2). These inputs can come from the F-LUT or G-LUT outputs or from CLB inputs. The third input always comes from a CLB input. The CLB can, therefore, implement cer-tain functions of up to nine inputs, like parity checking. The three LUTs in the CLB can also be combined to do any arbi-trarily defined Boolean function of five inputs.4DS060 (v1.6) September 19, 2001A CLB can implement any of the following functions:•Any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variablesNote: When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two unregistered function generator outputs are available from the CLB.•Any single function of five variables•Any function of four variables together with some functions of six variables•Some functions of up to nine variables.Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators significantly improves system speed. In addition, the design-software tools can deal with each function generator independently.This flexibility improves cell usage.Flip-FlopsEach CLB contains two flip-flops that can be used to regis-ter (store) the function generator outputs. The flip-flops and function generators can also be used independently (see Figure 2). The CLB input DIN can be used as a direct input to either of the two flip-flops. H1 can also drive either flip-flop via the H-LUT with a slight additional delay.The two flip-flops have common clock (CK), clock enable (EC) and set/reset (SR) inputs. Internally both flip-flops are also controlled by a global initialization signal (GSR) which is described in detail in Global Signals: GSR and GTS ,page 20.Latches (Spartan-XL only)The Spartan-XL CLB storage elements can also be config-ured as latches. The two latches have common clock (K)and clock enable (EC) inputs. Functionality of the storage element is described in Table 2.Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown)Clock InputEach flip-flop can be triggered on either the rising or falling clock edge. The CLB clock line is shared by both flip-flops.However, the clock is individually invertible for each flip-flop (see CK path in Figure 3). Any inverter placed on the clock line in the design is automatically absorbed into the CLB. Clock EnableThe clock enable line (EC) is active High. The EC line is shared by both flip-flops in a CLB. If either one is left discon-nected, the clock enable for that flip-flop defaults to the active state. EC is not invertible within the CLB. The clock enable is synchronous to the clock and must satisfy the setup and hold timing specified for the device.Set/ResetThe set/reset line (SR) is an asynchronous active High con-trol of the flip-flop. SR can be configured as either set or reset at each flip-flop. This configuration option determines the state in which each flip-flop becomes operational after configuration. It also determines the effect of a GSR pulse during normal operation, and the effect of a pulse on the SR line of the CLB. The SR line is shared by both flip-flops. If SR is not specified for a flip-flop the set/reset for that flip-flop defaults to the inactive state. SR is not invertible within the CLB.CLB Signal Flow ControlIn addition to the H-LUT input control multiplexers (shown in box "A" of Figure 2, page 4) there are signal flow control multiplexers (shown in box "B" of Figure 2) which select the signals which drive the flip-flop inputs and the combinatorial CLB outputs (X and Y).Each flip-flop input is driven from a 4:1 multiplexer which selects among the three LUT outputs and DIN as the data source.Each combinatorial output is driven from a 2:1 multiplexer which selects between two of the LUT outputs. The X output can be driven from the F-LUT or H-LUT, the Y output from G-LUT or H-LUT .Control SignalsThere are four signal control multiplexers on the input of the CLB. These multiplexers allow the internal CLB control sig-nals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be driven from any of the four general control inputs (C1-C4 in Figure 4) into the CLB. Any of these inputs can drive any of the four internal control signals.T able 2: CLB Storage Element FunctionalityLegend:XDon ’t careRising edge (clock not inverted).SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)Figure 3: CLB Flip-Flop Functional Block Diagram6DS060 (v1.6) September 19, 2001The four internal control signals are:•EC: Enable Clock•SR: Asynchronous Set/Reset or H function generator Input 0•DIN: Direct In or H function generator Input 2•H1: H function generator Input 1.Input/Output Blocks (IOBs)User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be con-figured for input, output, or bidirectional signals. Figure 6shows a simplified functional block diagram of the Spar-tan/XL IOB.IOB Input Signal PathThe input signal to the IOB can be configured to either go directly to the routing channels (via I1 and I2 in Figure 6) or to the input register. The input register can be programmed as either an edge-triggered flip-flop or a level-sensitive latch. The functionality of this register is shown in Table 3,and a simplified block diagram of the register can be seen in Figure 5.Figure 4: CLB Control Signal InterfaceFigure 5: IOB Flip-Flop/Latch Functional BlockDiagramTable 3: Input Register FunctionalityX Don ’t care.Rising edge (clock not inverted).SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)The register choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are also available. The clock signal inverter is also shown in Figure5 on the CK line.The Spartan IOB data input path has a one-tap delay ele-ment: either the delay is inserted (default), or it is not. The Spartan-XL IOB data input path has a two-tap delay ele-ment, with choices of a full delay, a partial delay, or no delay. The added delay guarantees a zero hold time with respect to clocks routed through the global clock buffers. (See Glo-bal Nets and Buffers, page12 for a description of the glo-bal clock buffers in the Spartan/XL families.) For a shorter input register setup time, with positive hold-time, attach a NODELAY attribute or property to the flip-flop.The output of the input register goes to the routing channels (via I1 and I2 in Figure6). The I1 and I2 signals that exit the IOB can each carry either the direct or registered input signal.The 5V Spartan input buffers can be globally configured for either TTL (1.2V) or CMOS (VCC/2) thresholds, using an option in the bitstream generation software. The Spartan output levels are also configurable; the two global adjust-ments of input threshold and output level are independent. The inputs of Spartan devices can be driven by the outputs of any 3.3V device, if the Spartan inputs are in TTL mode. Input and output thresholds are TTL on all configuration pins until the configuration has been loaded into the device and specifies how they are to be used. Spartan-XL inputs are TTL compatible and 3.3V CMOS compatible. Supported sources for Spartan/XL device inputs are shown in Table4.Spartan-XL I/Os are fully 5V tolerant even though the V CC is 3.3V. This allows 5V signals to directly connect to the Spar-tan-XL inputs without damage, as shown in Table4. In addi-tion, the 3.3V V CC can be applied before or after 5V signals are applied to the I/Os. This makes the Spartan-XL devices immune to power supply sequencing problems.Figure 6: Simplified Spartan/XL IOB Block Diagram8DS060 (v1.6) September 19, 2001Spartan-XL V CC ClampingSpartan-XL FPGAs have an optional clamping diode con-nected from each I/O to V CC . When enabled they clamp ringing transients back to the 3.3V supply rail. This clamping action is required in 3.3V PCI applications. V CC clamping is a global option affecting all I/O pins.Spartan-XL devices are fully 5V TTL I/O compatible if V CC clamping is not enabled. With V CC clamping enabled, the Spartan-XL devices will begin to clamp input voltages to one diode voltage drop above V CC . If enabled, TTL I/O com-patibility is maintained but full 5V I/O tolerance is sacrificed.The user may select either 5V tolerance (default) or 3.3V PCI compatibility. In both cases negative voltage is clamped to one diode voltage drop below ground.Spartan-XL devices are compatible with TTL, LVTTL, PCI 3V, PCI 5V and LVCMOS signalling. The various standards are illustrated in Table 5.Additional Fast Capture Input Latch (Spartan-XL only)The Spartan-XL IOB has an additional optional latch on the input. This latch is clocked by the clock used for the output flip-flop rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements.This additional latch allows the fast capture of input data,which is then synchronized to the internal clock by the IOB flip-flop or latch.T o place the Fast Capture latch in a design, use one of the special library symbols, ILFFX or ILFLX. ILFFX is a trans-parent-Low Fast Capture latch followed by an active High input flip-flop. ILFLX is a transparent Low Fast Capture latch followed by a transparent High input latch. Any of the clock inputs can be inverted before driving the library element,and the inverter is absorbed into the IOB.IOB Output Signal PathOutput signals can be optionally inverted within the IOB,and can pass directly to the output buffer or be stored in an edge-triggered flip-flop and then to the output buffer. The functionality of this flip-flop is shown in T able 6.T able 4: Supported Sources for Spartan/XL InputsT able 5: I/O Standards Supported by Spartan-XL FPGAsTable 6: Output Flip-Flop Functionality X Don ’t careRising edge (clock not inverted). SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)Z3-stateOutput Multiplexer/2-Input Function Generator (Spartan-XL only)The output path in the Spartan-XL IOB contains an addi-tional multiplexer not available in the Spartan IOB. The mul-tiplexer can also be configured as a 2-input function generator, implementing a pass gate, AND gate, OR gate, or XOR gate, with 0, 1, or 2 inverted inputs.When configured as a multiplexer, this feature allows two output signals to time-share the same output pad, effec-tively doubling the number of device outputs without requir-ing a larger, more expensive package. The select input is the pin used for the output flip-flop clock, OK.When the multiplexer is configured as a 2-input function generator, logic can be implemented within the IOB itself. Combined with a Global buffer, this arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe driven by a global buffer. The user can specify that the IOB function generator be used by placing special library symbols beginning with the letter "O." For example, a 2-input AND gate in the IOB func-tion generator is called OAND2. Use the symbol input pin labeled "F" for the signal on the critical path. This signal is placed on the OK pin — the IOB input with the shortest delay to the function generator. Two examples are shown in Figure7.Output BufferAn active High 3-state signal can be used to place the out-put buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (O) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each IOB (see Figure6, page7). An output can be config-ured as open-drain (open-collector) by tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground.By default, a 5V Spartan device output buffer pull-up struc-ture is configured as a TTL-like totem-pole. The High driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below V CC. Alternatively, the outputs can be globally configured as CMOS drivers, with additional p-channel pull-up transistors pulling to V CC. This option, applied using the bitstream generation software, applies to all outputs on the device. It is not individually programma-ble.All Spartan-XL device outputs are configured as CMOS drivers, therefore driving rail-to-rail. The Spartan-XL outputs are individually programmable for 12mA or 24mA output drive.Any 5V Spartan device with its outputs configured in TTL mode can drive the inputs of any typical 3.3V device. Sup-ported destinations for Spartan/XL device outputs are shown in Table7.Three-State Register (Spartan-XL Only)Spartan-XL devices incorporate an optional register control-ling the three-state enable in the IOBs. The use of the three-state control register can significantly improve output enable and disable time.Output Slew RateThe slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti-cal signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop.Spartan/XL devices have a feature called "Soft Start-up," designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is deter-mined by the individual configuration option for each IOB. Pull-up and Pull-down NetworkProgrammable pull-up and pull-down resistors are used fortying unused pins to V CC or Ground to minimize power con-sumption and reduce noise sensitivity. The configurablepull-up resistor is a p-channel transistor that pulls to V CC.The configurable pull-down resistor is an n-channel transis-tor that pulls to Ground. The value of these resistors is typi-cally 20KΩ − 100KΩ (See "Spartan DC Characteristics Figure 7: AND and MUX Symbols in Spartan-XL IOB10DS060 (v1.6) September 19, 2001Over Operating Conditions" on page 43.). This high value makes them unsuitable as wired-AND pull-up resistors.After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default,unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pull-up, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULL-DOWN library component to the net attached to the pad.Set/ResetAs with the CLB registers, the GSR signal can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two flip-flops can be individually configured to set or clear on reset and after configuration. Other than the global GSR net, no user-con-trolled set/reset signal is available to the I/O flip-flops (Figure 5). The choice of set or reset applies to both the ini-tial state of the flip-flop and the response to the GSR pulse.Independent ClocksSeparate clock signals are provided for the input (IK) and output (OK) flip-flops. The clock can be independently inverted for each flip-flop within the IOB, generating eitherfalling-edge or rising-edge triggered flip-flops. The clock inputs for each IOB are mon Clock EnablesThe input and output flip-flops in each IOB have a common clock enable input (see EC signal in Figure 5), which through configuration, can be activated individually for the input or output flip-flop, or both. This clock enable operates exactly like the EC signal on the Spartan/XL CLB. It cannot be inverted within the IOB.Routing Channel DescriptionAll internal routing channels are composed of metal seg-ments with programmable switching points and switching matrices to implement the desired routing. A structured,hierarchical matrix of routing channels is provided to achieve efficient automated routing.This section describes the routing channels available in Spartan/XL devices. Figure 8 shows a general block dia-gram of the CLB routing channels. The implementation soft-ware automatically assigns the appropriate resources based on the density and timing requirements of the design.The following description of the routing channels is for infor-mation only and is simplified with some minor details omit-ted. For an exact interconnect description the designer should open a design in the FPGA Editor and review the actual connections in this tool.The routing channels will be discussed as follows;•CLB routing channels which run along each row and column of the CLB array.•IOB routing channels which form a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the CLB routing channels.•Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals.CLB Routing ChannelsThe routing channels around the CLB are derived from three types of interconnects; single-length, double-length,and longlines. At the intersection of each vertical and hori-zontal routing channel is a signal steering matrix called a Programmable Switch Matrix (PSM). Figure 8 shows the basic routing channel configuration showing single-length lines, double-length lines and longlines as well as the CLBs and PSMs. The CLB to routing channel interface is shown as well as how the PSMs interface at the channel intersec-tions.T able 7: Supported Destinations for Spartan/XL OutputsNotes:1.Only if destination device has 5V tolerant inputs.CLB InterfaceA block diagram of the CLB interface signals is shown in Figure9. The input signals to the CLB are distributed evenly on all four sides providing maximum routing flexibility. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algo-rithms. Inputs, outputs, and function generators can freely swap positions within a CLB to avoid routing congestion during the placement and routing operation. The exceptions are the clock (K) input and CIN/COUT signals. The K input is routed to dedicated global vertical lines as well as four single-length lines and is on the left side of the CLB. The CIN/COUT signals are routed through dedicated intercon-nects which do not interfere with the general routing struc-ture. The output signals from the CLB are available to drive both vertical and horizontal channels.Programmable Switch MatricesThe horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each PSM consists of programmable pass transis-tors used to establish connections between the lines (see Figure10).For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a dou-ble-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix.Single-Length LinesSingle-length lines provide the greatest interconnect flexibil-ity and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associ-ated with each CLB. These lines connect the switching matrices that are located in every row and column of CLBs. Single-length lines are connected by way of the program-mable switch matrices, as shown in Figure10. Routing con-nectivity is shown in Figure8.Single-length lines incur a delay whenever they go through a PSM. Therefore, they are not suitable for routing signals for long distances. They are normally used to conduct sig-nals within a localized area and to provide the branching for nets with fanout greater than one.Figure 8: Spartan/XL CLB Routing Channels and Interface Block DiagramFigure 9: CLB Interconnect Signals。
C语言的DLL编写
1、打开C语言的Microsoft Visual C++ 6.0
2、选择file--> new ,在project选项中选择MFC AppWizard(dll),给工程起名字,
选择保存路径。
3、选择Regular DLLusingshared MFCDLL,点击finish
4、此时工程的结构图如下所示
5、在FourthSample源文件中写上对外暴露的dll函数方法
6、在FourthSample.def中追加对外暴露的方法名
7、选中FourthSample.cpp,编译源文件
8、生成dll文件
9、注意事项:在编译源文件时可能要报以下错误,
解决方法:
选中该源文件,点击右键Settings,
再次编译,通过。
C语言调用DLL
1、新建一个c的源文件,进行dll调用的测试
2、源代码如下,代码中有关键词用法,请参考其他资料
3、弹出一个对话框,说明dll调用成功。
注意事项:注意将test.dll动态链接库放在该程序目录下(FourthSample.dll重名为test.d ll)。
常用扩展名含义ISO:镜像文件RAR:压缩包html:网页zip:压缩包exe:安装包pdf:pdf文档rm:视频文件avi:视频文件tmp:临时文件xls:excel工作表mdf:虚拟光驱镜像文件txt:记事本doc:word文档MID:声卡声乐文件文件类型扩展名及打开方式文档文件txt(所有文字处理软件或编辑器都可打开)、doc(word及wps等软件可打开)、hlp(adobe acrobat reader可打开)、wps(wps软件可打开)、rtf(word及wps等软件可打开)、htm(各种浏览器可打开、用写字板打开可查看其源代码)、pdf(adobe acrobat reader 和各种电子阅读软件可打开)压缩文件rar(winrar可打开)、zip(winzip可打开)、arj(用arj解压缩后可打开)、gz(unix系统的压缩文件,用winzip可打开)、z(unix系统的压缩文件,用winzip可打开)图形文件bmp、gif、jpg、pic、png、tif(这些文件类型用常用图像处理软件可打开)声音文件wav(媒本播放器可打开)、aif(常用声音处理软件可打开)、au(常用声音处理软件可打开)、mp3(由winamp播放)、ram(由realplayer 播放)动画文件avi(常用动画处理软件可播放)、mpg(由vmpeg播放)、mov(由activemovie播放)、swf(用flash自带的players程序可播放)系统文件int、sys、dll、adt可执行文件exe、com语言文件c、asm、for、lib、lst、msg、obj、pas、wki、bas映像文件map (其每一行都定义了一个图像区域以及当该区域被触发后应返回的url信息)备份文件bak(被自动或是通过命令创建的辅助文件,它包含某个文件的最近一个版本)临时文件20686 ╳ord、excel等软件在操作时会产生此类文件)模板文件dot(通过word模板可以简化一些常用格式文档的创建工作)说明A 开头扩展名 说明A :对象代码库文件AAM :Authorware shocked 文件AAS :Authorware shocked 包ABF :Adobe 二进制屏幕字体ABK :CorelDRAW 自动备份文件ABS :该类文件有时用于指示一个摘要(就像在一篇有关科学方面的文章的一个摘要或概要,取自abstract )ACE :Ace 压缩文件格式ACM :Windows 系统目录文件ACP :Microsoft office 助手预览文件ACT :Microsoft office 助手文件AD :After Dark 屏幕保护程序ADA :Ada 源文件(非-GNAT )ADB :Ada 源文件主体(GNAT );HP100LX 组织者的约定数据库ADF :Amiga 磁盘文件ADI :AutoCAD 设备无关二进制绘图仪格式ADM :After Dark 多模块屏幕保护;Windows NT 策略模板ADP :FaxWork 用于传真调制解调器的交互安装文件;Astound Dynamite 文件ADR :After Dark 随机屏幕保护;Smart Address 的地址簿批处理文件bat (在ms-dos 中,bat 文件是可执行文件,由一系列命令构成,其中可以包含对其他程序的调用)ADS:Ada源文件说明书(GNAT)AFM:Adobe的字体尺度AF2/AF3:ABC的FlowChat文件AI:Adobe Illustrator格式图形AIF/AIFF:音频互交换文件,Silicon Graphic and Macintosh应用程序的声音格式AIFC:压缩AIFAIM:AOL即时信息传送AIS:ACDSee图形序列文件;Velvet Studio设备文件AKW:RoboHELP的帮助工程中所有A-关键词ALB:JASC Image Commander相册ALL:艺术与书信库AMS:Velvet Studio音乐模块(MOD)文件;Extreme的Tracker模块文件ANC:Canon Computer的调色板文件,包含一系列可选的颜色板ANI:Windows系统中的动画光标ANS:ANSI文本文件ANT:SimAnt For Windows中保存的游戏文件API:Adobe Acrobat使用的应用程序设计接口文件APS:Microsoft Visual C++文件ARI:Aristotle声音文件ARJ:Robert Jung ARJ压缩包文件ART:Xara Studio绘画文件;Canon Crayola美术文件;Clip Art文件格式;另一种光线跟踪格式;AOL使用的用Johnson-Grace压缩算法压缩的标记文件ASA:Microsoft Visual InterDev文件ASC:ASCⅡ文本文件;PGP算法加密文件ASD:Microsoft Word的自动保存文件;Microsoft高级流媒体格式(microsoft advancedstreaming format,ASF)的描述文件;可用NSREX打开Velvet Studio例子文件ASE:Velvet Studio采样文件ASF:Microsoft高级流媒体格式文件ASM:汇编语言源文件,Pro/E装配文件ASO:Astound Dynamite对象文件ASP:动态网页文件;ProComm Plus安装与连接脚本文件;Astound介绍文件ASV:DataCAD自动保存文件ASX:Cheyenne备份脚本文件;Microsoft高级流媒体重定向器文件,视频文件ATW:来自个人软件的Any Time Deluxe For Windows个人信息管理员文件AU:Sun/NeXT/DEC/UNIX声音文件;音频U-Law(读作“mu-law”)文件格式AVB:Computer Associates Inoculan反病毒软件的病毒感染后文件AVI:Microsoft Audio Video Interleave电影格式AVR:Audio Visual Research文件格式AVS:应用程序可视化格式AWD:FaxVien文档AWR:Telsis数字储存音频文件扩展名格式Axx:ARJ压缩文件的分包序号文件,用于将一个大文件压至几个小的压缩包中(xx取01-99的数字)A3M/A4M:Authorware Macintosh未打包文件A4P:Authorware无运行时间的打包文件A3W/A4W/A5W:未打包的Authorware Windows文件B开头扩展名说明BAK:备份文件BAS:BASIC源文件BAT:批处理文件BDF:West Point Bridger Designer文件BGL:Microsoft Flight Simulator(微软飞行模拟器)的视景文件BI:二进制文件BIF:Group Wise的初始化文件BIFF XLIFE 3D格式文件BIN 二进制文件BK/BK$ 有时用于代表备份版本BKS IBM BookManager Read书架文件BMK 书签文件BMP Windows或OS/2位图文件BOOK Adobe FrameMaker Book文件BRX 用于查看多媒体对象目录的文件BSP Quake图形文件BTM Norton 应用程序使用的批处理文件BUD Quicken的备份磁盘BUN CakeWalk 声音捆绑文件(一种MIDI程序)BW SGI黑白图像文件BWV 商业波形文件C开头扩展名说明C C代码文件CAB Microsoft压缩文件CAD Softdek的Drafix CAD文件CAL CALS压缩位图;日历计划表数据CAP 压缩音乐文件格式CAS 逗号分开的ASCⅡ文件CB Microsoft干净引导文件CC Visual dBASE用户自定义类文件CCB Visual Basic动态按钮配置文件CCH Corel图表文件CCO CyberChat数据文件CCT Macromedia Director Shockwave投影CDA CD音频轨道CDF Microsoft频道定义格式文件CDI Philip的高密盘交互格式CDM Visual dBASE自定义数据模块文件CDR CorelDRAW绘图文件;原始音频CD数据文件CDT CorelDRAW模板CDX CorelDRAW压缩绘图文件;Microsoft Visual FoxPro索引文件CFG 配置文件CGI 公共网关接口脚本文件CGM 计算机图形元文件CHK 由Windows磁盘碎片整理器或磁盘扫描保存的文件碎片CHM 编译过的HTML文件CHR 字符集(字体文件)CIF Adaptec CD 创建器CD映像文件CIL Clip Gallery下载包CLASS Java类文件CLL Crick Software Clicker文件CLP Windows 剪贴板文件CLS Visual Basic类文件CMF Corel元文件CMV Corel Move动画文件CMX Corel Presentation Exchange图像CNF Telnet,Windows和其他其内格式会发生改变的应用程序使用的配置文件CNM Windows应用程序菜单选项和安装文件CNT Windows(或其他)系统用于帮助索引或其他目的内容文件COD Microsoft C编译器产生的可显示机器码/汇编代码文件,其中附有源C代码作为注释COM 命令文件(程序)CPL 控制面板扩展名,Corel颜色板CPO Corel打印存储文件CPP C++代码文件CPR Corel提供说明书文件CPT Corel 照片-绘画图像CPX Corel Presentation Exchange压缩图形文件CRD Windows Cardfile文件CRP Corel 提供的运行时介绍文件;Visual dBASE自定义报表文件CRT 认证文件CSC Corel脚本文件CSP PC Emcee On_Screen图像CST Macromedia Director Cast文件CSV 逗号分隔的值文件CTL 通常用于表示一个包含控件信息的文件;FaxWork用它来保持有关每个传真收到或发出的信息CUR Windows光标文件CV Corel版本的档案文件;Microsoft CodeView信息屏幕文件CXX C++源代码文件D开头扩展名说明DAT 数据文件;WrodPerfect合并数据文件;用于一些MPEG格式的文件DB Borland的Paradox 7表DBC Microsoft Visual FoxPro数据库容器文件DBF dBASE文件DBX DataBearn图像;Microsoft Visual FoxPro表格文件DCM DCM模块格式文件DCS 桌面颜色分隔文件DCT Microsoft Visual FoxPro数据库容器DCU Delphi编译单元文件DCX Microsoft Visual FoxPro数据库容器;基于PCX的传真图像;宏DEM 用于表示数字高度模型的USGS基准的文件DER 认证文件DEWF Macintosh Sound Cap/Sound Edit录音设备格式DIB 设备无关位图DIC 目录DIF 可进行数据互换的电子表格DIG DigiLink格式;Sound DesignerⅠ音频文件DIR Macromedia Director文件DIZ 描述文件DLG C++对话框脚本文件DLL 动态链接库DLS 可下载声音文件DMD Visual dBASE数据模块文件DMF X-Trakker音乐模块(MOD)文件DOC Word文档DOT Microsoft Word文档模板DRAW Acorn的基于对象的矢量图像文件DRV 驱动程序DRW Micrografx Designer/Draw;Pro/E绘画文件DSF Micrografx Designer VFX文件DSG DOOM保存的文件DSM Dynamic Studio音乐模块(MOD)文件DSP Microsoft Developer Studio工程文件DSQ Corel QUERY(查询)文件DSW Microsoft Developer Studio工作区文件DTD SGML文档类型定义(DTD)文件DUN Microsoft拔号网络导出文件DV 数字视频文件(MIME)DXF 可进行互交换的绘图文件格式,二进制的DWG格式的文本表示;数据交换文件DXR Macromedia Director受保护(不可编辑)电影文件E开头扩展名说明EDA Ensoniq ASR磁盘映像EDD 元素定义文档(FrameMaker+SGML文档)EMD ABT扩展模块EMF Windows增强元文件EML Microsoft Outlook Express邮件消息(MIME RTC822)文件EPHTML Perl解释增强HTML文件EPS 压缩的PostScript图像EXE 可执行文件(程序)F开头扩展名说明FAV Microsoft Outlook导航条FAX 传真类型图像FCD 虚拟CD-ROMFDF A dobe Acrobat表单文档文件FFA/FFL/FFO/FFK Microsoft快速查找文件FIF Fractal图像文件FLA Macromedia Flash电影FLC Autodesk FLIC动画文件PLI Autodesk FLIC动画FM Adobe FrameMaker文档FML 文件镜象列表(GetRight)FNG 字体组文件(字体导航器,Font Navigator)FNK Funk Tracker模块格式FON 系统字体FOT 字体相关文件FRT Microsoft FoxPro报表文件FRX Visual Basic表单文本;Microsoft FoxPro报表文件FTG 全文本搜索组文件,由Windows帮助系统查找时产生--可以删除,并在需要时重建起来FTS 全文本搜索引文件,由Windows帮助系统查找时产生G开头扩展名说明GAL Corel多媒体管理器相集GDB InterBase数据库文件GDM 铃声、口哨声和声音板模块格式GEM GEM元文件GEN Ventura产生的文本文件GetRight GetRight未完成的下载文件GFI/GFX Genigraphics图形链接表示文件GHO Norton 克隆磁盘映像GIF CompuServe位图文件GIM/GIX Genigraphics图形链接介绍文件GKH Ensoniq EPS家簇磁盘映像文件GKS Gravis Grip Key文档GL 动画格式GNA Genigraphics图形链接介绍文件GNT 生成代码,Micro Focus属性格式里的可执行代码GNX Genigraphics图形链接介绍文件GRA Microsoft Graph文件GRF Grapher(Golden Software公司)图形文件GRP 程序管理组H开头扩展名说明HCOM 声音工具HCOM格式HGL HP图形语言绘图文件HLP 帮助文件;Date CAD Windows帮助文件HPJ Visual Basic帮助工程HPP C++程序头文件HST 历史文件HT HyperT erminal(超级终端)HTM/HTML 超文本文档HTT Microsoft超文本模板HTX 扩展HTML模板I开头扩展名说明ICB Targa位图文件ICC Kodak打印机格式文件ICL 图标库文件ICM 图形颜色匹配配置文件ICO Windows图标IDD MIDI设备定义IDF MIDI设备定义(Windows 95需要的文件)IDQ Internet数据查询文件IDX Microsoft FoxPro相关数据库索引文件;Symantec Q&A相关数据库索引文件;Microsoft Outlook Express文件IFF 交换格式文件;Amiga ILBMIGES 初始图形交换说明文件IGF 插入系统元文件ILBM 位图图形文件IMA WinImage磁盘映像文件INF 信息文件INI 初始化文件INRS INRS远程通信声频INS InstallShield安装脚本INT 中间代码,当一个源程序经过语法检查后编译产生一个可执行代码IQY Microsoft Internet查询文件ISO 根据ISD 9660有关CD-ROM文件系统标准列出CD-ROM上的文件IST 数字跟踪设备文件ISU InstallShield卸装脚本IWC Install Watch文档J开头扩展名说明J62 Ricoh照相机格式JAR Java档案文件JAVA Java源文件JBF Paint Shop Pro图像浏览文件JFF/JFIF/JIF JPEG文件JMP SAS的JMPDiscovery表格统计文件JPE/JPEG/JPG JPEG图形文件JS Javascript源文件JSP HTML网页,其中包含有对一个Java servlet的参考JTF JPEG位图文件K开头扩展名说明K25 Kurzweil 2500抽样文件KAR 卡拉OK MIDI文件KDC Kodak光增强器KEY DataCAD图标工具条文件KFX KoFak Group 4图像文件KIZ Kodak数字明信片文件KKW RoboHELP帮助工程索引设计器中与主题无关的K开头的所有关键字KMP Korg Trinity KeyMap文件KQP Konica照相机本地文件L开头扩展名说明LAB Visual dBASE标签文件LBM Deluxe Paint位图文件LBT/LBX Microsoft FoxPro标签文件LDB Microsoft Access加锁文件LDL Corel Paradox分发库LEG Legacy文档LFT 3D Studio(DOS)放样文件LGO Paintbrush(Microsoft画图应用程序)的徽标文件LHA LZH更换文件后缀LIB 库文件LIN DataCAD线型文件LIS 结构化查询报告(SQR)程序产生的输出文件LLX Laplink交换代理LNK Windows快捷方式文件LOG 日志文件LST 列表文件LU ThoughtWing库单元文件LYR DataCAD层文件LZH LH ARC压缩档案LZS Skyroads数据文件M开头扩展名说明M1V MPEG相关文件(M3U MPEG URL(MIME声音文件)MAD Microsoft Access模块文件MAF Microsoft Access表单文件MAM Microsoft Access宏MAP 映射文件;Duke Nukem 3D WAD游戏文件MAQ Microsoft Access查询文件MAR Microsoft Access报表文件MAT Microsoft Access表;3D Studio MAX材料库MB1 Apogee Monster Bash数据文件MBX Microsoft Outlook保存email格式;Eudora邮箱MCR DataCAD键盘宏文件MDB Microsoft Access数据库MDE Microsoft Access MDE文件MDL 数字跟踪器音乐模块(MOD)文件;Quake模块文件MDN Microsoft Access空数据库模板MDW Microsoft Access工作组文件MDZ Microsoft Access向导模板文件MIC Microsoft Image Composer文件MID MIDI音乐MIM,MIME,MME Internet邮件扩展格式的多用途文件,经常作为发送e-mail时在AOL 里附件而创建的文件;在一个多区MIM文件里的文件能用WinZip或其他类似程序打开MLI 3D Studio的材料库格式文件MNG 多映像网络图形MNU Visual dBASE菜单文件;Intertel Systems Interact菜单文件MOD Fast Tracker、Star Trekker、Noise Tracker(等等)音乐模块文件;Microsoft多计划电子表格;Amiga/PC磁道文件MOV QuickTime for Windows电影MP2 第二层MPEG音频文件MP3 第三层MPEG音频文件MPA MPEG相关文件,MIME“mpeg类型”MPE/MPEG/MPG MPEG动画文件MPP Microsoft工程文件;CAD绘图文件格式MPR Microsoft FoxPro菜单(已编译)MSG Microsoft邮件消息MSI Windows 安装文件包MSN Microsoft网络文档;Descent Mission文件MSP Microsoft Paint(画图)位图文件;Windows Installer路径文件MST Windows 安装器传输文件MTM Multi 跟踪器音乐模块(MOD)文件N开头扩展名说明NAN Nanoscope文件(Raw Grayscale)NAP NAP元文件NCB Microsoft Developer Studio文件NCD Norton改变目录NCF NetWare命令文件;Lotus Notes内部剪切板NFF 中性文件格式NFT NetObject Fusion模板文件NIL Norton光标库文件(EasyIcons-兼容)NIST NIST Sphere声音NLS 用于本地化的国家语言支持文件(例如,Uniscape)NLU Norton Live Update e-mail 触发器文件NTX CA-Clipper索引文件NWC Noteworthy Composer歌曲文件NWS Microsoft Outlook Express新闻消息O开头扩展名说明OBJ 对象文件OCX Microsoft对象链接与嵌入定制控件ODS Microsoft Outlook Express邮箱文件OFN Microsoft Office FileNew文件OFT Microsoft Outlook模板OLB OLE对象库OLE OLE对象OOGL 面向对象图形库OPO OPL输出可执行文件P开头扩展名说明P65 PageMaker 6.5文件PAB Microsoft个人地址簿PART Go!Zilla部分下载文件PAS Pascal源代码PBD PowerBuilder动态库,作为本地DLL的一个替代物PBL 用于在PowerBuilder开发环境中的PowerBuilder动态库PBM 可导出位图PBR PowerBuilder资源PCD Kodak Photo-CD映像;P-Code编译器测试脚本,由Microsoft测试与Microsoft Visual 测试PCL Hewlett-Packard打印机控制语言文件(打印机备用位图)PCM 声音文件格式;OKI MSM6376 合成芯片PCM格式PDD 可以用Paint Shop Pro或其他图像处理软件打开的图形图像PDF Adobe Acrobat 可导出文档格式文件(可用Web浏览器显示);Microsoft系统管理服务器包定义文件;NetWare打印机定义文件PFM 打印机字体尺度PGL HP绘图仪绘图文件PGM 可输出灰度图(位图)PH 由Microsoft帮助文件编译器产生的临时文件PHP/PHP3 包含有PHP脚本的HTML网页PHTML 包含有PHP脚本的HTML网页;由Perl分析解释的HTML PIC PC画图位图;Lotus图片;Macintosh PICT绘图PJX/PJT Microsoft Visual FoxPro工程文件PKG Microsoft Developer Studio应用程序扩展(与DLL文件类似)PNG 可移植的网络图形位图;Paint Shop Pro浏览器目录POT Microsoft Powerpoint模块PPA Microsoft Powerpoint内插器PPF Turtle Beach的Pinnacle程序文件PPM 可移植的象素映射位图PPS Microsoft Powerpoint幻灯片放映PPT Microsoft Powerpoint演示文稿PRF Windows系统文件,Macromedia导演设置文件PRG dBASE Clipper和FoxPro程序源文件;WAVmaker程序PRJ 3D Studio(DOS)工程文件PRN 打印表格(用空格分隔的文本);DataCAD Windows打印机文件PRT 打印格式化文件;Pro/ENGINEER元件文件PSD Adobe photoshop位图文件PSP Paint Shop Pro图像文件PST Microsoft Outlook个人文件夹文件PWZ Microsoft Powerpoint向导Q开头扩展名说明QIC Microsoft备份文件QIF QuickTime相关图像(MIME);Quicken导入文件QLB Quick库QRY Microsoft查询文件QTP QuickTime优先文件QTX QuickTime相关图像QW Symantec Q&A Write程序文件R开头扩展名说明RA RealAudio声音文件RAM RealAudio元文件RAR RAR压缩档案(Eugene Roshall格式)RDF 资源描述框架文件(涉及XML和元数据)REG 注册表文件REP Visual dBASE报表文件RES Microsoft Visual C++资源文件RFT 可修订的表单文本(IBM的DCA一部分或文档内容框架结构一部分)RGB/SGI Silicon图形RGB文件RM RealAudio视频文件RMD Microsoft RegMaid文档RPT Microsoft Visual Basic Crystal报表文件RTF Rich Text格式文档RUL InstallShield使用的扩展名RVP Microsoft Scan配置文件(MIME)S开头扩展名说明S 汇编源代码文件SAV 游戏保存文件SBL Shockwave Flash对象文件SCC Microsoft Source Safe文件SCF Windows Explorer命令文件SCP 拨号网络脚本文件SCR Windows屏幕保护;传真图像;脚本文件SCT SAS目录(DOS);Scitex CT位图;Microsoft FoxPro表单SCX Microsoft FoxPro表单文件SDT SmartDraw模板SDV 分号分隔的值文件SDX 由SDX压缩的MIDI抽样转储标准文件SEP 标签图像文件格式(TIFF)位图SFD SoundStage声音文件数据SFI Sound Stage声音文件信息SFR Sonic Foundry Sample资源SFX RAR自解压文件SGML 标准通用标签语言SHG 热点位图SHTML 含有服务器端包括(SSI)的HTML文件SHW Corel Show演示文稿SIG 符号文件SKA PGP秘钥SKL Macromedia导演者资源文件SL PACT的保存布局扩展名SPL Shockwave Flash对象;DigiTrakker抽样SQC 结构化查询语言(SQR)普通代码文件SQR 结构化查询语言(SQR)程序文件STR 屏幕保护文件SWA 在Macromedia导演文件(MP3文件)中的Shockwave声音文件SWF Shockwave Flash对象SYS 系统文件SYW Yamaha SY系列波形文件T开头扩展名说明TAZ UNIX gzip/tape档案TGA Targa位图THEME Windows桌面主题文件THN Graphics WorkShop for Windows速写TIF/TIFF 标签图像文件格式(TIFF)位图TIG 虎形文件,美国政府用于分发地图TLB OLE类型库TMP Windows临时文件TOL Kodak照片增强器TPL CakeWalk声音模板文件;DataCAD模板文件TRM 终端文件TRN MKS源完整性工程用法日志文件TTF TrueType字体文件TXT ASCⅡ文本格式的声音数据TXW Yamaha TX16W波形文件U开头扩展名说明UDF Windows NT/2000唯一性数据库文件ULT Ultra Tracker音乐模块(MOD)文件URL Internet快捷方式文件USE MKS源完整性文件UWF Ultra racker波形文件V开头扩展名说明VBP Microsoft Visual Basic工程文件VBW Microsoft Visual Basic工作区文件VBX Microsoft Visual Basic用户定制控件VCT/VCX Microsoft FoxPro类库VDA Targa位图VIR Norton Anti-Virus或其他杀毒产品用于标识被病毒感染的文件VIV VivoActive Player流视频文件VSD Visio绘画文件(流程图或图解)VSL 下载列表文件(GetRight)VSS Visio模板文件VST Targa位图VSW Visio工作区文件VXD Microsoft Windows虚拟设备驱动程序VBP Microsoft Visual Basic工程文件VBW Microsoft Visual Basic工作区文件VBX Microsoft Visual Basic用户定制控件VDA Targa位图VIR Norton Anti-Virus或其他杀毒产品用于标识被病毒感染的文件VQF Yamaha Sound-VQ文件(可能出现标准)VSD Visio绘画文件(流程图或图解)VSL 下载列表文件(GetRight)VSS Visio模板文件VST Targa位图VSW Visio工作区文件VXD Microsoft Windows虚拟设备驱动程序W开头扩展名说明W3L W3Launch文件WAB M icrosoft Outlook文件WAD 包含有视频、玩家水平和其他信息的DOOM游戏的大文件WAV Windows波形声形WBK Microsoft Word备份文件WCM WordPerfect宏WDB Microsoft Works数据库WFM Visual dBASE Windows表单WFN 在CorelDRAW中使用的符号WIL WinImage文件WIZ Microsoft Word向导WLL Microsoft Word内插器WMF Windows元文件WOW Grave Composer音乐模块(MOD)文件WP WordPerfect文档WPD WordPerfect文档或演示WPF 可字处理文档WPG WordPerfect图形WPS Microsoft Works文档WPT WordPerfect模板WR1 书写器文档WRK Cakewalk音乐声音工程文件WRL 虚拟现实模型WRZ VRML文件对象X开头扩展名说明X AVS图像格式XAR CorelXARA绘画XBM MIME“xbitmap”图像XI Scream Tracker设备抽样文件XLA Microsoft Excel内插器XLB Microsoft Excel工具条XLC Microsoft Excel图表XLD Microsoft Excel对话框XLK Microsoft Excel备份XLL Microsoft Excel内插器文件XLM Microsoft Excel宏XLS Microsoft Excel工作单XLT Microsoft Excel模板XLV Microsoft Excel VBA模块XLW Microsoft Excel工作簿/工作区XNK Microsoft Exchange快捷方式文件XPM X位图格式XWD X Windows转储格式XWF Yamaha XG Works文件(MIDI序列)X16 宏媒体扩展(程序扩展),16位X32 宏媒体扩展(程序扩展),32位Y开头扩展名说明YAL Arts& Letters剪贴艺术库Z开头扩展名说明Z UNIX gzip文件ZAP Windows软件安装配置文件ZIP Zip文件。
cDLL编程详解DLL(Dynamic Link Library)的概念,你可以简单的把DLL看成一种仓库,它提供给你一些可以直接拿来用的变量、函数或类。
在仓库的发展史上经历了“无库-静态链接库-动态链接库”的时代。
静态链接库与动态链接库都是共享代码的方式,如果采用静态链接库,则无论你愿不愿意,lib中的指令都被直接包含在最终生成的EXE文件中了。
但是若使用DLL,该DLL不必被包含在最终EXE文件中,EXE文件执行时可以“动态”地引用和卸载这个与EXE独立的DLL文件。
静态链接库和动态链接库的另外一个区别在于静态链接库中不能再包含其他的动态链接库或者静态库,而在动态链接库中还可以再包含其他的动态或静态链接库。
DLL:(1)DLL 的编制与具体的编程语言及编译器无关只要遵循约定的DLL接口规范和调用方式,用各种语言编写的DLL都可以相互调用。
譬如Windows提供的系统DLL(其中包括了Windows的API),在任何开发环境中都能被调用,不在乎其是Visual Basic、Visual C++还是Delphi。
(2)动态链接库随处可见我们在Windows目录下的system32文件夹中会看到kernel32.dll、user32.dll和gdi32.dll,windows的大多数API都包含在这些DLL中。
kernel32.dll中的函数主要处理内存管理和进程调度;user32.dll中的函数主要控制用户界面;gdi32.dll中的函数则负责图形方面的操作。
一般的程序员都用过类似MessageBox的函数,其实它就包含在user32.dll这个动态链接库中。
由此可见DLL对我们来说其实并不陌生。
(3)VC动态链接库的分类Visual C++支持三种DLL,它们分别是Non-MFC DLL(非MFC 动态库)、MFC Regular DLL(MFC规则DLL)、MFC ExtensionDLL(MFC扩展DLL)。
第1课DLL基础一、静态链接库(Static Link Library)程序员们把常用的代码集合放进独立的文件里,这样的文件就叫做库。
在写程序的时候,把这个库文件加入编译器,就能够使用这个库包含的所有功能而不必自己再去写一大堆代码。
但是这种方法会把库里所有的东西都包含进去,造成程序体积的增大。
二、动态链接库Dynamic Link Library(DLL)DLL的格式和EXE文件是一样的,但是不能直接执行。
它把代码封装到自己的内部,只是提供函数接口让外面的EXE程序调用。
在编译的时候不会将所包含的动态链接库编译到程序中。
编译的时候用.lib文件,执行的时候用.dll文件第2课DLL基础再讨论一、动态链接库的模块定义文件(.def)模块定义文件是一个有着.def文件扩展名的文本文件。
它被用于导出DLL的函数。
一二、动态链接库的入口函数(DLLMain()函数)每一个DLL必须有一个入口函数,DLLMain()函数是一个缺省的入口函数。
DLLMain()函数负责初始化和结束工作。
每当一个新的进程或该进程的新线程访问DLL时,或者访问第3次课进程权限的提升一、OpenProcessToken函数打开进程令牌环二、LookupPrivilegeValue函数获得进程本地唯一ID三、AdjustTokenPrivileges函数提升进程的权限第4次课远程线程的创建一、打开远程进程OpenProcess函数二、在远程进程的内存中分配空间VirtualAllocEx函数三、远程进程的内存的写入WriteProcessMemory函数四、找到LoadLibrary函数在Kernel32中的地址GetProcAddress函数五、在远程进程中线程(远程线程)CreateRemoteThread函数第5次课进程ID的获取一、系统进程快照CreateToolhelp32Snapshot函数二、在快照中搜索指定进程Process32First函数。
Features•CS5334Dynamic Range: 100 dBTHD+N: -90 dB•CS5335Dynamic Range: 105 dBTHD+N: -95 dB•128X Oversampling •Fully Differential Inputs•Linear Phase Digital Anti-Alias Filtering21.7 kHz passband (fs = 48kHz)85 dB stop band attenuation 0.0025 dB pass band ripple•High Pass Filter - DC offset removal •Peak Signal Level DetectorHigh Resolution and Bar Graph ModesGeneral DescriptionThe CS5334 and CS5335 are 2-channel, single +5V supply, pin compatable analog-to-digital converters for digital audio systems. The CS5334 and CS5335 perform sampling, analog-to-digital conversion and anti-alias fil-tering, generating 20-bit values for both left and right inputs in serial form. The output word rate can be up to 50 kHz per channel.The CS5334 and CS5335 use 4th-order, delta-sigma modulation with 128X oversampling followed by digital filtering and decimation, which removes the need for an external anti-alias filter. These ADCs use a differential architecture which provides excellent noise rejection.The CS5334 and CS5335 have a filter passband to 21.7kHz. The filter has linear phase, 0.0025 dB pass-band ripple, and >85 dB stopband rejection. An on-chip high pass filter is also included to remove DC offsets.ORDERING INFORMATION:Model Temp. Range Package Type CS5334-KS -10° to 70°C 20-pin Plastic SSOP CS5335-KS -10° to 70°C 20-pin Plastic SSOPCrystal Semiconductor Corporation NOV ’9620-Bit, Stereo A/D Converter for Digital AudioPUDGNDSDATA AGNDDIF1DIF0HP DEFEATCMOUTCS5334 CS5335This document contains information for a new product. CrystalSemiconductor reserves the right to modify this product without notice.Preliminary Product InformationSpecifications are subject to change without noticeANALOG CHARACTERISTICS (T A = 25°C; VA+ = VD+ = 5V; -1 dBFS Input Sinewave, 997 Hz;Fs = 48 kHz; MCLK = 12.288 MHz; SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Logic 0 = 0V, Logic 1 = VD+)CS5334CS5335ParameterSymbolMin Typ Max Min Typ Max Units Resolution20--20--Bits Dynamic PerformanceDynamic RangeA-weightedTBD TBD 10097--TBD TBD 105102--dB dB Total Harmonic Distortion + Noise-1 dB -20 dB -60 dBTHD+N----90-77-37TBD TBD TBD ----95-82-42TBD TBD TBD dB dB dB Interchannel Phase Deviation -0.01--0.01-Degree Interchannel Isolation(dc to 20 kHz)-100--105-dB dc AccuracyInterchannel Gain Mismatch -0.05--0.05-dB Gain Error --±5--±5%Gain Drift -200--200-ppm/°C Offset Errorwith HPFHP defeat with CAL--0+/-100----0+/-100--LSB LSBAnalog InputInput Voltage Range (Differential)VIN 1.9 2.0 2.1 1.9 2.0 2.1Vrms Input Impedance ZIN-30--30-k ΩInput Bias Voltage- 2.2-- 2.2-V Power SuppliesPower Supply CurrentI A I DPower Down (I A +I D )---38250.2TBD TBD ----40250.2TBD TBD -mA mA mA Power DissipationNormal Power Down--3151.0TBD ---3251.0TBD -mW mW Power Supply Rejection Ratio-50--55-dBDIGITAL FILTER CHARACTERISTICS (T A = 25 °C; VA+ = VD+ = 5V ± 5%; Fs = 48 kHz)Parameter Symbol Min Typ Max Units Passband(Note 1)0.02-21.7kHz Passband Ripple--±0.0025dB Stopband(Note 1)26.3-6118kHz Stopband Attenuation(Note 2)85--dB Group Delay (Fs = Output Sample Rate)t gd-32/Fs-s Group Delay Variation vs. Frequency∆t gd--0µs High Pass Filter CharacteristicsFrequency Response:-3 dB(Note 1)-0.01 dB --0.920--HzHzPhase Deviation@ 20 Hz(Note 1)- 2.6-Degree Passband Ripple--0dB Notes: 1.Filter characteristic scales with output sample rate.2.The analog modulator samples the input at 6.144 MHz for an output sample rate of 48 kHz. There isno rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.7kHzwhere n = 0,1,2,3...).DIGITAL CHARACTERISTICS (T A = 25 °C; VA+ = VD+ = 5V ± 5%)Parameter Symbol Min Typ Max Units High-Level Input Voltage V IH 2.4--V Low-Level Input Voltage V IL--0.8V High-Level Output Voltage at lo = -20 µA V OH(VD+)-1.0--V Low-Level Output Voltage at lo = 20 µA V OL--0.4V Input Leakage Current I in--10µAABSOLUTE MAXIMUM RATINGS (AGND = 0V, all voltages with respect to ground.)Parameter Symbol Min Typ Max Units DC Power Supply:VA+-0.3-+6.0V Input Current, Any Pin Except Supplies(Note 3)Iin--±10mA Analog Input Voltage(Note 4)V INA-0.7-(VA+)+0.7V Digital Input Voltage(Note 4)V IND-0.7-(VA+)+0.7V Ambient Temperature (power applied)T A-55-+125°C Storage Temperature T stg-65-+150°C Notes: 3.Any Pin except supplies. Transient currents of up to +/- 100 mA on the analog input pins will not cause SCR latch-up.4.The maximum over/under voltage is limited by the input current.WARNING:Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.SWITCHING CHARACTERISTICS(T A = 25 °C; VA+ = 5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VA+ = VD+; C L = 20 pF)Parameter Symbol Min Typ Max Units Output Sample Rate F s 2.0-50kHz MCLK Period MCLK / LRCK = 256t clkw78-1953ns MCLK Low MCLK / LRCK = 256t clkl31--ns MCLK High MCLK / LRCK = 256t clkh31--ns MCLK Period MCLK / LRCK = 384t clkw52-1302ns MCLK Low MCLK / LRCK = 384t clkl20--ns MCLK High MCLK / LRCK = 384t clkh20--ns MCLK Period MCLK / LRCK = 512t clkw39-976ns MCLK Low MCLK / LRCK = 512t clkl15--ns MCLK High MCLK / LRCK = 512t clkh15--ns MASTER MODESCLK falling to LRCK (Note 5)t mslr-10-10ns SCLK falling to SDATA valid(Note 5)t sdo-10-35ns SCLK Duty cycle-50-% SCLK falling to Frame Valid(Note 5)t sfo-10-(Note 6)ns LRCK edge to OVFL Valid t ovfl-10-30ns LRCK edge to OVFL edge delay t ovfl-10-(Note 10)ns SLAVE MODELRCK duty cycle255075% SCLK Period t sclkw(Note 7)--ns SCLK Pulse Width Low(Note 8)t sclkl(Note 11)--ns SCLK Pulse Width High (Note 9)t sclkh50--ns SCLK falling to SDATA valid(Note 5)t dss--(Note 11)ns LRCK edge to MSB valid t lrdss--(Note 11)ns SCLK rising to LRCK edge delay(Note 12)t slr150--ns LRCK edge to rising SCLK setup time(Note 12)t slr2(Note 11)--ns SCLK falling to Frame delay t sfo--(Note 13)nsNotes: 5.SCLK rising for Mode 1. 6.1(1024)(F s)+ 30ns7.1(96)(F s)8.Pulse Width High for Mode 19.Pulse Width Low for Mode 110.1(512)(F s)+ 20ns11.1(512)(F s)+ 50ns12.SCLK Falling for Mode 113.1(384)(F s)+35nsSDATASCLK input (SLAVE mode)(SLAVE mode)LRCK inputtt OVFLSCLK to LRCK & SDATA - SLAVE modeFormat 2SCLK outputSDATALRCK outputOVFLSCLK to SDATA & LRCK - MASTER modeFormat 2SCLK output*SDATALRCK outputOVFLSCLK to SDATA & LRCK - MASTER modeFormat 0 and 1SDATASCLK input*(SLAVE mode)(SLAVE mode)LRCK inputOVFLSCLK to LRCK & SDATA - SLAVE modeFormat 0 & 1 SCLK*FRAMESCLK to Frame Delay*SCLK is inverted for Format 1***Figure 1. Typical Connection DiagramSYSTEM DESIGNThe CS5334 and CS5335 are 20-bit, 2-channel Analog-to-Digital Converters designed for digital audio applications. These devices use two one-bit delta-sigma modulators which simultaneously sample the analog input signals at 128 times the output sample rate (Fs). The resulting serial bit streams are digitally filtered, yielding a pair of 20-bit values. This technique yields nearly ideal conversion performance independent of input frequency and amplitude. The converter does not require difficult-to-design or expensive anti-alias filters and does not require external sample-and-hold amplifiers or a voltage reference. V ery few external components are required to support these ADCs. Normal power supply decoupling components and a resistor and capacitor on each input for anti-aliasing are all that’s required, as shown in Figure 1.An on-chip voltage reference provides for a dif-ferential input signal range of 2.0 Vrms. Output data is available in serial form, coded as 2’s complement, 20-bit numbers. Typical power consumption is 325 mW which can be reduced to 1.0 mW using the power-down feature.Master ClockThe master clock (MCLK) is the clock source for the delta-sigma modulator sampling and digi-tal filters. In Master Mode, the frequency of this clock must be 256× Fs. In Slave Mode, the mas-ter clock must be either 256×, 384× or 512× Fs.Table 1 shows some common master clock fre-quencies.SERIAL DATA INTERFACEThe CS5334 and CS5335 support three serial data formats, including I 2S, which are selected via the digital input format pins DIF0 and DIF1.The digital input format determines the relation-ship between the serial data, left/right clock and serial clock. Table 2 lists the three formats, along with the associated figure number. The serial data interface is accomplished via the serial data output, SDA TA, serial data clock, SCLK, and the left/right clock, LRCK.Serial DataThe serial data block consists of 20 bits of audiodata presented in 2’s-complement format with the MSB-first, followed by 4 bits of zero and 8Peak Signal Level, PSL, bits as shown in Fig-ure 2. The data is clocked from SDA TA by the serial clock and the channel is determined by the Left/Right clock.LRCK (kHz)MCLK (MHz)256 X 384 X 512 X328.192012.288016.384044.111.289616.934422.57924812.288018.432024.5760Table 1. Common Clock FrequenciesSDATA FRAME20 AudioFigure 2. Data Block and FrameDIF1DIF0FORMAT FIGURE 00030114102511power-down -Table 2. Digital Input FormatsSDATAFRAMESCLKLRCKMASTERSLAVE20-Bit Left Justified Data20-Bit Left Justified DataData Valid on Rising Edge of 64x SCLKData Valid on Rising Edge of SCLK MCLK equal to 256x F s MCLK equal to 256x, 384x or 512x F sFigure 3. Serial Data Format 0SDATAFRAMESCLKLRCKMASTERSLAVE20-Bit Left Justified Data20-Bit Left Justified DataData Valid on Falling Edge of 64x SCLK Data Valid on Falling Edge of SCLK MCLK equal to 256x F sMCLK equal to 256x, 384x or 512x F sFigure 4. Serial Data Format 1SDATAFRAMESCLKLRCK MASTERSLAVEI 2S 20-Bit DataI 2S 20-Bit DataData Valid on Rising Edge of 64x SCLK Data Valid on Rising Edge of SCLK MCLK equal to 256x F s MCLK equal to 256x, 384x or 512x F sFigure 5. Serial Data Format 2Serial ClockThe serial clock shifts the digitized audio data from the internal data registers via the SDA TA pin. SCLK is an output in Master Mode. Internal dividers will divide the master clock by 4 to generate a serial clock which is 64× Fs. In Slave Mode, SCLK is an input with a serial clock typically between 48× and 128× Fs. How-ever, the serial clock must be a minimum of 64×Fs to access the Peak Signal Level bits.Left / Right ClockThe Left/Right clock determines which channel, left or right, is to be output on SDA TA. Although the outputs for each channel are transmitted at different times, Left/Right pairs represent simul-taneously sampled analog inputs. In Master Mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is an input whose frequency must be equal to the output sample rate, Fs.Master ModeIn Master mode, SCLK and LRCK are outputs which are internally derived from the Master Clock. Internal dividers will divide MCLK by 4 to generate a SCLK which is 64× Fs and by 256 to generate a LRCK which is equal to Fs. Master mode is only supported with a 256× master clock. The CS5334/5 is placed in the Master mode with a 47 kΩ pull-down resistor on the OVFL pin.Slave ModeLRCK and SCLK become inputs in SLA VE mode. LRCK must be externally derived from MCLK and be equal to Fs. The serial clock is typically between 64× and 128× Fs. A 48× Fs serial clock is possible though will not allow ac-cess to the Peak Signal Level bits. Master clock frequencies of 256×, 384× and 512× Fs are sup-ported. The ratio of the applied master clock to the left/right clock is automatically detected dur-ing power-up and internal dividers are set to gen-erate the appropriate internal clocks.Analog ConnectionsFigure 1 shows the analog input connections. The analog inputs are presented to the modula-tors via the AINR+/- and AINL+/- pins. Each analog input pin will accept a maximum of 1 Vrms centered at +2.2 V olt as shown in Fig-ure 6. Input signals can be AC or DC coupled and the CMOUT output may be used as a refer-ence for DC coupling. However, CMOUT is not buffered and the maximum current is 10 µA. The CS5334 and CS5335 sample the analog in-puts at 128×Fs, 6.144 MHz for a 48 kHz sample-rate. The digital filter rejects all noise above 26.3 kHz except for frequencies right around 6.144 MHz ± 21.7 kHz (and multiples of 6.144 MHz). Most audio signals do not have sig-nificant energy at 6.144 MHz. Nevertheless, a 150 Ω resistor in series with each analog input and a 2.2 nF capacitor across the inputs will at-tenuate any noise energy at 6.144 MHz, in addition to providing the optimum source imped-ance for the modulators. The use of capacitors which have a large voltage coefficient must be avoided since these will degrade signal linearity. NPO and COG capacitors are acceptable. If ac-tive circuitry precedes the ADC, it is recommended that the above RC filter is placed between the active circuitry and the AINR and AINL pins. The above example frequencies scale linearly with sample rate.3.6 V2.2 V0.78 V3.6 V2.2 V0.78 VCS5334CS5335AIN+AIN-Full Scale Input level= (AIN+) - (AIN-)= 5.67 VppFigure 6. Full Scale Input LevelsHigh Pass FilterThe operational amplifiers in the input circuitry driving the CS5334/5 may generate a small DC offset into the A/D converter. The CS5334 and CS5335 include a high pass filter after the deci-mator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high pass filter can be disabled with the HP DEFEA T pin. The high pass filter works by continuously subtracting a measure of the dc offset from the output of the decimation filter. If the HP DEFEA T pin is taken high during normal operation, the current value of the dc offset register is frozen and this dc offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system calibration by;1. removing the signal source (or grounding the input signal) at the input to the subsystem con-taining the CS5334/5,2. running the CS5334/5 with the HP DEFEA T pin low (high pass filter enabled) until the filter settles (approximately 1 second), and3. taking the HP DEFEA T pin high, disabling the high pass filter and freezing the stored dc offset.A system calibration performed in this way will eliminate offsets anywhere in the signal path be-tween the calibration point and the CS5334/5.The characteristics of the first-order high pass filter are outlined below for an output sample rate of 48 kHz. This filter response scales line-arly with sample rate.Frequency response:-3 dB @ 0.9 Hz-0.01 dB @ 20 Hz Phase deviation: 2.6 degrees @ 20 Hz Passband ripple:None INPUT LEVEL MONITORINGThe CS5334 and CS5335 include independent Peak Input Level Monitoring for each channel. The analog-to-digital converter continually moni-tors the peak digital signal for both channels, prior to the digital limiter, and records these val-ues in the Active registers. This information can be transferred to the Output registers by a high to low transition on the Peak Update pin (PU) which will also reset the Active register. The Ac-tive register contains the peak signal level since the previous peak update request.The 8-bit contents of the output registers are available in all interface modes and are present in the data block as shown in Figure 2. The monitoring function can be formatted to indicate either High Resolution Mode or Bar Graph Mode. The monitoring function is determined on power-up by the presence of a 47 kohm pull-down resistor on FRAME. The addition of a 47 kohm pull-down resistor on the FRAME pin sets the monitoring function to the Bar Graph mode.High Resolution ModeBits P7-P0 indicate the peak input level since the previous peak update (or low transition on the Peak Update pin). If the full scale input level is exceeded (Bit P7 high), bits P5-P0 represent the peak value up to 3 dB above full-scale in 1 dB steps. If the ADC input level is less than full-scale, bits P5-P0 represent the peak value from -60 dB to 0 dB of full scale in 1 dB steps. The PSL outputs are accurate to within 0.25 dB. Bit P6 provides a coarse means of determining an ADC input idle condition. Bit P7 indicates an ADC overflow condition, if the ADC input levelis greater than full-scale.P7 - Overrange0 - Analog input less than full-scale level1 - Analog input greater than full-scaleP6 - Idle channel0 - Analog input >-60 dB from full-scale1 - Analog input <-60 dB from full-scaleP5 to P0 - Peak Signal Level Bits (1 dB steps) Inputs <0 dB P5 - P00 dB000000-1 dB000001-2 dB000010-60 dB111100Inputs >0 dB P5 - P00 dB000000+1 dB000001+2 dB000010+3 dB000011Bar Graph ModeThis mode provides a decoded output format which indicates the peak Peak Signal Level in a "Bar Graph" format.Input Level P7 - P0Overflow111111110 dB to -3 dB01111111-3 dB to -6 dB00111111-6 dB to -10 dB00011111-10 dB to -20 dB00001111-20 dB to -30 dB00000111-30 dB to -40 dB00000011-40 dB to -60 dB00000001< - 60 dB00000000OverflowOverflow indicates analog input overrange, for both the Left and Right channels, since the last update request on the Peak Update pin. A value of 1 indicates an overrange condition. The left channel information is output on OVFL during the left channel portion of LRCK. The right channel information is available on OVFL during the right channel portion of LRCK. InitializationUpon initial power-up, the digital filters and delta-sigma modulators are reset and the internal voltage reference is powered down. The CS5334/5 will remain in the power-down mode until valid clocks are presented. A valid MCLK is required to exit power-down in Master Mode. However, in Slave Mode, MCLK and LRCK of the proper ratio are required to exit power-down. MCLK occurrences are also counted over one LRCK period to determine the MCLK / LRCK frequency ratio in Slave Mode. Power is then ap-plied to the internal voltage reference, the analog inputs will move to approximately 2.2V and out-put clocks will begin (Master Mode only). This process requires 32 periods of LRCK and is fol-lowed by the initialization sequence. Initialization with High Pass Filter Enabled 28,672 LRCK cycles are required for the initiali-zation sequence with the high pass filter enabled. This time is dominated by the settling time re-quired for the high pass filter.Initialization and Internal Calibration with High Pass Filter DisabledIf the HP DEFEA T pin is high (high pass filter disabled) during the initialization sequence, the CS5334/5 will perform an internal dc calibration by:1. disconnecting the internal ADC inputs from the input pins,2. connecting the (differential) ADC inputs to acommon reference voltage,DS237PP2113. running the high pass filter with a fast settling time constant,4. freezing the dc offset register, and5. reconnecting the internal ADC inputs to the input pins.This procedure takes 4,160 cycles of LRCK. Unlike the system calibration procedure de-scribed in the High Pass Filter section, a dc calibration performed during start-up will only eliminate offsets internal to the CS5334/5, and should result in output codes which accurately reflect the differential dc signal at the pins.Power-DownThe CS5334 and CS5335 have a power-down mode wherein typical consumption drops to 1.0 mW. This is initiated when a loss of clock is de-tected (either LRCK or MCLK in Slave Mode orDIF0 / DIF1 are at a logic 1. The initialization sequence will begin whenever valid clocks arerestored. If the MCLK / LRCK frequency ratio changes during power-down, the CS5334/5 will adapt to these new operating conditions. How-ever, only the RST method of power-down will include the Master/Slave decision in the initiali-zation sequence.Grounding and Power Supply DecouplingAs with any high resolution converter, the CS5334 and CS5335 require careful attention to power supply and grounding arrangements to op-timize performance. Figure 1 shows the recommended power arrangements with V A+ connected to a clean +5 volt supply. VD+ should be derived from V A+ through a 2 ohm resistor. VD+ should not be used to power additional digital circuitry. All mode pins which require VD+ should be connected to pin 6 of the CS5334/5. All mode pins which require DGND should be connected to pin 5 of the CS5334/5. AGND and DGND, Pins 4 and 5, should be con-nected together at the CS5334/5. DGND for the CS5334/5 should not be confused with the ground for the digital section of the system. The CS5334/5 should be positioned over the analog ground plane near the digital / analog ground plane split. The analog and digital ground planes must be connected elsewhere in the system. The CS5334/5 evaluation board, CDB5334/5, demon-strates this layout technique. This technique minimizes digital noise and insures proper power supply matching and sequencing. Decoupling ca-pacitors should be located as near to theCS5334/5 as possible.12DS237PP2Digital FilterFigures 7-10 show the performance of thedigital filter included in the CS5334/5. Allplots are normalized to Fs. Assuming a samplerate of 48 kHz, the 0.5 frequency point on theplot refers to 24 kHz. The filter frequency re-sponse scales precisely with the sample rate.Figure 7. CS5334/5 Digital Filter Stopband Rejection Figure 9. CS5334/5 Digital Filter Passband RippleFigure 8. CS5334/5 Digital Filter Transition Band Figure 10.CS5334/5 Digital Filter Transition Band DS237PP213PIN DESCRIPTIONSPower Supply ConnectionsV A+ - Positive Analog Power, Pin 3.Positive analog supply. Nominally +5 volts.VD+ - Positive Digital Power, Pin 6.Positive digital supply. Nominally +5 volts.AGND - Analog Ground, Pin 4.Analog ground reference.DGND - Digital Ground, Pin 5.Digital ground reference.Analog InputsAINR-, AINR+ - Differential Right Channel Analog Input, Pin 14 and Pin 13.Analog input connections of the right channel differential inputs. Typically 2 Vrms differential (1Vrms for each input pin) for a full-scale analog input signal.AINL-, AINL+ - Differential Left Channel Analog Input, Pin 16 and Pin 17.Analog input connections of the left channel differential inputs. Typically 2 Vrms differential (1Vrms for each input pin) for a full-scale analog input signal.Analog OutputsCMOUT - Common Mode Output, Pin 15.This output, nominally 2.2V , can be used to bias the analog input circuitry to the common mode voltage of the CS5334/5.High Pass Filter Defeat HP DEFEATDIF0 Digital Interface Format 0OverFlow OVFLDIF1 Digital Interface Format 1Analog Power VA+RST Reset Analog Ground AGNDAINL+ Non-Inverting Left Channel Input Digital Ground DGNDAINL- Inverting Left Channel Input Digital Power VD+CMOUT Common Mode Output Master Clock MCLKAINR- Inverting Right Channel Input Serial Data Clock SCLKAINR+ Non-Inverting Right Channel Input Serial Data Output SDATALRCK Left/ Right Clock Frame Signal FRAME PUPeak Update14DS237PP2Digital InputsMCLK - Master Clock, Pin 7.Clock source for the delta-sigma modulator sampling and digital filters.In Master Mode, the frequency of this clock must be 256× the output sample rate, Fs.In Slave Mode, the frequency of this clock must be either 256×, 384× or 512× Fs.DIF0, DIF1 - Digital Interface Format, Pins 19 and 20.These two pins select one of 3 digital interface formats or power-down. The format determines the relationship between SCLK, LRCK and SDA TA. The formats are detailed in Figures 3-5.A low logic level on this pin activates Reset.HP DEFEAT - High Pass Filter Defeat, Pin 1.A high logic level on this pin disables the digital high pass filter. A low logic level on this pinenables the high pass filter.PU - Peak Update, Pin 11.Transfers the Peak Signal Level contents of the Active Registers to the Output Registers on a high to low transition on this pin. This transition will also reset the Active register.Digital Inputs / OutputsLRCK - Left/Right Clock, Pin 12.LRCK determines which channel, left or right, is to be output on SDA TA. The relationship between LRCK, SCLK and SDA TA is controlled by DIF0 and DIF1. Although the outputs for each channel are transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs. In Master Mode, LRCK is an output clock whose frequency is equal to the output sample rate, Fs. In Slave Mode, LRCK is an input clock whose frequency must be equal to Fs.SCLK - Serial Data Clock, Pin 8.Clocks the individual bits of the serial data out from the SDA TA pin. The relationship between LRCK, SCLK and SDA TA is controlled by DIF0 and DIF1.In Master Mode, SCLK is an output clock with a frequency of 64x the output sample rate, Fs.In Slave Mode, SCLK is an input.Digital OutputsSDATA - Serial Data Output, Pin 9.Two’s complement MSB-first serial data of 20 bits is output on this pin. Included in the serial data output is the 8-bit Input Signal Level Bits. The data is clocked out via the SCLK clock and the channel is determined by LRCK. The relationship between LRCK, SCLK and SDA TA is controlled by DIF0 and DIF1.DS237PP215OVFL - Overflow, Pin 2.Overflow indicates analog input overrange, for both the Left and Right channels, since the last update request on the PEAK UPDA TE (PU) pin. A value of 1 in the register indicates an overrange condition. The left channel information is output on OVFL during the left channel portion of LRCK. The right channel information is available on OVFL during the right channel portion of LRCK. The registers are updated with a high to low transition on the PEAK UPDA TE pin. A 47 kohm pull-down resistor on this pin will set the CS5334/5 in Master Mode. FRAME - Frame Signal, Pin 10.Frames the Peak Signal Level (PSL) Bits. FRAME goes high coincident with the leading edge of the first PSL bit and falls coincident with the trailing edge of the last PSL bit as shown in Figures 3-5. A 47 kohm pull-down resistor on this pin will set the Peak Signal Level Monitoring format to "Bar Graph" mode.PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60dBFs signal. 60dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.Total Harmonic Distortion + Noise (THD+N)The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components.Expressed in decibels. Measured at -1 and -20 dBFs as suggested in AES17-1991 Annex A. Frequency ResponseA measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplituderesponse at 1 kHz. Units in decibels.Interchannel IsolationA measure of crosstalk between the left and right channels. Measured for each channel at theconverter’s output with no signal at the input under test and a full-scale signal applied to the other channel. Units in decibels.Interchannel Gain MismatchThe gain difference between left and right channels. Units in decibels.Gain ErrorThe deviation from the nominal full-scale analog input for a full-scale digital output.16DS237PP2。
DLL文件百科名片DLL是Dynamic Link Library的缩写,意为动态链接库。
DLL文件一般被存放在C:WindowsSystem目录下。
DLL是一个包含可由多个程序同时使用的代码和数据的库。
目录[隐藏]DLL文件简介程序使用 DLL 的优点使用较少的资源推广模块式体系结构简化部署和安装DLL 故障排除工具DLL 的类型DLL文件简介程序使用 DLL 的优点使用较少的资源推广模块式体系结构简化部署和安装DLL 故障排除工具DLL 的类型[编辑本段]DLL文件简介在Windows中,许多应用程序并不是一个完整的可执行文件,它们被分割成一些相对独立的动态链接库,即DLL文件,放置于系统中。
当我们执行某一个程序时,相应的DLL 文件就会被调用。
一个应用程序可有多个DLL文件,一个DLL文件也可能被几个应用程序所共用,这样的DLL文件被称为共享DLL文件。
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Windows 操作系统中的一些作为 DLL 实现的文件·ActiveX 控件 (.ocx) 文件ActiveX 控件的一个示例是日历控件,它使您可以从日历中选择日期。
·控制面板 (.cpl) 文件.cpl 文件的一个示例是位于控制面板中的项。