ARM汇编语言程序设计总结一、常用指令1. 存储器访问指令LDRSTRLDRLoad 32-bit word to Memory.Syntax LDR{ cond } Rd, [Rn]LDR{ cond } Rd, [Rn, offset]LDR{ cond } Rd, [Rn, offset]!LDR{ cond } Rd, labelLDR{ cond } Rd, [Rn], offsetDescription LDR{ cond } Rd, [Rn] (zero offset)Rn is used as address value.LDR{ cond } Rd, [Rn, offset] (Pre-indexed offset)Rn and offset are added and used as address value.LDR{ cond } Rd, [Rn, offset]{!} (Pre-indexed offset with update)Rn and offset are added and used as address value. The new address value is written to Rn.LDR{ cond } Rd, label (Program-relative)The assembler calculates the PC offset and generatesLDR{ cond } Rd, [R15, offset]. LDR{ cond } Rd, [Rn], offset (Post-indexed offset)Rn is used as address value. After memory transfer, the offset is added to Rn.STRStore register 32-bit words to Memory. The address must be 32-bit word-aligned.Syntax STR{ cond } Rd, [Rn]STR{ cond } Rd, [Rn, offset]STR{ cond } Rd, [Rn, offset]!STR{ cond } Rd, labelSTR{ cond } Rd, [Rn], offsetDescription STR{ cond } Rd, [Rn] (zero offset)Rn is used as address value.STR{ cond } Rd, [Rn, offset] (Pre-indexed offset)Rn and offset are added and used as address value.STR{ cond } Rd, [Rn, offset]! (Pre-indexed offset with update)Rn and offset are added and used as address value. The new address value is written to Rn.STR{ cond } Rd, label (Program-relative)The assembler calculates the PC offset and generatesSTR{ cond } Rd, [R15], offset. STR{ cond } Rd, [Rn], offset (Post-indexed offset)Rn is used as address value. After memory transfer, the offset is added to Rn.2. —般数据处理指令ADD SUB ADC SBCAND, ORR, EOR,CMP TSTUMULL, UMLAL, SMULL, and SMLALMUL, MLA, and MLSADCAdd with Carry.Syntax ADC{ cond }{S} Rd, Rn, Op2Description Add Rn and Op2 and Carry flag and store result to Rd. ADC is typical used for multi-word arithmetic.Condition Flags If S is specified update flags: N, Z, C, V.storeresult in R4SUBSubtract registers.Syntax Description Condition Flags SUB{ cond }{S} Rd, Rn, Op2subtracts the value of Op2 from the value in Rn. If S is specified update flags: N,乙C, V.Example SUBS R8,R6,#240 〃R8=R6-240 SBCSBC{ cond }{S} Rd, Rn, Op2 synthesize multiword arithmetic. If S is specified update flags: N,乙 C, V.ANDLogical AND operation.Syntax Description Condition Flags AND{ cond }{S} Rd, Rn, Op2Load Rd with logical AND of Rn with Op2. Rd := Rn AND Op2 If S is specified, N, Z flags are updated. C flag may be updated bycalculation of Op2. ExampleAND R9,R2,#0xFF00 // Load R9 with R2 and value in 0xFF00ORRLogical OR operation.ORR{ cond }{S} Rd, Rn, Op2OR operations on the values in Rn and Op2.If S is specified, N, Z flags are updated. C flag may be updated byORR R2, R0, R5 // Rd = R0 or R5CMPCompare. Used in combination with conditional branch instructions.Syntax CMP { cond } Rn, Op2Description subtracts the value of Op2 from the value in Rn (equals to the SUBSinstruction with a discarded result).This instruction updates the condition flags, but do not place a result in a register. Condition FlagsN, Z, C and V flags are updated.ExampleCMP R2, R9 //Subtract value of R9 from R2TSTTest. Syntax TST{ cond } Rn, Op2Descriptionperforms a bitwise AND operation on the value in Rn and the value of Op2.Subtract with carry. Syntax Description Condition FlagsSyntax Description Condition Flags calculation of Op2.ExampleThis is similar to the ANDS instruction, except that the result is discarded.Condition Flags N and Z flags are updated according the result. C flag may be updatedduring the calculation of Op2.Example TSTNE r1,r5,ASR r1MULMultiply (32-bit by 32-bit, bottom 32-bit result).Syntax MUL{ cond }{S} Rd, Rm, RsDescription multiplies the values from Rm and Rs, and places the least significant 32 bits of the result in Rd.Condition Flags If S is specified:N and Z flags according to the result.the C flag in ARM architecture v4 and earlier will be corrupted.the C flag in ARM architecture v5 and later is not affected.Example MUL R10, R2, R5 〃R10:= R2*R53. 分支控制指令B, BL, BX, BLX, and BXJBBranch to label. Used to jump to a specific program location.Syntax B{ cond } labelDescription The jump distance must be within -252 to +258 bytes for conditional and ±2 KBytes for unconditional branch.Condition Flags not modified.Example CMP R1,#1// compare R10 with #10BEQ val_ok // jump to label val_okBLBranch with Link. Use to call subroutines.Syntax Descriptiondistance must be withinBL{ cond } labelCopy address of next instruction to R14 and jump to label. ThejumpBXBranch indirect and switch CPU mode (Thumb / ARM) as required.Syntax BX{ cond } RmDescription Condition FlagsBranch to address in Rm. Change to ARM mode if bit 0 of Rm is clear. not modified.ExampleBX R5 // branch in direct to address fun cti on4. ARM 伪指令1•符号定义伪指令GBLA, GBLL, and GBLS LCLA, LCLL, and LCLS2.数据定义伪指令Condition Flagsnot modified.DCBDCD and DCDU 5. 条件代码Con diti on Codeinclude a condition code field. This{cond}A conditional instruction is only executed on match of the condition flags in theProgramStatus Register . For example, the BEQ ( B instruction with EQ condition) branches only if the {cond} field is empty the instruction is always executed.Examples:Most ARM instructions and the Thumb Branch instruction field is marked in the CPU instructions withZ flag is set. If the6•移位类型The ARM CPU has very powerful shift operations that can be used together with standard CPU instructions. The various shift types are explained below:Logical Shift Right (LSR)Logical shift right is encoded with LSR #n or LSR Rs in the bit 31 and the Carry flag (C) holds the last bit shifted out.3130 29lla--------------------------------------------------------------------------------------------------------------------------- rb■IArithmetic Shift Right (ASR)Arithmetic shift right is encoded with ASR #n or ASR Rs in the Op2 field. The sign bit (bit 31of value) is shifted into the high bit 31 and the Carry flag (C) holds the last bit shifted out.Rotate Right (ROR)Rotate right is encoded with ROR #n in the Op2 field. Bit 0 of the value is shifted into bit 31.The Carry flag (C) holds the last bit shifted out.31302&Bit211Q■h -■!lBh*■Op2 field. The value 0 is shifted intoBitLogical Shift Left (LSL)Logical shift left is encoded with LSL #n or LSL Rs in the bit 0 and the Carry flag (C) holds the last bit shifted out.Op2 field. The value 0 is shifted into313Bit------ 亦 3029Bil2-- ■1i■a■iIRotate Right Exte nded (RRX)Rotate right extended is encoded with RRX in the shiftedinto bit 31. The shifted out bit 0 is written to C. 31 30 29Binary operators RealView Compilati on Tools for 口 Visio n Versio nAssembler Guide 4.0Home > Assembler Reference > Expressions, literals, and operators> Binary operators Binary operators are written between the pair of subexpressions they operate on.Binary operators have lower precedence than unary operators. Binary operators appear in this section in order of precedence.NoteThe order of precedence is not the same as in C, see Multiplicative operatorsMultiplicative operators have the highest precedence of all binary operators. They act only on numeric expressions.Table 3.9 shows the multiplicative operators.Table 3.9. Multiplicative operators*A*BMultiply / A/BDivide:MOD: |% A:MOD:B A modulo BOp2 field. The value of the Carry flag (C) isOperator precedence in armasm and CString manipulation operatorsTable 3.10 shows the string manipulation operators. In In the slicing operators LEFT and RIGHT：A must be a stringB must be a numeric expression.Table 3.10. String manipulation operators:CC:」A:CC:B B concatenated onto the end of A:LEFT: J A:LEFT:B J The left-most B characters of A:RIGHT: A:RIGHT:B ]The right-most B characters of AShift operatorsShift operators act on numeric expressions, shifting or rotating the first operand by the amount specified by the second.Table 3.11 shows the shift operators.Table 3.11. Shift operators:ROL: A:ROL:B Rotate A left by B bits:ROR :A:ROR:B Rotate A right by B bits:SHL: << A:SHL:B Shift A left by B bits:SHR : >> A:SHR:BShift A right by B bitsNoteSHR is a logical shift and does not propagate the sign bit.CC, both A and B must be strings.Addition, subtraction, and logical operatorsAddition and subtraction operators act on numeric expressions.bitwise , that is, Logical operators act on numeric expressions. The operation is performed independently on each bit of the operands to produce the result.Table 3.12 shows addition, subtraction, and logical operators.Table 3.12. Addition, subtraction, and logical operators+ A+B Add A to B- A-B[Subtract B from A:AND:」& A:AND:B] Bitwise AND of A and B|EOR：」 A A:EOR:B| Bitwise Exclusive OR of A and B:OR: |1]A:OR:B Bitwise OR of A and BRelational operatorsTable 3.13 shows the relational operators. These act on two operands of the same type to produce a logical value.The operands can be one of:numericprogram-relativeregister-relativestrings.Strings are sorted using ASCII ordering. String A is less than string B if it is a leading substring of string B, or if the left-most character in which the two strings differ is less in string A than in string B.Arithmetic values are unsigned, so the value of 0>-1 is {FALSE}. Table 3.13. Relational operatorsBoolean operatorsThese are the operators with the lowest precedence. They perform the standard logical operations on their operands.In all three cases both A and B must be expressions that evaluate to either {FALSE}. Table 3.14 shows the Boolean operators.Table 3.14. Boolean operators:LAND: | && A:LAND:B JLogical AND of A and B:LEOR: J A:LEOR:B J Logical Exclusive OR of A and B :LOR: n II 1 A:LOR:B Logical OR of A and B= == A=B A equal to B>A>B A greater than B>=A>=B A greater than or equal to B<A<B A less than B<=A<=B A less than or equal to B/=l <> != A/=B| A not equal to B{TRUE} or。
