GL850A 电路

GL850AUSB 2.0 Low-Power HUB ControllerDatasheet Revision 1.69 Jul. 19, 2007Copyright:Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Disclaimer:ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks:is a registered trademark of Genesys Logic, Inc.All trademarks are the properties of their respective owners.Office:Genesys Logic, Inc.12F, No. 205, Sec. 3, Beishin Rd., Shindian City,Taipei, TaiwanTel: (886-2) 8913-1888Fax: (886-2) 6629-6168http ://Revision HistoryRevision Date Description1.0 03/21/2005 First release1.50 04/21/2005 1. Modify GREEN1~4 and AMBER1~4, Ch. 3.3, p.112. Add MaxPower Describe, Ch. 5.2.5, p.203. Add Ch.6.4 –Power Consumption, p.231.51 04/25/2005 Modify “MaxPoer” to “MaxPower”, table 5.1, p.20 1.52 04/26/2005 Modify Table3.3 Pin Descriptions(PSELF),p.11 1.60 06/20/2005 Modify Table 8.1 Ordering Information,p271.61 07/07/2005 1. Modify pin#46 ,pin#36 ,GL850A 48pin Pinout, Ch3.1,p.92. Modify pin#61 ,pin#49 ,GL850A 64pin Pinout Ch3.1,p.103. Add Pin name “EE_CS/EE_DI”, Hub Interface,table3.4, p.124. Modify Fosc ,table 6.1- Maximum Ratings,p.245. Modify Vcc ,table6.2 – Operating Ranges,p.241.62 09/07/2005 Modify Pin Descriptions ,table3.3 ,p.121.63 09/15/2005 Modify HUB Interface ,table3.3 Pin Description, p.131.64 12/28/2005 Modify Pin List and Pin Descriptions of EE_CS, EE_DI, EE_SK, p.11~12 1.65 03/29/2006 Add Input V oltage for digital I/O(Ovcur1-4,Pself,Reset) pins,p.24 1.66 11/03/2006 Modify 93C46 Configuration, Table 5.1, p.221.67 01/17/2007 Modify Table 6.1-Maximum Ratings, p.241.68 03/12/2007 Modify RESET# Setting, Ch5.2.1, p.181.69 07/19/2007 Modify PGANG/SUSPND Setting, Ch5.2.2, p.19TABLE OF CONTENTSCHAPTER 1 GENERAL DESCRIPTION (7)CHAPTER 2 FEATURES (8)CHAPTER 3 PIN ASSIGNMENT (9)3.1P INOUTS (9)3.2P IN L IST (11)3.3P IN D ESCRIPTIONS (12)CHAPTER 4 BLOCK DIAGRAM (15)CHAPTER 5 FUNCTION DESCRIPTION (16)5.1G ENERAL (16)5.2C ONFIGURATION AND I/O S ETTINGS (18)CHAPTER 6 ELECTRICAL CHARACTERISTICS (24)6.1M AXIMUM R ATINGS (24)6.2O PERATING R ANGES (24)6.3DC C HARACTERISTICS (24)6.4P OWER C ONSUMPTION (26)CHAPTER 7 PACKAGE DIMENSION (27)CHAPTER 8 ORDERING INFORMATION (29)LIST OF FIGURESF IGURE 3.1－GL850A48P IN LQFP P INOUT D IAGRAM (9)F IGURE 3.2－GL850A64P IN LQFP P INOUT D IAGRAM (10)F IGURE 4.1–GL850A B LOCK D IAGRAM (SINGLE TT) (15)F IGURE 5.1–O PERATING IN USB1.1 SCHEME (17)F IGURE 5.2–O PERATING IN USB2.0 SCHEME (18)F IGURE 5.3–RESET#(E XTERNAL R ESET) SETTING AND APPLICATION (19)F IGURE 5.4–P OWER ON SEQUENCE OF GL850A (19)F IGURE 5.5–T IMING OF PGANG/SUSPND STRAPPING (20)F IGURE 5.6–GANG M ODE S ETTING (20)F IGURE 5.7–SELF/BUS P OWER S ETTING (21)F IGURE 5.8–LED C ONNECTION (21)F IGURE 5.9–S CHEMATICS B ETWEEN GL850A AND 93C46 (23)F IGURE 7.1–GL850A48P IN LQFP P ACKAGE (27)F IGURE 7.2–GL850A64P IN LQFP P ACKAGE (28)LIST OF TABLEST ABLE 3.1－GL850A48P IN L IST (11)T ABLE 3.2－GL850A64P IN L IST (11)T ABLE 3.3-P IN D ESCRIPTIONS (12)T ABLE 5.1–93C46C ONFIGURATION (22)T ABLE 6.1–M AXIMUM R ATINGS (24)T ABLE 6.2–O PERATING R ANGES (24)T ABLE 6.3–DC C HARACTERISTICS E XCEPT USB S IGNALS (24)T ABLE 6.4–DC C HARACTERISTICS OF USB S IGNALS U NDER FS/LS M ODE (25)T ABLE 6.5–DC C HARACTERISTICS OF USB S IGNALS U NDER HS M ODE (25)T ABLE 6.6–DC S UPPLY C URRENT (26)T ABLE 8.1–O RDERING I NFORMATION (29)CHAPTER 1 GENERAL DESCRIPTIONGL850A is Genesys Logic’s advanced version Hub solutions which fully comply with Universal Serial Bus Specification Revision 2.0.GL850A embeds an 8-bit RISC processor to manipulate the control/status registers and respond to the requests from USB host. Firmware of GL850A will control its general purpose I/O (GPIO) to access the external EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM. Default settings in the internal mask ROM is responded to the host without having external EEROM. GL850A is designed for customers with much flexibility. The more complicated settings such as PID, VID, and number of downstream ports settings are easily achieved by programming the external EEPROM (Ref. to Chapter 5). Each downstream port of GL850A supports two-color (green/amber) status LEDs to indicate normal/abnormal status. GL850A also support both Individual and Gang modes (4 ports as a group) for power management. The GL850A (64-pin) is a full function solution which supports both Individual/Gang power management modes and the two-color (green/amber) status LEDs. The low pin-count version GL850A (48-pin) only supports Gang mode. Please refer the table in the end of this chapter for more detail.To fully meet the cost/performance requirement, GL850A is a single TT hub solution for the cost requirement. Genesys Logic also provides GL852 for multiple TT hub solution to target on systems which require higher performance for full/low-speed devices, like docking station, embedded system … etc.. Please refer to GL852 datasheet for more detailed information.*TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports.Product Name Package type Power mode LED supportGL850A 64LQFP Individual/Gang Green/AmberGL850A 48LQFP Gang Green/AmberCHAPTER 2 FEATURES•Compliant to USB specification Revision 2.0− 4 downstream ports−Upstream port supports both high-speed (HS) and full-speed (FS) traffic−Downstream ports support HS, FS, and low-speed (LS) traffic− 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload) −Backward compatible to USB specification Revision 1.1•On-chip 8-bit micro-processor−RISC-like architecture−USB optimized instruction set−Dual cycle instruction execution−Performance: 6 MIPS @ 12MHz−With 64-byte RAM and 2K internal ROM−Support customized PID, VID by reading external EEPROM−Support downstream port configuration by reading external EEPROM•Single Transaction Translator (STT)−Single TT shares the same TT control logics for all downstream port devices. This is the most cost effective solution for TT. Multiple TT provides individual TT control logics for each downstream port.This is a performance better choice for USB 2.0 hub. Please refer to GL852 datasheet for moredetailed information.•Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Revision 2.0•Support both individual and gang modes of power management and over-current detection for downstream ports (64-pin LQFP)•Support gang mode of power management and over-current detection for downstream ports •Conform to bus power requirements•Automatic switching between self-powered and bus-powered modes•Integrate USB 2.0 transceiver•PLL embedded with external 12 MHz crystal•Operate on 3.3 V olts•Embed serial resister for USB signals and integrate pull-up resister for upstream USB signal •Improve output drivers with slew-rate control for EMI reduction•Internal power-fail detection for ESD recovery•64/48-pin LQFP package•Applications:−Stand-alone USB hub−PC motherboard USB hub, Docking of notebook−Any compound device to support USB HUB functionCHAPTER 3 PIN ASSIGNMENT3.1 PinoutsGL850ALQFP - 48A V D D1A G N D2D M 03D P 04D M 15D P 16A V D D7A G N D8D M 29D P 210R R E F11A V D D 12A MB E R 2/E E _D IG R E E N 2/E E _D OD V D DD G N DA MB E R 3G R E E N 3N CT E S TR E S E T #D V D DD G N DA MB E R 4363534333231302928272625PSELF 37DGND 38DVDD39PGANG/SUSPND40OVCUR1#41PWREN1#42DGND 43DVDD44GREEN1/EE_SK 45AMBER1/EE_CS46DGND 47DVDD48GREEN4DP4DM4AGND AVDD DP3DM3AGND AVDD X2X1AGND242322212019181716151413Figure 3.1－GL850A 48 Pin LQFP Pinout Diagram3.2 Pin ListTable 3.1－GL850A 48 Pin ListPin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type1 AVDD P 13 AGND P 25 AMBER4 O 37 PSELF I2 AGND P 14 X1 I 26 DGND P 38 DGND P3 DM0 B 15 X2 O 27 DVDD P 39 DVDD P4 DP0 B 16 A VDD P 28 RESET# I 40 PGANG/SUSPNDB5 DM1 B 17 AGND P 29 TEST I 41 OVCUR1# I6 DP1 B 18 DM3 B 30 NC - 42 PWREN1# O7 A VDD P 19 DP3 B 31 GREEN3 O 43 DGND P8 AGND P 20 A VDD P 32 AMBER3 O 44 DVDD P9 DM2 B 21 AGND P 33 DGND P 45 GREEN1/EE_SKO10 DP2 B 22 DM4 B 34 DVDD P 46 AMBER1/EE_CSO11 RREF B 23 DP4 B 35 GREEN2/EE_DOB 47 DGND P12 A VDD P 24 GREEN4 O 36 AMBER2/EE_DIO 48 A VDD PTable 3.2 －GL850A 64 Pin ListPin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type1 AGND P 17 RREF B 33 NC - 49 AMBER2/EE_DIO2 NC - 18 A VDD P 34 GREEN4 O 50 PSELF I3 DM0 B 19 AGND P 35 AMBER4 O 51 DGND P4 DP0 B 20 X1 I 36 DGND P 52 DVDD P5 NC - 21 X2 O 37 DVDD P 53 PGANG/SUSPNDB6 NC - 22 A VDD P 38 RESET# I 54 OVCUR2# I7 NC - 23 AGND P 39 TEST I 55 PWREN2# O8 DM1 B 24 NC - 40 OVCUR4# I 56 OVCUR1# I9 DP1 B 25 DM3 B 41 PWREN4# O 57 PWREN1# O10 NC - 26 DP3 B 42 OVCUR3# I 58 DGND P11 A VDD P 27 NC - 43 PWREN3# O 59 DVDD P12 AGND P 28 A VDD P 44 GREEN3 O 60 GREEN1/EE_SKO13 NC - 29 AGND P 45 AMBER3 O 61 AMBER1/EE_CSO14 DM2 B 30 NC - 46 DGND P 62 DGND P15 DP2 B 31 DM4 B 47 DVDD P 63 A VDD P16 NC - 32 DP4 B 48 GREEN2/EE_DOB 64 A VDD P3.3 Pin DescriptionsTable 3.3 - Pin DescriptionsUSB InterfaceGL850APin Name48Pin# 64 Pin#I/O Type Description DM0,DP0 3,4 3,4 B USB signals for USPORTDM1,DP1 5,6 8,9 B USB signals for DSPORT1DM2,DP2 9,10 14,15 B USB signals for DSPORT2DM3,DP3 18,19 25,26 B USB signals for DSPORT3DM4,DP4 22,23 31,32 B USB signals for DSPORT4RREF 11 17 B A 680Ω resister must be connected between RREF and analog ground (AGND).Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to GL850A Design Guideline.HUB InterfaceGL850APin Name48Pin# 64 Pin#I/O Type DescriptionOVCUR1#~4 41 56,54,42,40I(pu)Active low. Over current indicator for DSPORT1~4OVCUR1# is the only over current flag for GANGmode.PWREN1#~4 42 57,55,43,41OActive low. Power enable output for DSPORT1~4PWREN1# is the only power-enable output for GANGmode.GREEN1~4 45,35,31,2460,48,44,341,3,4: O2: B(pd)Green LED indicator for DSPORT1~4*GREEN[1~2] are also used to access the external EEPROMFor detailed information, please refer to Chapter 5.AMBER1~4 46,36,32,2561,49,45,35O(pd)Amber LED indicator for DSPORT1~4*Amber[1~2] are also used to access the external EEPROMEE_CS/ EE_DI - - I Used to access the external EEPROM.For detailed information, please refer to Chapter 5.PSELF 37 50 I 0: GL850A is bus-powered. 1: GL850A is self-powered.PGANG/ SUSPND 40 53 BThis pin is default put in input mode after power-onreset. Individual/gang mode is strapped during thisperiod. After the strapping period, this pin will be set tooutput mode, and then output high for normal mode.When GL850A is suspended, this pin will output low.*For detailed explanation, please see Chapter 5Gang input:1, output: 0@normal, 1@suspendIndividual input:0, output: 1@normal, 0@suspendClock and Reset InterfaceGL850APin Name48Pin# 64Pin#I/O Type Description X1 14 20 I 12MHz crystal clock input.X2 15 21 O 12MHz crystal clock output.RESET# 28 38 IActive low. External reset input, default pull high 10KΩ.When RESET# = low, whole chip is reset to the initial state.System InterfaceGL850APin Name48Pin# 64 Pin#I/O Type DescriptionTEST 29 39I(pd)0: Normal operation.1: Chip will be put in test mode.Power / GroundGL850APin Name48Pin# 64 Pin#I/O Type DescriptionA VDD 1,7,12,16,20 11,18,22,28,64P 3.3V analog power input for analog circuits.AGND 2,8,13,17,21 1,12,19,23,29P Analog ground input for analog circuits.DVDD 27,34,39,44 37,47,52,59P 3.3V digital power input for digital circuitsDGND 26,33,38,43,4736,46,51,58,62P Digital ground input for digital circuits.NC 302,5~7,10,13,16,24,27,30,33- No connectionNote: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the ground plane. For detailed information, please refer to GL850A Design Guideline.Notation:Type O OutputI InputB Bi-directionalB/I Bi-directional, default inputB/O Bi-directional, default outputP Power / GroundA AnalogSO Automatic output low when suspend pu Internal pull uppd Internal pull downodpu Open drain with internal pull upCHAPTER 4 BLOCK DIAGRAMFRTIMER USPORTTransceiver RAMCPUControl/StatusRegisterUTMIUSPORTLogic SIED+D-GPIOREPEATERREPEATER / TT Routing LogicDSPORT1 Logic DSPORT2 Logic DSPORT3 Logic DSPORT4 LogicDSPORT Transceiver DSPORT DSPORT DSPORT12MHzD+D-LED/OVCUR/PWRENBD+D-LED/OVCUR/PWRENBD+D-LED/OVCUR/PWRENBD+D-LED/OVCUR/PWRENB TT (Transaction Translator)PLLx40, x10Transceiver Transceiver TransceiverROMFigure 4.1 – GL850A Block Diagram (single TT)CHAPTER 5 FUNCTION DESCRIPTION5.1 General5.1.1 USPORT TransceiverUSPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. USPORT transceiver will operate in full-speed electrical signaling when GL850A is plugged into a 1.1 host/hub. USPORT transceiver will operate in high-speed electrical signaling when GL850A is plugged into a 2.0 host/hub.5.1.2 PLL (Phase Lock Loop)GL850A contains a 40x PLL. PLL generates the clock sources for the whole chip. The generated clocks are proven quite accurate that help in generating high speed signal without jitter.5.1.3 FRTIMERThis module implements hub (micro)frame timer. The (micro)frame timer is derived from the hub’s local clock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame (SOF). FRTIMER keeps tracking the host’s SOF such that GL850A is always safely synchronized to the host. The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0.5.1.4 µCµC is the micro-processor unit of GL850A. It is an 8-bit RISC processor with 2K ROM and 64 bytes RAM.It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, µC can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub. These configurations include self/bus power mode setting, individual/gang mode setting, downstream port number setting, device removable/non-removable setting, and PID/VID setting.5.1.5 UTMI (USB 2.0 Transceiver Macrocell Interface)UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion.5.1.6 USPORT logicUSPORT implements the upstream port logic defined in section 11.6 of USB specification Revision 2.0. It mainly manipulates traffics in the upstream direction. The main functions include the state machines of Receiver and Transmitter, interfaces between UTMI and SIE, and traffic control to/from the REPEATER and TT.5.1.7 SIE (Serial Interface Engine)SIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with Μc to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol flow, CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is implemented in UTMI, not in SIE.5.1.8 Control/Status registerControl/Status register is the interface register between hardware and firmware. This register contains the information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based architecture, GL850A possesses higher flexibility to control the USB protocol easily and correctly.5.1.9 REPEATERRepeater logic implements the control logic defined in section 11.4 and section 11.7 of USB specification Revision 2.0. REPEA TER controls the traffic flow when upstream port and downstream port are signaling in the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup event is issued under the situation that hub is globally suspended.5.1.10. TT (Transaction Translator)TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL850A adopts the single TT architecture to provide the most cost effective solution. Single TT shares the same buffer control module for each downstream port. GL852 adopts multiple TT architecture to provide the most performance effective solution. Multiple TT provides control logics for each downstream port respectively. Please refer to GL852 datasheet for more detailed information.5.1.11 REPEATER/TT routing logicREPEATER and TT are the major traffic control machines in the USB 2.0 hub. Under situation that USPORT and DSPORT are signaling in the same speed, REPEATER/TT routing logic switches the traffic channel to the REPEATER. Under situation that USPORT is in the high speed signaling and DSPORT is in the full/low speed signaling, REPEATER/TT routing logic switches the traffic channel to the TT.5.1.11.1 Connected to 1.1 Host/HubIf an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1 mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the REPEATER.USB1.1 HOST/HUBREPEATER TTDSPORT operating in FS/LS signalingUSPORToperating in FS signalingTraffic channel is routed to REPEATERFigure 5.1 – Operating in USB 1.1 scheme5.1.11.2 Connected to USB 2.0 Host/HubIf an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will then be routed to the REPEATER when the device connected to the downstream port is signaling also in high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to the downstream port is signaling in full/low speed.USB2.0 HOST/HUBREPEATER TT USPORToperatingin HS signalingHS vs. FS/LS:Traffic channelis routed to TTHS vs. HS:Traffic channel is routed to REPEATERDSPORT operating in HS signaling DSPORT operating in FS/LS signalingFigure 5.2 – Operating in USB 2.0 scheme5.12 DSPORT logicDSPORT (downstream port) logic implements the control logic defined in section 11.5 of USB specification Revision 2.0. It mainly manipulates the state machine, the connection/disconnection detection, over current detection and power enable control, and the status LED control of the downstream port. Besides, it also output the control signals to the DSPORT transceiver.5.13 DSPORT TransceiverDSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. In addition, each DSPORT transceiver accurately controls its own squelch level to detect the detachment and attachment of devices. 5.2 Configuration and I/O Settings5.2.1 RESET# SettingGL850A integrates in the pull-up 1.5KΩ resister of the upstream port. When RESET# is enabled, the internal 1.5KΩ pull-up resister will be disconnected to the 3.3V power. To meet the requirement (p.141) of the USB 2.0 specification, pull-up resister should be disconnected while lacking of USB cable power (Vbus). Therefore, we suggest designing the RESET# circuit as following figure to meet the requirement mentioned above.AVDD (3.3V)CRVbus (5V)RESET#1.5K ohmDP0Inside GL850AOn PCB33 ohm RFigure 5.3 – RESET# (External Reset) setting and applicationGL850A internally contains a power on reset circuit. The power on sequence is depicted in the next picture. To fully control the reset process of GL850A, we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit.≒ 2.7 μsInternal resetExternal resetPower good voltage, 2.5~2.8VVCC(3.3V)Figure 5.4 – Power on sequence of GL850A5.2.2 PGANG/SUSPND SettingTo save pin count, GL850A uses the same pin to decide individual/gang mode as well as to output the suspend flag. The individual/gang mode is decided within 20us after power on reset. Then, about 50ms later, this pin is changed to output mode. GL850A outputs the suspend flag once it is globally suspended. For individual mode, a pull low resister greater than 100K Ω should be placed. For gang mode, a pull high resister greater than 100K Ω should be placed. In figure 5.6, we also depict the suspend LED indicator schematics. It should be noticed that the polarity of LED must be followed, otherwise the suspend current will be over spec limitation (2.5mA).RESET#GANG_CTL50msInput mode, strapping to decide individual or gang mode Output mode, indicating GL850A is in normal mode or suspend modeFigure 5.5 – Timing of PGANG/SUSPND strappingDVDD(3.3V)100K ohm100K ohm DVDD(3.3V)Suspend LEDIndicatorSuspend LEDIndicatorIndividualMode"0": Individual Mode"1": GANG ModeSUSPNDOGANG_CTLInside GL850AOn PCBPGANGFigure 5.6 – GANG Mode Setting5.2.3 SELF/BUS Power SettingGL850A can operate under bus power and conform to the power consumption limitation completely (suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL850A can be configured as a bus-power or a self-power hub.1: Power Self0: Power BusPSELFInside GL850AOn PCBFigure 5.7 – SELF/BUS Power Setting5.2.4 LED ConnectionsGL850A controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus Specification Revision2.0. Both manual mode and Automatic mode are supported in GL850A. When GL850A is globally suspended, GL850A will turn off the LED to save power.AMBER/GREENInside GL850AOn PCBDGND LEDFigure 5.8 – LED Connection5.2.5 EEPROM SettingGL850A replies to host commands by the default settings in the internal ROM. GL850A also offers the ability to reply to the host according to the settings in the external EEPROM(93C46). The following table shows the configuration of 93C46.Table 5.1 – 93C46 ConfigurationUnit: Byte00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F00h VID_L VID_H PID_L PID_H CHKSUM FF DEVICEREMOVABLEPORTNUMBERMaxPower FF FF FF FF FF FF FF10h VENDORLENGTHstart20h Vendor string (ASC II code)30h end40h PRODUCTLENGTHstart50h Product String(ASC II code)60h end70hSERIALNUMBERLENGTHstart Serial Number String(ASC II code) endNote: 1. VID_H/VID_L: high/low byte of VID value2. PID_H/PID_L: high/low byte of PID value3. CHKSUM: CHKSUM must equal to VID_H + VID_L + PID_H + PID_L + 1,otherwisefirmware will ignore the EEPROM settings.4. PORT_NO: port number, value must be 1~4.5. MaxPower : Describe the maximum power consumption, range=0Ma~500Ma .Value -> 00H~FAH (unit = 2Ma)6. DEVICE REMOVALBE:- - -PORT4REMOVABLEPORT3REMOVABLEPORT2REMOVABLEPORT1REMOVABLE-0: Device attached to this port is removable.1: Device attached to this port is non-removable.7. VENDOR LENGTH: offset 10h contains the length of the vendor string. Values of vendor string is contained from 11h~3Fh.8. PRODUCT LENGTH: offset 40h contains the length of product string. Values of product string is contained from 41h~6Fh.9. SERIAL NUMBER LENGTH: offset 70h contains the value of serial number string. Values of serial number string is contained after offset 71h.The schematics between GL850A and 93C46 is depicted in the following figures:VCC NC NC GNDCS SK DI DOEE_CS EE_SK EE_DI EE_DO93C46DVDDFigure 5.9 – Schematics Between GL850A and 93C46GL850A firstly verifies the check sum after power on reset. If the check sum is correct, GL850A will take the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being over-written, amber LED will be disabled when 93C46 exists.CHAPTER 6 ELECTRICAL CHARACTERISTICS6.1 Maximum RatingsTable 6.1 – Maximum RatingsSymbol Parameter Min. Max. UnitV CC Power Supply -0.5 +3.6 VV IN Input V oltage for digital I/O(EE_DO) pins -0.5 +3.6 VV IN Input V oltage for digital I/O(Ovcur1-4,Pself,Reset) pins -0.5 +5.25 VV INUSB Input V oltage for USB signal (DP, DM) pins -0.5 +3.6 VT S Storage Temperature under bias -60 +100 o CF OSC Frequency 12 MHz ± 0.05%6.2 Operating RangesTable 6.2 – Operating RangesSymbol Parameter Min. Typ. Max. Unit V CC Power Supply 3.0 3.3 3.6 VV IND Input V oltage for digital I/O pins -0.5 3.3 3.6 V V INUSB Input V oltage for USB signal (DP, DM) pins 0.5 3.3 3.6 VT A Ambient Temperature 0 - 70 o C6.3 DC CharacteristicsTable 6.3 – DC Characteristics Except USB SignalsSymbol Parameter Min. Typ. Max. Unit P D Power Dissipation 70 - 180 mA V DD Power Supply V oltage 3 3.3 3.6 VV IL LOW level input voltage - - 0.9 VV IH HIGH level input voltage 2.0 - - VV TLH LOW to HIGH threshold voltage 1.36 1.48 1.62 VV THL HIGH to LOW threshold voltage 1.36 1.48 1.62 VV OL LOW level output voltage when I OL=8Ma - - 0.4 VV OH HIGH level output voltage when I OH=8Ma 2.4 - - VI OLK Leakage current for pads with internal pull up or pulldown resistor- - 30 µAR DN Pad internal pull down resister 81K 103K 181K ΩR UP Pad internal pull up resister 81K 103K 181K Ω。

USB远距离光传输系统设计摘要：当前，远程USB传输系统的研究开发具有重要意义。

基于此，本研究设计提出了一种利用光纤传输技术实现USB信号远程传输的方案，得到了理想的光纤USB传输效果,为今后USB信号长距离传输进一步开发提供了参考。

关键词：光纤传输；USB技术；接收端USB在电子产品的设计中有着非常广泛的使用。

它具有支持设备的即插即用、热插拔、使用灵活等特点。

但是由于其传输距离短的缺点,大大阻碍了远距离场所的广泛应用。

随着USB技术这些年的快速发展, 我们有必要针对USB技术研发能使USB信号实现长距离传输的系统。

B 信号的远距离光传输系统总体构架系统的总体构架框图如图1 所示。

整个系统分为发射端和接收端两部分。

发射端通过USB 电缆与PC主机连接，接收端作为终端接口，提供4 个USB 用户接口。

发射端和接收端之间通过单模光缆连接。

PC 主机可以实现对终端设备的透明访问，终端接口允许设备热插拔并能自动识别插入设备类型[1]。

图1 USB 信号的远距离光传输系统总体构架2.系统功能单元的划分和设计本文按照系统的功能和信号传输要求，将设备划分为多个功能单元进行设计。

包括USB 信号处理单元、千兆以太网信号处理单元、光电转换单元、USB 接口扩展单元以及电源供电单元。

其中，USB 信号处理单元、千兆以太网信号处理单元、光电转换单元和电源供电单元在发射端和接收端可以通用，而USB 接口扩展单元只在接收端存在。

各功能单元系统框图如图2 所示。

（a）发射端（b）接收端图2 系统功能单元框图2.1 USB 信号处理单元设计USB 信号处理单元主要完成的功能是将USB 信号转换为RGMII 接口信号。

采用某公司的CH317 芯片，外加少量外围电路即可实现所需功能。

CH317 作为一款USB 延长器控制芯片，支持高速、全速和低速USB 传输；支持USB 扩展；不需要额外安装软件；兼容所有操作系统；支持热插拔、即插即用。

项目一认识音响与设备情景导入：机关、企事业单位、社会团体、体育馆、剧院、学校等，在进行集体活动时，往往都需要使用到音响设备，而音响设备的使用与维护，因涉与到声学、电学、音乐与材料学相关领域专业知识，这就需要专业人员进行使用和维护，从今开始，同学们将接触到相关知识，通过努力学习，定会给你带来快乐！知识目标：1、音响与音响概念2、音响系统的认识3、常用的音响设备能力目标：1、对各音响设备有一定认识2、各音响设备的功能音响( Sound) 是一个通俗的名词, 在物理学中, 音响可理解为人耳能听到的声音, 而在音响技术中, 音响是指通过放声系统重现的声音。

通过组合音响重现唱片或磁带中的音乐、歌曲与其他声音, 或者演出现场通过扩音系统播放出来的演唱、奏乐声等, 都属于音响的X畴。

音响系统是指把若干音响设备按一定规律连接, 组成一个受控体系, 能够重现声音的放声系统。

音响系统可分为家用音响系统和专业音响系统。

一、家用音响系统习惯上把适合于家庭使用的音响系统称为家用音响系统。

家用音响系统分为家庭音响系统与家庭AV 系统。

家庭音响系统又分为组合音响系统(组合音响) 和成套高保真音响系统(音响组合) ; 家庭AV 系统又分为家庭影院系统和多媒体家庭影院系统。

家庭音响系统是指一般家庭中用于放送音乐软件、播放电影、收听广播电视节目的音响系统, 一般以高质量地放送视、音频信号为主要目的, 常用于家庭音乐欣赏、家庭舞会、放送背景音乐等。

1 . 组合音响系统“组合音响”是指由生产厂家统一配接好的音响系统, 一般由音源设备、功率放大器和音箱三个部分组成。

如图1 - 1 所示。

由于它省却了许多配接的麻烦, 且价格适中, 吸引了不少一般的消费者。

组合音响可以达到极品档次, 但作为一款高档次的音响系统, 要达到高保真的音响效果, 对组成系统的各个硬件都必须具有极品档次, 只要其中某种设备达不到,就会使整个系统的档次下降。

这对一个厂家, 即便是一个实力雄厚的大厂家也不是一件容易的事情。

1、电气系统未经本公司同意，不可更改机器的电路。

如果擅自更改而造成机器损坏，本公司不负任何责任。

所有的维修保养工作，只能由专业的维修工程师来做，电路只能由专业的电气工程师来安装。

1.1 电源需求：380V/AC 50HZ 三相；1.2 操作与说明应急处理〔急停按钮〕功能范围：设备在运行过程中，如出现紧急情况如：水、油、气管脱离，机器动作异常，机器有异味或异常声音或其他意外时用到此急停按钮。

操作：当出现上述情况或其他意外时，请以最快的速度按下急停按钮，用力按下直到听到咔嗒一声响，并接着切断设备的电源开关。

请有关技术维修人员前来排除故障。

问题解决后开机按箭头方向转动此急停按钮可复原，即可进行手动或自动操作。

考前须知：设备正常工作中请勿按此按钮。

操作准备1)设备是否在平安状态，确认无检修作业、无杂物及其它异常。

2)检查电流、电压表显示是否在规定范围内。

3)合上动力控制箱里的总电源开关，并检查动力控制箱内空气开关是否都在合闸位置。

操作程序运行：电源开关“ON〞，电源指示正常后，按下主机启动按钮主机运行；运行中系统对负载电流通过检测变换后输入控制继电器，进行内部处理后输出控制信号驱动设备作相应运行，具体如下所叙：当检测电流值正常时，正常运行；当检测值大于严重过载设定值并持续设定时间后，主机停止运行，经延时后主机反转启动翻料，运行设定的反转时间后停止，经设定延时后主机再正转启动；至此根据负载状态自动选择运行。

停机：生产完成后请确认清料后,按下停止按钮停机，关闭电源“OFF〞。

1.3 维护与检修停机1〕电控设施需防水溅入、防火、防尘、防异物进入造成设备及元器件损坏；2〕进行检修前，请切断关闭电源，锁住电箱，并挂检修工作警示牌；3〕运行中随时对运行设备进行检查，确认其工作电流、电压、温升及响声有无异常；4〕定期对柜内电气元件及动力设备进行运行状态检查；5〕定期对电气设施进行除尘清扫，确保设备元器件工作可靠性；1.4 逻辑控制继电器操作说明及程序功能介绍〔附后第3-6页〕1.5 电气原理图〔附图1〕1.6 元件布置图〔附图2〕1.7 操作面板布置图〔附图3〕参数功能简介：LOGO！面板参数修改操作简介：1步：2步：3步：4步：例：1、时间参数1、将光标移动到需要更改参数的位置：按◀或▶键2、更改数值：按▲或▼键3、采用更改后的数值：按OK键2、电流设定阀值参数：移动光标选择要修改值，按◀或▶键更改数值，按▲或▼键采用更改数值按OK键。

ADC DRIVER AND 5X5MM HIGH-SPEED ADC DESCRIPTIONDemonstration circuit 900 is a reference design featuring Linear Technology Corporation’s Analog-Digital Converter (ADC Driver and 5x5mm High-Speed ADC families. DC900 demonstrates good circuit layout techniques and recommended com-ponent selection for optimal system performance. The ADC driver input and output networks are flexible, allowing for AC or DC coupling, single-ended or differential configurations, and signal low-pass or bandpass filtering before the ADC. DC900 allows flexibility of supply voltages, and supports Linear Technology’s entire line of 5mm x 5mm pin-compatible high-resolution high-speed ADC family. DC900 includes an on-board 40-pin edge connector for use with the DC718 Data Ac-quisition demo board and Linear Technology’s QuickEval-II data processing software, available on our website at .Design files for this circuit board are available. Call the LTC factory., LTC and LT are registered trademarks of Linear Technology Corporation.QUICK START PROCEDUREValidating the performance of the ADC Driver-ADC combination is simple with DC900, and requires only two signal generators and some basic lab equipment. Table 1 shows the function of each I/O connector on the board. Refer to Figure 1 for proper board evaluation equipment setup and fol-low the procedure below:1. Connect the power supplies as shown. The power supply connector labeled VCC powers the ADC driver. VDD powers the ADC, and OVDD provides power to both the ADC output stage and the two CMOS output buffers. The entire board and all components share a com-mon ground. Check the datasheets of the respective IC’s before applying power, to avoid damage from over-voltage conditions.2. Provide an encode clock to the ADC via SMA connector J2. For best performance, a high-quality sine wave synthesizer with an external band-pass filter will provide a stable, low-phase-noise clock source. A crystal oscillator will also provide good performance. DC900 includes anon-board clock buffer IC to provide a large-amplitude clock source to the ADC.NOTE. A poor quality encode clock can significantly degrade the signal-to-noise ratio (SNR) of the driver-ADC combination.Table 1: DC900 Connector and DescriptionsREFERENCE FUNCTIONJ1 (AIN+) Analog InputJ2 (CLK) ADC Encode Clock. For best perform-ance, use a high-quality low-jitter clocksource.J3 (AIN-) Analog Input (by default, tied to groundvia resistor R3 for transformer single-ended-to-differential conversion) J4 (40 pin conn) Provides direct connection to DC718.CMOS Output Buffers provide paralleldata output and clock signals (see sche-matic).3. Apply an input signal to the board. DC900 al-lows great flexibility in applying input signals (see the section on Applying Input Signals). For best results, use a low distortion, low noise sig-nal generator with high order low-pass or band-pass filtering to avoid degrading the measured performance of the ADC driver and ADC.DEMO CIRCUIT 900QUICK START GUIDE ADC Driver and 5x5mmHigh-Speed ADCADC DRIVER AND 5X5MM HIGH-SPEED ADC 4. Observe the ADC output with demo circuit DC718, a USB cable, a Windows computer, and Linear Technology’s QuickEval-II data process-ing software. See Figure 2 for the general board evaluation setup diagram.NOTE. See the DC718 Quick Start Guide for instructions on using the DC718 QuickDAACS data acquisition demo board.Figure 1. Proper Evaluation Equipment SetupFigure 2. Evaluation Setup with DC718, Computer, and QuickEval-II SoftwareSignal Generator Sine+BPF or SquarePower SupplyPower SupplyDC718 QuickDAACS Data Acquisition Board Input Signal Generatorwith LPF, BPFsynthesizer will still have noise attenuated with a low-pass or band-pass filter. For good-quality high order filters, see TTE, LarkADC DRIVER AND 5X5MM HIGH-SPEED ADCFigure 3. DC900 Input NetworkADDITIONAL INFORMATIONAlthough the DC900 demo board is ready to use, it has additional flexibility built in for various types of input networks, filtering configurations, and single-ended or differential inputs. Below is some infor-mation about configuring DC900 to meet the spe-cific needs of any application.APPLYING INPUT SIGNALSThe input network consists of various components designed to allow either single-ended or differential inputs, transformer-coupled or DC-coupled. Table 2 shows some possible input configurations, and which components to install. Linear Technology’s ADC driver families are generally characterized and designed for both single-ended and differential input drive, but for optimal performance differential input drive (or transformer-coupled drive) is rec-ommended. By default, transformer drive is used on DC900 so that only a single-ended input is needed. Table 2: DC900 Input Configuration GuideCONFIGURATION COMPONENTS NECESSARYSingle-Ended In-put Transformer Drive Install 0Ω jumpers at R8 and R3, or R7 and R2.Install transformer T1. If necessary, install R22 and R23 for impedance matching. Remove R15, R17.Install CIN+ and CIN- for AC coupling.Single-Ended In-putSingle-Ended Drive Install 0Ω jumpers at R8 and R3, or R7 and R2.Remove T1. Install R15, R17.Install R22 or R23, if necessary, for imped-ance matching.Install CIN+ and CIN- for AC coupling.Differential Input Transformer Drive Install 0Ω jumpers at R7 and R8, remove R2 and R3.Install transformer T1. If necessary, install R22 and R23 for impedance matching. Remove R15, R17.Install CIN+ and CIN- for AC coupling.ADC DRIVER AND 5X5MM HIGH-SPEED ADCDifferential Input No Transformer AC-Coupled Install 0Ω jumpers at R7 and R8, remove R2 and R3.Remove T1. Install R15, R17.Install R22 or R23, if necessary, for imped-ance matching.Install CIN+ and CIN- for AC coupling.Differential Input No Transformer DC-Coupled* Install 0Ω jumpers at R7 and R8, remove R2 and R3.Remove T1. Install R15, R17.Install R22 or R23, if necessary, for imped-ance matching.Remove CIN+ and CIN-, replace with 0Ωjumpers.NOTE. * When driving the ADC driver with a direct DC-coupled path, be aware of the increased input currents that may occur due to the output common-mode voltage and internal resistor networks. The DC common-mode voltage requirements of Linear Technology’s ADC drivers do not always extend to ground (the negative supply voltage). When replacing CIN+ and CIN- with 0Ωjumpers, make sure to level-shift the inputs so that the ADC driver’s input common-mode voltage requirement is met.Recommended 1:1 transformers for populating T1 are M-A/Com’s ETC1-1-13 and ETC1-1T. For 4:1 transformers, ETC4-1-2 and Mini-Circuit’s TCM4-19 is a good choice.POWER SUPPLY BYPASS CAPACITANCE Depending on the quality of the power supplies provided to DC900, it may be desirable to add lar-ger capacitors at C4, B22, and B23. This will not be necessary with good-quality lab power supplies with short wire leads.FILTER NETWORKSFor narrowband input signals, L1 and C6 are in-cluded at the output of the ADC driver for easy band-pass filter design. In addition, there are resis-tor pads R9, R13, R20-21 at the outputs of the ADC driver that could be populated with filtering components. CHANGING THE ADC DRIVER’S OUTPUT COMMON-MODE VOLTAGEThe output common-mode voltage of the ADC driver is independently tunable from the input common-mode voltage. This is done in one of two ways. By changing the resistors R25 and R26 that comprise a resistive divider from the VCC voltage, it is possible to tune the common-mode voltage independently of all other factors. Alternatively, R25 and R26 can be removed, and the ADC can supply the common-mode voltage by installing R24.The optimum common-mode input voltage of the ADC (the voltage supplied by R24) may not ex-actly match the optimum common-mode output voltage of the ADC driver. See the datasheets of the ADC driver and ADC.USING QUICKEVAL-II SOFTWARE QuickEval-II, downloadable from Linear Technol-ogy’s website /, processes data from the DC718 QuickDAACS board and dis-plays FFT and signal analysis information on the computer screen. This section describes how to use the software to view the output from DC900. The first step is to select the correct input board. See Figure 4. From the Configure menu in the toolbar, select DC718 (QuickDAACs). The next step is to use the proper settings for the DC900 output. See Figure 5 for the proper settings. Be sure to select a resolution that matches the on-board ADC. All of the other settings should be en-tered as shown in Figure 5. After configuration is through, the program should be ready to collect and display data. See the Help file for instructions on general software use.ADC DRIVER AND 5X5MM HIGH-SPEED ADCFigure 4. Selecting the correct input to QuickEval-IIFigure 5. Entering the correct device information for your ADC. Only the resolution (bits) should differ from this fig-ure.ADC DRIVER AND 5X5MM HIGH-SPEED ADCFigure 6. Demo Circuit DC900 Schematic。

UCC27200A,UCC27201AZHCS096A –FEBRUARY 2011–REVISED DECEMBER 2011120V 启动电压，3A 峰值电流的高频高端/低端驱动器查询样品:UCC27200A ,UCC27201A特性内容•技术规格针对－40℃至140℃的温度范围而拟订•可驱动两个采用高端/低端配置的N 沟道MOSFET 器件额定值2•最大启动电压：120V 电气特性4•最大VDD 电压：20V器件信息11•片载0.65V VF ，0.6ΩRD 自举二极管应用信息14•工作频率高于1MHz 附加参考22•20ns 传播延迟时间•3A 吸收，3A 供电输出电流说明•8ns 上升/7ns 下降时间（采用1000pF 负载时）UCC27200A /1A 系列高频N 沟道MOSFET 驱动器包•1ns 延迟匹配括一个120V 自举二极管和具有独立输入的高端/低端•用于高端和低端驱动器的欠压闭锁功能驱动器，旨在实现最大的控制灵活性。

这可在半桥•列表中PowerPad ™SOIC-8(DDA)，SON-8(DRM)，SON-9(DRC)和SON-10(DPR)封装式、全桥式、两开关正激式和有源箝位正激式转换器中提供N 沟道MOSFET 控制。

低端和高端栅极驱动器是应用范围独立控制的，并在彼此的接通和关断之间实现了至1ns •针对电信，数据通信和商业市场的电源的匹配。

UCC27200A /1A 基于广泛使用的•半桥式应用和全桥式转换器UCC27200/1驱动器，但进行了一些改进。

为了提升•隔离式总线架构噪声电源环境中的性能，UCC27200A /1A 运用了一•两开关正激式转换器种增强型ESD 输入结构，而且能够在其HS 引脚上承•有源箝位正激式转换器受－18V （最大值）的电压。

•高电压同步降压型转换器•D 类音频放大器简化的应用示意图Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPad is a trademark of Texas Instruments.UCC27200A,UCC27201AZHCS096A–FEBRUARY2011–REVISED These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.中说明（续）由于在芯片上集成了一个自举二极管，因此无需采用外部分立式二极管。