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5Stimulus and Response

5Stimulus and Response
5Stimulus and Response

CHAPTER 5STIMULUS AND RESPONSE

Stimulus and Response

Reference Signals

Stimulus and Response

duces a period of 16 nanoseconds because of rounding the result of the real division to an integer value.

Because the timescale in Sample 5-5 offers the necessary precision for a 7.5 nanoseconds half-period, only this model generates a 50percent duty-cycle clock signal with a precise 15 nanoseconds period.

Sample 5-3.Truncation errors in stim-ulus genera-tion

‘timescale 1ns/1ns

module testbench;

...

bit clk = 0;

parameter cycle = 15;

always

begin

#(cycle /2); // Integer division

clk =~clk;

end

endmodule Sample 5-4.Rounding errors in stim-ulus genera-tion

‘timescale 1ns/1ns

module testbench;

...

bit clk = 0;

parameter cycle = 15;

always

begin

#(cycle /2.0); // Real division

clk = ~clk;

end

endmodule Sample 5-5.Proper preci-sion in stimu-lus generation

‘timescale 1ns/100ps

module testbench;

...

bit clk = 0;

parameter cycle = 15;

always

begin

#(cycle/2.0);

clk = ~clk;

end

endmodule

Reference Signals

Stimulus and Response

Reference Signals Clock Multipliers

Implemented using PLLs.Many designs have a very high-speed front-end interface that is driven using a multiple of a recovered clock or the lower-frequency system clock. This clock multiplication is performed using an inter-nal or external PLL (phase locked loop). PLLs are inherently ana-log circuits. They are very costly to simulate in a digital simulator. When an internal PLL is used, the analog component that imple-ments the PLL is often modeled as an empty module. It is up to the testbench to create an appropriate multiplied clock signal in a behavioral fashion.

The reference clock could become the derived clock.A simple strategy is to reverse the role of the reference and derived clock. Since clock dividers are so easy to model, you could gener-ate the high-frequency clock then use it to derive the lower-fre-quency system-clock. Sample 5-9 shows a model for a multiply-by-4 clock generator using the divide-by-4 strategy. But this only works under two conditions: The reference clock is also an input to the design, and the frequency of the reference clock is known and fixed.

Synchronize the multiplied clock to the reference clock.The first condition can be eliminated by synchronizing the multi-plied clock signal with the reference clock. It will be possible to generate the multiplied clock signal even if the reference clock is supplied by the design. Sample 5-10 shows a model of a multiply-by-4 clock generator, synchronized with an input reference clock. But the problem of the hard-coded multiplied clock period remains. This model assumes a reference clock with an 80 nanoseconds period. What if the reference clock has a different frequency in a

Sample 5-8. Generating differential data signals wire [15:0] d;

bfm cpu(..., .d(d), ...);

design dut (..., .dp(d), .dn(~d), ...);

Sample 5-9. Generating clock multi-ples by divi-sion bit clk1 = 0;

bit clk4 = 0;

always

begin

repeat (4) #10 clk4 <= ~clk4; clk1 <= ~clk1;

end

Stimulus and Response

different simulation run? How can we generalize this model into a

generic clock-multiplier PLL model?

Measure the period of the ref-erence clock.Why not let the model learn the period of the reference signal? You can measure the time difference between two consecutive edges, divide this value by 4, and voila! A generic PLL model. Sample 5-11 shows a PLL model with a continuous measure of the reference signal. As the frequency of the reference clock signal changes, the frequency of the multiplied clock will adapt.

Sample 5-10. Synchroniz-ing multiplied clock to input reference clock always @(clk)

begin

clk4 <= ~clk4; clk4 <= #10ns clk4; clk4 <= #20ns ~clk4; clk4 <= #30ns clk4; end

Sample 5-11. Adaptive clock multi-plier model module pll(input bit ref_clk,

output bit out_clk);

parameter FACTOR = 4;

initial

begin

real stamp;

out_clk = 1’b0;

@(ref_clk);

stamp = $realtime;

forever begin

real period;

@(ref_clk);

period = ($realtime - stamp)/FACTOR; stamp = $realtime;

repeat (FACTOR-1) begin

out_clk = ~out_clk;

#(period);

end

out_clk = ~out_clk;

end

end

endmodule

Reference Signals

Stimulus and Response

of aligning objects. When writing a specification, you must be care-

ful that these implicit alignments do not create the illusion of a rela-

tionship. When reading a specification, do not assume a

relationship unless it is explicitly stated.

Generate unre-lated signals in separate threads.Sample 5-13 shows a better way to generate these unrelated clock signals. Since they are not synchronized in any way, they are gener-ated using separate concurrent threads. This separation will make it easier to modify the frequency of one signal without affecting the frequency of the other. Also, notice how each signal is explicitly skewed at the beginning of the simulation to avoid having the edges aligned at the same simulation time. This approach is a good prac-tice to highlight potential problems in the clock-domain crossing portion of the design. By varying these initial signal skew values, it will be possible to verify the correct functionality of the design across different asynchronous clock relationships.

Random Generation of Reference Signal Parameters

All signals are related in simu-lation.In the previous section, I explained why unrelated signals should be modeled as separate threads and skewed with respect to each other to avoid creating an implicit relationship that does not exist between them. The truth is: There is no way to accurately model unrelated signals. Each waveform is described with respect to the current simulation time. Because all waveforms are described using the same built-in reference, they are all implicitly related. Even though I made my best effort to avoid modeling any relationship between the two clock signals generated in Sample 5-13, they are related because of the deterministic nature of the simulator. Unless I manually modify one of the timing parameters, they will maintain the same relationship in all simulations.

Asynchronous means random.When we say that two signals are asynchronous to each other, we are saying that they have a random phase relationship. That phase relationship will be different every time and cannot be predicted. When I specified explicit skew delay values in Sample 5-13, I intro-

Sample 5-13. Generating unrelated waveforms bit clk100 = 0;

initial #2 forever #5 clk100 = ~clk100; bit clk33 = 0;

initial #5 forever #15 clk33 = ~clk33;

Reference Signals duced certainty where there wasn’t any. These delay values should be generated randomly to increase the chances that, over the thou-sands of simulation runs the design will be subjected to, any prob-lem related to clock skews will be highlighted.

Avoid using $random.One solution would be to call $random to generate the delay values, as shown in Sample 5-14. But this strategy can only produce evenly distributed delay values. It would not be possible to modify the dis-tribution of delay values toward more interesting corner cases, or constrain the delay values against each other to create interesting conditions.

Use skew vari-ables initialized with$random.Instead, as shown in Sample 5-15, use skew variables initialized using $random to determine the initial skew of each asynchronous waveform. Although it appears that little has been gained compared with Sample 5-14, this approach allows a testbench to modify or constrain the skew values. Notice the #1 delay inserted before the actual skew delay. This allows the testbench code, written in a pro-gram thread, to run and potentially replace the skew values before they are used. Sample 5-16 shows how a testbench can generate and replace new skew values with constrained random values that are deemed more interesting.

Sample 5-14. Generating unrelated waveforms using random skew bit clk100 = 0;

initial #({$random} % 10)

forever #5 clk100 = ~clk100; bit clk33 = 0;

initial #({$random} % 30)

forever #15 clk33 = ~clk33;

Sample 5-15. Generating unrelated waveforms using skew variables bit clk100 = 0;

int clk100_skew = {$random} % 10; initial #1 #(clk100_skew)

forever #5 clk100 = ~clk100; bit clk33 = 0;

int clk33_skew = {$random} % 30; initial #1 #(clk33_skew)

forever #15 clk33 = ~clk33;

Stimulus and Response

Reference Signals shown in Figure5-8 could appear to be violated. The race condition can be eliminated by using nonblocking assignments, as shown in Sample 5-18. Both clk and rst signals are assigned between timesteps when no blocks are executing. If the design under verifi-cation uses the falling edge of clk as the active edge, rst is already—and reliably—assigned.

Lack of main-tainability can introduce func-tional errors.The second problem, which is just as serious as the first one, is maintainability of the description. You could argue that the first problem is more serious, since it is functional. The entire simula-tion can produce the wrong result under certain conditions. Main-tainability has no such functional impact. Or has it? What if you made a change as simple as changing the phase or frequency of the clock. How would you know to change the generation of the reset signal to match the new clock waveform?

Conditions in real life are dif-ferent than those in this book.In the context of Sample 5-18, with Figure5-8 nearby, you would probably adjust the generation of the rst signal. But outside of this book, in the real world, these two blocks could be separated by hun-dreds of lines, or even be in different files. The specification is usu-ally a document three centimeters thick, printed on both sides. The timing diagram shown in Figure5-8 could be buried in an anony-mous appendix, while the pressing requirements of changing the clock frequency or phase was stated urgently in an email message. And you were busy debugging this other testbench when you received that pesky email message! Would you know to change the generation of the reset signal as well? I know I would not.

Model the syn-chronization within the gen-eration.Waiting for an apparently arbitrary delay cannot guarantee synchro-nization with respect to the delay of the clock generation. A much better way of modeling synchronized waveforms is to include the synchronization in the generation of the dependent signals, as shown in Sample 5-19. The proper way to synchronize the rst sig-

Sample 5-18. Race-free gen-eration of a synchronous reset bit clk = 0;

always #50 clk <= ~clk; bit rst = 0;

initial

begin

#150 rst <= 1’b1;

#200 rst <= 1’b0; end

Stimulus and Response

nal with the clk signal is for the generator to wait for the significant

synchronizing event, whenever it may occur. The timing or phase

of the clock generator can be modified now, without affecting the

proper generation of the rst waveform. From the perspective of a

design sensitive to the falling edge of clk,rst is reliably assigned

one delta-cycle after the clock edge.

Reset may need to be applied repeatedly dur-ing a simulation.There is a problem with the way the rst waveform is generated in Sample 5-19. The initial block runs only once and is eliminated from the simulation once completed. There is no way to have it exe-cute again during a simulation. What if it were necessary to reset the device under verification multiple times during the same simu-lation? An example is the “hardware reset” testcase that verifies proper reset operation: After setting some internal registers, the hardware reset must be applied to verify that these registers return to their reset value. The ability to control reset application is also very useful. This control lets testbenches perform preparatory oper-ations before resetting the design and starting the actual stimulus.

Generate reset from within a module task.The proper mechanism to encapsulate statements that you may need to repeat during a simulation is to use a task as shown in Sam-ple 5-20. To repeat the reset signaling, simply call the task. To maintain the behavior of using an initial block to reset the device under verification automatically at the beginning of the simulation (which may or may not be desirable), simply call the task in an ini-tial block.

Reset task should be in pro-gram.It will be possible to invoke the reset task in the module from the testbench program threads. The testbench will thus be able to reset the design any time the reset is required. An alternative would be to put the reset task in a program task, as shown in Sample 5-21.

Sample 5-19. Proper genera-tion of a syn-chronous reset bit clk = 0;

always #50 clk = ~clk; bit rst = 0;

initial

begin

@ (negedge clk);

rst <= 1’b1;

@ (negedge clk);

@ (negedge clk);

rst <= 1’b0;

end

Reference Signals

Because modules cannot call program tasks, it will be necessary for each testbench to call the reset program task to reset the DUT.However, this gives the testbench better control over the reset parameters and its coordination with other device stimuli, not just the clock. The section titled “Simulation Control” starting on page 124 of the Verification Methodology Manual for SystemVerilog defines a simulation sequence methodology that includes a pre-defined step for applying hardware reset to the design under verifi-cation.

Sample 5-20.Encapsulating the generation of a synchro-nous reset

module tb_top;

bit clk = 0;

bit rst = 0;

always #50 clk = ~clk;

...

task hw_reset

rst = 1’b0;

@ (negedge clk);

rst <= 1’b1;

@ (negedge clk);

@ (negedge clk);

rst <= 1’b0;

endtask: hw_reset

initial hw_reset ;

...

endmodule Sample 5-21.Synchronous reset program task.

program test;

task hw_reset

tb_top.rst <= 1’b0;

@ (negedge tb_top.clk);

tb_top.rst <= 1’b1;

@ (negedge tb_top.clk);

@ (negedge tb_top.clk);

tb_top.rst <= 1’b0;

endtask: hw_reset

initial

begin

hw_reset;

...

end

endprogram

Stimulus and Response

Simple Stimulus

Stimulus and Response

Simple Stimulus Instead of providing test vectors to perform these operations repeat-edly, why not provide subprograms that perform these operations? All that will be left is to call the subprograms in the appropriate order with the appropriate data.

Try to apply the worst possible combination of inputs.The task to perform the synchronous reset is very simple. It needs to assert the rst input, then wait for the active edge of the clock. But what about the other inputs? You could decide to leave them unchanged, but is that the worst possible case? What if the reset was not functional and the device loaded one of the inputs and that input was set to 0? It would be impossible to differentiate the wrong behavior from the correct one. To create the worst possible condi-tion, both d0 and d1 inputs must be set to 1. The sel input can be set randomly, since either input selection should be functionally identi-cal. An implementation of the reset procedure is shown in Sample 5-26.

Sample 5-25. Test vectors for 2-to-1 input sync reset D flip-flop clocking cb @ (negedge tb_top.clk); output #1 data = {tb_top.rst,

tb_top.d0,

tb_top.d1,

tb_top.sel}; endclocking: cb

initial

begin

// Input

@(cb); cb.data <= 4’b1110;

@(cb); cb.data <= 4’b0100;

@(cb); cb.data <= 4’b1111;

@(cb); cb.data <= 4’b0011;

@(cb); cb.data <= 4’b0010;

@(cb); cb.data <= 4’b0011;

@(cb); cb.data <= 4’b1111;

...

end

Sample 5-26. Abstracting the synchro-nous reset operation task sync_reset;

begin

cb.rst <= 1’b1;

cb.d0 <= 1’b1;

cb.d1 <= 1’b1;

cb.sel <= $random; @(cb);

endtask: sync_reset

Stimulus and Response

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Dear Editors and Reviewers, Thank you for your letter and comments on our manuscript titled “Temporal variability in soil moisture after thinning in semi-arid Picea crassifolia plantations in northwestern China” (FORECO_2017_459). These comments helped us improve our manuscript, and provided important guidance for future research. We have addressed the editor’s and the reviewers’comments to the best of our abilities, and revised text to meet the Forest Ecology and Management style requirements. We hope this meets your requirements for a publication. We marked the revised portions in red and highlighted them yellow in the manuscript. The main comments and our specific responses are detailed below: Editor: Please explain how the results in this paper are significantly different from those in Zhu, X., He, Z.B., Du, J., Yang, J.J., Chen, L.F., 2015. Effects of thinning on the soil moisture of the Picea crassifolia plantation in Qilian Mountains. Forest Research. 28, 55–60.)

投稿coverletter写法

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实验十一流类库与输入/输出(2学时) 一、实验目的 1.熟悉流类库中常用的类及其成员函数的用法。 2.学习标准输入输出及格式控制。 3.学习对文件的应用方法(二进制文件、文本文件)。 二、实验任务 1.观察以下程序的输出,注意对输出格式的控制方法; //labll—1.cpp #include Using namespace std; #define D(a)<<#a<

投稿经验

四.我的论文生活 本人现在5篇SCI,两篇IEEE TRANSACTION/JOURNAL (regular) paper,两篇IF=1.2*,一篇IF=0.8*.一个专利,两个应用证明。还有5篇SCI在审,IF分别为2.3*,0.5*,0.5*,0.4*,0.4*。所以我自认为在博士期间做的还可以,再加上博士期间做了太多的秘书工作,同时接手的项目自己独立完成,还是我以前没有接触的领域,也是实验室没有接触过的领域,所以我自己对自己还是比较满意的。当然在理工同窗面前我是非常普通,甚至不入流的学生之一,不过我希望把我一点经验分享大家,如果对于学弟学妹有一点帮助,我就非常开心了,如果没有帮助也请各位大牛不要见笑。下面我介绍一下我写论文的经验。 打铁还需自身强啊。首先我们应该从我们自己本身着手。博士与本科和硕士相比都不同,而且是根本上意义的不同。打个比方,如果给大家一个问题,大家能够非常快速的解决,并利用各种方法。但是这种训练方式完全是自下而上的教育方式,一直到硕士戛然而止。博士突然让我们思维方式出现了一个转变,这是很难的。这种原因可能因为我们小学到硕士一直是按照我们自己的思维方式在培养,到了博士我们学习西方思维方式培养,而产生了极大的落差。 博士不会在告诉你,你需要解决什么样的具体问题,而是在于你是否能发现问题。我们一直的教育都是我们解决问题的能力,对于中国的学生,特别是在理工大学培养的学生,解决问题的能力绝对是非常强的,没有任何问题,但是缺少一双发现问题的眼睛。我们不善于自己提出问题和解决我们觉得陌生的问题,我们喜欢解决别人提出来的问题,使用别人提出的方法,按照别人的思路。不能说孰优孰劣,但是在现有的博士培养体系下我们是处于劣势的。郑强教授说得对,如果找不到与自己发现问题相关的参考文献,通常我们都对自己的发现先产生怀疑,极度的不自信。 我们需要在别人研究内容的基础上发现存在的问题。例如某个同学会说,某某领域已经做烂了,没有东西做了。但是我要告诉你,把你放着一个新的领域,你还是不行。因为不是没有问题,而是你没有发现问题。这个劣势在工科中尤为突出。这样我们在读某篇论文或者某位牛人的大作的时候,读完了直呼精彩,但是我们这个时候就需要考虑这篇论文的问题在哪里,有没有限制条件,我们能不能发现新的问题,在我们解决新的问题的时候也是我们有目的的资料收集的时候,也就是我们写论文的时候,发论文的时候了。不过需要强调的是,思路对也好,不对也好,方法对也好,不对也好,除了结果不同以外,其他都是一样的。过程都是痛苦的,甚至会因为发现自己是如此的无知而感到深深的惭愧和不能接受。 上面的论点对于大多数人来说,大而空,该不懂还是不懂,该写不出来还是写不出来,没有办法,这个就是思维的问题。那么上面从自身入手,我再给出从外界获取资源的方法。只有将二者结合才能达到最佳结果。 如何获取外界资源。我看论文的时候,会有很多问题,论文中很多观点我看不懂,而且这些观点在论文中没有任何的解释,让我摸不着头脑,所以我会给论文的通信作者写信咨询。我的经验是别给中国人写信。中国人不喜欢Share,只喜欢require。下面我附上一封我写信请教问题的模板。 Dear and respected Prof. *** I am very sorry for troubling you, but can I ask you a question relevant to your paper?

实体、对象与类的概念

1、实体、对象与类的概念 2、类的定义 3、对象声明与引用 4、私有、公有与保护 5、日期类的设计 6、两种程序设计思想 7、汽车类的设计 8、几何图形圆类的设计 9、构造函数的定义10、重载构造函数11、析构函数的定义12、整数翻译函数13、实际意义的析构函数14、Person类的设计15、对象与指针16、this指针

?实体:指客观世界存在的某个事物?一所大学,例如:西安交通大学 ?某动物,例如:一只羊 ?一本图书,例如:《C++程序设计教程》?一篇文章,例如:“羊年趣赏羊联” ?一个专业班级,例如:材料21班 ?一名学生,例如:材料21班的蒋贵川?……

?可以拍摄视频描述实体 ?也可以写一篇文章描述实体 ?我们设计的程序都是为了求解某个(些)问题 ?如果求解的问题中涉及到某个实体,那么在程序中如何描述实体呢? ?通过对实体进行抽象,来描述实体

?每个实体都有其特征和功能,特征和功能通称为属性?实体与实体的不同在于属性的不同 ?所谓抽象描述实体是指: ?从实体中抽取出若干特征和功能,来表示实体 ?特征指实体的静态属性,功能指实体的动态属性 ?对实体加以抽象要注意下面两点: ?移出细节看主干 ?不是借助具体形象反映现实,而是以抽象表达科学的真实

毕加索画《牛》 1945年12月5日 1946年1月17日 ?形体逐渐概括 ?线条逐步简练 ?别人认为的终点,他 作为起点 ?每幅画不重复 ?精炼地表现了公牛的

?电视机的特征:?型号?尺寸?液晶?价格? ……?电视机的功能: ?播放影视?选频道?调颜色?调音量?……

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